JP2009088147A - Stencil mask and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stencil mask having high strength and heat resistance and superior machining accuracy, and to provide its manufacturing method. <P>SOLUTION: The manufacturing method comprises a step of forming a stencil pattern on a first thin film layer while forming an alignment pattern on the outer periphery of a stencil pattern arrangement region, the alignment pattern formed on the first thin film layer being in an outer periphery region beyond a region where a second thin film layer is pasted, a step of using a plurality of alignment patterns for pasting the second thin film layer on the surface of the first thin film layer, a step of forming resist on the surface of the second thin film layer, and a step of using the alignment patterns for positioning the stencil pattern and using stencil pattern data for the first thin film layer for drawing it superposed on the resist face of the second thin film layer so that an opening pattern in the same shape as the stencil pattern of the first thin film layer is superposed on the same position as the position of the stencil pattern of the first thin film layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a stencil mask and a method for manufacturing a stencil mask.

  In recent years, research has been conducted on a charged particle beam transfer method using a stencil mask. One of them is an ion implantation process using a stencil mask in a semiconductor manufacturing process. In this implantation method, impurities are implanted into the process substrate through the opening pattern of the stencil mask, so that a resist lithography process and a resist removal process are unnecessary as compared with the conventional ion implantation process. Furthermore, the process cost can be reduced by repeatedly using one stencil mask.

  In the stencil mask used in the ion implantation process, it is necessary to prevent thermal distortion at the time of ion implantation, and it is preferable to set the membrane thickness to, for example, 10 μm or more, depending on the incident energy to the mask and the membrane size. In the stencil mask, the implanted ions pass through the opening pattern formed in the self-supporting membrane, and the ions implanted onto the membrane are captured in the membrane, so that the ions can be implanted into a desired location on the substrate to be implanted. For this reason, the implantation process must be accurately controlled, and mask processing accuracy such as the opening dimension of the stencil pattern, the angle in the depth direction (taper angle), and the variation in the stencil mask surface is required.

  When a stencil pattern having an opening width w is processed on a membrane having a thickness t, it is generally advantageous that the aspect ratio A (= t / w) is small in order to satisfy the required processing accuracy. For example, when silicon is used as the thin film material, it is desirable that the aspect ratio A be 20 or less even when a Bosch process that excels in high aspect etching is used.

  In addition to the above ion implantation process, there is a transfer method using a stencil mask for electron beam lithography. In this method, there is an exposure apparatus called EBLITHO (manufactured by Holon Co., Ltd.) that can form a fine pattern with a low acceleration electron beam. In this apparatus, a resist fine pattern of several hundred nm or less can be formed in a region of 10 mm □ or more. According to this method, compared with photolithography and nanoimprinting, the method can be formed with a deeper depth of focus, which makes the lithography process easier. This feature is suitable for a process for forming a fine structure on the surface of an LED chip, and is expected to be applied to a process for increasing the brightness of an LED device.

  In the case of an ion implantation mask, a membrane thickness of 10 to 20 μm is often used. The minimum aperture width that can be processed with high accuracy in a membrane having a thickness of 10 μm is about 0.5 μm.

  However, the opening size required in the ion implantation process may not only be 0.5 μm or less, but if the current is increased to improve the throughput, the thermal load on the mask increases, so the film thickness must also be increased. . Therefore, a stencil mask having a higher aspect ratio than the current pattern by increasing the film thickness is effective, but cannot actually be manufactured (see Patent Document 1).

In the same-size exposure using a low acceleration electron beam such as EBLITHO, the pattern size used in the optical member processing is often about the wavelength of the target light source or less, and the size is from several tens of nm to It is about 500 nm. Further, the fine patterns are arranged at a pitch about twice the size, and a fine pattern group is formed at a high density. In order to form such a fine pattern, a membrane thickness of about 0.5 to 2.0 μm is used. When a 100 nm pattern is formed on a 0.7 μm thick membrane, the width is 100 nm and the height is 700 nm. When a very weak stencil beam is formed and a pattern is arranged at a high density with a pitch of about twice the size, the membrane strength is greatly reduced. Such a decrease in strength causes problems such as membrane deformation and breakage during use of the stencil mask and during manufacture.

  Therefore, it is possible to increase the membrane strength by increasing the film thickness, but it is impossible to form a high aspect pattern exceeding the processing limit. It is also possible to apply a material that is stronger than silicon, such as diamond, but it is very difficult to process diamond while forming a defect-free diamond layer and satisfying good processing accuracy. Therefore, it is not suitable for a member such as a mask that has severe defect control.

  As another method, a stencil pattern 1 is formed on an SOI substrate, a stencil pattern 2 obtained by mirror-inversion of the stencil pattern 1 is formed on another SOI substrate, and the two SOI substrates are bonded to each other. It is also possible to manufacture the above stencil mask. However, in general, the bonding accuracy is several μm or more, and the positional deviation between the stencil patterns of the two SOI substrates tends to be large, so this method is also not effective. Also, the larger the substrate is, such as 8 inches, and the greater the warpage, the larger this positional deviation, so it cannot be used as a stencil mask.

The known literature is described below.
JP 2004-200223 A

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a stencil mask having improved mechanical strength and heat resistance and having excellent processing accuracy, and a method for manufacturing the stencil mask.

The invention according to claim 1 of the present invention has a stencil pattern aspect ratio (A (= t / w)) in which a thin film layer having a predetermined thickness (t) has a stencil pattern with an opening width (w). A stencil mask,
The thin film layer is a multilayer membrane composed of a first thin film layer and a second thin film layer on the surface, and the stencil pattern formed on the multilayer membrane when the aspect ratio of the stencil pattern formed on the first thin film layer is Am. The stencil mask is characterized by having a stencil pattern having an aspect ratio greater than the aspect ratio (Am) of the stencil pattern formed on the first thin film layer.

  The invention according to claim 2 of the present invention is the stencil mask according to claim 1, wherein the multilayer membrane comprises two or more layers.

  The invention according to claim 3 of the present invention is characterized in that an opening pattern having the same shape as the stencil pattern of the first thin film layer is formed in the second thin film layer at the same position as the stencil pattern of the first thin film layer. The stencil mask according to claim 1 or 2.

The invention according to claim 4 of the present invention is characterized in that the material of the thin film layer is silicon or a material containing silicon, and is made of a material suitable for forming an opening pattern having an aspect ratio Am of 10 to 40. The stencil mask according to any one of claims 1 to 3.

  The invention according to claim 5 of the present invention is made of a highly conductive material containing at least one of Pt, Pd, Au, Cr, Ti, Ta, Mo, Zr, Ir, and Hf on the surface of the multilayer membrane. 5. The stencil mask according to claim 1, wherein a thin film layer is formed.

The invention according to claim 6 of the present invention is the method for manufacturing a stencil mask according to any one of claims 1 to 5,
When forming the stencil pattern on the first thin film layer, simultaneously forming a pattern for alignment on the outer periphery of the stencil pattern placement region;
Bonding the second thin film layer to the surface of the first thin film layer;
Forming a resist on the surface of the second thin film layer;
Positioning is performed using the alignment pattern, and an opening having the same shape as the stencil pattern of the first thin film layer is formed at the same position as the stencil pattern of the first thin film layer using the stencil pattern data of the first thin film layer. And a step of superposing and drawing on the resist surface of the second thin film layer so that the patterns overlap with each other.

  In the invention according to claim 7 of the present invention, the alignment pattern formed on the first thin film layer is an outer peripheral region than the region where the second thin film layer is bonded, and a plurality of alignment patterns are formed. The stencil mask manufacturing method according to claim 6, wherein

  The stencil mask of the present invention has high rigidity compared to a conventional stencil mask having the same opening width and a membrane thickness of 0.7 μm, so that not only can the distortion during transfer be reduced, but also by repeatedly using the mask. Damage to the mask can also be reduced.

  The stencil mask of the present invention can realize a stencil mask with improved mechanical strength and heat resistance and excellent processing accuracy. For example, it can be suitably used as an ion implantation mask or a stencil mask for electron beam lithography. Can be expected.

  A stencil mask and a method for manufacturing a stencil mask of the present invention will be described below based on an embodiment.

  FIG. 1 is a schematic view showing a stencil mask of the present invention. Hereinafter, the stencil mask of the present invention and the manufacturing method thereof will be described.

  First, the stencil mask of this invention is demonstrated using FIG. The stencil mask of the present invention has a multilayer membrane 4 composed of a first thin film layer 2 and a second thin film layer 3 having a thickness t, and the multilayer membrane layer is supported by a supporting silicon substrate layer 5. A pattern 1 is formed (see FIG. 1A). In the stencil pattern 1, the largest aspect ratio (= t / opening width of the stencil pattern 1: w) is Am. (See FIG. 1 (b)). Although the thickness of the first thin film layer and the second thin film layer is the same here, they may be different, and the present invention is not limited.

In addition, when the material of the thin film layer is silicon, the aspect ratio that can be processed with high precision is about 10 to 40 although it depends on the type of pattern, so that the stencil whose aspect ratio in the multilayer film in the stencil mask is about 80 at maximum. It is a mask.

  The stencil mask of the present invention has a membrane thickness that is twice that of the conventional case where a stencil pattern is formed on a thin film layer consisting of one layer, so that the mechanical rigidity is increased, and deformation and thermal deflection due to the holder in use. Can be prevented.

  Next, FIG. 2 is a sectional side view of the process for explaining the method for producing the stencil mask of the present invention. In the present invention, when the stencil pattern 1 is formed on the first thin film layer 2, the alignment pattern 6 is formed at the same time, the position coordinate of the first thin film layer 2 is detected using the alignment pattern 6, and the second thin film A method for producing a stencil mask, wherein a resist pattern for a stencil pattern is overlaid and drawn on the electron beam sensitive resist 8 on the layer 3.

  The method for producing a stencil mask of the present invention is such that the stencil pattern resist pattern of the second thin film layer 3 is overdrawn and drawn as compared with the case where two thin film layers on which the stencil pattern is formed are bonded. The stencil pattern of the second thin film layer 3 can be easily formed with high overlay accuracy with respect to the stencil pattern. As shown in FIG. 1C, when the positional deviation λ of the stencil pattern 1 of the second thin film layer 3 with respect to the stencil pattern 1 of the first thin film layer 2 is defined as a deviation from the center position of the two patterns, Although it depends on the accuracy of the drawing machine, it can be reduced to about 2 nm.

  3 to 5 are side sectional views of steps (a) to (l) showing the manufacturing method of the first embodiment of the present invention. Example 1 and Example 2 related to the stencil mask of the present invention were performed. This will be described below.

  Hereinafter, as an example of the stencil mask of the present invention, a stencil mask for ion implantation having a high aspect ratio pattern having a minimum opening width of 0.5 μm and a membrane thickness of 40 μm will be described with reference to FIGS. 3, 4, and 5. Example 1 will be described.

  First, an SOI substrate 13 having a diameter of 100 mmΦ and comprising a supporting silicon substrate 10 having a thickness of 525 μm, an intermediate oxide film 11 having a thickness of 0.5 μm, and a silicon active layer 12 having a thickness of 20 μm was prepared (FIG. 3A). reference). The substrate size is not limited to the present invention, and can be 3, 6, or 8 inches, which is a size generally used in a wafer process.

Next, an electron beam sensitive resist 14 (PMMA (polymethylmethacrylate-based) positive resist, sensitivity: 300 μC / cm ² ) was applied on the SOI substrate 13 to a film thickness of 1000 nm (FIG. 3B). reference).

Next, the resist 14 is irradiated with an electron beam so that the electron beam dose is 300 μC / cm ^2, and after development, a registration resist pattern 15, an injection stencil resist pattern 16, and a back registration resist mark 17 are obtained. (See FIG. 3 (c)).

  FIG. 6 is a top view showing the arrangement of the alignment pattern of the present invention. By arranging a large number of alignment patterns in as wide a range as possible, the position coordinates of the SOI substrate can be measured with high accuracy, so that the displacement of the stencil pattern between the first thin film layer and the second thin film layer can be reduced. it can. In the first embodiment, 24 alignment patterns are arranged on concentric circles having a diameter of 60, 70, and 80 mm from the center of the SOI substrate 13 so that the intervals between adjacent alignment patterns on the concentric circles are equal. Formed (see FIG. 6).

Next, the silicon active layer 1 is exposed until the intermediate oxide film 11 is exposed by dry etching using a fluorocarbon-based mixed gas plasma using the resist pattern as an etching mask.
2 was etched. Further, after the resist layer is peeled off by oxygen plasma, cleaning is performed by RCA cleaning such as ammonia-hydrogen peroxide, and the patterning pattern 100 mmΦ in which the alignment pattern 18, the injection stencil pattern 19, and the front and back alignment marks 20 are formed is formed. An SOI substrate 21 was manufactured (see FIG. 3D).

  Next, an SOI substrate 25 having a diameter of 50 mmΦ comprising a supporting silicon substrate 22 having a thickness of 525 μm, an intermediate oxide film 23 having a thickness of 1 μm, and a silicon active layer 24 having a thickness of 20 μm was prepared (see FIG. 4E). . If there is no commercially available 50 mmΦ SOI substrate, a 50 mmΦ SOI substrate can be easily obtained by cutting out from a 100 mmΦ SOI substrate.

  Next, the substrates were bonded so that the surface of the silicon active layer 24 of the 50 mmΦ SOI substrate 25 and the surface of the silicon active layer of the patterned SOI substrate 21 were in contact with each other, and the centers of the substrates 21 and 25 were overlapped. As a bonding method, the bonding surfaces of both substrates were activated by vacuum plasma, and the bonding surfaces were bonded. In this case, in order to obtain sufficient adhesion, heating and pressure of 300 to 500 ° C. were performed simultaneously with the bonding (see FIG. 4F).

  FIG. 7 is a top view showing a deviation between two bonded substrates of the present invention. In order to improve the alignment accuracy of the overlay drawing performed in the subsequent process, the positional deviation between the centers of the two substrates to be joined is small, and all the alignment marks 18 on the patterned SOI substrate after bonding, that is, 24 pieces are exposed. It is desirable that However, if the alignment mark 18 is exposed on the outer peripheral portion of the 50 mmΦ SOI substrate 25, sufficient alignment accuracy can be obtained. Here, since the radius of the SOI substrate 25 of 50 mmΦ is 25 mm and the alignment mark 18 is formed on a concentric circle having a radius of 30 to 40 mm, the alignment misalignment δ between the two substrates is usually in the radial direction. Up to acceptable. This indicates that the method of the present invention can be easily applied because high-precision alignment accuracy is not required (FIG. 7).

  Next, the support substrate layer 22 of the bonded SOI substrate 25 is removed to the intermediate oxide film layer 23 of the SOI substrate by polishing or etching, and then the intermediate oxide film layer 23 is removed by HF etching, thereby obtaining a silicon active layer. 24 was exposed. At this time, it is desirable to form a protective film layer such as a resist on the support substrate layer so that the alignment mark on the patterned SOI substrate is not damaged.

  Next, after performing RCA cleaning such as ammonia overwater, the silicon active layer 24 is exposed. Since the silicon active layer 24 was covered with the intermediate oxide film layer 23 formed by thermal oxidation, the surface with a very high cleanliness level can be exposed (see FIG. 4G).

Next, an electron beam sensitive resist 26 (PMMA (polymethylmethacrylate-based) positive resist, sensitivity: 300 μC / cm ² ) was applied on the silicon active layer 24 to a thickness of 1000 nm (FIG. 4 (h)). )reference).

Next, the alignment pattern 18 on the patterned SOI substrate 21 is detected by the electron beam drawing apparatus, and the position on the electron beam sensitive resist 26 is set so as to be the same position as the pattern on the patterned SOI substrate 21. After the development, an alignment pattern 18 and an implantation resist stencil pattern 27 were manufactured. At this time, the electron beam irradiation dose is 300 μC / cm ² (FIG. 5 (i)).

Next, etching is performed up to the silicon active layer of the patterned SOI substrate 21 by dry etching using a fluorocarbon-based mixed gas plasma using the resist pattern as an etching mask, the resist layer is peeled off by oxygen plasma, and ammonia-hydrogenated water. The stencil pattern 28 for injection was manufactured after cleaning by RCA cleaning such as
(Refer FIG.5 (j)).

  Since the alignment mark 18 of the first thin film layer 2 is detected by the electron beam drawing apparatus and the injection pattern 28 of the SOI layer of the second thin film layer 3 is formed, the injection pattern 28 and the patterned processed injection pattern 28 The positional deviation is about 2 nm which is the minimum position accuracy measurement limit. The positional deviation is a relative deviation between the two pattern centers. Further, even when the SOI substrate is adhered onto the alignment mark at the time of bonding and a part of the alignment mark cannot be observed, an approximate plane is calculated from the coordinate information of the remaining marks, The distortion of the SOI substrate can be calculated. Therefore, even if the bonding accuracy is normal, the positional deviation can be controlled, so that it can be several tens of nm or less.

  Next, a photoresist is applied on the supporting silicon substrate layer of the SOI substrate 13 with a spinner or the like to form a photosensitive layer 29 having a thickness of 50 μm, and patterning processing such as pattern exposure and development is performed, so that a resist for membrane opening is obtained. A pattern 30 was formed. At this time, the alignment of the front and back alignment mark pattern 20 and the photomask alignment mark is used for alignment between the substrate and the photomask for exposure of the membrane opening resist pattern during pattern exposure (see FIG. 5K).

  Next, a part of the supporting silicon substrate 10 is etched by dry etching using a fluorocarbon-based mixed gas plasma using the membrane opening resist pattern 30 as an etching mask, and further using the intermediate oxide film 11 as an etching stopper layer. Then, the intermediate oxide film 11 exposed by dry etching was removed (FIG. 5L).

  Next, washing was performed. At this time, as a cleaning process, a ratio of ammonia: hydrogen peroxide water: pure water is mixed at about 1: 1: 5, and immersed in ammonia overwater heated to 70 ° C. for 10 minutes to rinse pure water. Then, hydrofluoric acid treatment and overflow treatment are performed again, and IPA vapor drying is performed.

  From the above, a stencil mask for ion implantation of Example 1 having a high aspect ratio pattern with a minimum opening width of 0.5 μm and a membrane thickness of 40 μm was manufactured.

  A method is also conceivable in which an implantation pattern in which mirrors are inverted is formed in advance on two SOI substrates, and the substrates are aligned and bonded by a wafer bonding apparatus. However, the alignment accuracy of a commercially available wafer bonding apparatus is generally several μm and at most several hundred nm, and it is difficult to obtain good alignment accuracy.

  According to the method of the present invention, the alignment accuracy of the two layers does not depend on the alignment accuracy of the bonding apparatus, but is determined by the overlay accuracy of the drawing apparatus. Therefore, a very good alignment accuracy of several nm is easily realized. it can.

  FIG. 8 is an immediate cross-sectional view of steps (a) to (f) showing the manufacturing method of Example 2 of the present invention. Example 2 will be described below.

  Hereinafter, as an example of the stencil mask of the present invention, a pattern group in which a high aspect ratio pattern having a minimum opening width of 0.1 μm and a membrane thickness of 1.4 μm is located at the apex of an equilateral triangle having a side of 0.2 μm. A stencil mask for low-acceleration electron beam lithography of Example 2 was produced. Hereinafter, Example 2 will be described with reference to FIG.

First, a 100 mmφ SOI substrate 34 having a silicon active layer 31 having a thickness of 0.7 μm, an intermediate oxide film 32 having a thickness of 0.5 μm, and a supporting silicon substrate 33 having a thickness of 525 μm was prepared (FIG. 8A).

  Next, the silicon active layer 35 was doped with impurities so that the internal stress of the self-supporting membrane was 20 MPa or less when the self-supporting membrane was formed, thereby obtaining a stress-adjusted silicon active layer 35. When the active layer is silicon, the free-standing membrane is loosened due to the compressive stress of the intermediate oxide film when the free-standing membrane is formed. Therefore, it is necessary to apply a tensile stress to the silicon active layer. Therefore, an impurity having an atomic radius smaller than that of silicon, such as phosphorus or boron, is selected as the impurity (FIG. 8B).

Next, an electron beam sensitive resist 37 (PMMA (polymethylmethacrylate-based) positive resist, sensitivity: 300 μC / cm ² ) was applied to the stress-adjusted SOI substrate 36 with a film thickness of 200 nm (FIG. 8). (See (c)).

  Next, pattern processing in which electron beam irradiation, development processing, dry etching, and resist removal are performed as in Example 1 to form the alignment pattern 38, the stencil pattern 39 for electron beam lithography, and the front and back alignment marks 40 are performed. A manufactured 100 mm SOI substrate 41 was manufactured (see FIG. 8D).

  Next, the silicon active layer is previously doped with impurities so that the stress is 20 MPa or less when the free-standing membrane is formed, and the supporting silicon substrate 42 having a thickness of 525 μm and the intermediate oxide film 43 having a thickness of 0.5 μm. An SOI substrate 45 having a diameter of 50 mmΦ made of an impurity-doped silicon active layer 44 having a thickness of 0.7 μm was prepared (see FIG. 8E).

  Next, the same stencil for low acceleration electron beam as in Example 2 having a high aspect ratio pattern with a minimum opening width of 0.1 μm and a membrane thickness of 1.4 μm, which is similar to Example 1, in which bonding and electron beam lithography are performed. A mask was manufactured (see FIG. 8F).

It is a schematic diagram which shows the stencil mask of this invention. It is a sectional side view of the process explaining the manufacturing method of the stencil mask of this invention. It is a sectional side view of process (a)-(d) which showed the manufacturing method of Example 1 of this invention. It is side sectional drawing of process (e)-(h) which showed the manufacturing method of Example 1 of this invention. It is a sectional side view of process (i)-(l) which showed the manufacturing method of Example 1 of this invention. It is the top view which showed arrangement | positioning of the alignment pattern of this invention. It is a top view which shows shift | offset | difference of two bonded substrates of this invention. It is immediate sectional drawing of process (a)-(f) which showed the manufacturing method of Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Stencil pattern 2 ... 1st thin film layer 3 ... 2nd thin film layer 4 ... Multilayer membrane 5 ... Supporting silicon substrate 6 ... Positioning pattern 7 ... Membrane region 8 ... Electron beam sensitive resist 10 ... Supporting silicon substrate 11 ... Intermediate oxidation Film 12 ... Silicon active layer 13 ... 100 mmφ SOI substrate 14 ... (electron beam sensitive) resist 15 ... registration resist pattern 16 ... implantation stencil resist pattern 17 ... back registration resist mark 18 ... registration pattern 19 ... Stencil pattern for implantation 20 ... Front and back alignment mark 21 ... Pattern processed 100 mmΦ SOI substrate 22 ... Support silicon substrate 23 ... Intermediate oxide film 24 ... Silicon active layer 25 ... 50 mmΦ SOI substrate 26 ... Electron beam sensitive resist 27 ... Implant resist stencil pattern 28. Sill pattern 29 ... Photosensitive layer 30 ... Membrane opening resist pattern 31 ... Silicon active layer 32 ... Intermediate oxide film 33 ... Support silicon substrate 34 ... 100 mmΦ SOI substrate 35 ... Stress-adjusted silicon active layer 36 ... Stress-adjusted SOI substrate 37 ... Electron beam sensitive resist 38 ... Positioning pattern 39 ... Stencil pattern 40 for electron beam lithography ... Front and back side alignment mark 41 ... Pattern-processed 100 mmΦ SOI substrate 42 ... Support silicon substrate 43 ... Intermediate oxide film 44 ... Impurity doping Silicon active layer 45 ... Stress adjusted 50mmΦ SOI substrate

Claims (7)

A stencil mask having a stencil pattern aspect ratio (A (= t / w)) having a stencil pattern with an opening width (w) in a thin film layer having a predetermined thickness (t),
The thin film layer is a multilayer membrane composed of a first thin film layer and a second thin film layer on the surface, and the stencil pattern formed on the multilayer membrane when the aspect ratio of the stencil pattern formed on the first thin film layer is Am. A stencil mask comprising a stencil pattern having an aspect ratio greater than the aspect ratio (Am) of the stencil pattern formed on the first thin film layer.   The stencil mask according to claim 1, wherein the multilayer membrane comprises two or more layers.   3. The stencil mask according to claim 1, wherein an opening pattern having the same shape as the stencil pattern of the first thin film layer is formed in the second thin film layer at the same position as the stencil pattern of the first thin film layer. .   The material of the thin film layer is made of silicon or a material containing silicon, and is made of a material suitable for forming an opening pattern having an aspect ratio Am of 10 to 40. The described stencil mask.   A thin film layer made of a highly conductive material containing any one or more of Pt, Pd, Au, Cr, Ti, Ta, Mo, Zr, Ir, and Hf is formed on the surface of the multilayer membrane. Item 5. The stencil mask according to any one of Items 1 to 4. A method for manufacturing a stencil mask according to any one of claims 1 to 5,
When forming the stencil pattern on the first thin film layer, simultaneously forming a pattern for alignment on the outer periphery of the stencil pattern placement region;
Bonding the second thin film layer to the surface of the first thin film layer;
Forming a resist on the surface of the second thin film layer;
Positioning is performed using the alignment pattern, and using the stencil pattern data of the first thin film layer, the opening pattern having the same shape as the stencil pattern of the first thin film layer is located at the same position as the stencil pattern of the first thin film layer. And overdrawing on the resist surface of the second thin film layer so as to overlap with each other.   7. The stencil mask according to claim 6, wherein the alignment pattern formed on the first thin film layer is an outer peripheral region than the region where the second thin film layer is bonded, and a plurality of alignment patterns are formed. Production method.

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