JP2009088090A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an integration degree in a semiconductor device provided with a nonvolatile memory in the same chip. <P>SOLUTION: A nonvolatile memory cell NVM has a writing/deleting element WD having a common floating electrode FG, a reading transistor QR, and a MIS capacitor C. The writing/deleting element WD and the reading transistor QR are formed so as to be electrically connected with each other in the same p-type operating element forming p-well PW1 arranged on the main face S1 of a semiconductor substrate 1. The MIS capacitor C is formed in a p-type capacitor forming p-well PW2 separated from the operating element forming p-well PW1 and arranged along the operating element forming p-well PW1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device having a nonvolatile memory.

  Liquid crystal displays (LCDs) and the like that are widely put into practical use as display devices are being developed for higher definition and longer life. For the operation control of the LCD, a semiconductor device called an LCD driving integrated circuit (driver IC: Integrated Circuit or simply a driver) is used.

  In order to display a desired image, moving image, etc. with high image quality, the LCD driver is required to have gradation characteristics with high linearity so as to control the potential difference to the pixel with high accuracy. On the other hand, in an LCD driver produced through a mass production process, the characteristics of the transistors constituting it vary, so that the gradation characteristics are not uniform. In an LCD driver that requires high-precision gradation characteristics as described above, such transistor variations become a particularly significant problem.

  On the other hand, the LCD driver studied by the present inventors is adjusted in tone characteristics called trimming after manufacture and shipped in an optimal state. For this purpose, it is common to optimize the location where the gradation is shifted by an external variable resistor called a trimmer. On the other hand, according to the study by the present inventors, the recent trend in demand for LCDs is the rapid increase in mounting on mobile communication terminals, etc. Requests are made. Accordingly, the present inventors have studied a technique for providing the above trimming function in the semiconductor chip of the LCD driver in advance, adjusting the gradation characteristics at the manufacturing stage, and shipping.

  At this time, information related to adjustment of gradation characteristics is stored, and a relatively small capacity and highly reliable non-volatile memory (also referred to as an electric fuse) that keeps the information even when no power is applied after shipment. )Is required.

  From the above examination by the present inventors, it is desirable that the nonvolatile memory for adjusting the gradation characteristics of the LCD driver is formed on the same semiconductor chip at the same time as the LCD driver, and is formed by an easy manufacturing process. For example, in Japanese Patent Application Laid-Open No. 2007-110073 (Patent Document 1), in a MIS structure, carriers that pass through an insulating film due to a FN (Fowler-Nordheim) tunneling phenomenon from a channel inversion region are accumulated in a gate electrode. Among the non-volatile memories that hold information, a semiconductor device having a single charge storage layer is disclosed.

Compared with a general non-volatile memory, a non-volatile memory composed of a single charge storage layer is relatively easy to manufacture, and can be manufactured using the process of forming an LCD driver as it is. . The ease of the manufacturing process is effective for improving the manufacturing yield of semiconductor devices and improving the reliability of products.
JP 2007-110073 A

  However, when the present inventors examined a semiconductor device provided with a nonvolatile memory having a single charge storage layer as described above on the same semiconductor chip as the LCD driver, the following problems were found. It was.

  In general, a nonvolatile memory of a type that retains information by accumulating charges includes a capacitor unit that accumulates charges and a MIS (Metal Insulator Semiconductor) structure that performs write, read, and erase operations, or an MIS structure. A field effect transistor (FET) (hereinafter simply referred to as MIS transistor). Normally, the MIS transistors that perform the above-described write, read, and erase operations are the same transistor.

  Here, in the nonvolatile memory having the single charge storage layer described above, the present inventors have examined a nonvolatile memory of a type in which writing, reading, and erasing operations are performed in the same MIS structure. A challenge has been found.

  That is, it has been clarified that a malfunction, a writing failure, or an element breakdown occurs depending on the timing of applying a voltage during a writing operation. As a result, it has been found that this causes a decrease in the reliability of the semiconductor device as the nonvolatile memory. According to further studies by the present inventors, these are required operations such as a MIS transistor for read operation that operates as a normal transistor and a MIS structure for write / erase that transfers carriers. It has been found that the cause is that MIS structures having different characteristics are shared by the same MIS transistor and formed in the same well.

  Therefore, in the further study by the present inventors, the idea was to divide the above two types of MIS structures and form them in different wells. That is, a single-layer charge comprising three wells in one cell of the nonvolatile memory, that is, a well for forming a capacitor portion, a well for forming a write / erase MIS structure, and a well for forming a read MIS transistor. By introducing a non-volatile memory of a type having a storage layer, it was possible to solve the above-mentioned problems and avoid characteristics problems that caused a decrease in reliability.

  However, as described above, the demand for further refinement of LCDs combined with the recent demand for mounting LCDs in portable mobile communication terminals, etc., further miniaturization and higher integration of LCD drivers. Therefore, it has been found that it is difficult to fit a desired capacity within a desired occupied area in the 1-cell 3-well type nonvolatile memory as described above. In particular, it has become clear that it is difficult to realize a degree of integration of, for example, 2 kbit in the nonvolatile memory having the structure studied by the present inventors.

  Therefore, an object of the present invention is to provide a technique for improving the degree of integration in a semiconductor device including a nonvolatile memory in the same chip.

  The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. Of these, an outline will be briefly described as an example as follows.

  That is, in a nonvolatile memory cell having a data write / erase element having a common floating electrode, a read field effect transistor, and a capacitor, the data write / erase element and the read field effect transistor are: In the second semiconductor region of the same first conductivity type disposed on the main surface of the semiconductor substrate, the capacitor element is formed so as to be electrically connected, and the capacitor element is separated from the second semiconductor region And it is formed in the 3rd semiconductor region of the 1st conductivity type arranged so that the 2nd semiconductor region may be met.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  In other words, the degree of integration can be improved in a semiconductor device including a nonvolatile memory in the same chip.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
First, the configuration of the nonvolatile memory cell included in the semiconductor device studied by the present inventors and the problems found in the characteristics thereof will be described.

  FIG. 1 is a plan view of a nonvolatile memory cell NVMa examined by the present inventors. In FIG. 1, for easy understanding of the configuration of the nonvolatile memory cell NVMa, the semiconductor region is hatched, and other insulating films, for example, are omitted. FIG. 2 is a sectional view taken along line x1-x1 in FIG.

  The semiconductor substrate 1 constituting the semiconductor chip is formed of, for example, a p-type (second conductivity type) silicon single crystal. A separation portion 2 is formed on the main surface S1 of the semiconductor substrate 1. A buried n-well DNWx, which is an n-type (first conductivity type) semiconductor region, is formed in the semiconductor substrate 1 from the main surface S1 to a desired depth. In the buried n-well DNWx, a p-type semiconductor region, that is, an operating element forming p well PWx1 and a capacitor forming p well PWx2 are formed so as to extend in the first direction X. Similarly, an isolation n well NW, which is an n-type semiconductor region, is formed in the buried n well DNWx. In the buried n-well DNWx, the operating element forming p-well PWx1 and the capacitor-forming p-well PWx2 are included in a state of being separated by the separating n-well NW.

  On the main surface S1 of the semiconductor substrate 1, a floating electrode FGx is formed. The floating electrode FGx is made of, for example, polycrystalline silicon (also referred to as polysilicon).

  The floating electrode FGx includes an operating element floating gate electrode GExM and a capacitor floating gate electrode GExC. The floating electrode FGx is arranged so as to be in a so-called floating state so as not to be electrically connected to any other part. Thus, the floating electrode FGx in the floating state plays a role of holding data.

  Further, the main surface S1 of the semiconductor substrate 1 is planarly overlapped with a part of the p-well PWx1 for forming the operating element and along the operating element floating gate electrode GExM of the floating electrode FGx. A selection element gate electrode GExS is formed.

  An operating MIS field effect transistor QMx and a selection MIS field effect transistor QSx are formed in the operating element forming p well PWx1. Hereinafter, the MIS field effect transistor is simply referred to as a transistor. The operation transistor QMx is an element responsible for operations such as data writing, reading, and erasing in the nonvolatile memory cell NVMa. Further, the selection transistor QSx is a desired nonvolatile memory cell NVMa for performing the above-described operation without interfering with surrounding cells from among a large number of nonvolatile memory cells NVMa arranged in the semiconductor chip. Play a role to select. Detailed operations will be described later in detail.

  The operation transistor QMx has the following configuration. First, the floating gate electrode GExM for the operation element is provided. In addition, it has a floating gate electrode GExM for operating elements and a gate insulating film GIxM for operating elements formed between the semiconductor substrate 1. Further, it is an n-type semiconductor region located on the lower side of the operating element floating gate electrode GExM and formed in the main surface S1 of the semiconductor substrate 1 so as to be included in the operating element forming p well PWx1. It has a pair of source / drain regions SDx. In this pair of source / drain regions SDx, here, in particular, the side formed on the side where the selection element gate electrode GExS is present out of the lateral lower side of the operating element floating gate electrode GExM is defined as the shared source / drain region SDx. The drain region SDCx is described, and the other is described as the operating element source / drain region SDMx.

In the nonvolatile memory cell NVMa examined by the present inventors, the source / drain regions SDx and SDSx or the capacitor well power supply region VSCx and the capacitor source region SCx which is an n-type semiconductor region A semiconductor region having a low impurity concentration and a shallow junction depth, and a semiconductor region having a high impurity concentration and a deep junction depth. For example, in the case of the pair of source / drain regions SDx described above, the semiconductor region with a shallow junction depth is an n ⁻ semiconductor region, and the semiconductor region with a deep junction depth is an n ⁺ semiconductor region.

  The selection transistor QSx has the following configuration. First, the selection element gate electrode GExS constitutes a selection transistor QSx. In addition, a selection element gate insulating film GIxS formed between the selection element gate electrode GExS and the semiconductor substrate 1 is provided. The shared source / drain region SDCx extends from the lateral lower side of the operating element floating gate electrode GExM to the lateral lower side of the selection element gate electrode GExS, and constitutes the selection transistor QSx. It is also. That is, the shared source / drain region SDCx is shared between the operation transistor QMx and the selection transistor QSx, so that they are electrically connected in series. In addition, the n-type semiconductor region is formed on the main surface S1 of the semiconductor substrate 1 on the side where the shared source / drain region SDCx is not formed, and is located on the lower side of the selection element gate electrode GExS. It has a source / drain region SDSx for the selection element.

  Further, sidewall spacers 3 are formed on the side walls of the gate electrodes GExM and GExS. A silicide layer 4 is formed on the surface of each source / drain region SDCx, SDMx, SDSx and the surface of the gate electrode GExS for the selection element. In addition, an operating element well power supply region VSMx, which is a p-type semiconductor region, is formed on a part of the main surface S1 of the semiconductor substrate 1 in the operating element formation p well PWx1 with a separation portion 2 separated from other components. Has been.

  A MIS capacitor Cx is formed in the capacitor forming p-well PWx2. The MIS capacitor Cx is an element that plays a role of improving the voltage supply efficiency to the operation transistor QMx and the like in the nonvolatile memory cell NVMa.

  The MIS capacitor Cx has the following configuration. First, the capacitor floating gate electrode GExC is provided. Further, the capacitor gate insulating film GIxC formed between the capacitor floating gate electrode GExC and the semiconductor substrate 1 is provided. Further, in the capacitor formation p-well PWx2, as viewed in a plan view, for a capacitor, which is a p-type semiconductor region, formed on the main surface S1 of the semiconductor substrate 1 located in a region sandwiching the capacitor floating gate electrode GExC. It has a well power supply region VSCx and a capacitor source region SCx which is an n-type semiconductor region.

  A sidewall spacer 3 is formed on the sidewall of the capacitor floating gate electrode GExC. A silicide layer 4 is formed on the surfaces of the capacitor well power supply region VSCx and the capacitor source region SCx.

  Further, an interlayer insulating film 5 is formed on the main surface S1 of the semiconductor substrate 1. The interlayer insulating film 5 includes an insulating film 5a and an insulating film 5b formed thereon. A contact hole CH is formed in the interlayer insulating film 5 and is electrically connected to a desired region constituting the nonvolatile memory cell NVMa through the silicide layer 4 by a conductor portion 6 embedded therein. Each contact plug CPx1 to CPx6 is configured. Among them, in the nonvolatile memory cell NVMa studied by the present inventors, the capacitor well power supply contact plug CPx4 and the capacitor contact plug CPx5 existing at a plurality of locations are all connected to each other in the upper layer. It is assumed that power is supplied at the same time.

  A protective insulating film PI is formed on the upper surfaces of the capacitor floating gate electrode GExC and the operating element floating gate electrode GExM, so that the silicide layer 4 is not formed thereon. That is, the silicide layer 4 is formed on the selection element gate electrode GExS of the nonvolatile memory cell NVMa, and the silicide layer 4 is not formed on the floating gate electrodes GExC and GExM of the nonvolatile memory cell NVMa. It is configured. Note that the protective insulating film PI is formed of, for example, a silicon oxide film.

  The reason for forming such a protective insulating film PI will be described below. The floating electrode FGx is covered with a silicon nitride film (insulating film 5a) for forming a self-synthesis contact. The insulating film 5a is formed by, for example, a chemical vapor deposition (CVD) method using plasma in order to lower the process temperature. The silicon nitride film does not have conductivity, but may have slight conductivity depending on the gas flow rate ratio at the time of film formation and the rising state of plasma. In such a case, the charge stored in the floating electrode FGx may flow through the silicon nitride film and flow out to the substrate. For this reason, it has been clarified by the present inventors that a problem that the data in the memory cannot be held can be caused. In order to solve such a problem, a protective insulating film PI made of a silicon oxide film is sandwiched between the floating electrode FGx and the silicon nitride film (insulating film 5a), and the floating electrode FGx is transferred to the silicon nitride film. Prevents movement of charge.

  The protective insulating film PI is formed so as to extend in the gate length direction from the end of the side wall spacer 3 of each floating gate electrode GExM, GExC. As a result, the silicide layer 4 of the nonvolatile memory cell NVMa is formed in a self-aligned manner with respect to the protective insulating film PI.

The reason why the protective insulating film PI is formed as described above will be described by taking the operation transistor QMx of the nonvolatile memory cell NVMa examined by the present inventors as an example. For example, when the silicide layer 4 is formed in a self-aligned manner with respect to the sidewall spacer 3 without forming the protective insulating film PI, the end of the silicide layer 4 is, for example, n ^{+ of the} pair of source / drain regions SDx. It approaches the junction surface between the semiconductor region and the operating element forming p well PWx1. Furthermore, since the n ⁻ semiconductor region of the pair of source / drain regions SDx is a region having a very shallow junction depth, the silicide layer 4 reaches the operating element forming p well PWx 1 beyond the n ⁻ semiconductor region. There is also. That is, when the protective insulating film PI is not formed, from the end of the silicide layer 4 formed on the upper surface of the n ⁺ semiconductor region, toward the operating element forming p well PWx1 below the n ⁻ semiconductor region. It becomes a configuration in which a leak current easily flows. Therefore, in the nonvolatile memory cell NVMa studied by the present inventors, the protective insulating film PI is formed, and the silicide layer 4 is spoken from the n ⁻ semiconductor region. it can.

  The protective insulating film PI is also used for a resistance element or the like (not shown) formed in another region of the semiconductor substrate 1. By the protective insulating film PI, the silicide layer 4 can be selectively formed on the semiconductor substrate 1 or, for example, a polycrystalline silicon film. Thereby, a desired resistance value can be obtained, for example, in a resistance element.

  As described above, in the nonvolatile memory cell NVMa studied by the present inventors, the protective insulating film PI achieves the above-described effect at the same time.

  Next, the memory operation of the non-volatile memory cell NVMa having the above configuration studied by the present inventors will be described in detail with reference to FIGS. Hereinafter, the voltage applied to the operating well power supply contact plug CPx1 is the operating unit well voltage Vm, the voltage applied to the operating element contact plug CPx2 is the operating unit source voltage Vs, and the voltage applied to the selection element contact plug CPx3. The voltage applied to the read drain voltage Vd and the capacitor well power supply contact plug CPx4 and the capacitor contact plug CPx5 are represented as a capacitor portion applied voltage Vc, respectively.

  First, the write operation will be described. By setting the capacitor portion application voltage Vc to + 9V, a voltage of + 9V is applied to the capacitor forming p well PWx2 through the capacitor well power supply region VSCx. At this time, in the capacitor floating gate electrode GExC, which is the other electrode of the MIS capacitor Cx, a charge corresponding to −9 V is accumulated through the capacitor gate insulating film GIxC.

  Here, the charge corresponding to −9 V is supplied to the floating gate electrode GExC for the capacitor in the floating state from the portion of the floating electrode FGx that does not constitute the MIS capacitor Cx. That is, the operating element floating gate electrode GExM is charged to + 9V in order to preserve the charge of the entire floating electrode FGx.

  Thereby, in the operation transistor QMx, an electric field is applied to the operation element formation p-well PWx1 via the operation element gate insulating film GIxM. Then, a so-called inversion region is generated at the interface with the gate insulating film for operating element GIxM, and electrons which are minority carriers accumulate.

  Furthermore, since the operating part well voltage Vm is set to −9V, the operating part forming p well PWx1 and the operating element floating gate electrode GExM are set to 18V via the operating element gate insulating film GIxM. A corresponding voltage is applied. In the nonvolatile memory cell NVMa studied by the present inventors, the gate insulating film GIxM for the operating element is made sufficiently thin. Therefore, in this state, the electrons generated in the inversion region receive a high electric field corresponding to 18 V, and are injected into the operating element floating gate electrode GExM through the FN tunneling through the operating element gate insulating film GIxM.

  Note that, from the operating part source voltage Vs to which −9 V is applied, electrons e are supplied to the inversion region for lubrication. Further, if the selection transistor QSx is turned on and −9 V is applied to the read drain voltage Vd, the same electron can be supplied from here.

  As described above, electrons are injected into the floating electrode FGx by FN tunneling from the entire inversion region of the operation transistor QMx, and the floating electrode FGx is negatively charged. Since the floating electrode FGx is in a floating state, the accumulated charge is continuously held unless a specific voltage application condition is satisfied. That is, data is written in the nonvolatile memory cell NVMa cell by the above operation.

  Next, the reading operation will be described. First, when the capacitor unit applied voltage Vc is set to +3 V, similarly to the above, the capacitor floating gate electrode GExC, which is one electrode constituting the MIS capacitor Cx, is charged with −3 V.

  At this time, if the floating electrode FGx has not undergone the above writing operation and is not charged, the operating element floating gate electrode GExM is charged to + 3V. Further, when the floating electrode FGx is negatively charged after writing, the potential of the operating element floating gate electrode GExM is lower than +3 V in order to preserve the charge. That is, in the case of the operation transistor QMx, the threshold voltage for turning on changes depending on the presence or absence of writing.

  Here, if the selection transistor QSx is turned on, a source / drain current flows due to a potential difference between the read drain voltage Vd (= + 1 V) and the operation unit source voltage Vs (= 0 V). At this time, the magnitude of the source / drain current varies depending on the threshold voltage of the operation transistor QMx, that is, the presence or absence of data writing. As a result, the presence or absence of write data can be determined, and a read operation can be performed.

  Next, the erase operation will be described. Here, all the behaviors of electrons can be reversed by setting the conditions opposite to the voltage application conditions for executing the write operation described above. That is, electrons accumulated in the operating element floating gate electrode GExM by the write operation can be emitted to the operating element formation p-well PWx1 through the FN tunneling over the operating element gate insulating film GIxM. Thereby, an erasing operation can be performed.

  Since the electron supply source (source) at the time of erasing is on the side of the operating element floating gate electrode GExM which is a conductor portion, an inversion region is formed in the operating element forming p well PWx1 as in the writing operation. The operation unit source voltage Vs and the read drain voltage Vd may be in an open (open or open) state during the erase operation.

  As described above, data can be written, read and erased in the nonvolatile memory cell NVMa examined by the present inventors. However, the inventors have found a problem that an operation failure at the time of writing is caused by a shift in timing of voltage application to each region. Details will be described below.

  The problems found during the write operation found by the present inventors are mainly source / drain regions SDMx, SDCx, SDSx that are n-type semiconductor regions, and p-wells for forming operating elements that are p-type semiconductor regions. This is due to the pn junction composed of PWx1. In the nonvolatile memory cell NVMa examined by the present inventors, a voltage is applied to both, and these pn junctions constitute a parasitic diode.

  Here, during the write operation, the operating unit source voltage Vs and the read drain voltage Vd, which are voltages applied to the operating element source / drain region SDMx and the selection element source / drain region SDSx, are equal, respectively. . Further, if the selection transistor QSx is in the on state, the potential of the shared source / drain region SDCx is equal to these. Therefore, hereinafter, the applied voltages to the equivalent source / drain regions SDMx, SDCx, and SDSx are collectively described as the operation unit source voltage Vs. In the following, for the sake of convenience, the potential on the p-type semiconductor (operation element forming p well PWx1) side viewed from the n-type semiconductor (each source / drain region SDMx, SDCx, SDSx) side, which is the forward voltage of the pn junction. Is a positive potential and is described as a pn junction potential difference ΔVpn. That is, pn junction potential difference ΔVpn = operating unit well voltage Vm−operating unit source voltage Vs.

  As described above, during the write operation, a voltage of −9 V is applied to both the operation unit well voltage Vm and the operation unit source voltage Vs. Therefore, the potential difference between pn junctions is generally ΔVpn = 0V. However, the operating unit well voltage Vm and the operating unit source voltage Vs are applied with different voltages during other operations even if the same voltage is applied as described above during writing. Therefore, power is supplied to these from another voltage source, and it has been found that a shift in power supply timing at this time brings about the following problems.

  FIG. 3 is a timing chart for comparing changes in the operating unit well voltage Vm and the operating unit source voltage Vs by the time time when a write operation is performed in the nonvolatile memory cell NVMa examined by the present inventors.

At time time _{= t 1 m,} operation unit well voltage Vm is stepped down to -9 V. Here, it is assumed that the operation unit source voltage Vs is stepped down and the operation unit source voltage Vs is decreased to −9 V at time time = t _{1 s} . At this time, during the difference time Δt ₁ (= t _1s −t _1m ), the potential difference ΔVpn between the pn junctions ΔVpn = −9 V between the operating element forming p well PWx1 and the operating element source / drain region SDMx, for example. This causes a potential difference of. This is a reverse voltage with respect to the pn junction.

  In the non-volatile memory cell NVMa examined by the present inventors, the reverse breakdown voltage of the pn junction is about −6V, and the breakdown voltage breakdown occurs when the potential difference ΔVpn = −9V between the pn junctions. That is, a reverse voltage higher than the breakdown voltage makes the avalanche effect and the Zener effect remarkable, and a large reverse current starts to flow rapidly. The reverse current generated parasitically in this manner causes a deterioration in the performance of the nonvolatile memory cell, for example, causing a latch-up phenomenon.

On the other hand, in a situation different from the above, the operating unit source voltage Vs is stepped down to −9 V at time time = t _2s . Here, it is assumed that the timing of step-down of the operation unit well voltage Vm is delayed and the operation unit well voltage Vm is decreased to −9 V at time time = t _{2 m} . At this time, a potential difference of pn junction potential difference ΔVpn = + 9V is generated during the difference time Δt ₂ (= t _2m −t _2s ). This is a forward voltage with respect to the pn junction. Therefore, the forward current of the pn junction flows from the operating element forming p well PWx1 to, for example, the operating element contact plug CPx2 through the operating element source / drain region SDMx.

  In the nonvolatile memory cell NVMa examined by the present inventors, for example, a large number of elements operating at +9 V or less are connected to the tip of the operation element contact plug CPx2. Therefore, the forward current generated parasitically as described above causes a malfunction, damage to other components, and the like, which deteriorates the reliability of the nonvolatile memory.

  Therefore, as a further study by the present inventors, the forward direction generated at the parasitic pn junction as described above even when the step-down timing shift between the operation unit source voltage Vs and the operation unit well voltage Vm occurs. Alternatively, an attempt was made to open the operating unit source voltage Vs and the read drain voltage Vd so that the reverse current does not adversely affect.

  In this regard, in an integrated circuit configured by connecting a large number of elements, it is difficult to physically and completely open a terminal connected to a specific element. turn into. In this state, the operating unit well voltage Vm = −9 V is received, and a depletion region spreads in the vicinity of the pn junction. The electric field of the operating element forming p well PWx1 is concentrated in the depletion region.

  Here, in the write operation described with reference to FIG. 2, the operating element gate is generated by the potential difference (18 V) between the operating element floating gate electrode GExM (+9 V) and the operating element forming p well PWx1 (−9 V). This is a method in which electrons e are FN tunneled from the inversion region immediately below the insulating film GIxM to the floating electrode FGx. At this time, as described above, when the electric field generated by the voltage supplied to the p-well PWx1 for forming the operating element is concentrated and relaxed in a place other than the inversion region, the floating gate electrode for the operating element viewed from the inversion region. The potential difference to GExM is significantly lower than 18V. That is, the inventors have clarified a problem that due to the above electric field relaxation, normal FN tunneling of electrons is not realized and a writing failure is caused. As a result, the reliability of the nonvolatile memory cell NVMa is impaired.

  These problems are mainly due to the fact that the same element is responsible for the write operation, read operation, and erase operation. More specifically, it is as follows.

  In the nonvolatile memory cell NVMa studied by the present inventors, a field effect transistor having a MIS structure is used as the operation element. Here, a source / drain region having a conductivity type opposite to that of the well is required for the read operation, and a power supply region having the same conductivity type as that of the well is required for the write operation. Therefore, it is impossible to make them the same in order to avoid timing deviations in power feeding because different conductivity types are required. Furthermore, even if the terminal connected to the parasitic pn junction is opened in order to prevent the adverse effect of the timing shift, writing failure due to electrolytic relaxation in the depletion region is caused. That is, the present inventors have clarified that it is difficult to solve the above problem at least in this structure in which the write operation element and the read operation element are the same element.

  In view of this, the present inventors studied a nonvolatile memory cell having a structure in which an element for writing / erasing operation is separated from an element for reading operation and provided in another well. The plan view is shown in FIG. 4, and a cross-sectional view taken along line x2-x2 of FIG. 4 is shown in FIG.

  Other nonvolatile memory cells NVMb investigated by the present inventors include an operation transistor QMx, a selection transistor QSx, and a configuration similar to the nonvolatile memory cell NVMa described with reference to FIGS. MIS capacitor Cx. In particular, the operation transistor QMx and the selection transistor QSx are formed in the same operation element formation p-well PWx1, and the MIS capacitor Cx is formed in the capacitor formation p-well PWx2. The p wells PWx1 and PWx2 are formed in the embedded n well DNWx in a state of being separated by the separation n well NW.

  In addition, a write element forming p well PWx3 is provided in the same embedded n well DNWx. A write element WDx is formed in the write element forming p well PWx3. This is formed separately from the operation transistor QMx for performing the read operation as a dedicated element for performing the write and erase operations.

  The write element WDx includes a write element floating gate electrode GExW in which the floating electrode FGx overlaps the write element forming p well PWx3 in a plan view. In addition, the write element gate insulating film GIxW is formed between the write element floating gate electrode GExW and the semiconductor substrate 1. Also, in plan view, the write element source region SWx, which is an n-type semiconductor region, and a p-type semiconductor are formed on the main surface S1 of the semiconductor substrate 1 located in a region sandwiching the write element floating gate electrode GExW. A write element well power supply region VSWx, which is a region, is included. Further, a write element contact plug CPx7 is electrically connected to the write element source region SWx via the silicide layer 4. A write well power supply contact plug CPx8 is electrically connected to the write element well power supply region VSWx via the silicide layer 4.

  As described above, the following advantages can be obtained by separating the write element WDx that performs the write operation from the operation transistor QMx that performs the read operation. That is, in the write element WDx, it is not necessary to form both source / drain regions like the operation transistor QMw, and at least one of the write element well power supply regions VSWx having the same conductivity type as the write element forming p well PWx3 is eliminated. And a power feeding mechanism to the write element forming p well PWx3. Further, during a write operation and an erase operation using the write element WDx, the same voltage is always applied to the write element source region SWx and the write element well power supply region VSWx. Therefore, the write element contact plug CPx7 and the write well power supply contact plug CPx8 may be connected in the upper layer so that the same voltage can be applied simultaneously. As a result, it is possible to eliminate the cause of lowering the reliability of the nonvolatile memory, such as operation failure and element destruction, due to a shift in power feeding timing that occurs during the write operation.

  However, according to the study by the present inventors, it is said that the nonvolatile memory cell NVMb having the configuration described with reference to FIGS. 4 and 5 is not suitable for higher integration and larger capacity that will be required in the future. This is because three wells are used as the configuration, and it can be said that the surface area is large compared to the case where the nonvolatile memory cell NVMa initially studied is configured by two wells.

  As described above, in consideration of the stability of operation, the non-volatile memory cell NVMb having a three-well structure in which the writing element and the reading element are separated is significant, and in consideration of the integration capability, the two-well structure. It can be said that the non-volatile memory cell NVMa is significant. That is, in the nonvolatile memory used for the LCD driver, in the technology examined by the present inventors, there is a trade-off relationship between the requirement for reliability and the requirement for higher integration without causing a decrease in reliability. It was found that it was difficult to improve the degree of integration.

  Next, the semiconductor device of the first embodiment will be described.

  In general, during the manufacturing process of a semiconductor device, a high-purity semiconductor material using, for example, single crystal silicon (Si) as a base material is handled in a state of a thin plate having a substantially planar shape called a wafer. Then, the main surface is divided into regions that will later become semiconductor chips, and a similar chip group is formed in a large number of chip regions to form a semiconductor chip having a semiconductor integrated circuit having a desired circuit function. To do.

  The nonvolatile memory exemplified in the first embodiment is formed in the same chip as the semiconductor chip forming the LCD driver. In the following, a region for forming a circuit composed of field effect transistors having various operating voltages, for example, constituting the LCD driver will be referred to as a main circuit formation region, and a region for forming a nonvolatile memory will be referred to as a nonvolatile memory region.

  FIG. 6 shows a plan view of one cell in the non-volatile memory cell NVM formed in the non-volatile memory region in the semiconductor device formed on the semiconductor chip exemplified in the first embodiment. is there. One cell represents an area for storing 1-bit unit information. In FIG. 6, for easy understanding of the configuration of the nonvolatile memory cell NVM, the semiconductor region is hatched and other insulating films, for example, are omitted. Hereinafter, the plan view is the same unless otherwise specified. FIG. 7 shows a cross-sectional view taken along line x3-x3 of FIG.

  The semiconductor substrate 1 constituting the semiconductor chip is formed of, for example, a p-type (second conductivity type) silicon single crystal. A p-type is a state in which a group III element such as boron (B) is contained in, for example, silicon composed of a group IV element, and a semiconductor material in which majority carriers are holes (also referred to as holes). Represents conductivity type. Hereinafter, the same applies to the p-type conductivity type. The semiconductor substrate 1 has a main surface (first main surface) S1 and a back surface (second main surface) (not shown) located opposite to each other along the thickness direction. FIG. 6 is a view of the semiconductor substrate 1 as viewed from the main surface S1 side in order to see the configuration of the nonvolatile memory cell NVM formed on the main surface S1, for example. In FIG. Is shown enlarged.

  A separation portion 2 is formed on the main surface S1 of the semiconductor substrate 1. Here, the isolation part 2 is a so-called STI (Shallow Trench Isolation) groove formed by embedding an insulating film made of silicon oxide or the like in a shallow groove formed on the main surface S1 of the semiconductor substrate 1, for example. It is assumed that it is a mold separation unit 2.

  A buried n-well (first semiconductor region) DNW, which is an n-type (first conductivity type) semiconductor region, is formed in the semiconductor substrate 1 from the main surface S1 to a desired depth. The n-type is, for example, a state of containing a group V element such as phosphorus (P) or arsenic (As) in silicon or the like made of a group IV element, and the conductivity of a semiconductor material in which majority carriers are electrons. Represents a type. Hereinafter, the same applies to the n-type conductivity type.

  The buried n-well DNW includes an operating element forming p well (second semiconductor region) PW1 which is a p-type semiconductor region, and a capacitor forming p well (third semiconductor region) PW2 which is also a p-type semiconductor region. Are formed in the embedded n-well DNW. These p wells PW1 and PW2 are formed so as to extend in the first direction X and to be aligned along the second direction Y intersecting the first direction X. The impurity concentrations of both p wells PW1 and PW2 are approximately the same, and are higher than the impurity concentration of the semiconductor substrate 1.

  On the outer periphery of the operating element formation p-well PW1 and the capacitor formation p-well PW2, the isolation part 2 is formed so as to surround them and to be shallower than the buried n-well DNW.

  An isolation n well NW, which is an n-type semiconductor region, is formed at the bottom of the isolation portion 2. The separation n-well is formed over a shallower position than the buried n-well DNW. The separation n-well NW has a mechanism (not shown) that allows electrical conduction from the outside, and can be set to a desired potential.

  With the above configuration, the operating element forming p well PW1 and the capacitor forming p well PW2 are arranged along the first direction X and aligned along the second direction Y so as to be embedded in the buried n well DNW. It is arranged so that it is included. Further, the operating element forming p well PW1 and the capacitor forming p well PW2 are arranged in a state of being electrically separated from each other by the separating portion 2 surrounding the outer periphery and the separating n well NW formed at the bottom thereof. ing.

  The non-volatile memory cell NVM exemplified in the first embodiment is arranged so as to planarly overlap with the operating element forming p well PW1 and the capacitor forming p well PW2, and has the following configuration.

  First, the non-volatile memory cell NVM is arranged so as to planarly overlap a part of the operating element forming p well PW1 and a part of the capacitor forming p well PW2 on the main surface S1 of the semiconductor substrate 1. The floating electrode FG is arranged. The floating electrode FG is made of a conductor film whose base material is, for example, polycrystalline silicon. Further, the floating electrode FG is arranged so as to be in a floating state that is not electrically connected to any other part. Thus, the floating electrode FG in a floating state plays a role of holding data in the nonvolatile memory cell NVM exemplified in the first embodiment.

  Here, for example, when a similar gate electrode in a general semiconductor device is formed, there is a step of forming a conductor film or the like in order to form a contact. In the first embodiment, the surface of the floating electrode FG may be covered with a protective insulating film PI such as a silicon oxide film. Thereby, it can protect from the formation process of a conductor film, etc., and can improve the insulation from other places.

  Secondly, the nonvolatile memory cell NVM has a write / erase element (data write / erase element) WD formed in the operating element formation p-well PW1. The write / erase element WD is an element mainly responsible for data write and erase operations in the nonvolatile memory cell NVM illustrated in the first embodiment.

  Third, the nonvolatile memory cell NVM includes a read transistor (read field effect transistor) QR formed in the operating element formation p well PW1. As will be described in detail later, the read transistor QR is a MIS type field effect transistor, and is an element mainly responsible for reading data in the nonvolatile memory cell NVM exemplified in the first embodiment.

  As described above, in the nonvolatile memory cell NVM exemplified in the first embodiment, the write / erase element WD responsible for writing and erasing data and the read transistor QR responsible for reading data are separated from each other. However, it is formed in one operating element forming p well PW1. As a result, the nonvolatile memory cell NVM according to the first embodiment is the same as the element responsible for writing / erasing in the nonvolatile memory cell NVMb examined by the present inventors described above with reference to FIGS. The p-well PWx3 for forming the writing element formed independently is not required. As a result, the area of the nonvolatile memory cell NVM can be reduced.

  Fourth, the nonvolatile memory cell NVM includes a selection transistor (selection field effect transistor) QS formed in the operating element formation p-well PW1. In a general memory device, memory cells are arranged in a regular array in a semiconductor chip. The selection transistor QS included in the nonvolatile memory cell NVM exemplified in the first embodiment has the above-described configuration in order to prevent interference with surrounding cells when selecting a desired nonvolatile memory cell NVM from the memory array. A selection transistor QS is arranged in each cell as a switch. Thereby, the reliability of the nonvolatile memory cell NVM exemplified in the first embodiment can be improved. In the first embodiment, it is assumed that the selection transistor QS is electrically connected in series to the reading transistor QR.

  Fifth, the nonvolatile memory cell NVM includes a MIS capacitor (capacitance element) C formed in the capacitor forming p-well PW2. The MIS capacitor C is a capacitive element (capacitor, capacitor, coupling capacitor) having a MIS structure, as will be described in detail later. In the nonvolatile memory cell NVM exemplified in the first embodiment, it is an element mainly responsible for improving the voltage supply efficiency to the write / erase element WD or the like.

  Hereinafter, the respective configurations of the first to fifth elements included in the nonvolatile memory cell NVM exemplified in the first embodiment will be described in detail.

  First, the floating electrode FG includes a write / erase element floating gate electrode (first floating gate electrode) GEW, a read element floating gate electrode (second floating gate electrode) GER, and a capacitor floating gate electrode (first floating gate electrode). 3 floating gate electrodes) GEC.

  Here, the write / erase element floating gate electrode GEW extends from the position of the floating electrode FG that overlaps a part of the operating element forming p well PW1 to a part of the capacitor forming p well PW2. , A portion arranged so as to extend in a second direction Y intersecting the first direction X.

  Further, the floating gate electrode GER for the read element extends from the position of the floating electrode FG that overlaps a part of the p well PW1 for forming the operating element to a part of the p well PW2 for forming the capacitor. This is a portion arranged so as to be spaced apart from the floating gate electrode GEW for the write / erase element. That is, the write / erase element floating gate electrode GEW and the read element floating gate electrode GER are separated from each other within the arrangement range of the operating element formation p-well PW1.

  The capacitor floating gate electrode GEC is a portion of the floating electrode FG that is disposed so as to overlap with a part of the capacitor forming p well PW2.

  Here, it is assumed that the width of the capacitor floating gate electrode GEC in the first direction X is larger than the width of the write / erase element floating gate electrode GEW and the read element floating gate electrode GER in the first direction X.

  As described above, the write / erase element floating gate electrode GEW, the read element floating gate electrode GER, and the capacitor floating gate electrode GEC are part of the floating electrode FG and are arranged in the same layer. And As will be described in detail later, as a basic component of the nonvolatile memory cell NVM exemplified in the first embodiment, this single layer of floating electrode FG is the top of the conductor film except for various wiring layers. The upper layer. Therefore, for example, the non-volatile memory cell NVM can be formed in the non-volatile memory region by the same process as the formation of the main circuit forming region such as field effect transistors having various operating voltages. As a result, a semiconductor device with high productivity and reliability can be realized.

  Second, the write / erase element WD includes a write / erase element floating gate electrode GEW which is a part of the floating electrode FG.

  The write / erase element WD has a write / erase element gate insulating film (first gate insulating film) GIW formed between the write / erase element floating gate electrode GEW and the semiconductor substrate 1. The write / erase element gate insulating film GIW is formed of, for example, a silicon oxide film.

  The write / erase element WD is sandwiched between the write / erase element floating gate electrode GEW and the read element floating gate electrode GER as viewed in a plane in the operating element formation p-well PW1. A shared source / drain region (fourth semiconductor region) SDC, which is an n-type semiconductor region, is formed on the main surface S1 of the semiconductor substrate 1 located in the region. It is assumed that the impurity concentration of the shared source / drain region SDC is higher than that of the buried n-well DNW and the separation n-well NW that are the same n-type semiconductor region.

  Here, the shared source / drain region SDC is a region that reaches the lower side of the floating gate electrode GEW for the write / erase element in a plan view, and the shared source / drain region SDC in a sectional view. It has an n-type extension region nx1 formed in a region shallower than itself. It is assumed that the impurity concentration of the n-type extension region nx1 is lower than the impurity concentration of the shared source / drain region SDC that is the same n-type semiconductor region. Hereinafter, the impurity concentration of the extension region which is an n-type semiconductor region is the same unless otherwise specified.

  The write / erase element WD is paired with the shared source / drain region SDC in plan view in the operating element formation p-well PW1, so that the write / erase element floating gate is formed. An operating element well power supply region (fifth semiconductor region) VSM, which is a p-type semiconductor region, is formed on the main surface S1 of the semiconductor substrate 1 located in a region sandwiching the electrode GEW. It is assumed that the impurity concentration of the operating element well power supply region VSM is higher than the impurity concentration of the operating element forming p well PW1 and the capacitor forming p well PW2, which are the same p-type semiconductor regions.

  Here, the operating element well power supply region VSM is a region reaching the lower side portion of the write / erase element floating gate electrode GEW in plan view, and in cross section, the operating element well power supply region VSM. The p-type extension region px1 is formed in a region shallower than the region VSM itself. It is assumed that the impurity concentration of the p-type extension region px1 is lower than the impurity concentration of the operating element well power supply region VSM which is the same p-type semiconductor region. Hereinafter, the impurity concentration of the extension region which is a p-type semiconductor region is the same unless otherwise specified.

  Here, the reason why the shared source / drain region SDC which is an n-type semiconductor region is formed in the write / erase element WD will be described below. In other words, the addition of the n-type shared source / drain region SDC facilitates the formation of the inversion layer under the floating gate electrode. Further, electrons are minority carriers in the p-type semiconductor region, whereas electrons are majority carriers in the n-type semiconductor region. Therefore, by providing the n-type shared source / drain region SDC, injected electrons can be easily supplied to the inversion layer. As a result, the effective coupling capacitance can be increased, so that the potential of the floating electrode FG can be controlled efficiently. Therefore, the data writing speed can be improved. Further, variation in data writing speed can be reduced.

  The above is the configuration of the write / erase element WD. The write / erase element WD includes a write / erase element floating gate electrode GEW as a conductor part (Metal), a write / erase element gate insulating film GIW as an insulator part, and a semiconductor part (Semiconductor). This is composed of a three-layer MIS structure of p-well PW1 for forming an operating element. In the first embodiment, the write / erase element floating gate electrode GEW serving as the upper electrode is in a floating state, and the operating element forming p well PW1 serving as the lower electrode is formed by the operating element well power supply region VSM. It has a mechanism to be fed. Detailed description of the operation and the like will be made later together with other configurations.

  Thirdly, the read transistor QR has a read element floating gate electrode GER which is a part of the floating electrode FG.

  Further, the read transistor QR has a read element gate insulating film (second gate insulating film) GIR formed between the read element floating gate electrode GER and the semiconductor substrate 1. It is assumed that the read element gate insulating film GIR is formed of, for example, a silicon oxide film.

  Further, the read transistor QR has a shared source / drain region SDC so as to be shared with the write / erase element WD.

  Here, the shared source / drain region SDC is a region reaching the lower side of the read element floating gate electrode GER as viewed in a plan view, and as viewed in cross-section, than the shared source / drain region SDC itself. Has an n-type extension region nx2 formed in a shallow region.

  Further, the read transistor QR is paired with the shared source / drain region SDC in plan view in the operating element formation p well PW1, thereby sandwiching the read element floating gate electrode GER. A read element source / drain region (sixth semiconductor region) SDR, which is an n-type semiconductor region, is formed on the main surface S1 of the semiconductor substrate 1 located in the region. The impurity concentration of the source / drain region SDR for the read element is assumed to be approximately the same as the impurity concentration of the shared source / drain region SDC.

  Here, as described above, the pair of source / drain regions SDC and SDR are formed so as to sandwich the read element floating gate electrode GER extending in the second direction Y. . Further, the shared source / drain region SDC is configured to be shared with the write / erase element WD. Therefore, the read transistor QR and the write / erase element WD are arranged side by side in the first direction X.

  The read element source / drain region SDR is a region reaching a lower side portion of the read element floating gate electrode GER in plan view, and in read section source / drain region for read element. It has an n-type extension region nx3 formed in a region shallower than the SDR itself.

  The above is the configuration of the reading transistor QR. The read transistor QR includes a read element floating gate electrode GER as a gate electrode, a read element gate insulating film GIR as a gate insulating film, a shared source / drain region SDC as a source or drain region, and a source or drain. This is a MIS type field effect transistor having a read element source / drain region SDR as a basic structure. In particular, it is an n-channel field effect transistor formed in a p-type operating element forming p-well PW1 and having n-type source / drain regions SDC, SDR. In the first embodiment, the read element floating gate electrode GER which is a gate electrode is in a floating state, and the shared source / drain region SDC which is one source / drain region has a specific power feeding mechanism. Absent. Detailed description of the operation and the like will be made later together with other configurations.

  Fourth, the selection transistor QS includes a selection element gate electrode GES formed so as to overlap with a part of the above-described operating element formation p well PW1. The selection element gate electrode GES is along the read element floating gate electrode GER in a region opposite to the read / write element floating gate electrode GEW with respect to the read element floating gate electrode GER in plan view. It is arranged like that. However, the selection element gate electrode GES does not reach a region overlapping the capacitor forming p-well in a plan view. Furthermore, the selection element gate electrode GES is not integrated with the floating electrode FG but is formed independently. The selection element gate electrode GES is made of a conductive film having, for example, polycrystalline silicon as a base material.

  The selection transistor QS has a selection element gate insulating film GIS formed between the selection element gate electrode GES and the semiconductor substrate 1. The selection element gate insulating film GIS is formed of, for example, a silicon oxide film.

  Further, the read element source / drain region SDR included in the read transistor QR is disposed up to a region reaching the lower side of the select element gate electrode GES in plan view. The selection transistor QS has the read element source / drain region SDR as a source or drain region in a form shared with the read transistor QR. With this configuration, the reading transistor QR and the selection transistor QS are electrically connected in series.

  Here, the read element source / drain region SDR is a region reaching a lower side portion of the selection element gate electrode GES in plan view, and in read section source / drain region for read element. It has an n-type extension region nx4 formed in a region shallower than the SDR itself.

  The selection transistor QS is paired with the read element source / drain region SDR as viewed in plan in the operating element formation p-well PW1, thereby forming the selection element gate electrode GES. A source / drain region for selection element SDS, which is an n-type semiconductor region, is formed on the main surface S1 of the semiconductor substrate 1 located in the sandwiched region. It is assumed that the impurity concentration of the source / drain region for select element SDS is approximately the same as the impurity concentration of the source / drain region for read element SDR.

  Here, the source / drain region SDS for the selection element is a region reaching the lateral lower portion of the gate electrode GES for the selection element when seen in a plan view. It has an n-type extension region nx5 formed in a region shallower than the SDS itself.

  The above is the configuration of the selection transistor QS. The selection transistor QS includes a selection element gate electrode GES as a gate electrode, a selection element gate insulating film GIS as a gate insulating film, a selection element source / drain region SDS as a source or drain region, and a source or drain This is a MIS field effect transistor having a shared source / drain region SDC as a drain region as a basic configuration. In the first embodiment, the shared source / drain region SDC which is one of the source / drain regions does not have a specific power supply mechanism. Detailed description of the operation and the like will be made later together with other configurations.

  Fifth, the MIS capacitor C has a capacitor floating gate electrode GEC which is a part of the floating electrode FG.

  The MIS capacitor C includes a capacitor gate insulating film (third gate insulating film) GIC formed between the capacitor floating gate electrode GEC and the semiconductor substrate 1. It is assumed that the capacitor gate insulating film GIC is formed of, for example, a silicon oxide film.

  The MIS capacitor C is a p-type formed on the first main surface S1 of the semiconductor substrate 1 located in a region sandwiching the capacitor floating gate electrode GEC in plan view in the capacitor forming p well PW2. Capacitor well power supply region (seventh semiconductor region) VSC and capacitor source region (eighth semiconductor region) SC which is an n-type semiconductor region. The impurity concentration of the capacitor well power supply region VSC is assumed to be approximately the same as the impurity concentration of the operating element well power supply region VSM, which is the same p-type semiconductor region. In addition, the impurity concentration of the capacitor source region SC is approximately the same as that of the shared source / drain region SDC that is the same n-type semiconductor region.

  Here, the above-described capacitor well power supply region VSC is a region reaching the lower side of the capacitor floating gate electrode GEC in plan view, and is more than the capacitor well power supply region VSC itself in cross section. A p-type extension region px2 is formed in the shallow region. Further, the capacitor source region SC is a region reaching the lower side of the capacitor floating gate electrode GEC in plan view, and is formed in a region shallower than the capacitor source region SC itself in cross section. In addition, it has an n-type extension region nx6.

  Here, the reason why the capacitor source region SC which is an n-type semiconductor region is formed in the MIS capacitor C will be described below. In the erase operation, by adding the n-type capacitor source region SC, electrons can be smoothly supplied directly under the capacitor gate insulating film GIC. For this reason, since the inversion layer under the floating electrode FG can be formed quickly, the p-type capacitor forming p-well PW2 can be quickly fixed to −9V. As a result, the effective coupling capacitance can be increased, so that the potential of the floating electrode FG can be controlled efficiently. Therefore, the data erasing speed can be improved. In addition, variations in data erasing speed can be reduced.

  The above is the configuration of the MIS capacitor C. The MIS capacitor C is a capacitive element having a three-layer MIS structure of a capacitor floating gate electrode GEC as a conductor portion, a capacitor gate insulating film GIC as an insulating portion, and a capacitor forming p-well PW2 as a semiconductor portion. is there. In the first embodiment, the capacitor floating gate electrode GEC that is the upper electrode is in a floating state, and the capacitor forming p-well PW2 that is the lower electrode has a mechanism that is fed by the capacitor well feeding region VSC. Have. Detailed description of the operation and the like will be made later together with other configurations.

  Here, as described above, the MIS capacitor C is formed in the capacitor forming p-well PW2 extending in the first direction X. Further, as described above, the operating element formation p-well PW1 is arranged along the second direction Y so as to be along the first direction X with the capacitor formation p-well PW2. Accordingly, the MIS capacitor C is aligned with the write / erase element WD, the read transistor QR, and the selection transistor QS formed in the operating element formation p-well PW1 along the first direction X, and They are arranged along the two directions Y.

  The basic configuration of the nonvolatile memory cell NVM exemplified in the first embodiment is as described above. In addition to this, it has the following configuration.

  On the side walls of the gate electrodes GEW, GER, GES, and GEC, side wall spacers 3 made of an insulating film mainly composed of, for example, silicon oxide are formed. The side wall spacers 3 are formed for the purpose of insulation from wirings that are not intended to conduct with the respective gate electrodes GEW, GER, GES, and GEC.

  Further, on the surface of each well power supply region VSM, VSC, each source or drain region SDC, SDR, SDS, SC, which is a p or n type semiconductor region, and the gate electrode GES for selection elements made of polycrystalline silicon. A silicide layer 4 is formed. The silicide layer 4 is made of a conductor film such as cobalt silicide which is a compound of cobalt (Co) and silicon, for example, and is formed for the purpose of ohmic connection with an external electrical contact.

  On the main surface S1 of the semiconductor substrate 1 on which the nonvolatile memory cell NVM having the above configuration is formed, the interlayer insulating film 5 on which the interlayer insulating film 5 is formed includes an insulating film 5a made of, for example, silicon nitride, and the like. , And an insulating film 5b made of, for example, silicon oxide. In this way, the use of two different insulating films is useful, for example, when forming a contact hole leading to an arbitrary portion of the main surface S1 of the semiconductor substrate 1 under the interlayer insulating film 5. In other words, the so-called SAC (Self Align Contact) technique is applied, which makes use of the difference in etching rate between the two insulating films 5a and 5b to stop the etching in a self-aligned manner and enable more precise processing. Can do.

  Further, the nonvolatile memory cell NVM exemplified in the first embodiment has a contact hole CH formed in the interlayer insulating film 5 by the above SAC technique. Each of the contact plugs CP1 to CP6 electrically connected through the silicide layer 4 to a desired region constituting the nonvolatile memory NVM is constituted by the conductor portion 6 embedded therein. Details will be described below.

  First, it has a common part power supply contact plug (first conductive part) CP1 electrically connected to the shared source / drain region SDC. The shared portion power supply contact plug CP1 is electrically connected to the shared source / drain region SDC, thereby supplying the same potential to the n-type extension regions nx1 and nx2, which are regions joined by the same n-type semiconductor region. can do.

  Further, it has an operation well power supply contact plug (second conductive portion) CP2 electrically connected to the operation element well power supply region VSM. The operating well power supply contact plug CP2 is electrically connected to the operating element well power supply region VSM, thereby joining the same p type semiconductor region, the p type extension region px1, and the operating element formation The same potential can be supplied to the p-well PW1.

  Here, in the nonvolatile memory cell NVM exemplified in the first embodiment, the common part power supply contact plug CP1 present at a plurality of locations in the same cell and the operation well power supply contact present at a plurality of locations. The plugs CP2 are all connected to each other in the upper layer and are supplied with power simultaneously.

  Further, it has a read contact plug (third conductive portion) CP3 that is electrically connected to the source / drain region SDS for the selection element. The read contact plug CP3 supplies the same potential to the n-type extension region nx5, which is a region joined in the same n-type semiconductor region, by being electrically connected to the source / drain region SDS for the selection element. Can do.

  Here, consider the case where power is supplied to the read element source / drain region SDR, which is one of the pair of source / drain regions in the read transistor QR. In the first embodiment, the read element source / drain region SDR is also a source or drain region of the selection transistor QS. Therefore, by setting the selection transistor QS to the on state, substantially the same potential as that of the selection element source / drain region SDS can be supplied to the read element source / drain region SDR. That is, in the first embodiment, when the selection transistor QS is in the on state, the read contact plug CP3 is electrically connected to the read element source / drain region SDR.

  The capacitor well power supply contact plug (fourth conductive portion) CP4 is electrically connected to the capacitor well power supply region VSC. The capacitor well power supply contact plug CP4 is electrically connected to the capacitor well power supply region VSC, so that a p-type extension region px2 and a capacitor formation p-well PW2 are regions that are joined in the same p-type semiconductor region. In addition, the same potential can be supplied.

  Further, the capacitor contact plug (fifth conductive portion) CP5 is electrically connected to the capacitor source region SC. The capacitor contact plug CP5 can be supplied to the n-type extension region nx6, which is a region joined by the same n-type semiconductor region, by being electrically connected to the capacitor source region SC.

  Here, in the nonvolatile memory cell NVM exemplified in the first embodiment, the above-described capacitor well power supply contact plug CP4 present at a plurality of locations in the same cell and the capacitor contact plug CP5 present at a plurality of locations. Are all connected to each other in the upper layer, and are fed simultaneously.

  Further, a selection gate contact plug CP6 electrically connected to the selection element gate electrode GES is provided. The selection gate contact plug CP6 is electrically connected to the selection element gate electrode GES, whereby a gate voltage can be applied to the selection transistor QS.

  In each of the above contact plugs CP1 to CP6, the same ones present at a plurality of locations in the same cell are all connected to each other in the upper layer and are supplied with power simultaneously.

  In the following, the verification by the present inventors regarding the cell area of the nonvolatile memory cell NVM having the configuration exemplified above in the first embodiment will be described.

  The nonvolatile memory cell NVM exemplified in the first embodiment includes a write / erase element WD, a read transistor QR, a select transistor QS, and a MIS capacitor C. The above configuration is the same as that of the nonvolatile memory cell NVMb having the configuration described with reference to FIGS. 4 and 5 studied by the present inventors. Therefore, it is expected that the problem in the write operation described with reference to FIG. 3 seen in the nonvolatile memory cell NVMa having the configuration described with reference to FIGS. . The verification of the memory operation will be described in detail below.

  Here, as described with reference to FIG. 4, in the nonvolatile memory cell NVMb examined by the present inventors, the write / erase element WD, which is a separate element in order to exclusively handle the write / read operation, is provided. In another well (the writing element forming p well PWx3). The write element forming p well PWx3 is formed in the nonvolatile memory cell NVMb so as to be added in the direction along the second direction Y.

  On the other hand, in the nonvolatile memory NVM exemplified in the first embodiment, the write / erase element WD is arranged along the first direction X in the read transistor QR and the same operating element formation p well PW1. In this way it is formed. Accordingly, a new well or a new element is not added to the second direction Y, which is a part of the floating electrode FG and the write / erase element floating gate electrode GEW extends, and is non-volatile. The area of the memory cell NVM can be reduced.

  However, by using the write / erase element WD as a separate element, the write / erase element WD is simply formed in the same well in the nonvolatile memory cell NVM of the first embodiment in which the number of elements is increased due to the configuration. Only by doing so, the area in the first direction X increases.

  Such a technical problem is overcome in the nonvolatile memory cell NVM exemplified in the first embodiment as follows. That is, by sharing a semiconductor region that can be regarded as functionally identical within a range in which normal memory operation can be realized, the influence of an increase in area due to an increase in the number of elements is offset.

  Specifically, the write / erase element WD and the read transistor QR are arranged along the first direction X in the operating element formation p-well PW1, and both elements are a source or a drain. The region is shared as a shared source / drain region SDC. Further, a region for supplying power to the semiconductor layer and a region for supplying power to the operating element formation p-well PW1 necessary for the operation of the write / erase element WD are shared as the operating element well power supply region VSM. ing. As a result, in the nonvolatile memory cell NVM illustrated in the first embodiment, the combined width of the write / erase element WD and the read transistor QR in the first direction X is smaller than the width of the MIS capacitor C. can do. Therefore, an increase in the cell area in the first direction X can be avoided.

  Here, as described above, in order to improve the reliability of the memory operation, the nonvolatile memory cell NVM exemplified in the first embodiment uses the selection transistor QS. Since the selection transistor QS is electrically connected in series to the read transistor QR, the selection transistor QS is formed in the operating element formation p-well PW1. Thereby, there is a concern about an increase in the area of the nonvolatile memory cell NVM in the first direction X. In contrast, in the first embodiment, as described above, in the first direction X, the combined width of the write / erase element WD and the read transistor QR is made smaller than the width of the MIS capacitor C. Yes. As a result, even in the operating element forming p well PW1 including the selection transistor QS, the width in the first direction X can be the same as or smaller than that of the capacitor forming p well PW2. Therefore, an increase in the cell area in the first direction X can be avoided.

  As a result, the cell area of the non-volatile memory cell NVM illustrated in the first embodiment is the same as that of the non-volatile memory cell NVMa having a small cell area, which has been previously examined by the present inventors and described with reference to FIG. It can be about the same. Further, the non-volatile memory cell NVMb which is examined later and described with reference to FIG. 4 and having a normal operation has the following effect. It can be reduced to about 2/3 in the two directions Y.

  Therefore, in the nonvolatile memory NVM that can reduce the area by the configuration exemplified in the first embodiment, is it possible to perform an operation without a problem at the time of writing as in the nonvolatile memory cell NVMb examined by the present inventors? The present inventors verified.

  Subsequently, as shown in FIG. 7, the voltage applied to the common part power supply contact plug CP1 and the operation well power supply contact plug CP2 is the operating part supply voltage Vp, and the voltage applied to the read contact plug CP3 is the read drain voltage Vd. In addition, voltages applied to the capacitor well power supply contact plug CP4 and the capacitor contact plug CP5 are represented as a capacitor portion applied voltage Vc, respectively. Hereinafter, the accumulation of charges in the MIS capacitor C, the potential generated in the floating electrode FG, the electric field applied to the write / erase element WD, the behavior of electrons accumulated in the floating electrode FG due to FN tunneling, and the like will be described above. Since it is the same as that described in the nonvolatile memory cell NVMa previously examined by the inventors, detailed description thereof is omitted.

  First, read and erase operations will be described, which have no problem in the nonvolatile memory cell NVMa previously examined by the present inventors.

  As shown in FIG. 8, at the time of the read operation, for example, the operation unit supply voltage Vp = 0V, the read drain voltage Vd = 1V, and the capacitor unit applied voltage Vc = + 3V. Here, when the selection transistor QS is in the ON state, a voltage substantially equal to the read drain voltage Vd is also applied to the read element source / drain region SDR. Therefore, the read transistor QR has a source that varies depending on the potential of the floating gate electrode GER for the read element serving as a gate electrode, with the shared source / drain region SDC of 0V as the source and the source / drain region SDR for + 1V as the drain. / Drain Ids is generated.

  Here, for the same reason as the description regarding the read operation in the nonvolatile memory cell NVMa previously examined by the present inventors, the charge accumulation state of the read element floating gate electrode GER which is a part of the floating electrode FG is the data write It changes depending on the presence or absence. That is, the threshold voltage of the reading transistor QR changes depending on whether data is written. In particular, the reading transistor QR is an n-channel transistor. Therefore, in a state where the write operation is received, electrons that are negative charges are accumulated in the read element floating gate electrode GER, and the threshold voltage is increased. Since the source / drain current Ids varies significantly depending on the level of the gate potential with respect to the threshold voltage, the charge accumulation state, that is, the data retention state, can be determined and read based on the difference in the source / drain current Ids value.

  As shown in FIG. 9, at the time of the erase operation, for example, the operating unit supply voltage Vp = + 9V, the read drain voltage Vd is in an open state, and the capacitor unit applied voltage Vc = −9V. In the write / erase element WD, a voltage of −9 V is applied to the floating gate electrode GEW for the write / erase element by supplying power to the MIS capacitor C, and an operating element is formed by supplying power to the well power supply region VSM for operating element. A voltage of +9 V is applied to the p-well PW1. Accordingly, the electrons e accumulated in the floating electrode FG receive energy corresponding to a potential difference of 18 V toward the operating element formation p-well PW1 in the write / erase element floating gate electrode GEW. As a result, the electrons e FN tunnel the write / erase element gate insulating film GIW and are extracted to the operating element formation p-well PW1, thereby erasing the data holding state.

  Here, the p-type element forming p-well PW1 and the n-type shared source / drain region SDC joined thereto are boosted simultaneously by the operating unit supply voltage Vp. Therefore, there is no influence of the parasitic current at the pn junction. Similarly, the n-type selection element source / drain region SDS joined to the p-type operation element forming p well PW1 has an independent power feeding mechanism, but is also in an open state. There is no effect of parasitic current. Similarly, the n-type read element source / drain region SDR joined to the p-type element formation p-well PW1 has a selection element source / drain region SDR having substantially the same potential even when the selection transistor QS is on. Since the drain region SDS is in an open state, the pn junction is not affected by the parasitic current.

  Here, the nonvolatile memory cell NVMa previously examined by the present inventors has a problem of impairing reliability during a write operation as described with reference to FIG. Hereinafter, a write operation of the nonvolatile memory cell NVM exemplified in the first embodiment will be described with reference to FIG.

  During the write operation, the operating unit supply voltage Vp = −9 V, the read drain voltage Vd is in an open state, and the capacitor unit applied voltage Vc = + 9 V.

  In the write / erase element WD, the write / erase element floating gate electrode GEW is biased to +9 V by supplying power to the MIS capacitor C part. As a result, the inversion layer IL is formed in the operating element formation p well PW1 under the gate insulating film GIW for the write / erase element. Further, the power supply to the operating element well power supply region VSM biases the operating element formation p-well PW1 to −9V. Therefore, the electrons e generated in the inversion layer IL receive energy corresponding to a potential difference of 18 V, and FN tunnel the write / erase element gate insulating film GIW and are injected into the write / erase element floating gate electrode GEW. At this time, electrons e are lubricated to the inversion layer IL through the n-type extension region nx1 by the shared source / drain region SDC similarly biased to −9V. Thereby, charges can be accumulated in the floating electrode FG, that is, data can be written.

  Here, the p-type operating element forming p well PW1 and the n-type shared source / drain region SDC joined thereto are simultaneously stepped down by the operating unit supply voltage Vp. Therefore, there is no influence of the parasitic current at the pn junction. Similarly, the n-type selection element source / drain region SDS joined to the p-type operation element forming p well PW1 has an independent power feeding mechanism, but is also in an open state. There is no effect of parasitic current. Similarly, the n-type read element source / drain region SDR joined to the p-type operating element forming p well PW1 has a source for the select element that has substantially the same potential even when the select transistor QS is in the ON state. Since the / drain region SDS is in an open state, there is no influence of the parasitic current even in the pn junction.

  At this time, as described in the nonvolatile memory cell NVMa previously examined by the present inventors, a depletion layer that is parasitically generated in the p-type region even when the bias of the n-type region related to the pn junction is opened. Due to the electric field relaxation in the DL, the potential difference necessary for the FN tunneling cannot be given to the electrons e of the inversion layer IL, and there is a problem that writing failure occurs.

  In this regard, in the nonvolatile memory cell NVM exemplified in the first embodiment, the n-type region that is open is read when the source / drain region SDS for the selection element or the selection transistor QS is turned on. This is an element source / drain region SDR. These are not structural elements of the writing / erasing element WD that accumulates electric charges in the floating electrode FG using FN tunneling of electrons e at the time of writing, but are separated from each other in structure. Therefore, even if the depletion layer DL is generated in the p-type region joined to the n-type region in the open state, the write operation in the write / erase element WD is hardly affected. As a result, it is possible to prevent the occurrence of writing failure.

  The above effect is due to the fact that the elements responsible for the read operation and the write / erase operation are different elements.

  First, an element that is exclusively responsible for write / erase operations does not need a function as a transistor, and does not need a pair of n-type semiconductor regions that have different bias conditions like the source / drain regions. Therefore, by making the element responsible for reading that requires a transistor function a separate element, the element responsible for writing can collectively supply the same potential to the electron supply layer and the well power supply layer to the inversion region. As a result, it is possible to prevent the influence of the parasitic pn junction due to the shift of the feeding timing.

  In addition, it is desirable that a device exclusively responsible for reading does not require a bias at the time of writing / erasing operation, and a parasitic pn junction is opened. Here, when the element responsible for reading is a separate element, the element responsible for writing can prevent the occurrence of a depletion layer DL that causes a writing failure due to electric field relaxation. As a result, a highly reliable nonvolatile memory cell NVM can be realized.

  As described above, according to the nonvolatile memory cell NVM having the configuration exemplified in the first embodiment, a write operation can be realized without causing element destruction due to a parasitic pn junction current or a write failure. . As a result, the degree of integration can be improved without reducing the reliability of the nonvolatile memory by the technique exemplified in the first embodiment.

(Embodiment 2)
In the first embodiment, the configuration of a single nonvolatile memory cell NVM that records 1-bit information is exemplified. In an actual memory circuit, such memory cells are arranged in an array and are connected to each other to form a non-volatile memory that records multi-bit information. In the second embodiment, a memory circuit in which the nonvolatile memory cells NVM exemplified in the first embodiment are arranged in an array is illustrated. The description of FIGS. 13 to 25 describes the write operation and erase operation of the nonvolatile memory cell NVM in the second embodiment. At this time, if the selection transistor QS is in the ON state, the read contact plug CP3 may be equivalently connected to the read element source / drain region SDR. Accordingly, in the description of FIGS. 13 to 25, the selection transistor QS is assumed to be in an on state, and the description is omitted.

  FIG. 11 shows a plan view of the single nonvolatile memory cell NVM exemplified in the first embodiment to describe the power supply method to the nonvolatile memory cell NVM exemplified in the second embodiment. Is.

  First, the shared source / drain region SDC and the operating element well power supply region VSM included in the write / erase element WD of the nonvolatile memory cell NVM have bit lines (bit lines, data) extending in the second direction Y. BL (also referred to as a line or a data line) is electrically connected. In other words, the bit line BL is electrically connected to the shared portion power supply contact plug CP1 and the operation well power supply contact plug CP2, and can supply power thereto.

  By comparison with the nonvolatile memory cell NVM described with reference to FIGS. 6 and 7 in the first embodiment, the operating unit supply voltage Vp is applied to the bit line BL.

  Second, in the read element source / drain region SDR included in the read transistor QR of the nonvolatile memory cell NVM, the read bit line rBL extending in the second direction Y is electrically connected via the selection transistor QS. Connected. That is, the read bit line rBL is electrically connected to the read contact plug CP3 and can supply power thereto. In the read operation, the voltage supplied to the read bit line rBL is supplied to the read element source / drain region SDR only from the bit in which the selection transistor QS is turned on by the control line (or control line) SL. Is done.

  In comparison with the nonvolatile memory cell NVM described with reference to FIGS. 6 and 7 in the first embodiment, the read drain voltage Vd is applied to the read bit line rBL.

  Third, a word line (also referred to as a word line) WL extending in the first direction X is electrically connected to the capacitor well power supply region VSC and the capacitor source region SC of the MIS capacitor C of the nonvolatile memory cell NVM. It is connected to the. That is, the word line WL is electrically connected to the capacitor well power supply contact plug CP4 and the capacitor contact plug CP5 and can supply power thereto.

  By comparison with the nonvolatile memory cell NVM described with reference to FIGS. 6 and 7 in the first embodiment, the capacitor portion applied voltage Vc is applied to the word line WL.

  As shown in FIG. 12, in the actual memory array Mem, for example, nonvolatile memory cells NVM11, NVM12, NVM13, NVM14, etc. are arranged in the same row in the first direction X, for example, nonvolatile memory cells NVM11, NVM21, NVM31. Are arranged in the same row in the second direction Y. The memory array Mem exemplified in the second embodiment is assumed to be configured by the array arrangement as described above.

  Non-volatile memory cells NVM11 to NVM14, for example, arranged in the same row are connected by the same word line WL10. Further, for example, the non-volatile memories NVM11 to NVM31 arranged in the same column are connected by the same bit line BL01 or the same read bit line rBL01. An arbitrary nonvolatile memory cell NVM can be selected by designating one set of either the bit line BL or the read bit line rBL and the word line WL.

  In the second embodiment, for example, a case where the write operation is performed on the non-volatile memory cell NVM 22 hatched in FIG. 12 is illustrated. FIG. 13 shows a cross section of the MIS capacitor C, the read transistor QR, and the write / erase element WD in the nonvolatile memory cell NVM22, and the bias state to them. Hereinafter, it will be used in conjunction with FIG. 12 to explain the write operation.

  In order to perform a write operation on the nonvolatile memory cell NVM22, + 9V is applied to the word line WL20 and −9V is applied to the bit line BL02. Here, as described with reference to FIGS. 9 and 10 in the first embodiment, in the nonvolatile memory cell NVM, the difference between the capacitor unit applied voltage Vc and the operating unit supply voltage Vp is the write / This is a potential difference generated between the write / erase element floating gate electrode GEW of the erase element WD and the operating element formation p-well PW1. That is, in the second embodiment, the potential difference between the bit line and the word line conducted to the cell corresponds to this.

  Therefore, in the nonvolatile memory cell NVM22, a potential difference of about 18 V is generated between the write / erase element floating gate electrode GEW of the write / erase element WD and the operating element formation p-well PW1. This is the same bias condition as the write operation to the nonvolatile memory cell NVM described with reference to FIG. 10 in the first embodiment, and the write operation is performed.

  That is, in the nonvolatile memory cell NVM22, electrons e are injected into the floating electrode FG from the inversion layer IL immediately below the write / erase element gate insulating film GIW by FN tunneling that receives the above-described potential difference. As a result, the threshold voltage of the read transistor QR increases.

  FIG. 14 is a graph showing a change in the threshold voltage of the read transistor QR with respect to the write time. In the figure, the characteristic ex1 indicates the characteristic of the nonvolatile memory cell NVM22 that has undergone the above write operation. It can be seen that in the nonvolatile memory cell NVM22 which is a writing cell, electrons are injected into the floating electrode FG as the writing time elapses, and the threshold voltage of the reading transistor QR increases. As described with reference to FIG. 8 in the first embodiment, the data holding state is determined using this difference in threshold voltage.

  Here, in the second embodiment, a cell that does not receive the bias condition necessary for the write operation in the memory array Mem will be considered.

  For example, the non-volatile memory cells NVM11, NVM13, NVM14, NVM31, NVM33, and NVM34 are not electrically connected to both the −9V bit line BL02 and the + 9V word line WL20, and are not affected by any effect such as charge movement. It doesn't reach.

  On the other hand, attention is focused on a cell that receives power from either the bit line BL02 or the word line WL20.

  First, the non-volatile memory cells NVM12, NVM32, etc. in FIG. 12 are electrically connected to the −9V bit line BL02 although they are disconnected from the + 9V word line WL20. Therefore, the nonvolatile memory cells NVM12, NVM32, and the like are affected as follows by the power supply from the bit line BL02.

  FIG. 15 shows a cross-sectional view of, for example, the nonvolatile memory cell NVM12 connected to the bit line BL02. Under the bias conditions as described above, a voltage of −9 V is applied to the operating element forming p well PW1, and the writing / erasing element floating gate electrode GEW of the writing / erasing element WD and the operating element forming p well PW1. Therefore, a potential difference of about 9V is generated.

  This potential difference of 9 V is not high enough to allow the electrons e of the inversion layer IL to be smoothly injected into the write / erase element floating gate electrode GEW by FN tunneling as in the write operation (18 V). Not equivalent. However, FN tunneling of electrons e does not completely occur at a potential difference of 9V. Therefore, the electrons injected into the floating electrode FG gradually increase as the writing time elapses.

  Again in FIG. 14, what is indicated as a characteristic ex2 in the figure is the characteristic of the nonvolatile memory cell NVM12 that is supplied with power from the bit line BL02. As the write time elapses, the threshold voltage of the read transistor QR increases. This is due to accumulation of electrons injected into the floating electrode FG by FN tunneling. However, since the potential difference due to only the bit line BL02 is 9 V, which is smaller than that in the normal write operation, the threshold voltage rises and is saturated. Is also small.

  However, in the nonvolatile memory cell NVM12 that is not selected as a write target, an increase in the threshold voltage as described above has a possibility of erroneous writing. As described above, an increase in the threshold voltage of the read transistor QR in the nonvolatile memory cells NVM12, NVM32, etc., which is not originally a target of writing, but is affected by the bit line BL02 column supplied with power, may be disturbed. Called. In particular, the disturb phenomenon that occurs as a result of the power supply to the operating element formation p-well PW1 as described above is referred to as a well disturb (or data disturb) phenomenon.

  Secondly, the nonvolatile memory cells NVM21, NVM23, NVM24, etc. in FIG. 12 are electrically connected to the + 9V word line WL20, although they are disconnected from the −9V bit line BL02. Therefore, for example, as shown in FIG. 16 showing a cross-section of the nonvolatile memory cell NVM24, FN tunneling is caused by the potential difference generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1. The disturb phenomenon occurs due to the electrons e.

  However, the potential difference in this case is generated in the region as follows. First, +9 V of the word line WL20 is applied to the capacitor forming p-well PW2. In response to this, in the capacitor floating gate electrode GEC opposed via the capacitor gate insulating film GIC, charge movement occurs so as to have a negative potential corresponding to the positive potential of the capacitor forming p well PW2. In the floating electrode FG including the capacitor floating gate electrode GEC, the write / erase element floating gate electrode GEW which is a part of the floating electrode FG includes a capacitor floating gate electrode in order to preserve the original charge state. A positive charge corresponding to the negative charge moved to the GEC is charged. The potential difference generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1 is due to this positive charge. Therefore, a voltage drop occurs between the above paths, and the potential difference generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1 is applied to the capacitor formation p-well PW2. Compared to the + 9V applied.

  Here, in FIG. 14 again, what is indicated as the characteristic ex3 in the drawing is the characteristic of the nonvolatile memory cell NVM24 that is supplied with power from the word line WL20. As the writing time elapses, the disturb phenomenon occurs. However, the degree is smaller than the characteristic ex2 representing the well disturb phenomenon caused by the bit line BL02. As described above, an erroneous write phenomenon in the nonvolatile memory cells NVM21, NVM23, NVM24, etc., which is not originally a target of writing, but occurs due to the influence of the supplied word line WL20 is expressed as word disturb or the like.

  As described above, when the disturbed cell is used as it is, the threshold voltage of the reading transistor is in the writing state even though the cell has not been subjected to the writing operation due to repeated writing to the surrounding cells. May become equivalent. This means that there is a possibility of erroneous writing.

  In a memory circuit or the like, an applied voltage may be lowered by a scaling law because of a demand for reducing an element area for high integration. At this time, as described above, if a memory cell whose threshold voltage has increased due to a disturbance even though no writing has been performed is included, a margin from the threshold voltage of the memory cell to which writing has been performed normally is included. Becomes smaller. This has the potential to limit scaling.

  Therefore, in the memory array Mem composed of the nonvolatile memory cells NVM exemplified in the second embodiment, it is desirable not to cause an increase in the threshold voltage due to the disturb. Hereinafter, a technique capable of avoiding disturbance even in the nonvolatile memory cell NVM connected to either the bit line BL or the word line WL biased for writing will be described.

  FIG. 17 is a plan view showing a write state to the memory array Mem exemplified in the second embodiment. Normally, when writing to the memory array Mem, −9V is applied to a plurality of bit lines BL02, BL04, BL07, BL09 and the like, and + 9V is simultaneously applied to one word line WL40 and the like. As a result, the nonvolatile memory cells NVM42, NVM44, NVM47, NVM49, etc. connected to the biased bit lines BL02, BL04, BL07, BL09 and the word line WL40 undergo a write operation. Note that the number of bit lines and word lines to be biased may be plural, singular, or a combination thereof.

  At this time, as described with reference to FIGS. 14 and 15 and the like, the bit lines BL02, BL04, BL07, and BL09 biased to −9V are connected to the word line WL40 biased to + 9V. Non-volatile memory cells NVM02, NVM04, NVM07, and NVM09 that are not connected to each other cause well disturb.

  Further, as described with reference to FIGS. 14 and 16, the bit lines BL02, BL04, BL07, and BL09 that are connected to the word line WL40 biased to + 9V and biased to −9V Non-volatile memory cells NVM 40 that are not connected cause word disturb.

  In the second embodiment, in order to prevent the above-described disturbance, a specific voltage is applied to so-called unselected bit lines BL and word lines WL that are not used for cell selection and are not normally biased. The technique to apply is illustrated.

  First, in the word line WL, a voltage of −3 V is applied to the word line WL60, for example, other than the selected word line WL40 biased to + 9V. Here, FIG. 18 shows a cross-sectional view of the main part of the nonvolatile memory cell NVM64 as an example of the memory cell that is subject to well disturb, which receives the −3 V bias of the word line WL60. FIG. 19 shows the change of the threshold voltage in the nonvolatile memory cell NVM64 with respect to the writing time. In the drawing, the curve indicated by the characteristic ex4 is the characteristic of the nonvolatile memory cell NVM64.

  In the write / erase element WD, a potential difference generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1 is a difference between voltages applied to the bit line BL04 and the word line WL60. Therefore, in the above-described nonvolatile memory cell NVM64, the voltage is about 6V. Therefore, compared with the state of FIG. 14, the injection of electrons in the write / erase element WD is reduced, and an increase in threshold voltage is suppressed. That is, as described above, well disturb can be alleviated by applying a voltage of about −3 V to a memory cell that does not require the bias of the word line WL for the write operation. As a result, the reliability of the nonvolatile memory can be improved.

  Here, the technique of applying a bias of −3 V to the word line WL60 to alleviate the well disturb of the nonvolatile memory cell NVM64 has been described as an example. On the other hand, except for the word line WL40 to which a bias of +9 V for the write operation is applied, the same technique can be applied to alleviate the well disturb of the nonvolatile memory cells NVM02, NVM04, NVM07, and NVM09.

  Also, the effect can be mitigated by the same technique in the nonvolatile memory cell NVM40 that causes word disturb.

  Again, as shown in FIG. 17, in the non-volatile memory cell NVM 40 that causes word disturb, in order to relax the + 9V voltage caused by the word line 40, the bit lines BL01, BL03, BL05, BL06, which are not write targets, respectively. A positive voltage of +3 V is applied to BL08 and the like. Thereby, word disturb can be relieved.

  Here, in the above-described technology for mitigating disturbance, the bias to the word line WL for mitigating the well disturb and the bias to the bit line BL for mitigating the word disturb may be applied simultaneously. The word lines WL or the bit lines BL may be applied individually or collectively.

  In the second embodiment, the word line WL and the bit line BL, which originally do not need to be biased, are biased for the purpose of alleviating disturbance during writing. Therefore, the memory cell (for example, the non-volatile memory cell NVM11) that originally did not receive any power supply during the write operation and did not cause disturbance is also supplied with power. As a result, there is a concern about the occurrence of disturbance in the memory cell.

  On the other hand, in the second embodiment, the bias to the bit line BL and the word line WL for the purpose of avoiding disturbance is set to ± 3V. Therefore, even when both of the well disturb and the word disturb are avoided, the potential difference is about 6 V, and a large threshold voltage that causes a problem does not increase.

  Next, a technique for avoiding disturbance that occurs during the erase operation will be described.

  According to studies by the present inventors, for example, a nonvolatile memory formed in a semiconductor chip for the purpose of trimming, such as an LCD driver, has an area for holding information for trimming, and data is rewritten after shipment. And an area to be provided. Therefore, an area for rewriting data is provided, and the nonvolatile memory must be configured on the assumption that information is erased collectively. Here, according to a further study by the present inventors, the technique of using this non-volatile memory for rewriting as another chip is an undesirable technique because it causes a significant increase in chip area.

  FIG. 20 is a plan view for explaining a batch erase operation for a specific area, which is performed on the memory array Mem including the nonvolatile memories NVM arranged in the same chip. Here, the nonvolatile memory cell NVM constituting the memory array Mem is divided into two regions along the extending direction of the bit line BL, and one region is defined as the erase mat EM, and the nonvolatile memory belonging to the erase mat EM The cells NVMe are erased collectively. The other area is set as a non-erasable mat KM, and data is not erased in the nonvolatile memory cell NVMk belonging to the non-erasable mat KM. FIG. 21 is a cross-sectional view of the main part of the nonvolatile memory cell NVMe belonging to the erase mat EM. FIG. 22 is a cross-sectional view of the main part of the nonvolatile memory cell NVMk belonging to the non-erasable mat KM.

  As described with reference to FIG. 9 in the first embodiment, in order to erase the data in the nonvolatile memory cell NVM, the operating unit supply voltage Vp is + 9V, and the capacitor unit applied voltage Vc is −9V. Is applied. Therefore, in the nonvolatile memory NVMe in the second embodiment shown in FIG. 20 and FIG. 21, voltages of +9 V and −9 V are applied to the bit lines BL01 to BL09 and the word lines WL10 to WL50, respectively.

  As a result, a potential difference of about 18 V is generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1 with a polarity opposite to that at the time of writing. Therefore, the electrons e accumulated in the floating electrode FG receive this potential difference, and are emitted to the operating element forming p well PW1 over the write / erase element gate insulating film GIW by FN tunneling. Thereby, the data in the nonvolatile memory NVMe belonging to the erase mat EM is erased.

  On the other hand, the nonvolatile memory cell NVMk belonging to the non-erasable mat KM shown in FIG. 22 receives +9 V supplied from the bit lines BL01 to BL09, although there is no voltage supplied from the word lines WL60 to WL90. As a result, the same potential difference is generated between the write / erase element floating gate electrode GEW and the operating element formation p-well PW1. Therefore, although not as much as the nonvolatile memory cell NVMe shown in FIG. 22 that receives the erasing operation, the electrons e accumulated in the floating electrode FG are gradually emitted. That is, well disturb occurs.

  Here, as described above, when the electron e accumulated in the floating electrode FG is released as in the erase operation or the well disturb, the threshold voltage of the reading transistor QR which is an n-channel transistor is lowered. Then, it gradually returns to a state where it does not receive a write operation.

  FIG. 23 shows a change in the threshold voltage of the read transistor QR with respect to the erase time. A characteristic ex5 indicates the characteristic of the nonvolatile memory cell NVMe that has undergone the erasing operation, and a characteristic ex6 indicates the characteristic of the nonvolatile memory cell NVMk that has not received the erasing operation. Even in the non-volatile memory cell NVMk that has not been subjected to the erasing operation, well disturb occurs in which the threshold voltage decreases as the erasing time elapses, although not as much as the non-volatile memory cell NVMe that has undergone the erasing operation.

  As described above, when the disturbed cell is used as it is, the threshold voltage of the read transistor is set to the erased state by the repeated erase operation to the erase mat even though the cell is not subjected to the write operation. There is a possibility of becoming equivalent. This means that there is a possibility of erroneous erasure. Further, similar to the disturb that occurs during the above-described writing, there is a possibility that the memory circuit may be limited in scaling.

  Therefore, in the technique exemplified in the second embodiment, as shown in FIG. 24, a voltage of +9 V is applied to the word lines WL60 to WL90 connected to the non-erasable mat KM that is not the object of erasure. FIG. 25 shows a cross-sectional view of the main part of the nonvolatile memory cell NVMk belonging to the non-erasable mat KM at this time.

  By applying a voltage of + 9V to the word lines WL60 to WL90, the write / erase element floating gate electrode GEW and the operating element formation p-well PW1 have substantially the same potential, and the potential difference becomes approximately 0V. Thereby, in the nonvolatile memory cell NVMk, almost no electrons are emitted from the floating electrode FG to the operating element forming p well PW1. Therefore, well disturb in the non-erased mat KM can be mitigated by the technique exemplified in the second embodiment. As a result, the reliability of the nonvolatile memory can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to, for example, the semiconductor industry required to construct an integrated circuit for driving a liquid crystal display.

It is a principal part top view of the semiconductor device which the present inventors examined. FIG. 2 is a fragmentary cross-sectional view taken along line x1-x1 of the semiconductor device illustrated in FIG. 1. It is a timing chart figure showing the time change of the voltage impressed to the semiconductor device which the present inventors examined. It is a principal part top view of the other semiconductor device which the present inventors examined. FIG. 5 is a cross-sectional view of main parts taken along line x2-x2 of the semiconductor device shown in FIG. 1 is a main part plan view of a semiconductor device according to a first embodiment of the present invention; FIG. 7 is a fragmentary cross-sectional view taken along line x3-x3 of the semiconductor device illustrated in FIG. 6. It is principal part sectional drawing explaining the state at the time of the voltage application in the semiconductor device shown in FIG. FIG. 8 is a fragmentary cross-sectional view showing another voltage application state in the semiconductor device shown in FIG. 7. FIG. 8 is a fragmentary cross-sectional view showing a state when another voltage is applied in the semiconductor device shown in FIG. 7. It is a principal part top view of the semiconductor device which is Embodiment 2 of this invention. It is a top view which shows the state of the voltage application to the semiconductor device which is Embodiment 2 of this invention. It is principal part sectional drawing which shows the state at the time of the voltage application in the semiconductor device shown in FIG. It is a graph which shows the time change of the electrical property in the semiconductor device shown in FIG. FIG. 13 is a fragmentary cross-sectional view showing another state when a voltage is applied in the semiconductor device shown in FIG. 12. FIG. 13 is a fragmentary cross-sectional view showing another state when a voltage is applied in the semiconductor device shown in FIG. 12. It is a top view which shows the state of the other voltage application to the semiconductor device which is Embodiment 2 of this invention. FIG. 18 is a fragmentary cross-sectional view showing a state when a voltage is applied in the semiconductor device shown in FIG. 17. It is a graph which shows the time change of the electrical property in the semiconductor device shown in FIG. It is a top view which shows the state of the other voltage application to the semiconductor device which is Embodiment 2 of this invention. FIG. 21 is a fragmentary cross-sectional view showing a state when a voltage is applied in the semiconductor device shown in FIG. 20. FIG. 21 is a fragmentary cross-sectional view showing another state when a voltage is applied in the semiconductor device shown in FIG. 20; It is a graph which shows the time change of the electrical property in the semiconductor device shown in FIG. It is a top view which shows the state of the other voltage application to the semiconductor device which is Embodiment 2 of this invention. FIG. 25 is a fragmentary cross-sectional view showing a state when a voltage is applied in the semiconductor device shown in FIG. 24.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation part 3 Side wall spacer 4 Silicide layer 5 Interlayer insulation film 5a, 5b Insulation film 6 Conductor part S1 Main surface (1st main surface)
NVM nonvolatile memory cell DNW buried n-well (first semiconductor region)
NW isolation n-well PW1 operating element formation p-well (second semiconductor region)
PW2 capacitor formation p-well (third semiconductor region)
WD write / erase element (data write / erase element)
QR readout transistor (readout field effect transistor)
QS selection transistor (selection field effect transistor)
C MIS capacitor (capacitance element)
FG Floating electrode PI Protective insulating film GEW Floating gate electrode for write / erase element (first floating gate electrode)
Floating gate electrode for GER read element (second floating gate electrode)
GES selection element gate electrode GEC capacitor floating gate electrode (third floating gate electrode)
GIW Write / erase element gate insulating film (first gate insulating film)
GIR read element gate insulating film (second gate insulating film)
Gate insulating film for GIS selection element GIC Capacitor gate insulating film (third gate insulating film)
SDC shared source / drain region (fourth semiconductor region)
Source / drain region for SDR read element (sixth semiconductor region)
SDS selection element source / drain region VSM operation element well power supply region (fifth semiconductor region)
VSC capacitor well feeding region (seventh semiconductor region)
SC capacitor source region (eighth semiconductor region)
X first direction Y second direction nx1 to nx6 n-type extension region px1, px2 p-type extension region CH contact hole CP1 contact plug for supplying power to shared part (first conductive part)
CP2 Operation well power supply contact plug (second conductive part)
CP3 Read contact plug (third conductive part)
CP4 Capacitor well contact plug (fourth conductive part)
CP5 capacitor contact plug (fifth conductive part)
CP6 Select gate contact plug Vp Operating part supply voltage Vd Read drain voltage Vc Capacitor part applied voltage e Electron IL Inversion layer DL Depletion layer BL, BL01 to BL09 Bit line WL, WL01 to WL09 Word line SL Control line rBL Read bit line EM Erase mat KM Non-erase mat

Claims (13)

A semiconductor substrate having a first principal surface and a second principal surface located on opposite sides along the thickness direction;
A main circuit forming region disposed on the first main surface of the semiconductor substrate;
A non-volatile memory region disposed on the first main surface of the semiconductor substrate,
In the nonvolatile memory area,
A first semiconductor region of a first conductivity type formed on a first main surface of the semiconductor substrate;
A second conductivity type opposite to the first conductivity type, and a second semiconductor region disposed in the first semiconductor region so as to extend in a first direction;
In the first semiconductor region, the second semiconductor region is arranged so as to be electrically separated and aligned along a second direction intersecting the first direction. A third semiconductor region of the second conductivity type;
The second semiconductor region, and a non-volatile memory cell disposed to overlap the third semiconductor region in a plane,
The nonvolatile memory cell is
A floating electrode disposed so as to planarly overlap a part of the second semiconductor region and a part of the third semiconductor region;
A data write / erase element formed in the second semiconductor region;
A read field effect transistor formed in the second semiconductor region;
A capacitive element formed in the third semiconductor region;
The floating electrode is
A first floating gate electrode disposed so as to planarly overlap a part of the second semiconductor region and to extend in a second direction intersecting the first direction;
A second floating gate electrode disposed so as to planarly overlap a part of the second semiconductor region and along a distance from the first floating gate electrode;
A third floating gate electrode disposed so as to planarly overlap a part of the third semiconductor region,
The data write / erase element is
The first floating gate electrode;
A first gate insulating film formed between the first floating gate electrode and the semiconductor substrate;
In the second semiconductor region, the second semiconductor region is formed on a first main surface of the semiconductor substrate located in a region sandwiched between the first floating gate electrode and the second floating gate electrode in plan view. A fourth semiconductor region of one conductivity type;
The second semiconductor region is formed on the first main surface of the semiconductor substrate located in a region sandwiching the first floating gate electrode by making a pair with the fourth semiconductor region in plan view. And a fifth semiconductor region of the second conductivity type,
The readout field effect transistor comprises:
The second floating gate electrode;
A second gate insulating film formed between the second floating gate electrode and the semiconductor substrate;
The second semiconductor region is formed on the first main surface of the semiconductor substrate located in a region sandwiching the second floating gate electrode by pairing with the fourth semiconductor region in plan view. A sixth semiconductor region of the first conductivity type;
The fourth semiconductor region so as to be shared with the data writing / erasing element;
The capacitive element is
The third floating gate electrode;
A third gate insulating film formed between the third floating gate electrode and the semiconductor substrate;
A seventh semiconductor region having a conductivity type opposite to each other formed on a first main surface of the semiconductor substrate located in a region sandwiching the third floating gate electrode in plan view in the third semiconductor region; An eighth semiconductor region;
The first floating gate electrode, the second floating gate electrode, and the third floating gate electrode are arranged in the same layer,
The semiconductor device, wherein the floating electrode is arranged in a floating state not electrically connected to any part. The semiconductor device according to claim 1,
The data write / erase element and the read field effect transistor are arranged side by side in the first direction in the second semiconductor region,
The semiconductor device according to claim 1, wherein a width of the data writing / erasing element and the reading field effect transistor in the first direction is smaller than a width of the capacitor element in the first direction. The semiconductor device according to claim 1,
The width of the second semiconductor region in the first direction is the same as or smaller than the width of the third semiconductor region in the first direction. The semiconductor device according to claim 1,
The nonvolatile memory cell is
A first conductive portion electrically connected to the fourth semiconductor region;
A second conductive portion electrically connected to the fifth semiconductor region;
A third conductive portion electrically connected to the sixth semiconductor region;
A fourth conductive portion electrically connected to the seventh semiconductor region;
A fifth conductive portion electrically connected to the eighth semiconductor region;
The first conductive part and the second conductive part are connected to each other so as to be electrically at the same potential,
The fourth conductive portion and the fifth conductive portion are connected to each other so as to be electrically at the same potential. The semiconductor device according to claim 1,
2. A semiconductor device according to claim 1, wherein a field effect transistor for selection is electrically connected in series to the field effect transistor for reading of the nonvolatile memory cell. The semiconductor device according to claim 5.
The selection field effect transistor is:
Formed in the second semiconductor region;
A semiconductor device, wherein the sixth semiconductor region is electrically connected to the read field effect transistor by sharing the sixth semiconductor region with the read field effect transistor as a source or drain region. The semiconductor device according to claim 1,
Rewriting data with the data writing / erasing element is performed by charge FN tunneling over the entire channel surface. A semiconductor substrate having a first principal surface and a second principal surface located on opposite sides along the thickness direction;
A main circuit region disposed on the first main surface of the semiconductor substrate;
A non-volatile memory region disposed on the first main surface of the semiconductor substrate,
The nonvolatile memory cell in the nonvolatile memory area is
A first semiconductor region of a first conductivity type formed on a first main surface of the semiconductor substrate;
A second conductivity type opposite to the first conductivity type is a second conductivity type formed so as to extend along the first direction on the first main surface of the semiconductor substrate in the first semiconductor region. A semiconductor region;
The second conductivity type is formed so as to extend along the first direction on the first main surface of the semiconductor substrate in the first semiconductor region, and is separated from the first semiconductor region. A third semiconductor region arranged side by side along a second direction intersecting the first direction;
A data write / erase element and a read field effect transistor arranged side by side in the first direction in the second semiconductor region;
A capacitive element disposed in the third semiconductor region;
A floating electrode formed in a floating state via an insulating film on the first main surface of the semiconductor substrate;
Within the non-volatile memory cell arrangement range, the first floating gate electrode of the data write / erase element, the second floating gate electrode of the read field effect transistor, and the third floating gate electrode of the capacitor element are , Formed integrally as part of the floating electrode,
The semiconductor device, wherein the first floating gate electrode and the second floating gate electrode are separated from each other within an arrangement range of the second semiconductor region. The semiconductor device according to claim 8.
The data write / erase element and the read field effect transistor are arranged side by side in the first direction in the second semiconductor region,
The semiconductor device according to claim 1, wherein a width of the data writing / erasing element and the reading field effect transistor in the first direction is smaller than a width of the capacitor element in the first direction. The semiconductor device according to claim 8.
The width of the second semiconductor region in the first direction is the same as or smaller than the width of the third semiconductor region in the first direction. The semiconductor device according to claim 8.
2. A semiconductor device according to claim 1, wherein a field effect transistor for selection is electrically connected in series to the field effect transistor for reading of the nonvolatile memory cell. The semiconductor device according to claim 11.
The selection field effect transistor is:
Formed in the second semiconductor region;
A semiconductor device characterized in that a source or drain region is shared with the readout field effect transistor and thereby electrically connected to the readout field effect transistor. The semiconductor device according to claim 8.
Rewriting data with the data writing / erasing element is performed by charge FN tunneling over the entire channel surface.

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