JP2009087988A - Semiconductor device with analysis preventing circuit, and analysis preventing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with an analysis preventing circuit, which more effectively prevents outward appearances and electric operation, such as constitution and layout, of a circuit of the semiconductor from being analyzed by a third person, and to provide an analysis preventing method. <P>SOLUTION: The semiconductor device 10 has the analysis preventing circuit 18 having a substrate 12 which has a circuit element region 14a to be protected and including: a shield wiring layer 32 having a plurality of shield wiring lines provided at least over the circuit element region to be protected; a signal input circuit 34 which inputs signals to the respective plurality of shield wiring lines; a detecting circuit 36 which detects the respective signals of the plurality of shield wiring lines; and a collation circuit 38 which collates the input signals that the signal input circuit inputs to the plurality of shield wiring lines with the detection signals that the detecting circuit detects for each of the shield wiring lines and which can send out a signal invalidating the analysis of circuit elements of at least the circuit element region to be protected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an analysis prevention method including an analysis prevention circuit for preventing analysis of the circuit configuration, circuit layout, and operation of a semiconductor device by a third party other than the manufacturer.

  In a semiconductor device that is a crystal of the latest technology, particularly a semiconductor device manufactured by a leading-edge process such as a large-scale integrated circuit (LSI), the design matters such as the circuit configuration, circuit layout, and operation are analyzed. There was a problem that it was easily imitated by a person.

  For the purpose of preventing a physical analysis by a third party, a partial region of the semiconductor device to be prevented from being analyzed, that is, the upper side of the protected circuit region, or a part of the upper side is a conductive layer or a single conductive layer. A structure that is covered with a conductive wiring (pattern), that is, an analysis prevention circuit is known (for example, see Patent Document 1).

  According to Patent Document 1, a predetermined voltage is applied to the above-described conductive layer or wiring, and an analysis act such as cutting is detected based on a change in the voltage, for example, operation analysis using a tester is impossible.

Further, according to Patent Document 1, the analysis preventing device detects that the conductive layer or wiring described above has been cut or processed, and stops the operation of at least the circuit in the protected circuit region in response to this detection. It has a detector that outputs a signal that causes it to fall.
Japanese Patent No. 3048429

  In recent years, the progress of microfabrication technology has been remarkable. For example, a microfabrication technique using a focused ion beam (FIB) that can cut only an insulating film constituting a semiconductor device extremely finely has been developed.

  Even with the above-described conventional analysis prevention circuit, only the insulating film is peeled off by the application of such a microfabrication technology, and the analysis prevention circuit and the components of the circuit in the protected circuit region located below the analysis prevention circuit are provided. It is easily exposed and the components and their layout may be analyzed by appearance.

  Furthermore, the exposed analysis prevention circuit, particularly the analysis prevention circuit formed in a wiring (thin line) shape, for example, reconnects a plurality of wirings to each other so as to bypass the protected circuit area. May be physically or electrically invalidated by being formed or short-circuited.

  As a result, there is a possibility that an electrical operation analysis of the protected circuit area is performed.

  The inventor of the present invention, while advancing earnest research, configures the constituent elements of the analysis prevention circuit provided above the protected circuit area by a plurality of thin lines, that is, wirings, and particularly assigns different signals to these wirings. Thus, it has been found that the conventional problems can be solved by performing the input operation, and the present invention has been completed.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to more effectively analyze the appearance and electrical operation of a circuit configuration and layout of a semiconductor device by a third party. An object of the present invention is to provide a semiconductor device including an analysis preventing circuit that can be prevented and an analysis preventing method.

  According to a preferred configuration example of the semiconductor device including the analysis preventing circuit of the present invention, the following configuration is preferably provided.

  That is, the semiconductor device includes a substrate including an element region in which circuit elements are provided and a protected circuit element region is set.

  In addition, the semiconductor device, that is, the analysis preventing circuit, is built in the element region and a shield wiring layer having a plurality of shield wirings provided over at least the protected circuit region above the element region, A signal input circuit that inputs an input signal to each of the plurality of shield wirings and a detection circuit that is built in the element region and detects a signal of each of the plurality of shield wirings as a detection signal, and a circuit that is built in the element region A collation circuit connected to the signal input circuit and the detection circuit, capable of collating a plurality of input signals and detection signals for each shield wiring, and transmitting a signal that invalidates at least analysis of circuit elements in the protected circuit area; It has.

  According to the analysis preventing method of the present invention, the step of preparing the semiconductor device having the above-described configuration, the step of inputting the input signal to each of the plurality of shield wirings, A step of detecting each signal of the shield wiring as a detection signal, and a collation circuit collates a plurality of input signals and detection signals for each shield wiring, and the input signal and the detection signal in one or more shield wirings And a step of sending a signal for invalidating the analysis of the circuit elements in the protected circuit area based on the result of the collation that the two are inconsistent.

  According to the analysis preventing circuit of the present invention, the constituent elements of the analysis preventing circuit provided on the upper side of the protected circuit region are constituted by a plurality of thin wires, that is, shield wires.

  Also, different signals are assigned to the respective wirings for input operation. Therefore, it is possible to detect the processing for each shield wiring, and it is based on a technique that cannot be detected by a conventional analysis prevention circuit such as connecting a plurality of wirings to each other so as to bypass the protected circuit area. Processing can be detected.

  Thus, it is possible to take measures for preventing analysis such as stopping the operation of the circuit in the protected circuit area. Therefore, confidential matters such as the circuit configuration layout of the protected circuit area can be more effectively protected.

  Embodiments of the present invention will be described below with reference to the drawings. The drawings merely schematically show the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is not particularly limited thereby. Moreover, in each figure used for the following description, it should be understood that the same components are denoted by the same reference numerals, and redundant description thereof may be omitted.

(First embodiment)
[Configuration example of semiconductor device]
With reference to FIGS. 1A and 1B, a configuration example of a semiconductor device including an analysis preventing circuit according to an embodiment of the present invention will be described.

  FIG. 1A is a diagram schematically showing a configuration of an analysis preventing circuit as seen through a partial region on the upper surface side of the semiconductor device of the present invention. FIG. 1B is a schematic diagram illustrating a cut surface cut along a one-dot chain line illustrated in FIG.

  As shown in FIGS. 1A and 1B, a semiconductor device 10 according to an embodiment of the present invention includes a substrate 12. The substrate 12 is a substrate generally applicable to the manufacture of so-called semiconductor devices such as a silicon substrate.

  In FIGS. 1A and 1B, a further part of the element region 14 occupying a partial region of the substrate 12 is shown, but the planar shape of the entire substrate 12 can be any desired and desired shape. .

  The substrate 12 has a first main surface 12a that is an upper surface and a second main surface 12b that is a lower surface that faces the first main surface 12a in parallel.

  In the element region 14, a plurality of circuit elements 16 such as transistors are provided. That is, the circuit element 16 includes a so-called wiring structure such as a gate electrode, a well region into which conductive ions are implanted, and other regions.

  Since the circuit element 16 itself can have any suitable conventionally known configuration corresponding to a desired function, a detailed description thereof will be omitted.

  The element region 14 in which a plurality of circuit elements 16 are integrated includes a protected circuit element region 14a as a partial region. Here, the protected circuit element area 14a means an area related to some confidential matter, that is, an area where physical analysis by a third party is desired to be prevented.

  In this example, the protected circuit element region 14a is shown as a substantially rectangular shape, but is not limited thereto.

  An analysis preventing circuit 18 is provided outside the protected circuit element area 14a in this example of the element area 14 (details will be described later).

  A first insulating layer 20 is provided on the first main surface 12 a of the substrate 12. The first insulating layer 20 can be formed of any conventionally known suitable material such as a silicon oxide film.

  A first wiring layer 22 including a plurality of wirings is provided on the surface 20 a of the first insulating layer 20. The first wiring layer 22 may be formed using any suitable process rule, preferably using any suitable material such as aluminum or copper.

  The first wiring layer 22 is electrically connected to the circuit element 16 already described by the first contact 21.

  The first contact 21 is provided through the first insulating layer 20. The first contact 21 may preferably be any conventionally known conductive material such as tungsten.

  A second insulating layer 30 is provided on the first insulating layer 20. The second insulating layer 30 can be formed of any conventionally known suitable material such as a silicon oxide film.

  The second insulating layer 30 is provided so as to cover the surface 20 a of the first insulating layer 20 and the first wiring layer 22.

  A second wiring layer 32 is provided on the surface 30 a of the second insulating layer 30. In this example, the second wiring layer 32 is provided as a shield wiring layer. The shield wiring layer 32 is connected to the analysis preventing circuit by the second contact 31.

  A third insulating layer 40 is provided on the second insulating layer 30 so as to cover the shield wiring layer 32.

  The shield wiring layer 32 is one of the components of the analysis preventing circuit 18.

  The shield wiring layer 32 is provided on the upper side of the element region 14. In the shield wiring layer 32, individual shield wirings (hereinafter referred to as shield wirings 32) are provided across at least the protected circuit region 14a.

  In this example, a plurality of linear shield wires 32 are arranged in parallel to each other.

  In this example, the plurality of shield wirings 32 are provided so as to cross over two mutually opposing sides of the rectangular protected circuit element region 14a.

  Of the plurality of shield wirings 32, the outermost two outer surfaces are preferably positioned near the contour of the protected circuit element region 14a, that is, outside the contour of the protected circuit element region 14a. Alternatively, it is preferable to position the shielded circuit element region 14a inside the contour of the protected circuit element region 14a on condition that it is smaller than the wiring interval between the plurality of shield wirings 32.

  The wiring interval between the plurality of shield wirings 32 is preferably as small as possible within the range allowed by the process rule.

  The length of each shield wiring 32 is as short as possible, that is, it is preferably arranged in a straight line, for example.

  The line width of each shield wiring 32 and the interval between the plurality of shield wirings are preferably constant, and may be provided in a range of about 0.1 μm to 5 μm, for example.

  Thus, if the shield wiring 32 is configured to be as short as possible, the processing on the shield wiring can be detected more effectively. Therefore, since the processing of the shield wiring 32 itself becomes difficult, the analysis preventing effect is further improved.

  The shield wiring layer 32 is preferably configured as the uppermost wiring structure of a multilayer wiring structure, for example.

  In this example, the semiconductor device 10 has a multilayer wiring structure, and the configuration in which the shield wiring layer 32 is provided as the second wiring layer (32), which is a single wiring layer, is not limited thereto. The shield wiring layer 32 may be provided, for example, in the same layer as the first wiring layer 22, or may be provided as an upper wiring layer than the second wiring layer 32.

  Further, the shield wiring 32 may be configured such that the entire length is divided into two or more wiring layers. In this case, it is preferable that the divided shield wiring portions are electrically connected to each other by a conventionally known so-called embedded via in which a via hole is embedded with a conductive material.

  As shown in FIGS. 1A and 1B, the analysis preventing circuit 18 of the present invention includes a signal input circuit 34, a detection circuit 36, and a verification circuit 38 in addition to the shield wiring 32 already described. .

  The signal input circuit 34 is provided outside the protected circuit element region 14 a of the element region 14 of the substrate 12. The output terminal of the signal input circuit 34 is connected to one end of each of the plurality of shield wires 32. The signal input circuit 34 can input different input signals to each of the plurality of shield wirings 32.

  The detection circuit 36 is formed outside the protected circuit element region 14 a in the element region 14. The input terminal of the detection circuit 36 is connected to the other end of the signal input circuit 34 of each of the plurality of shield wirings 32 that is not connected. The detection circuit 36 detects each signal of the plurality of shield wires 32.

  That is, the output terminal of the signal input circuit 34 is connected to one end of each of the plurality of shield wires 32, and the input terminal of the detection circuit 36 is connected to the other end of each of the plurality of shield wires 32.

  In this example, the verification circuit 38 is formed outside the protected circuit element region 14 a in the element region 14. The verification circuit 38 is connected to the output terminals of the signal input circuit 34 and the detection circuit 36.

  The collating circuit 38 is configured to input the input signal input to each of the plurality of shield wirings 32 by the signal input circuit 34 and the detection signal detected for each of the shield wirings 32 by the detection circuit 36 for each shield wiring 32 corresponding to the input signal input. To match.

  The collation circuit 38 is based on the collation result, that is, the input signal input by the signal input circuit 34 (in this case, a signal defined by the magnitude of the voltage) and the detection signal detected by the detection circuit 36 (the magnitude of ) Is invalid so that at least the circuit elements in the protected circuit element region are inoperative, the entire semiconductor device 10 is inoperative, or analysis is impossible. It has a function capable of transmitting a signal to be converted, that is, a reset signal or a cutoff signal described later.

  Invalidation here refers to, for example, a predetermined signal that operates if at least the circuit elements in the protected circuit element area are normal, that is, in an unanalyzed state, by erasing the setting of the memory holding circuit inside the LSI. This means that even if is input, it becomes inactive.

  For example, the LSI generally includes components that store and hold data such as flip-flop circuits, register circuits, and random access memories (RAM), that is, memory holding circuits.

  Each of these has a so-called reset terminal. When a reset signal is input to the reset terminal, a part or all of the stored data is erased.

  In addition, if a switch circuit is provided for shutting off the power supply supplied to the LSI in an off state, the operation of the entire LSI can be stopped by inputting a cutoff signal for turning off the switch circuit. it can.

  That is, the output terminal of the verification circuit 38 is connected to the reset terminal of the memory holding circuit described above or the switch circuit that cuts off the power supply.

  According to the semiconductor device including such an analysis preventing circuit, input signals can be individually input to the plurality of shield wirings. Also, different input signals are input to each of the plurality of shield wires, and the input signal and the detection signal are independently verified for each shield wire. Therefore, even if processing such as detouring of wiring is performed, the processing can be easily detected. Therefore, physical analysis such as operation analysis of the semiconductor device can be effectively prevented.

[Operation]
Here, the operation of the semiconductor device of the first embodiment already described will be described with reference to FIGS. 1A and 1B and FIG.

  FIG. 2 is a flowchart for explaining the operation of the semiconductor device of the first embodiment of the present invention, that is, the analysis preventing circuit.

  First, the signal input circuit 34 inputs different input signals to the plurality of shield wires 32 for each of the wires (S1).

  The input signal referred to in this example means a voltage signal set as a specific size for each shield wiring 32.

  The detection circuit 36 detects an input signal input to each of the plurality of shield wirings 32 as a detection signal (S2).

  The collation circuit 38 collates the unique input signal input to each of the plurality of shield wirings 32 by the signal input circuit 34 and the detection signal detected by the detection circuit 36 for each of the shield wirings 32 for each shield wiring 32 (S3). .

  This collation is performed for each shield wiring 32 whether or not the input signal and the detection signal match (S4).

  As a result of the collation, when the input signal and the detection signal for each shield wiring 32 coincide with each other, the above-described series of operations of signal input to the shield wiring 32, signal detection and signal collation are repeated.

  When the verification circuit 38 detects that the detection signal is different from the input signal for one or more shield wires 32, that is, the magnitude of the input signal input by the signal input circuit 34 and the detection circuit 36 If the detected signal is different in magnitude, the verification circuit 38 sends a reset signal to the reset terminal of the memory holding circuit described above to reset the memory holding circuit or switch off the power supply Sends a cut-off signal to the circuit to cut off the power supply.

  In this way, the verification circuit 38 is configured so that at least the circuit elements in the protected circuit element region 14a are not operating, that is, cannot function and cannot be analyzed, or the entire semiconductor device 10 is disabled. Alternatively, the analysis action is invalidated so that the function is lost and the analysis becomes impossible (S5).

(Second Embodiment)
[Configuration example of semiconductor device]
With reference to FIG. 3, a further configuration example of the semiconductor device including the analysis preventing circuit of the present invention will be described.

  FIG. 3 is a diagram schematically showing a configuration of the analysis preventing circuit, transparently viewing a partial region on the upper surface side of the semiconductor device. Since the drawing schematically showing the cut surface is not different from FIG. 1B, its illustration is omitted.

  This configuration example is characterized in that a clock signal is further used as a signal for detecting physical analysis.

  In the semiconductor device of this embodiment, the configuration other than the analysis prevention circuit is the same as the configuration of the first embodiment already described, and the meaning of the terms used is the same unless otherwise described. Detailed descriptions of the other constituent elements will be omitted.

  As shown in FIG. 3, the semiconductor device 10 according to the embodiment of the present invention includes a shield wiring layer 32 that is a component of the analysis preventing circuit 18. The shape and installation mode of the shield wiring 32 itself is not different from the first embodiment already described.

  That is, the plurality of shield wirings 32, that is, the shield wiring layers are provided on the upper side of the element region 14 as in the first embodiment.

  As shown in FIG. 3, the analysis preventing circuit 18 of this embodiment includes a clock signal input circuit 39, in addition to the shield wiring 32 and the signal input circuit 34 having the same configuration as that described in the first embodiment. A delay detection circuit 36 'and a verification circuit 38' are provided.

  The clock signal input circuit 39 is provided outside the element region 14 of the substrate 12, in this example, the protected circuit element region 14a. The output terminal of the clock signal input circuit 39 is branched into a plurality, and is connected to a delay detection circuit 36 ′, a plurality of first flip-flop circuits 33, and a second flip-flop circuit 35 described later in a one-to-one correspondence relationship. Has been.

  The clock signal input circuit 39 can input a clock signal to each of the plurality of shield wirings 32 corresponding to each of the first flip-flop circuits 33 via each of the plurality of first flip-flop circuits 33.

  The signal input circuit 34 is provided in the element region 14 as in the first embodiment.

  An output terminal of the signal input circuit 34 is connected to an input terminal of each of the plurality of first flip-flop circuits 33.

  The signal input circuit 34 can input different input signals, preferably voltage signals of different magnitudes in this example, to each of the plurality of shield wirings 32 via the first flip-flop circuit 33.

  The clock signal input circuit 39 may be configured to input a clock signal having the same frequency to all of the first flip-flop circuit 33 and the second flip-flop circuit 35, or the first flip-flop circuit 33 and the second flip-flop circuit 33 A configuration may be adopted in which clock signals having different frequencies are input to the respective flip-flop circuits 35.

  The delay detection circuit 36 'is formed outside the element region 14, in this example, the protected circuit element region 14a. The input terminals of the delay detection circuit 36 ′ are connected to the output terminals of a plurality of second flip-flop circuits 35 that are connected to the plurality of shield wirings 32, respectively.

  The delay detection circuit 36 ′ is required until the wiring delay of each of the plurality of shield wirings 32, that is, the voltage signal generated by the signal input circuit 34 output from the first flip-flop circuit 33 reaches the second flip-flop circuit 35. The number of clocks (number of cycles) of the clock signal is detected and output as a delay detection signal.

  The output terminal of the first flip-flop circuit 33 is connected to one end, that is, the input end of each of the plurality of shield lines 32, and the second flip-flop is connected to the other end, that is, the output end of each of the plurality of shield lines 32. The input terminal of the circuit 35 is connected.

  Each of the first flip-flop circuit 33 and the second flip-flop circuit 35 described above has an input terminal to which the clock signal generated by the clock signal input circuit 39 is input, and the rising edge of the clock signal input thereto Alternatively, it is a so-called synchronous flip-flop circuit that operates at the descending timing.

  The verification circuit 38 'is formed outside the element region 14, in this example, the protected circuit element region 14a. The input terminal of the verification circuit 38 'is connected to the output terminal of the delay detection circuit 36'.

  Further, another output terminal of the signal input circuit 34 is connected to another input terminal of the verification circuit 38 ′. Further, another output terminal of the clock signal input circuit 39 is connected to another input terminal.

  The collation circuit 38 ′ can read out and contrast the wiring delay inherent to each shield wiring 32, that is, a predetermined number of clock signals required for an input voltage signal to propagate through each shield wiring 32 as a comparison target. It is preset as data.

  The verification circuit 38 ′ preferably includes, for example, a so-called flip-flop circuit or a register circuit as a component responsible for such data storage.

  The predetermined number of clocks of the clock signal, that is, the specific number of cycles means that the voltage signal generated by the signal input circuit 34 passes through the shield wiring 32, that is, propagates from the first flip-flop circuit 33 to the second flip-flop circuit 35. This is the number of clocks required for the shield wiring 32 to be set in advance.

  The collation circuit 38 ′ receives the delay detection signal output from the delay detection circuit 36 ′, and stores in advance the delay detection signal, that is, the number of clocks of the clock signal required to propagate through the shield wiring 32. It has a function of reading out a corresponding predetermined number of clocks and comparing each shield wiring.

  Further, the collation circuit 38 ′, based on the collation result, that is, when the wiring delay detected by the delay detection circuit 36 ′ is different from the intended wiring delay, at least circuit elements in the protected circuit element region. Has a function capable of transmitting a reset signal or a shut-off signal for invalidating the semiconductor device 10 so that it does not operate or the entire semiconductor device 10 does not operate.

  The invalidation here means that, as described in the first embodiment, the setting of the memory holding circuit such as the flip-flop circuit, the register circuit, and the random access memory (RAM) in the LSI is deleted. This means that at least the circuit elements in the protected circuit element region are in a normal state, that is, in a non-analyzed state even if a predetermined signal (signal) that operates is input.

  Further, as already described, the operation of the entire LSI may be stopped by inputting a cutoff signal for turning off the switch circuit.

  That is, the output terminal of the verification circuit 38 ′ is connected to the reset terminal of the memory holding circuit or the switch circuit that cuts off the power supply.

  According to the semiconductor device having such an analysis preventing circuit, input signals are individually input to the plurality of shield wirings. Also, different input signals are input to each, and the signals are verified independently for each shield wiring.

  Therefore, processing such as detouring of wiring becomes extremely difficult. Therefore, physical analysis such as operation analysis of the semiconductor device can be effectively prevented.

  In addition, when the clock signal is used as described above, so-called synchronous design is possible, so that the design becomes easier and the development period of the semiconductor device can be further shortened.

  In addition, if it is configured to be able to allocate and input clock signals with different frequencies for each wiring, even when the wiring length and wiring width of the shield wiring are locally different due to circumstances such as wiring layout, Since the input clock frequency can be adjusted correspondingly, analysis by a third party can be accurately detected even in such a case.

[Operation]
Here, the operation of the semiconductor device of the second embodiment will be described with reference to FIGS.

  FIG. 4 is a flowchart for explaining the operation of the semiconductor device of the second embodiment already described, that is, the analysis preventing circuit.

  First, the clock signal input circuit 39 inputs a clock signal for each of the plurality of shield wirings 32 via the first flip-flop circuit 33. At the same time, the signal input circuit 34 inputs a voltage signal as an input signal for each of the plurality of shield wirings 32 via the first flip-flop circuit 33 (S1).

  The input clock signal may have the same frequency for all the shield wirings 32, or may have a different frequency for each shield wiring 32.

  The clock signals having different frequencies in this example mean clock signals that are preset as frequencies unique to each shield wiring 32.

  The delay detection circuit 36 ′ detects the number of clocks (cycle number) required for the voltage signal input from the signal input circuit 34 to reach the second flip-flop circuit 35, that is, the wiring delay, in each of the plurality of shield wirings 32. (S2).

  The collation circuit 38 'collates the number of clocks detected by the delay detection circuit 36' with the preset number of clocks for each shield wiring 32 (S3).

  This collation is performed by reading out the clock number of the clock signal required for the voltage signal input to the shield wiring 32 to propagate through the shield wiring 32 and the predetermined clock number stored in advance, and comparing them. Whether or not it is done is performed for each shield wiring 32 (S4).

  As a result of the collation, when the number of clocks set in advance for each shield wiring 32 matches the number of detected clocks, that is, when the wiring delays match, the clock signal input to the shield wiring 32, the wiring delay detection, and A series of operations called wiring delay verification is repeated.

  When the verification circuit 38 ′ detects a wiring delay different from a predetermined wiring delay for one or more shield wirings 32, the verification circuit 38 ′ outputs a reset signal to the reset terminal of the memory holding circuit described above. Is sent to reset the memory holding circuit, or the power supply is cut off by sending a cut-off signal to the switch circuit that cuts off the power supply.

  In this way, the verification circuit 38 ′ causes at least the circuit elements in the protected circuit element region 14a to be non-operational, that is, cannot function, or disables the entire semiconductor device 10 or loses its function. The analysis is invalidated (S5).

(A) is a figure which shows typically the structure of the analysis prevention circuit which transparently saw the partial area | region of the upper surface side of the semiconductor device of this invention. FIG. 2B is a schematic diagram illustrating a cut surface cut along a one-dot chain line illustrated in FIG. 3 is a flowchart for explaining the operation of the semiconductor device of the first embodiment of the present invention, that is, the analysis preventing circuit. It is a figure which shows typically the structure of the analysis prevention circuit of 2nd Embodiment which transparently saw the partial area | region of the upper surface side of the semiconductor device. It is a flowchart for demonstrating operation | movement of the semiconductor device of 2nd Embodiment, ie, an analysis prevention circuit.

Explanation of symbols

10: Semiconductor device 12: Substrate 12a: First main surface 12b: Second main surface 14: Element region 14a: Protected circuit element region 16: Circuit element 18: Analysis prevention circuit 20: First insulating layer 20a, 30a: Surface 21: first contact 22: first wiring layer 30: second insulating layer 31: second contact 32: shield wiring (layer) (second wiring layer)
33: first flip-flop circuit 34: signal input circuit 35: second flip-flop circuit 36: detection circuit 36 ': delay detection circuit 38, 38': verification circuit 39: clock signal input circuit 40: third insulating layer

Claims (7)

A circuit element is provided, and includes a substrate including an element region in which a protected circuit element region is set;
A shield wiring layer having a plurality of shield wirings provided over at least the protected circuit region above the element region; and
A signal input circuit that is built in the element region and inputs an input signal to each of the plurality of shield wires;
A detection circuit that is built in the element region and detects a signal of each of the plurality of shield wires as a detection signal;
Built in the element region, connected to the signal input circuit and the detection circuit, a plurality of the input signal and the detection signal are collated for each shield wiring, and at least of the protected circuit region What is claimed is: 1. A semiconductor device comprising: an analysis preventing circuit including a verification circuit capable of transmitting a signal for invalidating analysis of a circuit element. A circuit element is provided, and includes a substrate including an element region in which a protected circuit element region is set;
A shield wiring layer having a plurality of shield wirings provided over at least the protected circuit region above the element region; and
A plurality of first flip-flop circuits built in the element region and connected to one end of each of the plurality of shield wires in a one-to-one correspondence;
A plurality of second flip-flop circuits formed in the element region and connected in a one-to-one correspondence relationship to the other ends of the shield wires;
A signal input circuit which is built in the element region and inputs an input signal to each of the plurality of first flip-flop circuits;
A clock signal of the same frequency generated in the element region, connected to each of the plurality of first flip-flop circuits and the second flip-flop circuit, and generated by a clock signal input circuit; A first clock signal that is input to one flip-flop circuit and reaches the second flip-flop circuit through the shield wiring, a second clock signal input to the second flip-flop circuit, and a delay detection circuit directly Based on the input third clock signal and the input signal, the delay detection circuit for detecting the wiring delay of each of the shield wirings and a predetermined wiring for each of the plurality of shield wirings, which are built in the element region Read the delay, the predetermined wiring delay and the delay detection circuit to each shield wiring An analysis preventing circuit including a matching circuit capable of collating the detected wiring delay for each shield wiring and sending at least a signal for invalidating the analysis of the circuit element in the protected circuit region. Semiconductor device.   The semiconductor device according to claim 1, wherein each of the plurality of shield wires is arranged in a straight line. Preparing the semiconductor device according to claim 1;
The signal input circuit inputting an input signal to each of the plurality of shield wires; and
The detection circuit detecting a signal of each of the plurality of shield wires as a detection signal;
The collation circuit collates a plurality of the input signals and the detection signals for each shield wiring, and collates that the input signal and the detection signal do not coincide with each other in one or more shield wirings. And a step of transmitting a signal for invalidating the analysis of the circuit element in the protected circuit region based on the result. Preparing a semiconductor device according to claim 2;
The delay detection circuit is a clock signal of the same frequency generated by the clock signal input circuit, and is input to the first flip-flop circuit and reaches the second flip-flop circuit through the shield line A wiring delay of each of the plurality of shield wirings based on the second clock signal input to the second flip-flop circuit and the third clock signal input directly to the delay detection circuit and the input signal; Detecting step;
The collation circuit reads out a predetermined wiring delay for each of the plurality of shield wirings, and collates the predetermined wiring delay and the wiring delay detected by the delay detection circuit for each of the shield wirings for each shield wiring. A signal that invalidates at least the analysis of the circuit element in the protected circuit area based on a collation result that the predetermined wiring delay and the detected wiring delay do not match in one or more shield wirings A method for preventing analysis.   The analysis preventing method according to claim 4, wherein the plurality of input signals are set as signals having different magnitudes.   6. The analysis preventing method according to claim 5, wherein the clock signals input to the first flip-flop circuits are set as clock signals having different frequencies.

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