JP2009086880A - Layout verification program and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout verification program and a layout verification method that can improve the verification precision of a pair arrangement. <P>SOLUTION: Pair arrangement element verification processing (Step 21-24) between elements for which pair arrangement is required is performed, and if there is a violation of a condition, pair arrangement resistance element verification processing (Step 25) is performed. Thereby, a pair arrangement can be verified by taking the resistance elements whose shapes of main bodies are different into consideration. Then pair arrangement peripheral graphic verification processing (Steps 26 and 27) is performed in the scope where a graphic that affects the elements for the verification of the pair arrangement is included, and, if the graphic shape is not the same, pair arrangement peripheral graphic reverse rotation processing (Step 28) is performed. As pair arrangement MOS transistor verification processing (Step 29) is performed when an element which is a candidate for a pair arrangement is a MOS transistor, the pair arrangement can be verified taking the direction of the drain current of the MOS transistor into consideration, and transistor characteristics can be uniformed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a layout verification program and a layout verification method for verifying the layout of elements arranged in a semiconductor device.
In recent years, semiconductor devices (LSIs) have been increased in scale and integration, and the amount of design data has increased. In designing a semiconductor device, it is necessary to consider various layout (arrangement of elements and the like) constraints. For this reason, layout verification tends to take a lot of time in designing a semiconductor device, and a technique for shortening the work time is required.

  In the layout design of a semiconductor device, it is required to arrange a plurality of elements in pairs. Here, the term “pair arrangement” means that elements having the same shape are arranged close to each other so that the influence of peripheral elements and patterns acts equally. Thereby, an element with high relative accuracy is formed. For example, a differential circuit and a current mirror circuit in an analog electronic circuit require a plurality of transistors having the same characteristics. For this reason, by arranging a plurality of transistors in pairs, a transistor having a small difference in relative characteristics, that is, a transistor with high relative accuracy is obtained. In semiconductor device layout verification, a verification device has been proposed for verifying whether or not pair placement is correctly performed. For example, Patent Document 1 and Patent Document 2.

  The verification apparatus determines whether or not a plurality of target elements are arranged in pairs, that is, has a pair property, depending on the type of element, the distance between elements, and the arrangement direction of the elements. Verify whether or not. For example, as shown in FIG. 28A, when the types of the target elements C1 and C2 are the same and the arrangement conditions (rotation and inversion) are the same, both elements C1 and C2 are arranged in pairs. It is judged. Further, as shown in FIG. 28B, when the arrangement conditions of the target elements C1 and C2 are different, it is determined that the elements C1 and C2 are not arranged in pairs.

In FIG. 28A, the triangles shown at the lower left of the elements C1 and C2 indicate the reference points of the elements C1 and C2, respectively. Therefore, as shown in FIG. 28 (b), when the element C2 is rotated 90 degrees counterclockwise, the reference point is at the lower right of the element C2.
JP 2001-229215 A JP 2001-175700 A

  However, in the conventional verification, there are cases where the verification cannot be performed correctly depending on the arrangement of elements. For example, this is a case where the layout data does not have a hierarchical structure. As a specific example, as shown in FIG. 28C, there is a case where data of the gates G1 and G2 of the transistor and the diffusion layers D1 to D4 are not related. Since the element shape and the arrangement position cannot be extracted from the layout data, the pair arrangement cannot be determined.

  Another example of the case where the conventional verification cannot be performed correctly is the case shown in FIG. 28D, which is widely used as a method of performing pair arrangement while reducing the area of the resistance element. As shown in FIG. 28 (d), the outer shapes of the resistance layers RL1 and RL2 that bear the main body portions R1 and R2 of the resistance elements C1 and C2 are formed according to the resistance element C1 having a large resistance value. The resistance element C2 having a small resistance value is configured by disposing contact layers CL3 and CL4 having the same shape as each of the contact layers CL1 and CL2 that bear a connection portion with the outside in the resistance element C1. The arrangement positions of the contact layers CL3 and CL4 are positions on the resistance layer RL2, and the main body portion R2 has a target resistance value. In this arrangement, since the resistance layers RL1 and RL2 and the contact layers CL1 and CL3, CL2 and CL4 have the same shape, it is recognized that the resistance elements C1 and C2 having different resistance values are arranged in pairs. is there. However, since each element is laid out as a cell in the conventional verification, it is not determined that a pair is arranged unless the cells of the target element match. The resistance elements C1 and C2 shown in FIG. 28 (d) are not determined to be paired because the main body portions R1 and R2 functioning as resistors have different shapes.

  Further, in the conventional verification, it is necessary to align the drain current of the MOS transistor with respect to the crystal orientation of the silicon substrate in order to align the transistor characteristics, but this point is not mentioned.

  Since there are cases as described above, it is confirmed by visual inspection whether the pair arrangement is made. If overlooked, the operation is different from the simulation, leading to a failure of the semiconductor device. In addition, since visual inspection requires a lot of manpower, it has been a factor in increasing design man-hours.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a layout verification program and a layout verification method capable of improving the accuracy of verification of pair placement.

  The layout verification program according to the first and second inventions of the present application relates to information processing based on a physical property or a technical property of a layout of elements arranged in a physical or technical object of a semiconductor device. It belongs to the creation of technical ideas using the laws of nature.

  A layout verification program according to the first invention of the present application is a program for causing a computer system to execute the layout verification method according to the first invention of the present application. The layout verification method includes a step of extracting a set of MOS transistors that are candidates for pair placement, a step of specifying a drain current direction for the extracted set of MOS transistors, and a direction of the specified drain current. And a step of recognizing a pair of MOS transistors as a pair-arranged MOS transistor when they are in the same direction.

  According to the layout verification program and the layout verification method according to the first invention of the present application, it is possible to verify the pair arrangement in consideration of aligning the directions of the drain currents of the MOS transistors. Since the drain current directions of the MOS transistors arranged in pairs are aligned in the same direction, the transistor characteristics can be aligned.

  A layout verification program according to the second invention of the present application is a program for causing a computer system to execute the layout verification method according to the second invention of the present application. The layout verification method includes a step of extracting a resistance element having a different shape of a set of main body portions that are candidates for pair arrangement, and a main body portion of the resistance element between resistance elements having different shapes of the extracted set of main body portions. And comparing the shape of the contact layer that bears the connection portion with the outside of the resistance element between the resistance elements having different shapes of the pair of extracted body parts. And a step of recognizing that a pair of resistance elements having different shapes of the main body portions are resistance elements arranged in pairs when the outer shape of the resistance layer matches the shape of the contact layer.

  Here, in the semiconductor device, the resistance element usually includes a resistance layer that serves as a main body portion and a contact layer that serves as a connection portion with the outside of the resistance element. In the resistance element, a portion sandwiched between the contact layers in the resistance layer such as a diffusion layer or a polysilicon layer becomes a main body portion that functions as a resistance.

  According to the layout verification program and the layout verification method according to the second invention of the present application, it is possible to verify the pair arrangement in consideration of resistance elements having different shapes of the main body portion. It is not necessary to rely on visual inspection to check whether the pair placement by the method of performing the pair placement while suppressing the area of the resistance element described above, and preventing the verification accuracy of the pair placement from being lowered. it can.

  According to the layout verification program and layout verification method of the present invention, it becomes possible to verify the pair arrangement considering the direction of the drain current of the MOS transistor, or to verify the pair arrangement considering the resistance elements having different shapes of the main body part, The accuracy of verification of the pair arrangement can be improved.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a computer system that causes a layout verification program to execute layout verification.

  The computer 11 includes a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter referred to as a CPU) 12, a memory 13, a magnetic disk 14, a display device 15, an input device 16, and an external storage device 17. They are connected to each other via a bus 18.

  The CPU 12 executes a program using the memory 13 and executes a layout verification process of the semiconductor device. The memory 13 stores programs and data necessary for realizing various processes. The memory 13 usually includes a cache memory, a system memory, a display memory, and the like (not shown).

  The display device 15 is used for display of a layout display, a parameter input screen, and the like. Usually, a CRT, LCD, PDP, or the like (not shown) is used for this. The input device 16 is used to input requests and instructions from users and parameters, and a keyboard and mouse device (not shown) are used for this.

  The magnetic disk 14 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, etc. (not shown). The magnetic disk 14 stores various data such as program data for a semiconductor device layout verification process, a net list, and layout data. In response to an instruction from the input device 16, the CPU 12 transfers the program data to the memory 13 and executes it sequentially.

  Program data executed by the CPU 12 is provided on the recording medium 19. The external storage device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads program data from the recording medium 19 via the external storage device 17 and installs it on the magnetic disk 14.

  The recording medium 19 is a computer-readable recording medium. For example, an optical disk 19a such as a CDROM or DVD, a magnetic medium 19b such as a magnetic tape (MT), a flexible disk, or a magneto-optical disk (MO, MD,...) Is used. . A semiconductor memory, an externally connected hard disk device, or the like may be used. The above-described program data can be stored in the recording medium 19 and loaded into the memory 13 for use as necessary.

  The recording medium 19 includes a medium on which program data uploaded or downloaded via a communication medium is recorded, a disk device, a storage device of a server device to which the computer 11 is connected via a communication medium, and the like. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

Next, an outline of the pair placement verification process for the layout data of the semiconductor device will be described.
FIG. 2 is a schematic flowchart of the layout verification method, and is a schematic flowchart of the pair placement verification process. It is the procedure of the layout verification program which makes the computer system of FIG. 1 perform layout verification.

  In step 21, the CPU 12 recognizes each element included in the semiconductor device based on the layout data of the semiconductor device and the control card. The control card is data including information defining elements to be paired. This control card includes definition information such as element names and arrangement constraints, graphic information and connection information such as wiring constituting the elements, and search area information. The CPU 12 recognizes the shape / location of the element from the layout data based on the information on the control card.

  The graphic information corresponds to the information in the database that defines the elements, and the layout data is generated based on the definition information in the database and the net list. Therefore, even in layout data in which graphic information is not hierarchized, an element (for example, a MOS transistor) composed of a plurality of figures can be obtained by comparing the laid-out graphic shape with the graphic information included in the control card. Can be recognized.

  Next, in step 22, the CPU 12 determines the element name from the net list for the element recognized in step 21 based on the connection state of the element. Next, in step 23, based on the control card, an element name that requires pair arrangement and an allowable interval value at which the pair arrangement is established are set.

  Next, in step 24 (verification processing between paired elements), pair arrangement is verified based on the determined element name, figure shape / arrangement position, and allowable interval value. In this verification, element shape comparison and interval verification are performed. That is, the CPU 12 determines whether or not the shapes of a plurality of adjacent elements are the same. Further, the CPU 12 calculates an interval between the plurality of elements from the arrangement location, and determines whether or not the interval is within an allowable interval value.

  Next, step 25 (verification processing between paired resistive elements) is performed when there is a condition violation in the verification of step 24. Even if it is determined in step 24 that the shapes do not match, if the shape is a resistance element, the outer shape of the resistance layer is the same, and the shape of the contact layer is the same in step 25, a pair arrangement is made. It is assumed that the element is a candidate. That is, even if the resistance elements have different shapes, the pair arrangement is verified by comparing the outer shape of the resistance layer and the shape of the contact layer.

  Next, in step 26, the CPU 12 sets, as a search area, a range including a graphic affected by an element whose pair placement is verified, according to the control card. In step 27 (pair arrangement peripheral figure verification process), the CPU 12 extracts the figure in the set area from the layout data, and the shape and arrangement of the figure are the same for each element for verifying the pair arrangement. Verify that there is. If the shapes are not the same, in step 28 (pair arrangement peripheral figure reverse rotation processing), the CPU 12 reverses / rotates the figure such as the element, and whether the respective figure shapes match or the relative positions are the same. Judge whether or not.

  Then, in step 29 (verification processing between paired MOS transistors), it is determined whether or not the direction of the drain current is the same for a pair of MOS transistors that are candidates for paired placement.

  As described above, the elements are extracted from the layout data figure, and it is verified whether or not the extracted elements are arranged in pairs. Therefore, the pair arrangement is verified even in layout data having no hierarchical structure. The number of visual check steps can be reduced.

  Even if the resistance elements have different shapes, the outer shape of the resistance layer and the shape of the contact layer are compared. It is not necessary to rely on visual inspection for confirmation of whether or not, and it is possible to prevent the accuracy of verification of pair placement from being lowered.

  In addition, for a plurality of elements arranged in pairs, a search area is set, wiring in the search area is extracted, and the shape / placement position of each element including the extracted figure is verified. Misjudgments can be reduced.

  Further, the direction of the drain current is specified for a pair of MOS transistors arranged in a pair, and it is verified whether or not the direction of the drain current of the specified MOS transistor is the same. The direction of the drain current of the transistors is aligned in the same direction, so that the transistor characteristics can be aligned.

Next, details of the pair placement verification process will be described.
Steps 301 to 327 shown in FIGS. 3 to 8 are detailed steps of steps 21 to 29 shown in FIG. 2.

  Steps 301 to 308 shown in FIG. 3 are pair-placed-element verification processing (steps 21 to 24 in FIG. 2) between elements that require pair placement. In step 301, the CPU 12 recognizes each element (instance) included in the semiconductor device based on the layout data 51 and the control card 52. The control card 52 describes the layer definition data 52a in which the correspondence between the level code and the layer name is described, the wiring layer definition, the interlayer connection definition data 52b in which the hole definition is described, and the mask layer calculation method for each element type. Element extraction condition data 52c. For example, a MOS transistor is composed of a diffusion layer and a pattern made of polysilicon. Therefore, in the element extraction condition data 52c, the mask layer graphic data for forming the diffusion layer and the mask layer graphic data for forming the polysilicon pattern overlapped as a condition for extracting the MOS transistor. Extracting a portion.

  The CPU 12 stores the coordinate data 53 of the external coordinates of each instance in the memory 13 or the magnetic disk 14 of FIG. Further, net information is extracted as the graphic connection information included in the layout data 51, and a list (net list) 54 of the net information is stored in the memory 13 or the magnetic disk 14 of FIG. Further, source terminal and drain terminal position information is extracted as terminal information made of the diffusion layer of the MOS transistor, and the source terminal and drain terminal position information 55 is stored in the memory 13 or the magnetic disk 14 of FIG.

  In step 302, the CPU 12 compares the net list 54 created previously with the net list 56 created in circuit design, and for the element recognized in step 301, the net list 56 is based on the connection state of the element. The element name (instance name) is extracted from the information, and the correspondence information 57 of the instance name is stored. Further, here, the source terminal position information of the MOS transistor is extracted based on the source terminal / drain terminal position information 55 and the source terminal position information 58 is stored.

  Next, in step 303, it is determined whether or not the comparison results in step 302 match. If they do not match, the process is stopped in step 304. In this case, the layout is corrected by the designer or tool, and the layout verification is performed again.

  If the comparison results of the net lists 54 and 56 match at step 303, the CPU 12 proceeds to step 305. In step 305, the CPU 12 determines an instance name as correspondence information with the net list 56, and stores the determined instance name in the coordinate data 53 in association with the external coordinates of each instance. Further, the CPU 12 calculates the reference coordinates of each element and stores the reference coordinates in the coordinate data 53 in the same manner.

  Next, in step 306, the CPU 12 converts the external coordinates stored in the coordinate data 53 into coordinate values in a coordinate system with the lower left of the figure as a reference. In other words, in this step 306, the CPU 12 unifies the orientation of the figure with respect to the reference position in all instances stored in the coordinate data 53. Then, the CPU 12 stores the coordinate value after conversion and the coordinate value of the reference position in the coordinate data 53.

  Next, in step 307, the CPU 12 refers to the control card 52 and deletes unnecessary instances. The control card 52 includes request data 52d in which instance names arranged as a pair request are described, and first condition data 52e in which a distance between elements and an element shape are described as pair condition 1. Based on the request data 52 d, the CPU 12 deletes data related to instances that do not require pair placement from the coordinate data 53.

  Further, the CPU 12 verifies the instance remaining in the coordinate data 53, that is, the instance for which pair placement is required, based on the first condition data 52e according to the condition 1 of the pair. In this verification, the CPU 12 extracts external coordinates and arrangement positions of instance names for which there is a pair request from the coordinate data 53, and compares the shapes of a plurality of instances. Further, the CPU 12 calculates the distance between the instances based on the external coordinates and the arrangement position extracted from the coordinate data 53, and compares the calculated distance between the instances and the distance between the elements in the condition 1 of the pair.

  That is, in step 307, verification based on the pair condition 1 is performed only for the instance for which pair placement is required. In step 308, the CPU 12 determines whether there is a violation of the pair condition 1. If there is no violation, the CPU 12 proceeds to step 314 shown in FIG. 5, and if there is a violation, the step shown in FIG. 309.

  Steps 309 to 313 shown in FIG. 4 are pair placement resistance element verification processing (step 25 in FIG. 2) performed when a condition violation occurs in the pair placement element verification processing of steps 301 to 308. Although the element characteristics match when the main body portions of the resistance elements are aligned and closely arranged, if the resistance values of the resistance elements arranged in pairs are different, the number of necessary resistance elements increases. For example, when the shape of the main body portion of the resistance element is aligned with a resistance element having a small resistance value, a resistance element having a large resistance value is generated by connecting resistance elements having a small resistance value in series, and conversely, In the case where the resistance elements are arranged to be large, the resistance elements having a small resistance value must be generated by connecting the resistance elements having a large resistance value in parallel. This directly increases the chip area and increases the cost. Therefore, as a method of reducing the area of the resistance element and performing the pair arrangement, the outer shape of the resistance layer such as the diffusion layer or the polysilicon layer that carries the main body of the resistance element is created according to the resistance element having a large resistance value. A resistance element having a small value is widely created by making the shape of the contact layer that bears the connection portion with the outside of the resistance element equal and adjusting the position thereof. However, resistance elements having different shapes of the main body part violate the pair condition 1 that the shapes of the respective elements are equal. In step 309, the CPU 12 determines whether or not the instance having the pair request is a resistance element. If it is a resistance element, the process proceeds to step 310, and the outer shape of the resistance layer is compared between the resistance elements having a pair requirement. The comparison of the outer shape of the resistance layer is performed by comparing the lengths of the sides constituting the outer shape of the resistance layer.

  Next, in step 311, it is determined whether or not the comparison results in step 310 are the same. If they are the same, in step 312, the shape of the contact layer is compared between the resistive elements that are required to be paired. The comparison of the shape of the contact layer is performed by making the contact layer into a figure with the center of the side in contact with the contact layer in the main body portion of the resistance element as the origin (0, 0) and comparing the shapes of the figures. In step 313, it is determined whether or not the comparison results in step 312 are the same. If they are the same, the process proceeds to step 314 shown in FIG. That is, even if it is determined in step 308 that the pair condition 1 is violated, in steps 309 to 313, if it is a resistance element, the outer shape of the resistance layer is equal, and the shape of the contact layer is equal, It is assumed that the element is a candidate for pair arrangement, and the process proceeds to step 314 as in the case where there is no violation of the condition 1 of the pair. Therefore, even if the resistance elements have different main body shapes, the pair arrangement is verified by comparing the outer shape of the resistance layer and the shape of the contact layer.

  Also, if it is determined in step 309 that the element is not a resistance element, if it is determined in step 311 that the outer shape of the resistance layer is not the same, or if it is determined in step 313 that the shape of the contact layer is not the same, The process proceeds to step 326 shown in FIG.

  Steps 314 to 316 shown in FIG. 5 are pair arrangement peripheral figure verification processing (steps 26 and 27 in FIG. 2) in a range including a figure affected by an element whose pair arrangement is verified. In step 314, the CPU 12 performs verification based on the condition 2 of the pair based on the second condition data 52 f of the control card 52. In the second condition data 52f, a condition for checking interference with an element is stored as the condition 2 of the pair, and this condition is a mask (MASK) layer name to be verified and a search distance. In the semiconductor device, signals are transmitted by wiring patterns formed in a plurality of wiring layers. The wiring layer on which the wiring pattern is formed serves as a mask for exposure processing in the semiconductor device manufacturing process. That is, the wiring layer is a mask layer in the process. The layout data 51 has a layer structure in which diffusion layers, gate wirings, wirings between elements, etc. have layer information corresponding to processes.

  Along the upper surface of the substrate of the semiconductor device, it is easily influenced by wiring formed at a position close to the element, and is hardly influenced by wiring far from the element. For this reason, the CPU 12 sets a range in which the element is affected as a search area, and extracts a mask layer in the search area. At this time, the CPU 12 expands the shape of the element whose instance name is determined in step 305 in accordance with the search distance of the condition 2 of the pair, and uses the expanded graphic as a search area. Thereby, the search area | region according to the shape of an element can be set easily. Since the distance that affects the element differs depending on the mask layer, the search distance is set according to the mask layer.

  Next, the CPU 12 extracts a figure in the set search area in each mask layer, and uses the coordinate value of the extracted figure as a coordinate value with the reference point of the search area in each mask layer as the origin (0, 0). And the coordinate value after the conversion is stored in the work data 59. That is, a search area is set for each element in each mask layer for a plurality of elements (figures) whose pair arrangement is to be verified, and a graphic included in each search area is extracted. Then, the extracted coordinate values of the figure are converted into coordinate values having the reference point of each search area as the origin and stored in the work data 59.

  Next, in step 315, the CPU 12 confirms whether or not the figure included in the extracted mask layer is the same shape between the search areas based on the coordinate values stored in the work data 59. In this confirmation, the CPU 12 performs an exclusive OR (XOR) process on the figure in each search area by matching the reference points of each search area. As a result, in each search area, a figure having the same shape and matching coordinate values does not remain. Therefore, if a figure remains after XOR processing, the figure included in each search area does not match, that is, there is a figure that is not in the same position with respect to each element in a plurality of elements that are desired to be paired. become. For this reason, the CPU 12 determines that the pair is not arranged when the figure exists in the search area after the XOR process, and determines that the pair is arranged when the figure does not exist.

  The CPU 12 can determine whether or not the pair arrangement is made only by performing the XOR process on the graphic, and this XOR process has a small load on the CPU 12. That is, the pair arrangement can be determined in a short time.

  In step 316, the CPU 12 proceeds to step 321 in FIG. 7 if the figure shapes of the mask layers confirmed in step 315 are the same, and proceeds to step 317 in FIG. 6 if they are not the same.

  Steps 317 to 320 shown in FIG. 6 are pair placement peripheral figure inversion rotation processing (step 28 in FIG. 2) performed when the figure shapes are not the same in the pair placement peripheral figure verification processing of steps 314 to 316. . In step 317, the CPU 12 determines whether or not the figure may be mirror-inverted and rotated based on the third condition data 52g of the control card 52. In the third condition data 52g, as the condition 3 of the pair, each condition of whether to allow X-axis mirror inversion, Y-axis mirror inversion, or rotation is set. Therefore, when the reversal / rotation is not permitted, the CPU 12 proceeds to step 326 shown in FIG. 8, and displays an error on the display device 15 of FIG. Therefore, it is possible to easily cope with elements that are not arranged in pairs based on the displayed error. On the other hand, if at least one of inversion and rotation is permitted, the CPU 12 proceeds to step 318.

  In step 318, the CPU 12 converts one figure data of the plurality of search areas extracted in the mask layer according to the permitted condition, and then coordinates in the coordinate system with the vertex in the same direction as the other search area as the origin. The value is converted into a value, and the converted coordinate value is stored in the work data 59.

  Next, in step 319, the CPU 12 compares the graphic data in the plurality of search areas in the mask layer stored in the work data 59 as in step 315. In step 320, the CPU 12 displays an error in step 326 shown in FIG. 8 if the graphics in the search areas are not the same. On the other hand, if the figures are the same, the CPU 12 proceeds to step 321 shown in FIG.

  Steps 321 to 325 shown in FIG. 7 are pair placement MOS transistor inter-verification verification processing (step 29 in FIG. 2) when the element extracted as the pair placement candidate in steps 301 to 320 is a MOS transistor. In step 321, the CPU 12 determines whether or not the element extracted as a pair arrangement candidate is a MOS transistor. If it is a MOS transistor, the process proceeds to step 322, and it is determined whether or not the gate terminal is divided for a pair of MOS transistors that are candidates for pair placement. If there is division of the gate terminal, in step 323, a gate terminal to be a target to be focused on when the source terminal position is confirmed in step 324 is determined. If there is no division of the gate terminal, the process proceeds to step 324 without passing through step 323. In step 324, based on the source terminal position information 58 of the MOS transistor, the source terminal position with respect to the gate terminal is confirmed for each pair of MOS transistors that are candidates for pair placement. That is, in step 324, the direction of the drain current of each MOS transistor that is a candidate for pair arrangement is specified. Next, in step 325, it is determined whether or not the source terminal position with respect to the gate terminal confirmed in step 324 is the same. If they are not the same, the CPU 12 displays an error in step 326 shown in FIG. If they are the same, the CPU 12 proceeds to step 327 shown in FIG.

  On the other hand, if it is determined in step 321 that the element extracted as the pair arrangement candidate is not a MOS transistor, steps 322 to 325 are not necessary for verification of the pair arrangement, so the CPU 12 proceeds to step 327 shown in FIG. Transition.

  Steps 326 and 327 shown in FIG. 8 are error processing and end processing. In the verification of the pair arrangement in steps 301 to 325, if it is determined that the pair arrangement is not completed, an error is displayed in step 326, and the process proceeds to step 327. On the other hand, if it is determined that the pair is arranged, the process proceeds to step 327 as it is. In step 327, it is determined whether or not verification has been completed for all patterns. If verification of all patterns has been completed, the process ends. If verification of all patterns has not been completed, the process proceeds to step 307. Continue the verification.

The operation when the layout verification program configured as described above causes the computer system to execute layout verification will be described.
FIG. 9 is an explanatory diagram of the layout data 51 (see FIG. 3) configured by graphic data having no hierarchical structure.

  The layout data 51 includes data of diffusion layers 61a and 61b, patterns 62a and 62b formed of polysilicon, patterns 63a to 63e formed of metal, and holes 64a to 64f. Each data is stored in the layout data 51 as data of a layer (mask layer) corresponding to the material and process to be formed.

  FIG. 10 is an explanatory diagram of the control card 52 (see FIG. 3). FIG. 10 shows request data 52d, first condition data 52e, element extraction condition data 52c, interlayer connection definition data 52b, and second condition data 52f among various data constituting the control card 52.

  First, the element shape and connection information are extracted from the layout data 51 (step 21 in FIG. 2 and step 301 in FIG. 3). At this time, based on the element extraction condition data 52c of the control card 52, the overlapping portions of the polysilicon patterns 62a and 62b and the diffusion layers 61a and 61b shown in FIG. 9 are extracted as MOS transistors 71 and 72 (see FIG. 11). Then, the extracted external coordinates (vertex coordinates) of the MOS transistors 71 and 72 are stored in the coordinate data 53 of FIG. Further, based on the element extraction condition data 52c, source, drain and gate terminals are defined for the extracted MOS transistors 71 and 72, and stored as MOS transistor source terminal and drain terminal position information 55 (see FIG. 3). To do. Then, connection information for each terminal of the MOS transistors 71 and 72 is extracted based on the interlayer connection definition data 52b, and the extracted connection information is used as a net list (from layout) 54 generated from the layout data 51 (see FIG. 3). ).

  Next, the netlist 56 (see FIG. 3) in the circuit design is compared with the netlist 54, and the instance names of the extracted MOS transistors 71 and 72 are determined (step 22 in FIG. 2, step in FIG. 3). 302-305). That is, the netlist 56 in the circuit design is searched, and circuit elements having the same connection state as the MOS transistors 71 and 72 are extracted. The extracted element name (instance name) of the circuit element is applied to the MOS transistors 71 and 72, and the correspondence information 57 (see FIG. 3) is stored. Also, the source terminal position of the MOS transistor is determined and stored as source terminal position information 58 (see FIG. 3) of the MOS transistor.

Next, verification of pair arrangement is performed (steps 23 and 24 in FIG. 2 and steps 306 to 308 in FIG. 3). At this time, the element spacing and the element shape are verified according to the first condition data 52e of the control card 52 of FIG.
First, it is verified whether or not the interval between the MOS transistors 71 and 72 is within the set interval of the first condition data 52e. If the interval between the MOS transistors 71 and 72 is within the set interval, the element shape is verified. If the interval between the MOS transistors 71 and 72 is not within the set interval, it is determined that the pair is not arranged.

  Next, the shapes of the MOS transistors 71 and 72 are compared. At this time, based on the vertex coordinates of the MOS transistors 71 and 72, it is verified whether or not the shapes match. If the shapes match, the process proceeds to the peripheral graphic verification process, and if the shapes do not match, the process proceeds to the next paired resistance element verification process.

  In the pair-arranged resistance element verification process (step 25 in FIG. 2, FIG. 4), it is first determined whether the element is a resistance element. Since the MOS transistors 71 and 72 are not resistance elements, it is determined that the pair arrangement is not made.

An example in which the element for verifying the pair arrangement is a resistance element will be described with reference to FIGS.
First, with respect to the resistance element whose pair arrangement is to be verified, the outer shapes of the resistance layers such as the diffusion layer and the polysilicon layer constituting the main body of the resistance element are compared. For the resistance elements 901 and 902 shown in FIGS. 12A and 12A, the outer shapes of the resistance layers 91a and 91b are compared as shown in FIGS. The comparison of the external shapes is performed by confirming whether the lengths of the sides of the external shape of the resistance layer are equal. Since the resistance layers 91a and 91b are equal in both length and width, it is determined that the resistance elements 901 and 902 have the same outer shape. On the other hand, regarding the resistance elements 901 and 903 shown in FIGS. 12B and 12A, among the sides of the outer shape of the resistance layers 91a and 91c, the width is the same, but the length is different. Therefore, it is determined that the resistance elements 901 and 903 have the same outer shape of the resistance layer. If the outer shapes of the resistance layers are not equal, it is determined that the pair is not arranged. If they are equal, the contact layer shapes are subsequently compared.

  A specific example of the comparison of the shape of the contact layer is shown in FIG. With respect to the resistance elements 901 and 902 shown in FIGS. 13 (a) and (1), the centers of the sides of the resistance element main bodies 93a and 93b that are in contact with the contact layers 92a to 92d are the origins (0, 0). The contact layer is made into a figure (see FIGS. 13A and 13B). In addition, the triangle in a figure shows the origin of contact layers 92a-92d, respectively. If there is a figure with the same shape between the resistance elements 901 and 902, the contact layers are determined to have the same shape. As shown in FIGS. 13A and 13B, since 92A and 92C and 92B and 92D are the same shape between the resistance elements 901 and 902, respectively, the resistance elements 901 and 902 are judged to have the same contact layer shape. . On the other hand, the resistance elements 901 and 904 shown in FIGS. 13B and 13A have the same shapes as the contact layers 92A and 92G and 92B and 92H, but the same shape as 92I of the resistance element 904. A figure does not exist in the resistance element 901. Therefore, it is determined that the resistance elements 901 and 904 have the same contact layer shape. If the contact layers are not equal in shape, it is determined that the pair is not arranged. If they are equal, the process proceeds to the peripheral graphic verification process.

  As described above, even when the element shapes of the resistance elements do not match, the pair arrangement is determined by comparing the outer shape of the resistance layer and the shape of the contact layer. Therefore, it is possible to verify the pair arrangement considering resistance elements having different shapes of the main body portions.

The peripheral graphic verification process (steps 26 and 27 in FIG. 2 and FIG. 5), which is the next process, will be described with the MOS transistors 71 and 72 as an example again.
As shown in FIG. 14A, search areas S1 and S2 are set for each of the MOS transistors 71 and 72 based on the respective shapes and the second condition data 52f of the control card 52 (see FIG. 10). . Then, the figures in the search areas S1 and S2 are extracted from the figures included in the set mask layers (for example, the mask layer for forming the polysilicon pattern and the mask layer for forming the diffusion layer), respectively. To do. That is, as shown in FIG. 14B, a figure group 81a included in the search area S1 set corresponding to the MOS transistor 71 and a figure group 81b included in the search area S2 set corresponding to the MOS transistor 72. And extract. At this time, the frames of the extracted graphic groups 81a and 81b are the same as the frame shapes of the search areas S1 and S2. In addition, in FIG. 14, the up-down direction is displayed short.

  Then, the origin of the plurality of extracted graphic groups 81a and 81b is set to a predetermined position (in this embodiment, the lower left vertex), and the coordinates of the graphic included in the graphic groups 81a and 81b are converted into coordinates based on the origin. The subsequent graphic groups 81a and 81b are subjected to logical operation processing (XOR processing). By converting the coordinates of each figure into coordinate values in a coordinate system with the origin as a reference, the coordinates of each figure are made relative to the origin. As a result, the coordinates of the figures present at the same position relative to the origin in each figure group are the same, so the calculation load is reduced.

  In the graphic groups 81a and 81b (see FIG. 14B) generated by the search areas S1 and S2 shown in FIG. 14A, one graphic group 81a is a MOS transistor 71 for which the pair arrangement is to be verified. , 72 (diffusion layers 61a and 61b and patterns 62a and 62b) and MOS transistors (diffusion layer 61c and pattern 62c) included in the search region S1, and the other graphic group 81b is a target for verifying the pair arrangement. Only MOS transistors 71 and 72 are included. Therefore, the diffusion layer 61b and the pattern 62b exist in the result 82 of the logical operation process shown in FIG. Therefore, it is determined that the MOS transistors 71 and 72 are not paired.

As another example, a specific example of the processing for verifying the pair arrangement by mirror inversion (step 28 in FIG. 2, FIG. 6) will be described.
In each data of the layout data 51 shown in FIG. 15A, the second condition data 52f of the control card 52 (AREA: Hole Metal -X = 1 um + X = 1 um-Y = 0 um + Search areas S3 and S4 (see FIG. 15B) are set in accordance with (Y = 0 um MIR). Next, the data of the mask layer for forming the metal wiring included in the search regions S3 and S4 and the data of the mask layer for forming the hole are searched to obtain the graphic groups 83a and 83b shown in FIG. . The figure group 83a includes the transistor 71, some patterns 65a and 65b of the patterns 63a and 63d, and holes 64c and 64e. The figure group 83b includes the transistor 72 and some patterns 63c and 63e. Patterns 65c and 65d and holes 64d and 64f are included.

  When logical operation processing (XOR processing) is performed on these graphic groups 83a and 83b, patterns 65a and 65b and holes 64c and 64e, graphic groups are included in the graphic group 83a as shown in FIG. In 83b, patterns 65c and 65d and holes 64d and 64f remain. For this reason, both figure groups 83a and 83b do not coincide.

  Next, as shown in FIG. 10, in the second condition data 52f of the control card 52, in the [AREA] designating the search range, mirror inversion is performed on the figure extracted by the [Hole, Metal] mask layer. An instruction [MIR] that permits the above is described. For this reason, as shown in FIG. 15D, a figure group 83c in which the mirror is inverted on the Y axis is generated. The figure group 83c is compared with the non-inverted figure group 83a. In this case, since no figure remains in the result of the logical operation process, the process proceeds to the next inter-pair MOS transistor verification process as a candidate for pair arrangement.

A specific example of the inter-pair arrangement MOS transistor verification process (step 29 in FIG. 2, FIG. 7) will be described with reference to FIGS.
First, it is determined whether or not an element extracted as a candidate for pair arrangement is a MOS transistor. If it is not a MOS transistor, the pair placement MOS transistor verification process is unnecessary, and therefore it is determined that the pair placement is completed. In the case of a MOS transistor, it is determined whether or not there is a division of the gate terminal.

  FIG. 16 shows a specific example when the gate terminal is not divided. In the MOS transistors 905 and 906 shown in FIG. 16A, the positions of the source terminals 94a and 94b with respect to the gate terminals 95a and 95b are confirmed. The MOS transistor 905 has a source terminal 94a disposed on the left side of the gate terminal 95a, and the MOS transistor 906 has a source terminal 94b disposed on the left side of the gate terminal 95b. Accordingly, it is determined that the positions of the source terminals of the MOS transistors 905 and 906 are equal to the gate terminal. Therefore, the directions of the drain currents of both the MOS transistors are equal, and it is determined that the MOS transistors 905 and 906 are paired. On the other hand, for the MOS transistors 905 and 907 shown in FIG. 16B, the MOS transistor 905 has a source terminal 94a disposed on the left side of the gate terminal 95a, and the MOS transistor 907 has a source terminal 94c disposed on the right side of the gate terminal 95c. Has been. Therefore, it is determined that the positions of the source terminals of the MOS transistors 905 and 907 are not equal to the gate terminal. The directions of the drain currents of the two MOS transistors are different, and it is determined that the MOS transistors 905 and 907 are not paired.

  FIG. 17 shows a specific example in the case where the gate terminal is divided. When there is a division of the gate terminal, first, a gate terminal as a target to be focused on when confirming the source terminal position is determined. Since the source terminal and the drain terminal are alternately arranged in the layout of the MOS transistor, it is only necessary to pay attention to one gate terminal located at the same position between the MOS transistors whose pair arrangement is verified. This is because, if the positions of the adjacent source terminals with respect to one gate terminal at the same position between the MOS transistors are the same, the positions of the source terminals are equal for the other divided gate terminals. In the MOS transistors 908 and 909 shown in FIG. 17A, attention is paid to the leftmost gate terminals 95d and 95g as target gate terminals in the present embodiment. The MOS transistor 908 has a source terminal 94d disposed on the left side of the gate terminal 95d, and the MOS transistor 909 has a source terminal 94f disposed on the left side of the gate terminal 95g. Accordingly, it is determined that the positions of the source terminals of the MOS transistors 908 and 909 are equal to the gate terminals. Therefore, the directions of the drain currents of both the MOS transistors are equal, and it is determined that the MOS transistors 908 and 909 are paired. On the other hand, regarding the MOS transistors 908 and 910 shown in FIG. 17B, focusing on the leftmost gate terminals 95d and 95j as the target gate terminals, the MOS transistor 908 has a source terminal 94d disposed on the left side of the gate terminal 95d. The MOS transistor 910 has a source terminal 94h disposed on the right side of the gate terminal 95j. Accordingly, it is determined that the positions of the source terminals of the MOS transistors 908 and 910 are not equal to the gate terminal. The directions of the drain currents of the two MOS transistors are different, and it is determined that the MOS transistors 908 and 910 are not paired.

The case where two elements are extracted as the target for verifying the pair arrangement has been described above, but the case where the target for verifying the pair arrangement is three or more elements may be used.
(Case 1)
For example, as shown in FIG. 18 (a), the differential section is composed of four transistors A1, A2, B1, and B2. In this case, in order to make the transistor characteristics of the transistor group A by the transistors A1 and A2 connected in parallel with the transistor characteristics of the transistor group B by the transistors B1 and B2 connected in parallel, shown in FIG. Thus, the transistors A1, A2, B1, and B2 may be alternately arranged.

  In the transistor arranged as described above, the center coordinate of each element is used as a reference. Then, the distances between the transistors A1 and A2 constituting one transistor group A and the transistors B1 and B2 constituting the other transistor group B existing in the arrangement direction are calculated. For example, for the transistor A1, the distance between the transistor A1 and the transistors B1 and B2 existing in the arrangement direction is calculated.

As a verification condition,
(A) The distances between the elements existing in the arrangement direction all match in the arrangement direction,
(B) The total number of transistor pairs whose distances are calculated is set to be equal to the total number of arranged transistors−1.

  In the case of the transistors A1, A2, B1, and B2 arranged as shown in FIG. 18B, the right direction is the plus direction and the left direction is the minus direction in the figure, and the distance between the transistors B1 and B2 adjacent to the transistor A1. The distance between the transistor A2 and the adjacent transistor B2 is calculated. The calculation result is shown in FIG. All distances match. The calculated number of transistor pairs (= 3) matches the total number of arranged transistors (= 4) -1 (= 3). Accordingly, it is determined that the transistors A1, A2, B1, and B2 arranged as shown in FIG.

(Case 2)
As shown in FIG. 19A, verification in a differential section in which the number of corresponding transistors is different will be described. In this case, as shown in FIG. 19B, when the transistors A1 and A2 of the transistor group A and the transistors B1 to B3 of the transistor group B are alternately arranged, as in the above, FIG. , The distance between the transistor A1 and the adjacent transistors B1 and B2, and the distance between the transistor A2 and the adjacent transistors B2 and B3 are calculated. In this case, all the distances match, and the calculated number of transistor pairs (= 4) matches the total number of transistors arranged (= 5) -1 (= 4). Accordingly, it is determined that the transistors A1, A2, B1, B2, and B3 arranged as shown in FIG.

(Case 3)
In the above transistors A1, A2, B1, B2, and B3, as shown in FIG. 20A, when the transistors B2 and B3 are arranged adjacent to each other, the distance between the adjacent elements is adjacent to the transistor A1. The distance between the transistors B1 and B2 and the distance between the transistor A2 and the adjacent transistor B3 are calculated. In this case, the calculated number of transistor pairs (= 3) does not match the total number of transistors arranged (= 5) -1 (= 4). Therefore, it is determined that the transistors A1, A2, B1, B2, and B3 arranged as shown in FIG.

(Case 4)
As shown in FIG. 21A, when the transistors A1 to A4 and the transistors B1 to B3 are alternately arranged, the measurement result of the distance between adjacent transistors is as shown in FIG. In this case, all the distances match, and the calculated number of transistor pairs (= 6) matches the total number of transistors arranged (= 7) -1 (= 6). Therefore, it is determined that the transistors A1 to A4 and B1 to B3 arranged as shown in FIG.

(Case 5)
As shown in FIG. 22A, when the transistors A1 to A4 and the transistors B1 to B3 are arranged, the measurement result of the distance between adjacent transistors is as shown in FIG. In this case, all the distances match, but the calculated number of transistor pairs (= 4) does not match the total number of arranged transistors (= 7) -1 (= 6). Therefore, it is determined that the transistors A1 to A4 and B1 to B3 arranged as shown in FIG.

  FIG. 23 shows the determination result of each condition in the above cases 1 to 5 and the determination result for the pair arrangement. In each figure, in each condition, “OK” indicates that the condition is satisfied, and “NG” indicates that the condition is not satisfied. In the determination result for the pair arrangement, “OK” represents the determination result that the pair is arranged, and “NG” represents the determination result that the pair is not arranged.

Next, a case where the extracted elements are arranged in two directions (X direction and Y direction) will be described.
In this case, the distance in each direction is calculated. And as a verification condition,
(A) the distances between adjacent elements all coincide in the first direction (± X direction);
(B) the distances between adjacent elements all coincide in the second direction (± Y direction);
(C) The total number of transistor pairs whose distances are calculated matches the total number of arranged transistors.

(Case 6)
As shown in FIG. 24A, when the transistors A1 and A2 of the first transistor group and the transistors B1 to B3 of the second transistor group are arranged in a checkered pattern (checker pattern), the distance between each element The calculation result is as shown in FIG. In this case, the distances in the X direction and the Y direction match, and the calculated number of transistor pairs (= 5) matches the total number of transistors arranged (= 5). Therefore, it is determined that the transistors A1, A2, and B1 to B3 arranged as shown in FIG. In this case 6, the same result can be obtained even when the transistor B3 is not provided.

(Case 7)
When the transistors A1 and A2 of the first transistor group and the transistors B1 to B3 of the second transistor group are arranged in a checkered pattern (checker pattern) as shown in FIG. The calculation result is as shown in FIG. In this case, the distance between the transistor A1 and the transistor B1 is different from the distance between the transistor A2 and the transistors B2 and B3, and the total number of transistors (= 5) in which the calculated number of transistor pairs (= 5) is arranged. ). Therefore, it is determined that the transistors A1, A2, and B1 to B3 arranged as shown in FIG.

(Case 8)
As shown in FIG. 26 (a), when the transistors A1 and A2 of the first transistor group and the transistors B1 to B3 of the second transistor group are arranged to form different columns, respectively, The distance calculation result is as shown in FIG. In this case, the distance is not calculated in the column direction (X direction), the distances in the Y direction match, and the calculated number of transistor pairs (= 2) does not match the total number of transistors arranged (= 5). Therefore, it is determined that the transistors A1, A2, B1 to B3 arranged as shown in FIG.

  FIG. 27 shows the determination result of each condition in the above cases 6 to 8 and the determination result for the pair arrangement. In each figure, in each condition, “OK” indicates that the condition is satisfied, and “NG” indicates that the condition is not satisfied. In the determination result for the pair arrangement, “OK” represents the determination result that the pair is arranged, and “NG” represents the determination result that the pair is not arranged.

Here, the correspondence with the claims is as follows.
The net information, net list 54, and net list (from layout) 54 are examples of connection information extracted from the layout data of the semiconductor device.
The net list 56 is an example of a net list of a semiconductor device.
The comparison between the net list 54 and the net list 56 is an example of comparison between connection information extracted from the layout data of the semiconductor device and the net list of the semiconductor device.
The vertical and horizontal are examples of the length of each side constituting the outer shape of the resistance layer.
The center of the side in contact with the contact layer is an example of a reference point set on the side in contact with the contact layer.
The patterned contact layer is an example of a positional relationship between a reference point set on a side in contact with the contact layer and a reference point of the contact layer.

As described above, according to the present embodiment, the following effects can be obtained.
(1) First, a verification condition for a plurality of elements for verifying the pair arrangement is set, and the pair arrangement between the plurality of elements is verified based on the verification condition. Next, a search area is set for each of a plurality of elements whose pair arrangement is verified, a figure included in the search area is extracted for each element, and the shape of the figure extracted between the elements whose pair arrangement is verified is It was made to verify whether it is the same. As a result, a search area is set for multiple elements that are placed in pairs, the wiring in the search area is extracted, and the shape and placement position of each element including the extracted figure is verified. Since it is possible to verify a pair arrangement by extracting a figure that affects the element, erroneous determination can be reduced.

  (2) The element is recognized from the layout data 51 of the semiconductor device, and the shape and coordinate value of the element are stored. And the verification process was performed with respect to the recognized element. As a result, an element is extracted from the figure of the layout data 51, and it is verified whether or not the extracted element is pair-arranged. Therefore, the pair arrangement is verified even in the layout data 51 having no hierarchical structure. The number of visual check steps can be reduced.

  (3) Even if the resistance element has a different shape of the main body part, since the outer shape of the resistance layer and the shape of the contact layer are compared, verification of the pair arrangement considering the resistance element having a different shape of the main body part should be performed. Can do. It is not necessary to rely on visual inspection to confirm whether or not the pair placement by the method of performing the pair placement while suppressing the area of the resistance element, and it is possible to prevent the verification accuracy of the pair placement from being lowered.

  (4) A set of MOS transistors that are candidates for pair arrangement is extracted, the direction of the drain current is specified for the extracted set of MOS transistors, and the direction of the drain current is the same when the specified direction of the drain current is the same. A set of MOS transistors is recognized as a MOS transistor arranged in a pair. As a result, it is possible to verify the pair arrangement in consideration of aligning the direction of the drain current of the MOS transistor. Since the drain current directions of the MOS transistors arranged in pairs are aligned in the same direction, the transistor characteristics can be aligned.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, various conditions and settings for verifying the pair arrangement are included in the control card 52. However, the control card 52 may be divided into two or more data.
In the above embodiment, when the coordinate value is converted, the lower left vertex is used as the reference point, but it goes without saying that the present invention is not limited to this.
In the above embodiment, the outer shape of the resistance layer is compared by comparing the lengths of the sides constituting the outer shape of the resistance layer, but the XOR operation is performed with the reference point of the outer shape of the resistance layer as the origin. You may make it perform.
In the above embodiment, when comparing the shapes of the contact layers, the center of the side of the resistance element that contacts the contact layer is used as the reference point as the origin (0, 0). However, the present invention is not limited to this. In addition, for example, the reference point may be set on the side in contact with the contact layer in the main body portion of the resistance element. Other than that, it goes without saying that there is no problem as long as the reference points can compare the shapes of the contact layers.
In the above embodiment, the comparison of the shape of the contact layer is performed by making the contact layer into a figure, but there is no problem as long as the positional relationship of the contact layer can be specified and the shape can be compared.
In the above embodiment, the direction of the drain current is specified by confirming the position of the source terminal with respect to the gate terminal, but is not limited thereto. For example, the position of the drain terminal with respect to the gate terminal may be confirmed. Other than that, there is no problem as long as the direction of the drain current can be specified.
In the above embodiment, when the gate terminal is divided, attention is paid to the leftmost gate terminal, but it is needless to say that the present invention is not limited to this.

The technical ideas that can be grasped from the above embodiments are described below.
(Appendix 1)
A layout verification program for causing a computer system to execute layout verification of elements arranged in a semiconductor device,
Extracting a set of MOS transistors that are candidates for pair placement;
Identifying a direction of drain current for the set of MOS transistors;
Recognizing that the pair of MOS transistors is a MOS transistor arranged in a pair when the direction of the drain current is the same direction,
A layout verification program executed by the computer system.
(Appendix 2)
The step of specifying the direction of the drain current includes:
The layout verification program according to appendix 1, wherein the computer system is caused to execute a step of specifying a source terminal and / or a drain terminal of the MOS transistor.
(Appendix 3)
The step of specifying the source terminal or / and the drain terminal includes:
The layout verification program according to appendix 2, wherein the computer system is caused to execute a step of comparing connection information extracted from layout data of the semiconductor device and a net list of the semiconductor device.
(Appendix 4)
The step of extracting a set of MOS transistors that are candidates for the pair arrangement is as follows:
A condition setting step for setting verification conditions for a plurality of elements for verifying the pair arrangement;
An inter-device verification step for verifying a pair arrangement between the plurality of devices based on the verification conditions;
An area setting step for setting a search area for each of a plurality of elements for verifying the pair arrangement;
Extracting a figure included in the set region, and verifying whether or not the shape of the extracted figure is the same between the elements for verifying the pair arrangement, and a peripheral figure verification step,
The layout verification program according to any one of appendices 1 to 3, which is executed by the computer system.
(Appendix 5)
Recognizing an element from the layout data of the semiconductor device, and executing an element recognition step of storing the shape and coordinate value of the element;
The layout verification program according to appendix 4, wherein the condition setting step causes the computer system to execute a step of verifying the element recognized in the element recognition step.
(Appendix 6)
Storing connection information extracted from the layout data for the elements recognized in the element recognition step;
Comparing the connection information with a netlist of a semiconductor device to determine an element name of the recognized element;
The layout verification program according to appendix 5, which is executed by the computer system.
(Appendix 7)
The layout verification program according to any one of appendices 4 to 6, wherein the search area is set by enlarging a graphic extracted as a target according to a set value.
(Appendix 8)
If it is determined that the shape is different in the peripheral figure verification step, at least one of a reversal process for reversing a figure corresponding to one element of a plurality of elements about a predetermined axis and a rotation process for rotating the figure by a predetermined angle The computer system is caused to execute a step of verifying whether or not the figure after processing and the figure corresponding to another element are the same, and any one of Supplementary Notes 4 to 7 The layout verification program described in 1.
(Appendix 9)
The layout data is composed of data of a plurality of mask layers corresponding to a manufacturing process of a semiconductor device,
The layout verification program according to any one of appendices 5 to 8, wherein the search area is set for each mask layer.
(Appendix 10)
Note that the coordinate values of a plurality of elements for verifying the pair arrangement are converted to coordinates based on the origin at a predetermined position, and the shapes of the elements are compared based on the converted coordinate values. The layout verification program according to any one of 4 to 9.
(Appendix 11)
The coordinate value of the figure extracted based on the search area is converted into a coordinate based on the origin of the predetermined position, and the shape of the figure between the elements is compared based on the coordinate value after the conversion. The layout verification program according to any one of supplementary notes 4 to 10, characterized by:
(Appendix 12)
The layout verification program according to any one of appendices 4 to 11, which causes the computer system to execute a step of displaying an error when the shapes of the figures do not match.
(Appendix 13)
A layout verification program for causing a computer system to execute layout verification of elements arranged in a semiconductor device,
A step of extracting resistance elements having different shapes of a pair of main body portions that are candidates for pair placement;
A step of comparing the outer shape of the resistance layer that bears the main body portion of the resistance element between the resistance elements having different shapes of the set of main body portions;
A step of comparing the shape of the contact layer that bears the connection portion with the outside of the resistance element, between the resistance elements having different shapes of the set of main body portions;
A step of recognizing that the resistance elements having different shapes of the pair of main body portions are resistance elements arranged in pairs when the outer shape of the resistance layer and the shape of the contact layer match.
A layout verification program executed by the computer system.
(Appendix 14)
The step of comparing the outer shape of the resistance layer includes:
14. The layout verification program according to appendix 13, wherein the computer system is caused to execute a step of comparing the lengths of the sides constituting the outer shape of the resistance layer between the resistance layers.
(Appendix 15)
The step of comparing the outer shape of the resistance layer includes:
14. The layout verification program according to appendix 13, wherein the computer system executes the step of performing an XOR operation between the resistance layers using the reference point of the outer shape of the resistance layer as an origin.
(Appendix 16)
The step of comparing the shapes of the contact layers includes:
Causing the computer system to perform a step of comparing a positional relationship between a reference point set on a side of the main body portion of the resistance element that contacts the contact layer and a reference point of the contact layer between the contact layers The layout verification program according to any one of supplementary notes 13 to 15, wherein

The schematic block diagram of a layout verification apparatus. FIG. 3 is a schematic flowchart of a layout verification method. Flow diagram of layout verification method (verification processing between paired elements). Flow diagram of layout verification method (verification processing between paired resistors). Flow diagram of layout verification method (pair placement peripheral figure verification process). Flow chart of layout verification method (pair arrangement peripheral figure inversion rotation processing). Flow chart of layout verification method (verification processing between paired MOS transistors). Flow diagram of layout verification method (error processing and end processing). Explanatory drawing of layout data. Explanatory drawing of a control card. Explanatory drawing of the extracted element. (A), (b) is explanatory drawing of a verification process. (A), (b) is explanatory drawing of a verification process. (A)-(c) is explanatory drawing of a verification process. (A)-(d) is explanatory drawing of a verification process. (A), (b) is explanatory drawing of a verification process. (A), (b) is explanatory drawing of a verification process. (A) is a circuit diagram to be verified, (b) is a schematic layout diagram to be verified, and (c) is an explanatory diagram of a distance calculation result. (A) is a circuit diagram to be verified, (b) is a schematic layout diagram to be verified, and (c) is an explanatory diagram of a distance calculation result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. Explanatory drawing of a verification result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. (A) is a schematic layout diagram of a verification target, (b) is an explanatory diagram of a distance calculation result. Explanatory drawing of a verification result. (A)-(d) is a schematic layout drawing of verification object.

Explanation of symbols

11 Computer 12 Central processing unit (CPU)
13 Memory 14 Magnetic disk 15 Display device 16 Input device 17 External storage device 18 Bus 19 Recording medium 19a Optical disk 19b Magnetic medium 51 Layout data 52 Control card 52a Layer definition data 52b Interlayer connection definition data 52c Element extraction condition data 52d Pair request data 52e First condition data 52f Second condition data 52g Third condition data 53 Coordinate data 54 Net list (from layout)
55 MOS transistor source terminal and drain terminal position information 56 Net list (from circuit design)
57 Instance name correspondence information 58 of each net list Source terminal position information 59 of MOS transistor Work data 61a to 61c Diffusion layers 62a to 62c Patterns 63a to 63e formed of polysilicon Patterns 64a to 64f formed of metal Hole 65a to 65d Part of pattern 71 made of metal, 72 MOS transistors 81a and 81b Figure group 82 Results of logical operation processing of figure groups 81a and 81b 83a to 83c Figure groups 91a to 91d Resistance layers 92a to 92i Contact layers 92A to 92I Shaped contact layers 93a to 93d Resistive element body portions 94a to 94i Source terminals 95a to 95l Gate terminals 96a to 96i Drain terminals 901 to 904 Resistive elements 905 to 910 MOS transistors A1 to A4 transistors B1 to B3 Transistors C1 and C2 Element cells CL1 to CL4 Contact layers D1 to D4 Diffusion layers G1 and G2 Gate terminals R1 and R2 Resistive element body parts RL1 and RL2 Resistance layers S1 to S4 Search region

Claims (8)

A layout verification program for causing a computer system to execute layout verification of elements arranged in a semiconductor device,
Extracting a set of MOS transistors that are candidates for pair placement;
Identifying a direction of drain current for the set of MOS transistors;
Recognizing that the pair of MOS transistors is a MOS transistor arranged in a pair when the direction of the drain current is the same direction,
A layout verification program executed by the computer system. The step of specifying the direction of the drain current includes:
The layout verification program according to claim 1, wherein the computer system is caused to execute the step of specifying a source terminal and / or a drain terminal of the MOS transistor. The step of specifying the source terminal or / and the drain terminal includes:
3. The layout verification program according to claim 2, wherein the computer system is caused to execute a step of comparing connection information extracted from layout data of the semiconductor device and a net list of the semiconductor device. A layout verification program for causing a computer system to execute layout verification of elements arranged in a semiconductor device,
A step of extracting resistance elements having different shapes of a pair of main body portions that are candidates for pair placement;
A step of comparing the outer shape of the resistance layer that bears the main body portion of the resistance element between the resistance elements having different shapes of the set of main body portions;
A step of comparing the shape of the contact layer that bears the connection portion with the outside of the resistance element, between the resistance elements having different shapes of the set of main body portions;
A step of recognizing that the resistance elements having different shapes of the pair of main body portions are resistance elements arranged in pairs when the outer shape of the resistance layer and the shape of the contact layer match.
A layout verification program executed by the computer system. The step of comparing the outer shape of the resistance layer includes:
5. The layout verification program according to claim 4, wherein the computer system is caused to execute a step of comparing the lengths of the sides constituting the outer shape of the resistance layer between the resistance layers. The step of comparing the outer shape of the resistance layer includes:
5. The layout verification program according to claim 4, wherein the computer system executes the step of performing an XOR operation between the resistance layers, using the reference point of the outer shape of the resistance layer as an origin. 6. A layout verification method for verifying a layout of elements arranged in a semiconductor device,
Extracting a set of MOS transistors that are candidates for pair placement;
Identifying a direction of drain current for the set of MOS transistors;
And a step of recognizing that the pair of MOS transistors are MOS transistors arranged in pairs when the directions of the drain currents are the same. A layout verification method for verifying a layout of elements arranged in a semiconductor device,
A step of extracting resistance elements having different shapes of a pair of main body portions that are candidates for pair placement;
For a resistance element having a different shape of the set of main body parts, comparing the outer shape of the resistance layer that carries the main body part of the resistance element;
For the resistance elements having different shapes of the set of main body portions, a step of comparing the shape of the contact layer that bears the connection portion with the outside of the resistance elements;
A step of recognizing that the resistor elements having different shapes of the pair of main body portions are resistor elements arranged in pairs when the outer shape of the resistor layer and the shape of the contact layer match. Layout verification method.

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