JP2009086862A - Method for processing operation clock and bus signal of cpu incorporated in programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability on the operation of a programmable controller by removing noise from an operation clock and a bus signal of a CPU. <P>SOLUTION: A processing method includes a step for analyzing the frequency spectrum of each of a standard waveform of an operation clock and a bus signal measured in a first environment in which noise is suppressed when a CPU executes a sequence program and an actual waveform of the operation clock and the bus signal measured in a second environment in which noise is not suppressed; a step for digitally calculating the difference of both the frequency spectrums; a step for storing and registering the digitally calculated difference in a memory as data of a noise frequency included in the operation clock and the bus signal while the CPU executes the sequence program; and a step for suppressing the noise frequency components included in the operation clock and the bus signal while the CPU executes the sequence program by using the data of the noise frequency stored and registered in the memory when the CPU executes the sequence program in the second environment. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for processing an operation clock and a bus signal of a CPU built in a programmable controller.

  Programmable controllers are generally installed in factories and the like in a noise-prone environment. Conventionally, the built-in CPU and its series have been double-designed to prevent the CPU from running out of control due to noise, and a noise filter is provided. However, it was expensive and not necessarily able to provide high reliability.

Such a CPU runaway is not limited to a programmable controller, and a technology for preventing a CPU runaway due to noise intrusion has been conventionally proposed in general CPU-equipped electronic devices (Patent Documents 1, 2, etc.). .
JP 2001-236240 A JP 2001-188687 A

  According to the present applicant, as the cause of the CPU runaway, the operation clock and bus signal waveforms of the CPU are distorted due to noise, and the distortion points of the operation clock and bus signal waveforms are false operation clocks and bus signals. I thought it was partly because of the runaway.

 Therefore, the problem to be solved by the present invention is to suppress the noise frequency component from the operation clock and bus signal of the CPU, and to improve the reliability in the operation of the programmable controller controlled by the CPU.

  The present invention relates to a method for processing an operation clock and a bus signal indicating an operation frequency of a CPU that is built in a programmable controller and executes a sequence program, and is measured in a first environment in which noise is suppressed when the CPU executes the sequence program. Analyzing the frequency spectrum of each of the standard waveforms of the operating clock and bus signal and the actual waveforms of the operating clock and bus signal measured in the second environment where noise is not suppressed, and digitally calculating the difference between the two frequency spectra. A step of saving and registering the digitally calculated difference in a memory as data of a noise frequency included in an operation clock and a bus signal during execution of the sequence program by the CPU, and the CPU executing the sequence program in the second environment And a step of suppressing a noise frequency component included in an operation clock and a bus signal during execution of a sequence program by the CPU using noise frequency data stored and registered in the memory. Is.

  According to the present invention, since the operation clock and bus signal from which noise has been removed are given to the CPU, the reliability of the sequence program execution operation of the programmable controller can be greatly improved.

  According to the present invention, since noise is removed from the operation clock and the bus signal, the operational reliability of the programmable controller can be improved.

  Hereinafter, an operation clock and bus signal processing method of a CPU (microprocessor) built in a programmable controller according to an embodiment of the present invention will be described with reference to the accompanying drawings. The programmable controller includes the CPU, a program memory such as a system program and a sequence program, an auxiliary memory, other memories, an input / output circuit, and the like. The system program is a basic program for CPU operation control, and the sequence program is a user program. These are the same as a general programmable controller. The entire programmable controller is controlled by an operation clock and a bus signal indicating the operating frequency of the CPU. For this reason, if the operation clock and the bus signal include noise, the CPU cannot execute the sequence program normally and runs out of control. Therefore, in the embodiment, according to the flowchart shown in FIG. 1, the programmable controller analyzes the frequency spectrum of the CPU operation clock and the bus signal separately in the noise suppression environment and the noise environment, and the noise frequency component from both frequency spectra. Get the data.

  Hereinafter, the method will be described with reference to FIG. 1. In step n1, a programmable controller is placed in an environment in which noise is suppressed, and a sequence program is executed. This sequence program may be an actual factory where a control machine is arranged. In this factory or the like, an environmental state in which noise is suppressed is set, a programmable controller is arranged therein, and a sequence program is executed by the CPU. In step n2, a frequency spectrum analysis / arithmetic unit such as a DSP (digital signal processor) is used to analyze the frequency spectrum of the CPU operation clock and bus signal.

  Next, in step n3, the programmable controller is arranged in a noise environment where the factory is actually operated and noise is not suppressed, and the sequence program is executed. In step n4, the frequency spectrum of the CPU operation clock and bus signal is analyzed using the same frequency spectrum analysis / arithmetic apparatus as described above.

  After step n1 to step n4, in step n5, the frequency spectrum of the operation clock and bus signal under the noise suppression environment and the frequency spectrum of the operation clock and bus signal under the noise environment are digitized and the digital The obtained frequency spectrum difference is digitally calculated, and in step n6, the difference is stored in the memory as noise frequency data included in the operation clock and bus signal in a noise environment. This memory is a memory built in the programmable controller.

  The noise frequency described above changes with a time function in the execution process of the sequence program. Since this time function is related to the progress of execution of the sequence program, each program element in which the CPU executes the sequence program. Corresponds to noise frequency components included in each operation clock and bus signal involved.

  Next, when operating the programmable controller in a factory or the like under a noise environment, the CPU reads out the data of the noise frequency from the noise frequency data storage memory for each operation clock and bus signal output during execution of the sequence program. By canceling the noise frequency component included in the operation clock and bus signal with the read noise frequency component, the waveform of the operation clock and bus signal becomes a normal waveform, and the sequence program can be executed normally. No runaway occurs.

  FIG. 2 shows a block for understanding steps n1 and n2. The CPU 11 of the programmable controller 10 arranged under the noise suppression environment 16 sends an operation clock and a bus signal to the measurement unit 12 including a DSP or the like. Output. The measurement unit 12 includes a frequency spectrum analysis unit 13 and a digitization unit 14. The frequency spectrum analysis unit 13 analyzes the frequency spectrum of the operation clock and the bus signal input from the CPU 11 and digitally analyzes the analyzed frequency spectrum. The conversion unit 14 converts the digital signal and registers the first digital data of the frequency spectrum in the memory 15.

  FIG. 3 shows a block for the purpose of understanding steps n3 and n4, and shows a programmable controller 10, a measurement unit 12, and a memory 15 similar to FIG. The CPU 11 of the controller 10 is disposed under the noise environment 17. 2, the CPU 11 of the programmable controller 10 disposed under the noise environment 17 outputs an operation clock and a bus signal to the measurement unit 12 including a DSP or the like. The measurement unit 12 analyzes the frequency spectrum of the operation clock and bus signal input from the CPU 11, converts the analyzed frequency spectrum to digital, and registers the second digital data of the frequency spectrum in the memory 15.

  FIG. 4 shows a block for understanding steps n5 and n6. The first and second digital data registered in the memory are subjected to a difference calculation by the difference calculation unit 18, and the calculated difference data is converted into a noise frequency. It is registered in the memory 19 as data.

  As described above, the memory 19 is registered with the operation frequency of the CPU 11 of the programmable controller 10 arranged under the noise environment 17 and the noise frequency data included in the bus signal.

  FIG. 5 shows a block configuration of a programmable controller having a memory in which noise frequency data is registered and stored. In FIG. 5, the programmable controller 10 is disposed under a noise environment 17. The programmable controller 10 includes a CPU 11, a system program memory 20, a sequence program memory 21, a noise frequency data memory 19, another memory 22, and an input / output interface 23. In the programmable controller 10, the CPU 11 is controlled by the system program stored in the system program memory 20, executes the sequence program stored in the sequence program program memory 21, and controls the control machine 25 through the input / output device 24. It can be controlled.

  When the programmable controller 10 is operated in the noise environment 17, the CPU 11 stores the noise frequency data registered and stored in the noise frequency data memory 19 for each operation clock and bus signal output during the execution of the sequence program. Since the noise frequency component included in the operation clock and the bus signal is canceled with the read noise frequency component and the sequence program is executed with the operation clock and bus signal with the noise frequency component canceled, the CPU 11 does not run out of control. .

FIG. 1 is a flowchart for explaining a method of processing an operation clock and a bus signal of a CPU according to an embodiment of the present invention. FIG. 2 is a block diagram for understanding steps n1 and n2 of FIG. FIG. 3 is a block diagram for understanding steps n3 and n4 of FIG. FIG. 4 is a block diagram for understanding steps n5 and n6 of FIG. FIG. 5 is a block diagram of a programmable controller having a noise frequency component data memory.

Explanation of symbols

10 Programmable controller 11 CPU
DESCRIPTION OF SYMBOLS 12 Measurement part 13 Frequency spectrum analysis part 14 Digitization part 15 Memory 16 Noise suppression environment 17 Noise environment 18 Difference calculating part 19 Noise frequency data memory

Claims (1)

In a method of processing an operation clock and a bus signal indicating an operation frequency of a CPU built in a programmable controller and executing a sequence program,
Standard waveforms of the operation clock and bus signal measured in the first environment where noise is suppressed when the CPU executes the sequence program, and actual waveforms of the operation clock and bus signal measured in the second environment where noise is not suppressed Analyzing the frequency spectrum of
Digitally calculating a difference between the two frequency spectra;
Saving and registering the digitally calculated difference in a memory as data of a noise frequency included in an operation clock and a bus signal during execution of a sequence program by the CPU;
When the CPU executes the sequence program in the second environment, the CPU uses the noise frequency data stored and registered in the memory to suppress the noise frequency component included in the operation clock and bus signal during execution of the sequence program. When,
A method for processing an operation clock and a bus signal of a CPU built in a programmable controller.

Images