JP2009081859A - Oscillator, and electronic device having oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by preventing a decrease in negative resistance. <P>SOLUTION: An oscillator circuit includes a first terminal A, a second terminal B, a vibrator OSC that is connected to the first terminal A and the second terminal B, a first capacitor Cg that is connected to the first terminal A and a ground line GND supplying the ground electric potential, a second capacitor Cd that is connected to the second terminal B and the ground line GND, an inverter array of (m) inverters IN1 to IN3, where (m) is an odd number equal to or larger than three, which are connected in series between the first terminal A and the second terminal B, and a third capacitor Cf that is connected across an input terminal of the n-th (where (n) is an integer satisfying 1≤n≤m) inverter, counted from an input side of the inverter array and an output terminal of the (n+1)-th inverter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an oscillator using a vibrator and an electronic apparatus including the oscillator.

In electronic devices such as computers, there is an increasing demand for faster operation every year. These electronic devices control the operation timing of the circuits of each unit using a clock signal generated by a built-in oscillator. Therefore, in order to increase the operation speed of these electronic devices, it is necessary to increase the oscillation frequency of the oscillator. For example, Patent Document 1 discloses a third-order overtone oscillation circuit in which the amplification factor of an inverting amplifier is increased to improve oscillation startability.

Japanese Patent No. 3229900

However, the conventional method has a problem that the negative resistance decreases due to the parasitic component of the MOS transistor constituting the inverter, and the power consumption increases in order to obtain a desired negative resistance.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
Between a first terminal, a second terminal, a vibrator connected between the first terminal and the second terminal, and a ground line for supplying a ground potential to the first terminal. A first capacitor connected to the second capacitor, a second capacitor connected between the second terminal and the ground line, and m (between the first terminal and the second terminal). m is an odd number of 3 or more) inverter series connected in series, and the n + 1th input terminal of the inverter and the n + 1th (n is an integer of 1 ≦ n <m) counted from the input side of the inverter series And a third capacitor connected between the output terminal of the inverter.

According to this configuration, by connecting the third capacitor between the input terminal of the nth inverter and the output terminal of the (n + 1) th inverter and applying feedback, the oscillation loop of m inverters and vibrators is Since another oscillation loop can be formed, the negative resistance obstruction factor is reduced, and low power consumption can be realized.

[Application Example 2]
In the oscillator described above, the oscillator further includes an input terminal of the p-th (p is an integer other than n when 1 ≦ p <m) and p + 1-th inverter counted from the input side of the inverter row And a fourth capacitor connected between the output terminals of the oscillator.

According to this configuration, the fourth capacitor is further connected between the input terminal of another p-th inverter and the output terminal of the (p + 1) -th inverter, and feedback is applied to further reduce the negative resistance obstruction factor. In addition, further reduction in power consumption can be realized.

[Application Example 3]
In the oscillator described above, each of the m inverters includes a first active element and a second active element having drain terminals connected to each other, and the source terminal of the first active element has a resistance An element is connected to the ground line via a first load element that is a load element connected in parallel with a capacitive element, and a source terminal of the second active element is a second load element that is the load element An oscillator, characterized in that it is connected to a power supply voltage line for supplying a power supply voltage via the.

According to this configuration, the addition of the resistance element can suppress the inverter current, and the addition of the capacitance element increases the AC gain of the circuit, thereby reducing the negative resistance obstruction factor. High negative resistance can be maintained and low power consumption can be realized.

[Application Example 4]
In the oscillator described above, each of the m inverters includes a first active element and a second active element having drain terminals connected to each other, and the source terminal of the first active element has an inductance. An element is connected to the ground line via a first load element that is a load element connected in parallel with a capacitive element, and a source terminal of the second active element is a second load element that is the load element An oscillator, characterized in that it is connected to a power supply voltage line for supplying a power supply voltage via the.

According to this configuration, the addition of the inductance element can suppress the inverter current, and the addition of the capacitance element increases the AC gain of the circuit, thereby reducing the negative resistance obstruction factor. High negative resistance can be maintained and low power consumption can be realized.

[Application Example 5]
An electronic apparatus comprising the oscillator according to any one of the above, and controlled based on a signal output from the first terminal or the second terminal of the oscillator.

  According to this configuration, a low power consumption electronic device can be realized.

  Hereinafter, embodiments of an oscillator will be described with reference to the drawings.

(First embodiment)
<Configuration of oscillator>
First, the configuration of the oscillator according to the first embodiment will be described with reference to FIG. FIG.
1 is a circuit diagram illustrating a configuration of an oscillator according to a first embodiment. FIG.

As shown in FIG. 1, the oscillator 100 includes a first terminal A, a second terminal B, and a first terminal A.
A vibrator OSC composed of a SAW (Surface Acoustic Wave) vibrator connected between the first terminal A and the second terminal B; a ground line GND for supplying a ground potential to the first terminal A; Between the first capacitor Cg connected between the second terminal C and the second capacitor Cd connected between the second terminal B and the ground line GND, and between the first terminal A and the second terminal B. 3 connected in series to
(M = 3) inverters IN1 to IN3, the first (n = 1) inverter IN1 input terminal I1 and the second (n + 1 = 1 + 1) inverter IN2 output terminal O2 connected. 3 capacitors Cf.

The inverter IN1 includes an Nch transistor N1 that is a first active element and a Pch transistor P1 that is a second active element connected in series between a ground line GND and a power supply voltage line VDD that supplies a power supply voltage. ing. The inverter IN2 includes an Nch transistor N2 and a Pch transistor P2 connected in series between the ground line GND and the power supply voltage line VDD. The inverter IN3 includes an Nch transistor N3 and a Pch transistor P3 connected in series between the ground line GND and the power supply voltage line VDD.

Here, the principle that the negative resistance obstruction factor is reduced by connecting the third capacitor Cf between the input terminal I1 of the inverter IN1 and the output terminal O2 of the inverter IN2 will be described.

FIG. 5 is a circuit diagram showing a configuration of a conventional oscillator 103. As shown in FIG. 5, the conventional oscillator 103 does not include the third capacitor Cf connected between the input terminal I1 of the inverter IN1 and the output terminal O2 of the inverter IN2 shown in the oscillator 100 of FIG.

FIG. 6 is an equivalent circuit diagram of three inverters of the conventional oscillator 103. Inverter IN
1 includes an Nch transistor N1 and a Pch transistor P1, which are connected to a power supply voltage line VDD.
6 and the ground line GND are considered to be equivalent in terms of alternating current, and therefore, as shown in FIG. Can be replaced by C1. The inverter IN2 can also be replaced by the voltage controlled current source gm2Vgs2, the drain resistor Rd2, and the capacitor C2. The inverter IN3 can also be replaced by a voltage controlled current source gm3Vgs3, a drain resistor Rd3, and a capacitor C3.

By solving a node equation of Kirchhoff's law between the first terminal A and the second terminal B, the current Ix flowing through the three inverters IN1 to IN3 is expressed by the following expression (1).
Ix = jω (C1 + Cg) × Vgs1 = Ya × Vgs1 (1)
Note that the admittance Ya of C1 + Cg is Ya = jω (C1 + Cg). Also, V
gs1 is a gate-source voltage of the inverter IN1.

Next, the gate-source voltage Vgs2 of the inverter IN2 is expressed by the following equation (2).
Vgs2 = −gm1 × Vgs1 × Rd1 / (1 + Rd1 × Y2) (2)
The admittance Y2 of C2 is Y2 = jωC2.

Similarly, the gate-source voltage Vgs3 of the inverter IN3 is expressed by the following equation (3).
Vgs3 = −gm2 × Vgs2 × Rd2 / (1 + Rd2 × Y3) (3)
The admittance Y3 of C3 is Y3 = jωC3.

Further, the voltage Vout applied to the second capacitor Cd is expressed by the following equation (4).
Vout = (Ix + gm3 × Vgs3) × Rd3 / (1 + Rd3 × Yd) (4)
The admittance Yd of the second capacitor Cd is Yd = jωCd.

By substituting the equations (2) and (3) into the equation (4), the voltage Vout is expressed by the following equation (5).
It becomes.
Vout = − {Ix + gm1 × gm2 × gm3 × ((Rd1 × Rd2 × Vgs1) / (
1 + Rd1 × Y2) × (1 + Rd2 × Y3))} × (Rd3 / (1 + Rd3 × Yd)).
(5)

Amplifier gain coefficient Gm = gm1 × gm2 × gm3, resistance Rd = Rd1 × Rd2 × Rd3
Substituting Vgs1 = Ix / Ya from equation (1), and three inverters IN from equation (5)
When the negative resistance -Rx0 of 1 to IN3 is obtained, the following equation (6) is obtained.
−Rx0 = (1 / Ya) + {Rd3 / (1 + Rd3 × Yd)} + {Gm × Rd / (Ya
× (1 + Rd1 × Y2) × (1 + Rd2 × Y3) × (1 + Rd3 × Yd))} (6
)

When the imaginary number is removed from the equation (6) and only the real part is extracted, the negative resistance equation shown in the following equation (7) is obtained.
−Rx0 = {(− gm1) / (ω ² × (Cg + C1) × Cd)} × {(gm2 × Rd1
) / (1+ (ω × C2 × Rd1) ² )} × {(gm3 × Rd2) / (1+ (ω × C3 × R)
d2) ² )} × {1 / (1+ (1 / (ω × Cd × Rd3) ² )} + {Rd3 / (1+ (ω ×
Cd × Rd3) ² )} (7)

FIG. 2 shows three inverters IN1 to IN3 and a third capacitor C of the oscillator 100 of FIG.
It is an equivalent circuit diagram of f. Compared to the conventional equivalent circuit of FIG. 6, the input terminal I of the inverter IN1.
1 and the output terminal O2 of the inverter IN2, a third capacitor Cf is added. Therefore, the negative resistance equation of the negative resistances -Rx of the three inverters IN1 to IN3 of the oscillator 100 is The following equation (8) is obtained.
−Rx = {(− gm1) / (ω ² × (Cg + C1−Cf) × Cd)} × {(gm2 × R
d1) / (1+ (ω × C2 × Rd1) ² )} × {(gm3 × Rd2) / (1+ (ω × C3
× Rd2) ² )} × {1 / (1+ (1 / (ω × Cd × Rd3) ² )} + {Rd3 / (1+ (
ω × Cd × Rd3) ² )} (8)

That is, the denominator (Cg + C1−) in equation (8) is different from (Cg + C1) in the denominator in equation (7).
Cf), the negative resistance -Rx of the oscillator 100 increases.

  According to the present embodiment described above, the following effects can be obtained.

In the present embodiment, the input terminal I1 of the first inverter IN1 and the second inverter IN1
By connecting a third capacitor Cf between the two output terminals O2 and applying feedback, an oscillation loop different from the oscillation loop of the three inverters IN1 to IN3 and the transducer OSC can be formed. As a result, the power consumption can be reduced.

(Modification 1) Modification 1 of the oscillator will be described. In the first embodiment, the oscillator 1
00 is connected to the third capacitor Cf between the input terminal I1 of the first inverter IN1 and the output terminal O2 of the second inverter IN2 in the three inverters IN1 to IN3. A capacitor may be added for feedback. For example,
In the oscillator 100 of FIG. 1, another fourth capacitor may be connected between the input terminal I2 of the second inverter IN2 and the output terminal O3 of the third inverter IN3 to provide feedback.
With this configuration, the denominator of the equation (8) is further reduced and the negative resistance -Rx is increased, so that the negative resistance obstruction factor is reduced and low power consumption can be realized.

In the first embodiment, the case of m = 3 inverters has been described, but the same applies to three or more inverters. FIG. 3 is a circuit diagram illustrating a configuration of the oscillator 101 according to the first modification. As shown in FIG. 3, the oscillator 101 includes five inverters IN1 to IN5,
A third capacitor Cf1 is connected between the input terminal I1 of the first inverter IN1 and the output terminal O2 of the second inverter IN2, and the input terminal I2 of the second inverter IN2 and the output terminal of the third inverter IN3. A fourth capacitor Cf2 is connected to O3,
A fifth capacitor Cf3 is connected between the input terminal I3 of the third inverter IN3 and the output terminal O4 of the fourth inverter IN4. With this configuration, the negative resistance -R
Since x increases, negative resistance impeding factors are reduced, and low power consumption can be realized.

(Modification 2) Modification 2 of the oscillator will be described. FIG. 4 shows an oscillator 10 according to the second modification.
2 is a circuit diagram showing a configuration of 2. FIG. As shown in FIG. 4, in the first inverter IN11, N
The source terminal of the ch transistor N1 is connected to the ground line GND via a load element (first load element) in which the resistor element R12 is connected in parallel with the capacitor element C12. The source terminal of the Pch transistor P1 is connected to the resistor element R11 is connected to the power supply voltage line VDD via a load element (second load element) connected in parallel with the capacitive element C11. Similarly, in the second inverter IN12, the source terminal of the Nch transistor N2 is such that the resistance element R22 is the capacitive element C22.
22 is connected to the ground line GND through a load element connected in parallel with the node 22, and the source terminal of the Pch transistor P2 is connected to the power supply voltage line VDD via a load element in which the resistor element R21 is connected in parallel with the capacitor element C21. It is connected. Furthermore, in the third inverter IN13, N
The source terminal of the ch transistor N3 is connected to the ground line GND through a load element in which the resistor element R32 is connected in parallel with the capacitor element C32. The resistor terminal R31 of the source terminal of the Pch transistor P3 is in parallel with the capacitor element C31. Power supply voltage line VD through a load element connected to
D is connected.

According to this configuration, the inverter I is obtained by adding the six resistance elements R11 to R32.
The current of N11 to IN13 can be suppressed, and the gain is increased by adding the six capacitive elements C11 to C32. Therefore, the negative resistance becomes constant, and low power consumption can be realized.

(Modification 3) Modification 3 of the oscillator will be described. In the first embodiment, the vibrator OS
Although the case where C is composed of SAW vibrators has been described, tuning fork vibrators, AT vibrators, FBARs (
Film Bulk Acoustic Resonator), MEMS vibrator, SMR (Solid Mounted Resonator)
) Or the like.

(Modification 4) Modification 4 of the oscillator will be described. In the first modification, the oscillator 101 including the five inverters IN1 to IN5 as illustrated in FIG. 3 has been described. However, the oscillator 104 as illustrated in FIG. 7 may be configured. FIG. 7 is a circuit diagram illustrating a configuration of an oscillator according to the fourth modification. As shown in FIG. 7, a third capacitor Cf1 is connected between the input terminal I1 of the inverter IN1 and the output terminal O2 of the inverter IN2, and the input terminal I1 of the inverter IN1.
And a fourth capacitor Cf2 may be connected between the inverter IN4 and the output terminal O4 of the inverter IN4.
With this configuration, by adding the fourth capacitor Cf2, the magnitude of the negative resistance and the frequency at which the negative resistance becomes maximum can be selected more flexibly than when there is only one third capacitor.

(Modification 5) Modification 5 of the oscillator will be described. In the first embodiment, the first capacitor Cg and the second capacitor Cd have been described as using fixed-capacitance capacitors. However, the capacitance is controlled by the control voltage Vc as in the oscillator 105 shown in FIG. Controllable variable capacitance diodes VCg and VCd may be used. In this case, the variable capacitance diode VCg and the first
It is necessary to insert DC-cut capacitors DC1 and DC2 between the two terminals A and between the variable capacitance diode VCd and the second terminal B.

(Modification 6) Modification 6 of the oscillator will be described. In the above-described modification 2, the case where the resistive element is a load element connected in parallel with the capacitive element has been described. However, as in the oscillator 106 shown in FIG. 9, the inductance element is a load element connected in parallel with the capacitive element. May be. FIG.
Instead of the six resistance elements R11 to R32, the six inductance elements L11 to L3, respectively.
2 is connected.

(Modification 7) Modification 7 of the oscillator will be described. In the second modification, the case where the resistive element is a load element connected in parallel with the capacitive element has been described, but the oscillator 107 shown in FIG.
As described above, the six variable capacitance diodes VC11 to VC32 whose capacitance can be controlled by the control voltage Vc of the six capacitance elements C11 to C32 and the DC cut capacitors DC11 to DC3.
2 may be substituted. As in the oscillator 108 shown in FIG. 11, the six resistance elements R11 to R32 in FIG. 10 may be replaced with six inductance elements L11 to L32.

(Modification 8) An example of an electronic device using an oscillator will be described. FIG. 12 is a schematic diagram illustrating a configuration of a mobile phone that is an electronic device using the oscillator according to the modification 8. Cell phone 1200
Includes a main body 1210 including operation buttons and a display 1220 including a liquid crystal panel.
Are connected by a hinge part 1230 so as to be foldable. Main body 121
0 includes a built-in oscillator 100 (or any one of 101, 102, and 104 to 108), and the oscillator 100 is controlled based on a signal output from the first terminal A or the second terminal B (not shown). The display unit 1220 includes a receiving circuit (not shown), and data such as a moving image, a still image, and voice is transmitted and received from the main body unit 1210 to the display unit 1220 by wireless communication. By configuring the cellular phone 1200 with the oscillator 100, the transmission circuit, and the reception circuit, data such as a moving image, a still image, and voice can be transferred from the main body 1210 to the display unit 1220 at high speed. Note that the electronic device using the oscillator 100 can be applied to a wristwatch, a PDA, a remote controller, a portable music player, and the like that are small battery driven and require low power consumption.

1 is a circuit diagram showing a configuration of an oscillator according to a first embodiment. FIG. 2 is an equivalent circuit diagram of three inverters and capacitors of the oscillator of FIG. 1. FIG. 6 is a circuit diagram showing a configuration of an oscillator according to Modification 1; FIG. 9 is a circuit diagram showing a configuration of an oscillator according to Modification 2. The circuit diagram which shows the structure of the conventional oscillator. The equivalent circuit diagram of three inverters of the conventional oscillator. FIG. 10 is a circuit diagram showing a configuration of an oscillator according to Modification 4; FIG. 10 is a circuit diagram showing a configuration of an oscillator according to Modification 5. FIG. 10 is a circuit diagram showing a configuration of an oscillator according to Modification 6. FIG. 10 is a circuit diagram showing a configuration of an oscillator according to Modification 7. FIG. 10 is a circuit diagram showing a configuration of an oscillator according to Modification 7. FIG. 10 is a block diagram showing a configuration of an electronic device using an oscillator according to Modification Example 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Oscillator 101 ... Oscillator 102 ... Oscillator 103 ... Oscillator 104 ... Oscillator 105 ... Oscillator 106 ... Oscillator 107 ... Oscillator 108 ... Oscillator 1200 ... Mobile phone.

Claims (5)

A first terminal;
A second terminal;
A vibrator connected between the first terminal and the second terminal;
A first capacitor connected between the first terminal and a ground line for supplying a ground potential;
A second capacitor connected between the second terminal and the ground line;
An inverter array in which m (m is an odd number of 3 or more) inverters are connected in series between the first terminal and the second terminal;
A third capacitor connected between the input terminal of the nth inverter (n is an integer of 1 ≦ n <m) and the output terminal of the (n + 1) th inverter counted from the input side of the inverter row;
including,
An oscillator characterized by that. The oscillator according to claim 1, wherein
The oscillator is further p-th counting from the input side of the inverter row (p is 1 ≦ p <m
A fourth capacitor connected between the input terminal of the inverter and the output terminal of the (p + 1) th inverter;
An oscillator comprising: The oscillator according to claim 1 or 2,
Each of the m inverters includes a first active element and a second active element whose drain terminals are connected to each other. The source terminal of the first active element has a resistance element in parallel with the capacitive element. It is connected to the ground line via a first load element that is a connected load element, and the source terminal of the second active element supplies a power supply voltage via the second load element that is the load element. An oscillator characterized by being connected to a power supply voltage line. The oscillator according to claim 1 or 2,
Each of the m inverters includes a first active element and a second active element having drain terminals connected to each other, and the source terminal of the first active element has an inductance element in parallel with a capacitive element. Connected to the ground line via a first load element which is a connected load element;
The oscillator characterized by the source terminal of the said 2nd active element being connected to the power supply voltage line which supplies a power supply voltage via the 2nd load element which is the said load element. An electronic apparatus comprising the oscillator according to claim 1, wherein the electronic apparatus is controlled based on a signal output from the first terminal or the second terminal of the oscillator.

Images