JP2009077222A - Terminal device, center device, optical communication network system, and uplink signal timing control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To independently set bit rates of an uplink signal and a downlink signal in PON and thereby facilitate processing for establishment of synchronization and attain low cost. <P>SOLUTION: The uplink signal timing control method of the present invention is applicable to PON. The method is to control the timing of an uplink optical signal from the terminal device to a center device at an ideal timing. The center device transmits optical clock pulses in synchronism with the ideal timing to the terminal device and the terminal device subjects the incoming optical clock pulses to delay control and transmits them in return. The center device detects a timing shift between the ideal timing and the returned optical clock pulses, and reflects digital data at least containing timing shift information on waveforms of outgoing optical clock pulses. The terminal device performs delay control to the optical clock pulses received in response to the incoming digital data. The center device assumes completion of timing control when the timing shift is less than a threshold. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a terminal device, a center device, an optical communication network system, and an uplink signal timing control method. For example, in a PON (Passive Optical Network), time division multiplexing is performed between a center (central station) device and a plurality of terminal devices. (TDM: Time Division Multiplexing) Bidirectional Time Division Multiplexing Optical Communication Network System for Bidirectional Communication (In particular, Time Slot Control Method for Establishing Uplink Signal Synchronization from Terminal Device to Center Device) And a configuration for realizing this control method).

  With the realization of broadband communication, it is believed that anyone can use high-speed, high-quality communication at low cost. In GE-PON (Gigabit Ethernet (registered trademark) -Passive Optical Network), which is attracting attention as a subscriber optical access network, a packet-multiplexed signal is transmitted from the OLT (Optical Line Terminal) to the terminal side. By simultaneously distributing and performing self-other signal identification on the ONU (Optical Network Unit) side, an appropriate signal can be received. However, the uplink signal (signal from ONU to OLT) is subjected to complex control based on TDMA (Time Division Multiple Access) in order to avoid signal collision in the optical branching device. When loaded, it is difficult to talk at the same bit rate above and below. In the future, with the emergence of applications such as file sharing typified by Pear-to-Pear, traffic from each subscriber is expected to increase, so a new optical access network that enables two-way bandwidth guarantee will be developed. Realization at low cost is desired, and Patent Documents 1, 2, and 3 have been proposed.

  The network described in Patent Document 1 includes a station-side device, a station-side device that solves one transmission path among a plurality of transmission paths, and a subscriber apparatus that transmits and receives signals. The apparatus is provided with transmission path information transmitting means for transmitting operational type information indicating which transmission path is currently used and standby state information indicating a failure in the standby system to the station side apparatus. It is characterized by comprising transmission path monitoring means for receiving system information and standby system status information and monitoring the status of the transmission path. In the network configuration described in the embodiment, the station side device and the optical subscriber line termination unit are branched by the star coupler via the optical subscriber line, and the downlink signal multiplexing system is TDM (Time Division Multiplexing), This is an optical burst signal multiplex transmission system that uses TDMA (Time Division Multiple Access) for multiplexing of upstream burst signals and TCM (Time Compression Multiplexing) for bidirectional transmission, and shows an example in which the optical transmission path has a duplex configuration. Yes. At present, an optical network configured by branching by a star coupler via a station side device and an optical subscriber line termination unit via an optical subscriber line is called a PON, and in particular, one-core bidirectional Since PON can realize FTTH at low cost, it has been actively researched in recent years.

  The optical access network system disclosed in Patent Document 2 can increase the capacity of downstream signals while maintaining compatibility with an optical access network system using a conventional PON without increasing the speed of ONUs constituting the system. It has the feature of being possible.

  Non-Patent Document 1 describes a system using GE-PON as an optical access network system based on the TDM method that has been attracting attention in recent years. A great merit of GE-PON is that a 1 Gbit / sec band between the OLT and the ONU can be secured, and the spread of subscriber traffic has been increasing in recent years.

  In addition, as all the media will be integrated into IP as will be attracting attention in the next generation network (NGN), in the near future, even sending and receiving from each subscriber's home will be several hundred M to 1 Gbit / sec. It is easily anticipated that there will be an era in which the required bandwidth is constantly required, and a new high-speed access network that replaces the GE-PON based on the statistical multiplexing effect should be provided at a low cost.

In the system described in Patent Document 3, different wavelengths are assigned to the respective channels. Therefore, each channel does not need to establish synchronization like the PON based on the above-mentioned TDM, and the upstream signal and the downstream are independently set. Since it is possible to set the signal to the same bit rate, the system configuration is simplified as compared with the PON based on TDM.
JP 2000-49702 A JP 11-298430 A JP 2004-222255 A “GE-PON Technology, 3rd DBA Function”, NTT Technical Journal, October 2005, pp. 67-70

  However, in the optical access network system described in Patent Document 2, the exact distance from the optical branching / combining device (star coupler) constituting the PON to each ONU is determined in advance, and the time slot of the upstream signal is set in advance to the OLT. It is necessary to set parameters for recognizing and establishing synchronization.

  The system described in Non-Patent Document 1 does not guarantee a 1 Gbit / sec bandwidth between subscriber interfaces. For example, when 32 ONUs are shared by all subscribers, Only a minimum of about 30 Mbit / sec can be secured. Therefore, when the subscriber traffic tries to transmit / receive data of about 50 Mbit / sec at a time, a congestion state occurs, and the throughput is significantly reduced due to packet collision or the like. Such a situation is likely to occur at the present time when streaming distribution becomes familiar. Further, in the system described in Non-Patent Document 1, software based on complicated algorithms necessary for maintaining the fairness of bandwidth utilization efficiency and control for preventing collision of upstream signals transmitted from each ONU to the OLT Processing is essential.

  Furthermore, the WDM system PON described in Patent Document 3 needs to prepare light sources corresponding to the number of ONUs in the OLT, and requires abundant wavelength resources. In order to secure abundant wavelength resources, it is necessary to prepare a plurality of wavelength light sources that are precisely wavelength-controlled, and the realization of cost becomes a problem in practice.

  Therefore, a terminal device, a center device, and an optical communication network system that can independently set the bit rate of the uplink signal and the downlink signal without performing periodic band allocation, can easily perform the process for establishing synchronization, and can achieve low cost. In addition, an uplink signal timing control method is desired.

  An uplink signal timing control method according to a first aspect of the present invention includes: (1) an uplink signal timing control method for controlling an uplink optical signal timing from a terminal apparatus to a center apparatus to a timing intended by the center apparatus; ) An optical clock pulse synchronized with the timing is transmitted from the center apparatus to the terminal apparatus. (3) The terminal apparatus delays the optical clock pulse and sends it back to the center apparatus. (4) The center apparatus detects a timing shift between the timing and the returned optical clock pulse, forms digital data including at least the timing shift information, and transmits the digital data to the waveform of the optical clock pulse to be transmitted. The terminal device transmits the digital signal reflected in the received optical clock pulse. Data is extracted, and the delay control is performed in accordance with the timing shift information included in the extracted digital data. (5) The center device shifts the timing between the timing and the returned optical clock pulse. Is characterized in that the completion of the timing control of the upstream optical signal is captured when is equal to or less than the threshold value.

  A center device according to a second aspect of the present invention is (1) the center device in the optical communication network system in which one or a plurality of terminal devices are accommodated in the center device, and each of the terminal devices and the center device constitute a PON. , (2) generating an optical clock pulse synchronized with the timing of an upstream signal from the terminal device to be controlled to the center device, and controlling the terminal device to be controlled with the waveform of the optical clock pulse An optical clock pulse generating / transmitting means for transmitting an optical signal reflecting digital data to be transmitted to the current terminal device to be controlled; and (3) delay control from the timing and the terminal device to be controlled. Timing comparison means for detecting the timing deviation of the returned optical clock pulse, and (4) the detected timing deviation from the threshold value. (5) detected timing difference information adding means for causing the terminal device to transmit the optical clock pulse generation / transmission means including the timing deviation information in the digital data reflected in the transmitted optical clock pulse. And timing control completion recognition means for recognizing completion of the timing control.

  A terminal device according to a third aspect of the present invention is (1) in the terminal device in an optical communication network system in which one or a plurality of terminal devices are accommodated in a center device, and each of the terminal devices and the center device constitute a PON. (2) Optical clock pulse return means for returning an optical clock pulse coming from the center device, and extracting digital data reflected in the optical clock pulse coming from the center device, and being included in the digital data Delay means for delaying the optical clock pulse to be returned in accordance with the received information.

  An optical communication network system according to a fourth aspect of the present invention includes: (1) an optical communication network system in which one or a plurality of terminal devices are accommodated in a center device, and each of the terminal devices and the center device constitute a PON; 2) The center device of the second invention is applied as the center device, and (3) the terminal device of the third invention is applied as each terminal device.

  According to the terminal device, the center device, the optical communication network system, and the uplink signal timing control method of the present invention, the bit rate of the uplink signal and the downlink signal can be set independently without performing periodic band allocation, and synchronization is established. This process is simple and can achieve low cost.

(A) Main Embodiment Hereinafter, an embodiment of a terminal device, a center device, an optical communication network system, and an uplink signal timing control method according to the present invention will be described in detail with reference to the drawings. Note that the optical communication network system of this embodiment is a bidirectional time division multiplexing optical communication network system. Further, the terminal device and the center device of this embodiment are an ONU and an OLT.

(A-1) Configuration of Embodiment FIG. 2 is a block diagram showing the overall configuration of the bidirectional time division multiplexing optical communication network system 1 of this embodiment.

  The bidirectional time division multiplexing optical communication network system 1 includes an OLT 101, an optical splitter 102, and an ONU 103.

  The bidirectional time division multiplexing optical communication network system 1 has a PON (Passive Optical Network) configuration in which a branching device is inserted in the middle of an optical fiber network and a single fiber is shared by a plurality of terminals.

  The OLT 101 is a station side (center side) termination device (OLT: Optical Line Terminal), and the ONU 103 is a subscriber side termination device (ONU: Optical Network Unit). Here, it is assumed that the bidirectional time division multiplexing optical communication network system 1 has four ONUs 103 (103-1 to 103-4).

  The optical splitter 102 branches one optical fiber connected to the OLT 101 and connects it to each ONU 103-1 to 103-4. Note that a commercially available optical splitter can be used as the optical splitter 102.

  Bidirectional communication using time division multiplexing (TDM) is performed between the OLT 101 and the ONUs 103-1 to 103-4. Also, in downlink (OLT 101 to ONU 103) communication and uplink (ONU 103 to OLT 101) communication, full-duplex communication is performed using a single optical fiber by changing the wavelength of the carrier used for communication. To do. In the following description, it is assumed that the wavelength of the carrier wave used for downlink communication is “λ0” and the wavelength of the carrier wave used for uplink communication is “λ1”.

  FIG. 3 is a block diagram showing the internal configuration of the OLT 101. The OLT 101 includes a router 201, an OTDM multiplexing unit 202, an OTDM separation unit 204, and an optical circulator 203. The router 201 is a communication device located at the boundary with the upper network in the bidirectional time division multiplexing optical communication network system 1, and all the data is transmitted to the lower network (OTDM multiplexing unit 202, ONU 103) based on the same clock. Is sent. Here, NRZ (Non Return to Zero) signal data is given from router 201 to OTDM multiplexing section 202.

  The OTDM multiplexing unit 202 has a function of, for example, converting the NRZ signal input from the router 201 into an RZ (Return to Zero) signal, and transmitting the time-division multiplexed signal to the ONU 103 by bit interleaving. I'm responsible.

  The optical circulator 203 transmits and receives an optical signal to and from a plurality of ONUs 103 by using a single transmission line optical fiber. Then, the optical fiber is branched and an optical signal is sent out to the route of the OTDM separation unit 204. As the optical circulator 203, for example, a commercially available optical circulator can be used.

  FIG. 4 is a block diagram showing an internal configuration of the OTDM multiplexing unit 202. The OTDM multiplexing unit 202 includes a CW light source 301, an isolator 302, three modulators 303 (303-1 to 303-4), three quarter delay units 304 (304-1 to 304-3), and four ESWs 305 ( 305-1 to 305-4), an NRZ / RZ conversion unit 306, an ESW drive circuit 307, and a delay device 308. The functions of the components 301 to 308 of the OTDM multiplexing unit 202 will be clarified in the description of operations described later.

  FIG. 5 is a block diagram showing the internal configuration of the NRZ / RZ conversion unit 306. The NRZ / RZ conversion unit 306 includes four O / E converters 401 (401-1 to 401-4), a clock extractor 402, four multiplication circuits 403 (403-1 to 403-4), and a pulse constrictor. 404. The functions of the constituent elements 401 to 404 of the NRZ / RZ conversion unit 306 will be clarified in the operation description to be described later.

  FIG. 6 is a block diagram showing an internal configuration of the OTDM separation unit 204. The OTDM separation unit 204 includes four voltage intensity detectors 501 (501-1 to 501-4), four O / E converters 502 (502-1 to 502-4), a phase difference detection unit 503, and a control packet generation. Part 504 and four BPDs 505 (505-1 to 505-4). The functions of the components 501 to 505 of the OTDM separation unit 204 will be clarified in the description of operations described later.

  FIG. 7 is a block diagram illustrating an internal configuration of the control packet generation unit 504. The control packet generation unit 504 includes a signal strength determination unit 600, a timing detection unit 601, a CPU 602, a memory 603, a signal generation unit 604, and a counter 605. The functions of the constituent elements 600 to 605 of the control packet generation unit 504 will be clarified in the description of operations described later.

  FIG. 8 is a block diagram showing an internal configuration of the phase difference detection unit 503. The phase difference detection unit 503 includes an optical coupler 701, four modulators 702-1 to 702-4, four optical couplers 703-1 to 703-4, and three quarter-bit delay units 704-1 to 704-. 3. The functions of the components 701 to 704 of the phase difference detection unit 503 will be clarified in the operation description to be described later.

  FIG. 9 is a block diagram showing an internal configuration of each of the ONUs 103-1 to 103-4. Each of the ONUs 103-1 to 103-4 includes an optical circulator 801, an O / E converter 802, a clock pulse generation unit 803, a multiplication circuit 804, a BPS 805, a media converter 806, a control packet decoding unit 807, a variable delay control circuit 808, A variable delay unit 809, a 1-bit delay unit 810, a multiplication circuit 811, a modulator 812, a CW light source 813, an OSW 814, and a termination unit 815 are provided. The functions of the components 801 to 815 of the ONU 103 will be clarified in the description of operations described later.

  FIG. 10 is a block diagram showing an internal configuration of the control packet decoding unit 807. The control packet decoding unit 807 includes a timing detection unit 901, a memory 902, a data comparison unit 903, a signal generation unit 904, and a CPU 905. The functions of the components 901 to 905 of the control packet decoding unit 807 will be clarified in the description of operations described later.

  FIG. 11 is a block diagram illustrating an internal configuration of the clock pulse generation unit 803. The clock pulse generation unit 803 includes a clock extractor 1001, a frequency divider 1002, a pulse constrictor 1003, and a ¼ bit delay unit 1004. The functions of the constituent elements 1001 to 1004 of the clock pulse generation unit 803 will be clarified in the operation description to be described later.

(A-2) Operation of Embodiment Next, an operation in the bidirectional time division multiplexing optical communication network system 1 having the above-described configuration will be described. An operation (control method) related to time slot control for establishing synchronization of an uplink signal from the ONU 103 (103-1 to 103-4) to the OLT 101, which is a feature of the embodiment in particular, will be described.

  The operation related to the control of the time slot for establishing synchronization, in other words, the synchronization establishing operation, for example, immediately after each element of the bidirectional time division multiplexing optical communication network system 1 is installed and can be activated, in other words, It is executed when the bidirectional time division multiplexing optical communication network system 1 is started up.

  Details of the method of this embodiment will be described below. The OLT 101 designates one of the plurality of ONUs 103-1 to 103-4, forms a feedback group with the designated ONU 103-i, and Establish synchronization with the ONU 103-i, and then specify another ONU 103-j and establish synchronization using the feedback group in the same manner as described above, and establish synchronization with such one ONU. This is a method of establishing synchronization with all the ONUs 103-1 to 103-4 by sequentially performing them. Here, it is assumed that the ONU 103 designation order in the OLT 101 is the order from the ONU 103-1 to the ONU 103-4.

  FIG. 1 is a sequence diagram showing a flow of a time slot control method (uplink mobile synchronization establishment method) in the bidirectional time division multiplexing optical communication network system 1.

Step S1:
In step S1, a baseband clock signal is extracted from an NRZ signal supplied from an external device to the OTDM multiplexing unit 202 of the OLT 101, and the extracted baseband clock signal is used as a reference in the entire bidirectional time division multiplexing optical communication network system 1. And a clock pulse having a pulse width of 1 / (number of ONUs) of one bit period of the master clock signal. The pulse width may be narrower than this.

  The details of step S1 and the initial state of the OLT 101 will be described below. In the initial state, the OTDM multiplexing unit 202 receives an NRZ signal having the same transmission rate synchronized from the outside. Here, it is assumed that the NRZ signal is input from the router 201.

  FIG. 12 is a signal waveform diagram illustrating an example of signals for the ONUs 103-1 to 103-4 that are input from the router 201 to the OTDM multiplexing unit 202. A signal input from the router 201 to the OTDM multiplexing unit 202 is in the form of an NRZ signal as shown in FIG. FIG. 12A illustrates an example of a signal for the ONU 103-1. Similarly, FIG. 12B shows an example of the signal for the ONU 103-2, FIG. 12C shows an example of the signal for the ONU 103-3, and FIG. 12D shows an example of the signal for the ONU 103-4.

  FIG. 13 is a signal waveform diagram showing an example of a master clock signal extracted by the clock extractor 402.

  The NRZ signal input from the router 201 is input to the NRZ / RZ conversion unit 306 of the OTDM multiplexing unit 202. The NRZ signal input to the NRZ / RZ conversion unit 306 is input to the O / E converters 401-1 to 401-4 in the NRZ / RZ conversion unit 306, and converted into electrical signals. Then, an NRZ signal converted into an electrical signal from any one of the O / E converters 401-1 to 401-4 (for example, the O / E converter 401-4 here) is converted into a clock extractor. The clock extractor 402 extracts the clock component (baseband clock signal) of the NRZ signal, that is, the master clock signal (see FIG. 13). The O / E converters 401-1 to 401-4 may be, for example, commercially available photoelectric converters, and the clock extractor 402 is, for example, a commercially available PLL circuit (Phase Locked Loop, phase locked loop). It is realizable by using.

  FIG. 14 is a signal waveform diagram showing an example of a master clock signal converted by the pulse constrictor 404. When a master clock signal (see FIG. 13) is input from the clock extractor 402 to the pulse constrictor 404, a clock pulse having a pulse width of 1/4 period (1/4 period since the number of ONUs is 4). (Clock pulse train) (see FIG. 14). The pulse constrictor 404 can be realized, for example, by processing a spectral shape using a commercially available RF amplifier, a bandpass filter, or the like, and converting the spectral shape into a desired pulse shape.

  The converted clock pulse (see FIG. 14) is branched by the pulse constrictor 404 and input to the multiplication circuits 403-1 to 403-4 and the OTDM separation unit 204. However, the upstream signals output from the O / E converters 401-1 to 401-4 are in the initial state where the setting states of the ESWs 305-1 to 305-4 are routed to the modulators 303-1 to 303-4. Therefore, the signal given from the router 201 to the OTDM multiplexing unit 202 is not sent to the transmission path (ONU 103 side). The ESWs 305-1 to 305-4 are signals input to the modulators 303-1 to 303-4 (1/4 delay units 304-1 to 304-3) in accordance with the control signal from the ESW drive circuit 307. The route is switched by selecting either the route of the delay device 308 or the route of the NRZ / RZ conversion unit 306.

  The ESWs 305-1 to 305-4 can be realized by using a commercially available electronic circuit, for example. Further, for example, commercially available modulators can be used as the modulators 303-1 to 303-4, and commercially available delay devices for electric signals are used as the 1/4 delay devices 304-1 to 304-3, for example. For example, a commercially available multiplier can be used as the multiplier circuits 403-1 to 403-4.

  In the OTDM separation unit 204, the clock pulse (see FIG. 14) given from the NRZ / RZ conversion unit 306 (pulse constrictor 404) is input to the phase difference detection unit 503 and the control packet generation unit 504.

  In the control packet generator 504, the clock pulse (see FIG. 14) input from the NRZ / RZ converter 306 (pulse constrictor 404) and the control packets (control signals) directed to the ONUs 103-1 to 103-4 are provided. ) Is superimposed and input to the OTDM multiplexer 202 (delay unit 308). The details of the operation and configuration of the control packet generation unit 504 will be described in step S7 described later. In the initial state (step S1), as described above, since the ONU 103 that is currently controlled is the ONU 103-1, the control packet generated by the control packet generation unit 504 includes information for identifying the ONU 103-1. It is. In step S4 to be described later, each of the ONUs 103-1 to 103-4 determines whether or not its own device is currently a control target based on the information of the control packet described above, and between the OLT 101 and the ONU 103-1. Thus, a feedback group is formed.

  When the time slot control is completed for each of the ONUs 103-1 to 103-4, an ESW control instruction is given from the OTDM separation unit 204 (counter 604) to the ESW drive circuit 307, and the ESW 305-1 Although corresponding to 305-305-4, the switch state is changed to the route of the NRZ / RZ conversion unit 306 (see step S <b> 11 described later).

Step S2:
In step S2, OTDM signals for the ONUs 103-1 to 103-4 on which the carrier wave λ0 is superimposed are generated and transmitted based on the clock pulse (see FIG. 14) generated by the clock extractor 402 in step S1 described above. This is a step sent to the road (ONU 103-1 to 103-4).

  Details of step S2 will be described below. In the above-described initial stage (see the description of step S1 above), the control packet generator 504 of the OTDM separator 204 receives a clock pulse (see FIG. 14) from the OTDM multiplexer 202 (NRZ / RZ converter 306). At this time, the control packet generator 504 superimposes a control packet including a control signal indicating that the ONU 103-1 is a slot position control target on the clock pulse, and sends it to the OTDM multiplexer 202. Have been entered.

  FIG. 16 is an explanatory diagram showing an example of an OTDM signal transmitted from the OTDM multiplexing unit 202 toward the transmission path.

  In the OTDM multiplexing unit 202, the control packet superimposed on the clock pulse is input to the modulators 303-1 to 303-4 via the delay unit 308 and the ESWs 305-1 to 305-4, and the modulators 303-1 to 303-3 are input. In 303-4, a signal superimposed on the carrier wave λ0 input from the CW light source 301 via the isolator 302 is transmitted to the transmission line. However, signals input from the ESWs 305-1 to 305-4 to the modulators 303-1 to 303-4 are routed through the 1/4 delay units 304-1 to 304-3 as shown in FIG. Therefore, the signals sent to the transmission lines (ONUs 103-1 to 103-4) are subjected to OTDM (Optical Time Division Multiplexing). For example, a commercially available DFB laser can be used as the CW light source 301, and a commercially available optical isolator can be used as the isolator 302, for example.

  In FIG. 16 described above, the OTDM signal for the ONU 103-1 is a signal in the time slot T1, the ONU 103-2 corresponds to T2, the ONU 103-3 corresponds to T3, and the ONU 103-4 corresponds to T4. When generating the OTDM signal as shown in FIG. 16 described above, since the delay width of the OTDM signal for the ONU 103-1 is 0, the 1/4 delay unit 304 may not be arranged. Further, for example, in the OTDM signal for the ONU 103-2, the delay width is set to 1/4 bit, that is, 1/4 cycle of the 1-bit period of the master clock signal (see FIG. 13). The clock signal is controlled at the time slot position. That is, for the ONU 103-n, the delay width set in the ¼ delay unit 304 is generally (n−1) / 4 periods of the clock pulse (see FIG. 13) extracted by the clock extractor 402.

Step S3:
In step S3, in the ONU 103-1, the clock component (clock signal) is extracted based on the OTDM signal (see FIG. 16) input from the OLT 101 in the above-described step S2, and further, based on the extracted clock signal, In the upstream signal, a clock pulse adjusted to the slot position corresponding to the own device (ONU 103-1) is extracted.

  Details of step S3 will be described below.

  FIG. 17 is an explanatory diagram illustrating an example of signals input from the O / E converter 802 to the clock pulse generation unit 803 and the multiplication circuit 804. When an OTDM signal (see FIG. 16) is input from the OLT 101 to the ONU 103-1, it is converted into an electrical signal by the O / E converter 802 and input as a TDM signal to the clock pulse generation unit 803 and the multiplication circuit 804. . As the O / E converter 802, for example, a commercially available photoelectric converter can be used.

  FIG. 18 is a signal waveform diagram showing an example of a clock pulse extracted by the clock pulse generation unit 803 and adjusted in slot position. The clock pulse generator 803 extracts a clock component (clock signal) from the TDM signal. Then, in the clock pulse generation unit 803, the extracted clock component is adjusted to the slot position corresponding to the own device (ONU 103-1) and output as a short pulse (see FIG. 18). Part 807 and variable delay unit 809. Details of the operation and configuration of the clock pulse generator 803 will be described later.

  FIG. 19 is a signal waveform diagram illustrating an example of a signal obtained by multiplying the clock pulse and the TDM signal by the multiplication circuit 804. The multiplication circuit 804 multiplies the clock pulse (see FIG. 18) given from the clock pulse generation unit 803 and the TDM signal (see FIG. 17) given from the O / E converter 802, and uses the TDM signal as its own device. Only the signal at the slot position addressed to (ONU 103-1) is extracted (see FIG. 19) and input to the BPS 805. For the multiplier circuit 804, for example, a commercially available multiplier can be used.

  Next, the internal operation of the clock pulse generator 803 will be described.

  FIG. 20 is a signal waveform diagram showing an example of the clock component extracted by the clock extractor 1001. In the clock pulse generation unit 803, when the TDM signal is supplied to the clock extractor 1001, a clock component (clock signal) is extracted from the TDM signal (see FIG. 20) and supplied to the frequency divider 1002. The clock extractor 1001 can be realized by using, for example, a commercially available PLL circuit.

  FIG. 21 is an explanatory diagram showing an example of the clock signal divided by the frequency divider 1002. When the clock signal is supplied, the frequency divider 1002 divides the clock signal by 4 (divided by 4 because the number of ONUs is 4) (see FIG. 21), and is supplied to the pulse constrictor 1003.

  When the frequency-divided clock signal is given, the pulse constrictor 1003 has a clock pulse (clock pulse train) having a pulse width of ¼ period (1/4 period since the number of ONUs is 4) (the above-described figure). 14). The pulse constrictor 1003 can be realized by using a commercially available RF amplifier, a band-pass filter, or the like, for example, in the same manner as the pulse constrictor 404 described above. Further, as the frequency divider 1002, for example, a commercially available frequency divider can be used.

  When a clock pulse is input from the pulse constrictor 1003, the 1/4 bit delay unit 1004 adjusts the input clock pulse to the slot position addressed to its own device (ONU 103-1) (see FIG. 18). ). In the ONU 103-1, the delay width to be set in the 1/4 bit delay device 1004 is set to 0, and the clock signal is controlled at the position of the time slot of T1 in FIG. Further, for example, in the ONU 103-2, the delay width is set to 1/4 bit, that is, the 1/4 cycle of the clock signal (see FIG. 21) divided by the frequency divider 1002, and in FIG. The clock signal is controlled at the time slot position of T2. That is, in general, in the ONU 103-n, the delay width set in the 1/4 bit delay unit 1004 is (n-1) / 4 periods of the clock signal (see FIG. 21) divided by the frequency divider 1002. To do. The 1/4 bit delay device 1004 can be realized by using, for example, a commercially available electrical signal delay device. As described above, the clock pulse generation unit 803 generates a clock pulse adjusted to the slot position of the own device (ONU 103-1).

  FIG. 22 is a signal waveform diagram showing an example in which an RZ format signal is converted into an NRZ format signal by the BPS 805. In the BPS 805, the signal (see FIG. 19) given from the multiplication circuit 804 is converted from the RZ format to the NRZ format (see FIG. 22), and given to the media converter 806 and the control packet decoding unit 807. In the media converter 806, when a signal converted into the NRZ format is given, it is converted into a signal of a predetermined format and given to a lower-level device (terminal side). The BPS 805 can be realized by using, for example, a commercially available band pass filter. As the media converter 806, a commercially available media converter can be used.

Step S4:
In step S4, whether or not the control packet included in the OTDM signal (see FIG. 16) input from the OLT 101 in the ONU 103-1 is addressed to the own apparatus (ONU 103-1) in the above step S2. This is a step of determining whether or not.

  Details of step S3 will be described below. In the memory 902 of the control packet decoding unit 807, data based on a signal (see FIG. 22) given from the BPS 805 is accumulated when a certain number of bits are accumulated, and when a certain number of bits is accumulated. The data is provided to the data comparison means 903. At this time, the timing detection unit 901 has a trigger function for storing data bit by bit in the memory 902 at the timing of the clock pulse (see FIG. 18) input from the clock pulse generation unit 803.

  Then, the data comparison means 903 determines whether or not the control packet from the OLT 101 included in the data given from the memory 902 is addressed to the own device (ONU 103-1). In accordance with the contents of the control packet, a predetermined control signal is given from the CPU 905 to the variable delay device control circuit 808 or the OSW 814 via the signal generation means 604.

  In step S4, the control packet is given a control packet for starting synchronization control from the OLT 101 to the ONU 103-1, so the CPU 602 sets the route to the OSW 814 via the signal generation means 604. A control signal to be changed is issued, and the switched route is changed in OSW 814. Note that the OSW 814 (terminating unit 815) determines the path of the signal input to the optical circulator 801 or the path of the terminating unit 815 according to the control signal from the control packet decoding unit 807. One of these is selected and switched. Since the route of the OSW 814 in the initial state is set to the termination unit 815, signals from all the ONUs 103-1 to 103-4 are not sent to the OLT 101, but a control signal for changing the above route setting Is changed to the modulator 812 side.

  The timing detection unit 901, the memory 902, the data comparison unit 903, and the signal generation unit 904 can be realized by combining electronic circuits such as commercially available FFs (flip-flops), for example. The CPU 905 can be realized by, for example, installing a predetermined program or the like in a program implementation configuration such as a commercially available microprocessor, ROM, or RAM. Furthermore, the memory 902, the data comparison unit 903, and the like may be realized as hardware or software on the CPU 905.

Step S5:
In step S5, the upstream signal is superimposed on the clock pulse (see FIG. 18) adjusted to the slot position of the own device (ONU 103-1) generated by the clock pulse generation unit 803 in step S3 described above, and the OLT 101 This is a step sent out toward.

  Details of step S5 will be described below. In step S4 described above, in OSW 814, the switched route is changed, and the route is changed to the modulator 812 side. As a result, the uplink signal given from the lower side (terminal side) via the media converter 806 is superimposed on the clock pulse (see FIG. 18) generated by the clock pulse generation unit 803, and is transmitted toward the OLT 101. .

  FIG. 23 is a signal waveform diagram showing an example of an upstream signal input from media converter 806 to 1-bit delay device 810. When the upstream signal from the media converter 806 and the clock pulse from the variable delay device control circuit 808 are input to the 1-bit delay unit 810, the upstream signal is synchronized depending on the presence or absence of the clock pulse. The 1-bit delay device 810 can be realized by using, for example, a commercially available D-FF (flip flop) circuit. As a result, the two synchronized signals are multiplied by the multiplier circuit 811, and the upstream signal input from the media converter 806 is converted from the NRZ signal to the NR signal and is supplied to the modulator 812. Note that a commercially available multiplier can be used as the multiplier circuit 811.

  FIG. 24 is a signal waveform diagram showing an example of a signal superimposed on the upstream carrier wave λ1 by the modulator 812. The signal (see FIG. 24) multiplied by the multiplication circuit 811 is superimposed on the upstream carrier wave λ1 input from the CW light source 813 by the modulator 812, and transmitted toward the OLT 101 via the OSW 814 and the optical circulator 801. . For example, a commercially available modulator can be used as the modulator 812, and a commercially available DFB laser can be used as the CW light source 813, for example.

Step S6:
Step S5 is a step in which the OLT 101 detects a difference in timing between the signal input from the ONU 103-1 (see FIG. 24) and the clock pulse (see FIG. 14) based on the master clock signal.

  Details of step S5 will be described below. A signal superimposed on the carrier wave λ <b> 1 from the ONU 103-1 is input to the OTDM separation unit 204 via the optical circulator 203. This is simultaneously input to the phase difference detection unit 503.

  In the phase difference detection unit 503, the signal given from the ONU 103-1 is branched by the optical coupler 701 and input to the modulators 702-1 to 702-4, respectively. The modulators 702-1 to 702-4 receive clock signals (see FIG. 14) from the OTDM multiplexing unit 202 (clock extractor 402) via the 1/4 bit delay units 704-1 to 704-3. Entered. The timing of the clock signal input to each of the modulators 702-1 to 702-4 is the slot position to be targeted in the upstream signal from the corresponding ONU 103-1 to 103-4. Matching the signal timing is a control target in the time slot control.

  As the optical coupler 701, for example, a commercially available optical coupler can be used. Moreover, for example, commercially available delay devices for electric signals can be used as the 1/4 bit delay devices 704-1 to 704-3, and for example, commercially available modulators are used as the modulators 702-1 to 702-4. Can be used.

  Signals output from the modulators 702-1 to 702-4 are branched by optical couplers 703-1 to 703-4, respectively. Hereinafter, as shown in FIG. 8, one of the signals branched by the optical couplers 703-1 to 703-4 is represented as C-501 to C-504, and the other is represented as D-501 to D-504. For example, commercially available optical couplers can be used as the optical couplers 703-1 to 703-4.

  The C-501 to C-504 are input to the BPDs 505-1 to 505-4, respectively, and the spectrum is sliced, converted from RZ to a signal having a large pulse width close to NRZ, and input to the router 201. The BPDs 505-1 to 505-4 can be realized by using, for example, a commercially available band pass filter.

  In the phase difference detection unit 503, the modulators 702-1 to 702-4 can be regarded as multiplication elements of the clock signal and the upstream signals from the ONUs 103-1 to 103-4. Accordingly, D-501 to D-504 have the maximum output intensity, that is, the most desirable waveform shape in the control of the time slot when the clock signal and the timing of the upstream signal coincide.

  In the O / E converters 502-1 to 502-4 of the OTDM separation unit 204, the signals D-501 to D-504 given from the phase difference detection unit 503 are converted into electric signals, and the voltage intensity detector 501 -1 to 501-4. Then, in the voltage strength detectors 501-1 to 501-4, when an electric signal is given, a control signal corresponding to the input signal strength is given to the control packet generation unit 504. The O / E converters 502-1 to 502-4 can be realized by using, for example, an apparatus having a commercially available light receiving device. The voltage intensity detector 501 measures the voltage intensity converted from light to an electrical signal, and provides the control packet generator 504 with a signal intensity that varies with time.

  As will be described later, the control packet generator 504 changes the delay time to the corresponding ONUs 103-1 to 103-4 based on the control signals given from the voltage intensity detectors 501-1 to 501-4. A control signal (control packet) to be transmitted is generated and transmitted, and the timing of the uplink signal is adjusted. The control packet generator 504 transmits the control packet several times to the ONU 103-1, and receives the clock pulse (see FIG. 14) input from the OTDM multiplexer 202 (NRZ / RZ converter 306) and the upstream signal. , When the signal strength inputted to the voltage strength detector 501-1 reaches the maximum, the control packet generator 504 next identifies the identifier of the ONU 103-2. Is transmitted to each of the ONUs 103-1 to 103-4, and the timing of the upstream signal of the ONU 103-2 is adjusted. At this time, in the phase difference detection unit 503, each of the modulators 702-1 to 702-4 is used for establishing the slot positions of the ONUs 103-1 to 103-4, respectively. That is, the signals output from the voltage intensity detectors 501-1 to 501-4 indicate the degree of timing coincidence between the clock pulse based on the master clock signal and the upstream signals from the ONUs 103-1 to 103-4, respectively. Show.

  FIG. 25A is an explanatory diagram showing an example of the timing difference between the clock pulse (see FIG. 18) input to the modulator 702-1 and the upstream signal (see FIG. 24) from the ONU 103-1. .

  FIG. 25B shows the signal output from the modulator 702-1 when there is a large difference between the timing of the clock pulse input to the modulator 702-1 and the timing of the upstream signal from the ONU 103-1. It is explanatory drawing shown about the example.

  FIG. 25C shows the signal output from the modulator 702-1 when the difference between the timing of the clock pulse input to the modulator 702-1 and the timing of the upstream signal from the ONU 103-1 is small. It is explanatory drawing shown about the example.

  For example, here, since the ONU 103-1 is first subject to the control of the time slot, the modulator 702-1 responds to the difference between the input clock pulse and the upstream signal from the ONU 103-1. The intensity of the output signal varies. When the timing deviation is large, as shown in FIG. 25B, the intensity of the signal output from the modulator 702-1 is weak, and when the timing deviation is small, the above-described FIG. ), The intensity of the signal output from the modulator 702-1 increases. At this time, control is performed by steps S7 to S8, which will be described later, so that the intensity of the signal output from the modulator 702-1 becomes a certain level or more.

  FIG. 26 is an explanatory diagram illustrating an example of the timing difference between the clock pulse input to the modulator 702-2 and the upstream signal from the ONU 103-2. For the ONU 103-1, when the adjustment of the timing deviation described above is completed, that is, when the control of the time slot is completed, the control for the ONU 103-2 is started in step S10 described later. As shown in FIG. 26, the control packet generation unit 504 performs control so that the timing of the upstream signal from the ONU 103-2 matches the position of the time slot T2.

Step S7:
Step S7 is a timing shift between the upstream signal input from the ONU 103-1 to the OLT 101 and the clock pulse based on the master clock signal in the OLT 101 detected in Step S6 (see FIG. 25A). In response to this, a control packet is generated and transmitted to the ONU 103-1.

  Details of step S7 will be described below. When a shift in timing between the signal input from the ONU 103-1 (see FIG. 24) and the clock pulse based on the master clock signal (see FIG. 14) is detected (see step S6 above), the timing at that point in time is detected. A signal corresponding to the deviation is given from the voltage strength detector 501-1 to the signal strength discriminating means 600 of the control packet generator 504, and the signal strength discriminating means 600 measures and measures the strength of the given signal. The signal strength value obtained is given to the CPU 602. Then, the CPU 602 generates a control packet in which a delay amount is set according to the given signal strength value and provides the generated control packet to the memory 603. Thereafter, the control packet stored in the memory 603 is sent out to each of the ONUs 103-1 to 103-4. At this time, the data of the control packet stored in the memory 603 is given to the OTDM multiplexing unit 202 (delay unit 308) bit by bit by the signal generation unit 604. Also, a signal that triggers from the timing detection unit 601 to the signal generation unit 604 at a timing synchronized with a clock pulse (see FIG. 14) provided from the OTDM multiplexing unit 202 (clock extractor 402 of the NRZ / RZ conversion unit 306). From the signal generation means 604, the data of the control packet is provided to the OTDM multiplexing unit 202 (delay unit 308) bit by bit at that timing.

  The signal strength determination unit 600, the timing detection unit 601, the memory 603, the signal generation unit 604, and the counter 605 can be realized by combining electronic circuits such as commercially available FFs (flip-flops). The CPU 602 can be realized by installing a predetermined program in an implementation configuration of a program such as a commercially available microprocessor, ROM, or RAM. Furthermore, the memory 603, the counter 605, and the like may be realized as hardware or software on the CPU 602.

Step S8:
In step S8, when the control packet in which the delay amount is set to the ONU 103-1 is given from the OLT 103 in the above-described step S7, the above-described step S8 is performed according to the delay amount set in the given control packet in the ONU 103-1. In step S5, the clock pulse transmitted to the OLT 103 is delayed.

  Details of step S8 will be described below. Through the same operation as in step S4 described above, the control packet given from the OLT 101 is decoded by the control packet decoding unit 807, and it is determined that the packet is addressed to the own apparatus (ONU 103-1). Then, the CPU 905 provides a control signal corresponding to the delay amount set in the control packet to the variable delay device control circuit 808 via the signal generation unit 904. Then, the variable delay device control circuit 808 controls the variable delay device 809 in accordance with the given control signal. As a result, in the variable delay device 809, the clock pulse (see FIG. 18) provided from the clock pulse generation unit 803 is delayed and provided to the 1-bit delay device 810. The variable delayer control circuit 808 and the variable delayer 809 can be realized by using, for example, commercially available electronic circuits.

Step S9:
Step S9 is a step in which the uplink signal is superimposed on the clock pulse delayed by the variable delay device 809 in Step S8 described above, and is transmitted toward the OLT 101. The details of the operation in step S9 are the same as those in step S5 described above, and a detailed description thereof will be omitted.

  FIG. 28 is a sequence diagram illustrating an operation when a control packet is transmitted from the OLT 101 (control packet generator 504) to each of the ONUs 103-1 to 103-4 and the slot position of the uplink signal is controlled. When the operations in steps S6 to S9 described above are repeated, as shown in FIG. 28, a control packet in which a delay amount is set is transmitted from the OLT 101 to the ONU 103-1, and the ONU 103-1 changes the contents of the control packet. An upstream signal based on the delayed clock pulse is transmitted to the OLT 101. The OLT 101 adjusts the slot position of the upstream signal of the ONU 103-1 by repeating the transmission of the control packet until the timing deviation is within the allowable range.

  When the adjustment of the slot position of the upstream signal is completed for the ONU 103-1, the control packet generation unit 504 (CPU 602) generates a control packet indicating the completion of the adjustment of the slot position for the ONU 103-1, and sends it to the ONU 103-1. Sent. In the ONU 103-1, the control packet decoding unit 807 decodes the contents of the control packet. Then, the OSC 814 is controlled by the CPU 905, and the path set on the modulator 812 side in the OSW 814 is switched to the path of the termination unit 815.

Step S10:
Step S10 is a step in which the time slot control of the upstream signal of the ONU 103-1 is completed and the time slot control is performed for the next ONU (ONU 103-2).

  Details of step S10 will be described below. The operation of controlling the slot position adjustment of the upstream signal of the ONU 103-2 is the same as that in which the ONU to be controlled is replaced with the ONU 103-2 in the description of steps S2 to S9 described above. However, in order to form a feedback group between the OLT 101 and the ONU 103-2, the control packet generation unit 504 (CPU 905) generates the control packet that is generated and sent to each of the ONUs 103-1 to 103-4. -2 is different.

  In the initial stage, the counter 605 of the control packet generation unit 504 has a value set to 0. When the control of the time slot of the upstream signal for the ONU 103-1 is completed in step S9, the CPU 602 The value of the counter 605 is incremented by 1. Similarly, when the synchronization control is completed up to the ONU 103-2, ONU 103-3, and ONU 103-4, the value finally set in the counter 605 becomes 4, and the CPU 602 determines all the target slots (ONUs 103-1 to 103-). Recognizing that the synchronous control is completed for 4).

Step S11:
When the set value of the counter 604 of the OLT 101 (control packet generator 504) becomes 4, a predetermined control signal is transmitted from the CPU 602 to the ESW drive circuit 307. Then, the ESW drive circuit 307 controls the routes of the ESWs 305-1 to 305-4 to the NRZ / RZ conversion unit 306 side, and thereafter, signals from the upper side (router 201) are sent to the ONUs 103-1 to 103, respectively. -4.

  FIG. 15 is a signal waveform diagram showing an example of signals given from the NRZ / RZ conversion unit 306 to the ESWs 305-1 to 305-4. In the NRZ / RZ conversion unit 306, the multiplication circuits 403-1 to 403-4 receive the NRZ signals (see FIG. 12) input from the O / E converters 401-1 to 401-4 and the pulse constrictor 404. Clock pulses (see FIG. 14) to be superimposed are converted into RZ signals (see FIG. 15). The RZ signals (see FIG. 15) converted by the NRZ / RZ conversion unit 306 are converted into ESWs 305-1 to 305-4, 1/4 delay units 304-1 to 304-3, and modulators 303-1 to 303-. 4 is sent to each of the ONUs 103-1 to 103-4.

  Further, the CPU 602 generates a control packet for starting communication with respect to all the ONUs 103-1 to 103-4, and transmits the control packets to the respective ONUs 103-1 to 103-4. In each ONU 103-1 to ONU 103-4, the contents of the control packet are decoded by the control packet decoding unit 807. Then, the OSC 814 is controlled by the CPU 905, and the path set in the termination unit 815 in the OSW 814 is switched to the path on the modulator 812 side, and the signal based on the upstream signal from the media converter 806 is changed to the OLT 101. Sent to the.

  FIG. 29 is a flowchart illustrating an example of the operation of the control packet generation unit 504 when the uplink signal timing is synchronized between the OLT 101 and the ONU 103.

  First, in the CPU 602 of the control packet generation unit 504, a control packet for starting the synchronization of the ONU 103-1 to be synchronized first is generated and given to each of the ONUs 103-1 to 103-4. Then, in the ONU 103-1, the upstream signal is superimposed on the clock pulse (see FIG. 18) adjusted to the slot position of the own device (ONU 103-1), and is transmitted toward the OLT 101 (see FIG. 24) (S21). ). Step S21 is an operation corresponding to steps S2 to S5 described above.

  In step S21 described above, a signal corresponding to the timing difference between the signal input from the ONU 103-1 (see FIG. 24) and the clock pulse based on the master clock signal (see FIG. 14) is a voltage intensity detector. 501-1 is applied to the signal strength discriminating unit 600 of the control packet generation unit 504. The signal strength discriminating unit 600 measures the strength of the given signal, and the measured signal strength value is provided to the CPU 602. . Then, the CPU 602 temporarily stores the given signal strength value (S22).

  Next, the CPU 602 generates a control packet addressed to the ONU 103-1 indicating the delay amount and the delay direction according to the signal strength value stored in step S 22 described above, and provides the memory 603 with the control packet. Then, the generated control packet is sent to each of the ONUs 103-1 to 103-4 (S23). Note that the delay direction here is either the direction in which the phase difference increases or decreases with respect to the reference signal.

  Then, in the ONU 103-1, the uplink signal is superimposed on the delayed clock pulse (see FIG. 18) according to the contents of the control packet received in step S23 described above, and is sent to the OLT 101 (FIG. 24). Reference) (S24).

  Next, in step S24 described above, the signal strength value corresponding to the timing difference between the signal input from the ONU 103-1 (see FIG. 24) and the clock pulse based on the master clock signal (see FIG. 14) is: The signal strength discriminating means 600 gives the CPU 602. When the signal strength value is given, the CPU 602 compares the given signal strength value with the value stored in step S22 described above (S25).

  When it is determined in step S25 described above that the given signal strength value is greater than the stored value, the CPU 602 performs control in which the changed delay amount is set according to the given signal strength value. A packet is generated and provided to memory 603. Then, the generated control packet is sent to each of the ONUs 103-1 to 103-4 in the same manner as in step S21 described above (S26).

  On the other hand, if it is determined in step S25 described above that the given signal strength value is smaller than the stored value, the CPU 602 generates a control packet in which the delay direction is set in reverse, and gives it to the memory 603. It is done. Then, the generated control packet is sent to each of the ONUs 103-1 to 103-4 in the same manner as in step S21 described above (S27).

  Next, in the ONU 103-1, the upstream signal is superimposed on the delayed clock pulse (see FIG. 18) according to the contents of the control packet received in step S26 or S27 described above (see FIG. 24), and the OLT 101 (S28).

  Similarly to step S22 described above, the signal strength value corresponding to the timing difference between the signal input from the ONU 103-1 (see FIG. 24) and the clock pulse based on the master clock signal (see FIG. 14) is obtained. The CPU 602 replaces the value stored in step S22 and stores the value (S29).

  Next, the CPU 602 determines whether or not the value of the signal intensity stored in the above step S29 is larger than a predetermined reference value (S30). If it is determined that the value is small, the operation starts from the above step S25. Then, the operations in steps S25 to S30 are repeated until the signal strength value reaches a predetermined reference value.

  If it is determined in step S30 that the stored signal strength value is greater than the predetermined reference value, the CPU 602 generates a control packet indicating that the control of the time slot for the ONU 103-1 has ended, It is sent to each ONU 103-1 to 103-4 (S31).

  When the control of the time slot for the ONU 103-1 is completed, the operation is performed from the above-described step S 21 instead of the ONU 103-2. Is repeated (S32).

  FIG. 27 is an explanatory diagram illustrating a time series when a control packet is transmitted from the control packet generation unit 504 to the ONUs 103-1 to 103-4 and controlled.

  A control packet is transmitted from the control packet generator 504 to the ONUs 103-1 to 103-4 at predetermined time intervals in the above-described step S26 (or S27). In FIG. 27, Δt1 indicates the time from when the OLT 101 sends the control packet to when the ONUs 103-1 to 103-4 receive it. Δt2 indicates the time from when the ONUs 103-1 to 103-4 receive the control packet until the delay control is started. Δt3 indicates the time from the start to the end of the delay control based on the received control packet in the ONUs 103-1 to 103-4. Δt4 indicates the time from when the signal intensity corresponding to the timing deviation is detected in the OLT 101 until the control packet is transmitted to the ONUs 103-1 to 103-4. In FIG. 27, it is assumed that the OLT 101 transmits a control packet at a period of Δt0 + Δt4. At this time, delay control is performed by the ONUs 103-1 to 103-4, the signal strength is detected by the voltage strength detectors 501-1 to 501-4 in the OLT 101, and a control packet needs to be transmitted. Therefore, in this case, it is desirable that Δt0> Δt1 + Δt2 + Δt3.

(A-3) Effect of Embodiment According to the above embodiment, the synchronization of the upstream signal from each of the ONUs 103-1 to 103-4 can be accurately performed from the optical splitter 102 to the ONUs 103-1 to 103-4. This can be achieved without determining the distance.

  Further, according to the above-described embodiment, it is not necessary to establish synchronization by complicated packet processing by an upper layer such as control for preventing collision of uplink signals transmitted from the respective ONUs 103-1 to 103-4. That is, synchronization can be established by using a control method independent of the upper layer. Furthermore, it is only necessary to perform the synchronization establishing operation at a limited opportunity such as when the system is installed or during maintenance, and it is not necessary to always perform control, so that power consumption can be reduced.

  Furthermore, the light source may be two types of light sources, downstream signals and upstream signals. In other words, unlike the WDM-PON, it is not necessary to arrange light sources proportional to the number of ONUs in the OLT. An effect similar to that of WDM-PON, that is, an effect that the upstream signal and the downstream signal can be independently set to the same bit rate can be achieved at low cost.

  Furthermore, according to the above-described embodiment, it is possible to execute downlink communication even when uplink synchronization is established.

  In the above embodiment, the delay amount is set in the OLT 101 according to the timing difference between the upstream signal from the ONU 103 and the clock pulse based on the master clock signal in the OLT 101 by the above-described steps S6 and S7. A control packet is generated and given to the ONU 103. As a result, the delay amount can be notified from the OLT 101 to the ONU 103 by a digital signal, so that the delay amount intended in the OLT 101 is accurately notified to the ONU 103, and the number of times that the control packet is transmitted from the OLT 101 to the ONU 103 is reduced. The time slot control can be completed early.

(B) Other Embodiments (B-1) In the above embodiment, the case where there are four ONUs is shown, but the number of ONUs may be any number. As described above, the unit for delaying the clock pulse may be changed by the 1/4 delay unit 304 or the 1/4 bit delay unit 704 in accordance with the number of ONUs. Here, the number of ONUs may be one, and in this case as well, the timing of the upstream signal can be made as intended by the OLT.

(B-2) In the above embodiment, in the 1/4 delay unit 304, the 1/4 bit delay unit 704, and the 1/4 bit delay unit 1004, the delay width to be delayed is a 1/4 bit period. However, other units may be applied. For example, a 3/4 bit period may be applied.

(B-3) In the above-described embodiment, an example is shown in which uplink communication is started after synchronization is established with all ONUs. However, synchronization is not established even if any ONU synchronization is established. The established ONU may perform upstream communication.

(B-4) During the synchronization establishment operation (step S5 described above), the signal sent from the ONU 103-1 to the OLT 101 is not for regular communication. It may be a dummy prepared.

It is a sequence diagram showing a time slot control method (uplink mobile synchronization establishment method) in the optical communication network system according to the embodiment. FIG. 2 is a block diagram illustrating an overall configuration of the optical communication network system according to the embodiment. It is a block diagram which shows the internal structure of OLT which concerns on embodiment. It is a block diagram which shows the internal structure of the OTDM multiplexing part which concerns on embodiment. It is the block diagram which showed the internal structure of the NRZ / RZ conversion part which concerns on embodiment. It is a block diagram which shows the internal structure of the OTDM isolation | separation part which concerns on embodiment. It is a block diagram which shows the internal structure of the control packet production | generation part which concerns on embodiment. It is a block diagram which shows the internal structure of the phase difference detection part which concerns on embodiment. It is a block diagram which shows the internal structure of ONU which concerns on embodiment. It is a block diagram which shows the internal structure of the control packet decoding part which concerns on embodiment. It is a block diagram which shows the internal structure of the clock pulse generation part which concerns on embodiment. It is the signal waveform diagram which showed the example of the signal for ONU input into the OTDM multiplexing part from the router which concerns on embodiment. It is a signal waveform diagram which shows the example of the master clock signal extracted in the clock extractor which concerns on embodiment. It is a signal waveform diagram showing an example of a master clock signal converted by the pulse constrictor according to the embodiment. It is the signal waveform diagram which showed the example converted into the RZ signal from the NRZ signal by the NRZ / RZ conversion part which concerns on embodiment. It is a signal waveform diagram showing an example of an OTDM signal sent out from the OTDM multiplexing unit according to the embodiment toward a transmission line. It is the signal waveform diagram which showed the example of the signal input into the clock pulse generation part and the multiplication circuit from the O / E converter which concerns on embodiment. It is the signal waveform diagram shown about the example of the clock pulse with which the slot position was adjusted extracted by the clock pulse generation part which concerns on embodiment. It is a signal waveform diagram showing an example of a signal obtained by multiplying the clock pulse and the TDM signal by the multiplication circuit according to the embodiment. It is the signal waveform diagram which showed the example of the clock pulse extracted by the clock extractor which concerns on embodiment. It is the signal waveform diagram which showed the example of the clock pulse frequency-divided by the frequency divider which concerns on embodiment. It is a signal waveform diagram showing an example in which an RZ format signal is converted into an NRZ format signal by the BPS according to the embodiment. It is the signal waveform diagram shown about the example of the upstream signal output from the media converter which concerns on embodiment. It is a signal waveform diagram showing an example of a signal superimposed on an upstream carrier wave λ1 by the modulator according to the embodiment. It is explanatory drawing shown about the example of the timing shift of the clock pulse input into the modulator which concerns on embodiment, and the upstream signal from ONU103-1. It is explanatory drawing shown about the example of the timing shift of the clock signal input into the modulator which concerns on embodiment, and the upstream signal from ONU103-2. It is explanatory drawing explaining the time series at the time of a control packet being transmitted from the control packet production | generation part which concerns on embodiment to ONU, and being controlled. It is the sequence diagram shown about the operation | movement at the time of a control packet being transmitted to ONU from the control packet generation part which concerns on embodiment, and being controlled. It is the flowchart which showed the example of operation | movement of the control packet generation part which concerns on embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Two-way time division multiplexing optical communication network system, 101 ... OLT, 102 ... Optical splitter, 103, 103-1 to 103-4 ... ONU, 201 ... Router, 202 ... OTDM multiplexing part, 204 ... OTDM separation part, 203 ... Optical circulator, 301 ... CW light source, 302 ... Isolator, 303-1 to 303-4 ... Modulator, 304-1 to 304-3 ... 1/4 delay unit, 305-1 to 305-4 ... ESW, 306 ... NRZ / RZ converter, 307... ESW drive circuit, 308... Delay device, 401-1 to 401-4... O / E converter, 402... Clock extractor, 403-1 to 403-4. Pulse constrictor, 501-1 to 501-4 ... voltage intensity detector, 502-1 to 502-4 ... O / E converter, 503 ... phase difference detector, 504 ... control packet generation , 505-1 to 505-4 ... BPD, 600 ... signal intensity discrimination means, 601 ... timing detection means, CPU ... 602, 603 ... memory, 604 ... signal generation means, 605 ... counter, 701 ... optical coupler, 702 ... Modulator, 702-1 to 702-4 ... Modulator, 703-1 to 703-4 ... Optical coupler, 704-1 to 704-3 ... 1/4 bit delay device, 801 ... Optical circulator, 802 ... O / E Converter, 803... Clock pulse generation unit, 804... Multiplying circuit, 805... BPS, 806... Media converter, 807 ... Control packet decoding unit, 808 ... Variable delay control circuit, 809 ... Variable delay, 810 ... 1 bit delay 811 ... multiplier circuit 812 ... modulator 813 ... CW light source 814 ... OSW 815 ... termination unit 901 ... timing detection means 902 Memory, 903 ... data comparison unit, 904 ... signal generator, 905 ... CPU, 1001 ... clock extractor, 1002 ... divider, 1003 ... pulse narrowing unit, 1004 ... 1/4-bit delay device.

Claims (6)

In the upstream signal timing control method for controlling the timing of the upstream optical signal from the terminal device to the center device to the timing intended by the center device,
An optical clock pulse synchronized with the timing is transmitted from the center device to the terminal device,
The terminal device delay-controls the optical clock pulse and returns it to the center device.
The center apparatus detects a timing shift between the timing and the returned optical clock pulse, forms digital data including at least the timing shift information, and transmits the digital data to the waveform of the optical clock pulse to be transmitted. The terminal device extracts the digital data reflected in the received optical clock pulse, and performs the delay control according to the timing shift information included in the extracted digital data. ,
The upstream signal timing control method, wherein the center device catches completion of upstream optical signal timing control when a timing difference between the timing and the returned optical clock pulse is equal to or less than a threshold value. The center device accommodates a plurality of terminal devices,
The center device transmits the digital data reflected in the optical clock pulse including the identification information of the terminal device to be controlled,
The uplink signal timing control method according to claim 1, wherein the terminal apparatus identifies whether or not the terminal apparatus is a terminal apparatus to be controlled based on identification information included in the digital data.   The uplink signal timing control method according to claim 1 or 2, wherein the center device sequentially switches the terminal devices to be controlled to execute timing control of the uplink optical signal for all the terminal devices. In the center device in an optical communication network system in which one or a plurality of terminal devices are accommodated in a center device, and each of the terminal devices and the center device constitute a PON,
A digital signal for generating an optical clock pulse synchronized with the timing of an upstream signal from the terminal device to be controlled to the center device, and controlling the terminal device to be controlled with the waveform of the optical clock pulse. Optical clock pulse generation and transmission means for transmitting an optical signal reflecting data to the terminal device to be controlled at present;
Timing comparison means for detecting the timing difference between the timing and the optical clock pulse returned from the terminal device to be controlled by delay control;
When the detected timing deviation is larger than the threshold, the optical clock pulse generation / transmission means includes the timing deviation information in the digital data reflected in the transmitted optical clock pulse and transmits the timing deviation information to the terminal device. Additional means;
And a timing control completion recognition means for recognizing completion of the detected timing control. In the terminal device in the optical communication network system in which one or a plurality of terminal devices are accommodated in a center device, and each of the terminal devices and the center device constitute a PON,
An optical clock pulse return means that returns an optical clock pulse that has arrived from the center device, and digital data reflected in the optical clock pulse that has arrived from the center device are extracted, and depending on the information contained in the digital data And a delay means for delaying the returned optical clock pulse. In an optical communication network system in which one or a plurality of terminal devices are accommodated in a center device, and each of the terminal devices and the center device constitute a PON,
While applying the center device according to claim 4 as the center device,
An optical communication network system, wherein the terminal device according to claim 5 is applied as each of the terminal devices.

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