JP2009075804A - Positioning controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a positioning controller for generating pulse outputs of a series of variable speed patterns based on a desired operation speed pattern given before start-up. <P>SOLUTION: A conversion setting means 120 writes first and second set values corresponding to pulse cycles for low-speed/high-speed operations to first and second setting registers 133, 132 of a first high-speed counter 130 beforehand, and writes a half value of a target generated pulse and the number of low-speed operation pulses to first and second setup registers 153, 152 of a second high-speed counter 150. The first high-speed counter 130 generates low-speed pulse output or high-speed pulse output in cooperation with a selection switch circuit 141 and an alternating output circuit 142. The selection switch circuit 141 switches the speed from low-to high to low by increase comparison output P2, count-up output Q2 and decrease comparison output P2 of the second high-speed counter 150. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention, for example, generates a pulse output for positioning control on the basis of setting command information from a microprocessor that performs input / output control in a programmable controller, and drives the stepping motor or servo motor to determine the movement position of the workpiece. The present invention relates to an improvement of a positioning control device for controlling.

  Using a microprocessor and a hardware pulse output circuit together, variable speed operation of workpiece movement vs. speed characteristics with multiple steps or trapezoidal speed patterns is a widely used technology. is there. With this technology, it is possible to improve high-speed operation and stopping accuracy.

  As a conventional technique, there is a stepping motor driving method that performs multi-stage speed control by controlling a pulse output unit and a pulse counter using a microprocessor in a programmable controller that performs input / output control (for example, Patent Document 1). reference).

  In addition to the microprocessor in the programmable controller that performs input / output control, a dedicated microprocessor is used to control the pulse output unit (pulse generator) and pulse counter (hard counter), and the speed of the multistage broken line characteristics. There is a driving method of a stepping motor that performs control (see, for example, Patent Document 2).

JP 05-061551 A JP 2002-014707 A

  In each of Patent Documents 1 and 2, the microprocessor that controls the pulse output unit and the pulse counter executes the interrupt program at the inflection point of the speed characteristics in each case, and sets the next movement amount and the target pulse period or frequency. Are sequentially commanded.

  Therefore, in the case of Patent Document 1, there is a problem that the control load of the microprocessor that performs the input / output control as the programmable controller in parallel is high and is not suitable for high-speed and high-precision positioning control. In the case of Patent Document 2, there is a problem that an extra dedicated microprocessor is required and the product is expensive.

  The present invention has been made to solve the above-described problems, and provides a positioning control device capable of generating a series of variable speed pattern pulse outputs based on a desired driving speed pattern given before starting. The first purpose is to provide it.

  Another object of the present invention is to provide a small and inexpensive two-speed operation positioning control device suitable for performing simple positioning control.

  It is a third object of the present invention to provide a positioning control device with gradually increasing / decreasing speed characteristics suitable for performing advanced positioning control.

  A positioning control device according to the present invention is a positioning control device including a pulse output circuit unit that generates a pulse output for positioning control in accordance with a desired operation speed pattern, and includes a target number of generated pulses and a pulse output cycle. Alternatively, it further comprises conversion setting means for determining a parameter for specifying a desired operation speed pattern based on frequency transition characteristics, and the pulse output circuit unit includes a current value register in which a count current value of an input signal is stored; A first setting register in which a first parameter among the parameters determined by the conversion setting unit is set, and a value equal to or lower than the first parameter is set as a second parameter among the parameters specified by the conversion setting unit. A second setting register; a first comparison circuit for outputting a comparison result between the current value register and the first setting register; A first high-speed counter and a second high-speed counter each having a second comparison circuit for outputting a comparison result between the current value register and the second setting register. The reference clock signal or the frequency-divided signal of the reference clock signal is input, the current count value of the reference clock signal or frequency-divided signal is stored in the current value register, and the second high-speed counter receives the pulse output for positioning control as input The elapsed state of the number of generated pulses is stored in the current value register, and the first comparison circuit provided in the first high-speed counter and the second high-speed counter has the current value register value set to the first setting register. A count-up output is generated when the value coincides with or exceeds the coincidence point or the coincidence point is exceeded, and the first high-speed counter and the second high-speed counter In the second comparison circuit, the value of the current value register matches the set value of the second setting register or has passed the matching state in the process in which the value of the current value register increases or decreases. To generate at least one of the rising comparison output and the falling comparison output, and the pulse output circuit unit generates the count-up output by the first high-speed counter and the rising comparison output or the falling comparison output by the second high-speed counter. In response to the generation of at least one of the outputs, a pulse output with a desired operation speed pattern based on the target number of pulse generations and transition characteristics is generated.

In the positioning control device according to the present invention, at the start of the positioning control operation, a control constant is set from the conversion setting means to the pulse output circuit unit, and a pulse output of a target number of pulses is output by the first and second high-speed counters. The first and second high-speed counters are provided with first and second setting registers and first and second comparison circuits, respectively, so that the pulse output circuit section is completed until the positioning operation is completed. A pulse output with a variable period or a variable frequency is generated by the function of.
Therefore, for example, in a positioning control device using a microprocessor, the microprocessor does not need to sequentially command speed patterns, reduces the control burden, and generates an accurate speed pattern with a simple hardware configuration. There is an effect that positioning control of high-speed and high-performance operation can be performed at low cost.

  Hereinafter, preferred embodiments of a positioning control device of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram of a positioning control device according to Embodiment 1 of the present invention.
In FIG. 1, for example, a positioning control device 100 that constitutes a programmable controller includes a CPU unit 100a and a pulse output circuit unit 100b that is a part of an input / output unit.

  The CPU unit 100a is supplied with a predetermined stabilization voltage Vcc via a power supply circuit 110 that is fed from an external power supply that is a commercial power supply of AC 100V to 240V, for example.

  In the CPU unit 100a, a microprocessor 120, a program memory 121, and a RAM memory 122 are provided. Here, the program memory 121 is, for example, a non-volatile flash memory, and stores an input / output control program created by the user.

  The pulse output circuit unit 100b is connected to the microprocessor 120 by a bus, and exchanges command / monitoring signals.

  The driver 101 receives the rotation direction command output DIR and the forward / reverse rotation pulse output FRP from the pulse output circuit unit 100b and drives the stepping motor 102. By driving the stepping motor 102, the workpiece 104 is moved in the forward direction or the reverse direction.

  When the logical level of the rotation direction command output DIR is “H”, the forward rotation drive (forward drive) is performed, and when the logical level is “L”, the reverse drive (reverse drive) is performed. Further, when the forward / reverse rotation pulse output FRP generates a pulse, the rotation is driven, and when the pulse generation is stopped, the rotation is stopped.

  A command input signal 108 is connected to the microprocessor 120 via an interface circuit (not shown). For example, a forced stop command, a backward limit command by the reverse rotation limit switch 105, a forward limit command by the forward rotation limit switch 107, a manual forward command, Manual reverse command, automatic operation command, etc. are input.

  When a forced stop command, forward rotation limit command, or reverse rotation limit command is input, the pulse output circuit unit 100b immediately stops generating pulses. When a manual forward command or manual reverse command is given, a low-speed forward rotation pulse output or a low-speed reverse rotation pulse output is generated. Further, when an automatic operation command is given, the number of pulses commanded by the speed pattern based on the control program stored in the program memory 121 is generated and stopped.

  The pulse output circuit unit 100b is mainly composed of a first high-speed counter 130 and a second high-speed counter 150. For example, the clock signal generation circuit 140 generates the reference clock signal CLK1 having a period of 1 μsec and supplies the reference clock signal CLK1 to the count input terminal IN of the first high-speed counter 130.

  The addition mode terminal UP of the first high-speed counter 130 is fixed to the logic level “H”, and the subtraction mode terminal DN is fixed to the logic level “L”. As a result, the current value register 131 of the first high-speed counter 130 performs an addition operation of 1 count when the count input signal (reference clock signal CLK1) changes from the logic level “L” to “H”. It has become.

  The first setting register 133 of the first high-speed counter 130 stores a numerical value corresponding to 1/2 of the target low-speed output pulse cycle T1. The second setting register 132 stores a numerical value corresponding to 1/2 of the target high-speed output pulse period T2.

  When the current count value of the current value register 131 increases and reaches the setting value N1 of the first setting register 133 or the setting value N2 (N2 ≦ N1) of the second setting register 132, the count-up output Q1 or increases A comparison output P1 is generated. As a result, a reset command is supplied to the reset terminal RS of the first high-speed counter 130 via the OR element 144, and the output of the alternating output circuit 142 is alternately inverted.

  Which set value of the first and second setting registers 133 and 132 is used is determined by a logical operation of a selection switching circuit 141 described later.

  As the first high-speed counter 130 is reset and the value of the current value register 131 returns to zero, the count-up output Q1 and the rising comparison output P1 are also reset, and the counting of the reference clock signal CLK1 starts again. As a result, if the signal period of the reference clock signal CLK1 is τ = 1 μsec, the period of the pulse output PLS of the alternating output circuit 142 is 2 × N1 or 2 × N2 (μsec).

  The output selection circuit 143 determines an output mode according to a command from the microprocessor 120 and generates, for example, a forward / reverse pulse output FRP and a rotation direction command output DIR.

  The second high-speed counter 150 counts up and down the pulse output PLS that is the output signal of the alternating output circuit 142. Further, the first setting register 153 of the second high-speed counter 150 stores a value that is ½ of the target total pulse generation number N. Depending on the number of generated pulses, for example, the entire movement by the stepping motor is performed. The amount is determined.

  However, if the target number of generated pulses is an odd number, the even half value before and after that is stored in the first setting register 153, and the current value register 151 is initially set to +1 or -1. It is set as a value.

  The second setting register 152 of the second high-speed counter 150 stores a target low-speed pulse generation number. The amount of movement of the stepping motor due to the low-speed start operation and the low-speed operation before the stop is determined by the number of generated pulses.

  When the current count value of the current value register 151 of the second high-speed counter 150 increases and reaches the set value M2 of the second setting register 152, the rising comparison output P2 is generated. As a result, the selection switching circuit 141 switches the setting cycle of the first high-speed counter 130 from the low-speed cycle to the high-speed cycle.

  When the current count value of the current value register 151 of the second high-speed counter 150 further increases and reaches the set value M1 (M2 ≦ M1) of the first setting register 153, the count-up output Q2 is generated, The high-speed counter 150 starts a subtraction operation. On the other hand, the addition operation is stopped by the negative logic element 159.

  When the descending comparison coincidence output P2 is activated, the selection switching circuit 141 switches the setting cycle of the first high-speed counter 130 from the high-speed cycle to the low-speed cycle again.

When the count current value of the current value register 151 of the second high-speed counter 150 further decreases and returns to zero and the return output Q2 is activated, the reset terminal RS of the first high-speed counter 130 via the OR element 144. A reset command is supplied to stop counting operation. This state is input to the microprocessor 120 as a pulse generation completion signal M4.

As a result, the total number N of pulses generated by the first high-speed counter 130 is the number of low-speed pulses M2 until the rising comparison output P2 of the second high-speed counter 150 is activated and the high-speed pulses until the count-up output Q2 is generated. The sum of the number (M1-M2), the number of high-speed pulses (M1-M2) until the lower comparison output P2 is activated by the subtraction operation, and the number of low-speed pulses M2 until the return output Q2 is activated. Therefore, although the total number of generated pulses is N = 2 × M1, a low-speed pulse is generated for each M2 pulse as an inner number before and after.

  However, the total number of generated pulses is 2 × M1-1 when the current value register 151 is previously set to plus 1 at the start of counting. On the other hand, when minus 1 is set, the total number of generated pulses is 2 × M1 + 1.

  The microprocessor 120 generates a reset command RST for the first and second high-speed counters 130 and 150, and then sets the set values for the first and second setting registers 133 and 132, 153 and 152 from the output port DO. Send. Further, the microprocessor 120 transmits a rotation direction command signal DIR, cancels the reset command RST, and transmits a start command ST / SP. As a result, the first and second high-speed counters 130 and 150 start operating.

  The current value of the number of pulses generated by the current value register 151 is transmitted to the microprocessor 120 through the input port DI. The microprocessor 120 can stop pulse generation in response to a forward rotation limit stop command, a reverse rotation limit stop command, a forced stop command, and the like.

  In addition, the pulse output circuit unit 100 b gives a rotational drive command to the stepping motor 102. The driver 101 for driving the stepping motor 102 includes a driver having a normal rotation drive terminal and a reverse rotation drive terminal, and a driver 101 having a normal rotation drive terminal and a rotation direction command terminal.

  The output selection circuit 143 can generate a pulse output corresponding to these drive formats.

  In the above description, the first high-speed counter 130 and the second high-speed counter 150 are operated as follows in order to perform the low-speed start operation, high-speed operation, low-speed operation before stop, and stop operation at the two-stage speed. ing. That is, the first high-speed counter 130 serving as a pulse generator obtains a low-speed or high-speed output pulse cycle by switching the set value for circulating operation as a ring counter by the first and second setting registers 133 and 132. To work. The second high-speed counter 150 operates so as to count the number of generated pulses and generate a speed switching command signal.

In this speed switching control, the rising comparison output P2 and the falling comparison output P2 that respond to the occurrence of the number of low-speed pulses are used.

  Here, at the start of operation of the second high-speed counter 150, a negative number corresponding to the number of low-speed start operation pulses generated is stored in the current value register 151, and the number of high-speed operation pulses is set in the second setting register 152 In addition, the number of high-speed operation pulses + the number of low-speed operation pulses before stopping can be set in the first setting register 153. If such a setting is made, the low speed start operation is performed while the current value register 151 is negative, the high speed operation is performed after the current value register 151 becomes a positive value, and the rising comparison output P2 Can be operated to stop at a low speed before stopping, and to stop when the count-up output Q2 is generated.

  Next, details of the comparison circuit will be described. FIG. 2A is an overall configuration diagram of a comparison circuit included in the first and second high-speed counters 130 and 150 according to Embodiment 1 of the present invention. When the values of the first setting registers 133 and 153 match the values of the current value registers 131 and 151, the first comparison circuits 136 and 156 generate a comparison match output and set the memory circuit S1. . The set output by the storage circuit S1 is the count-up output Q1 and Q2.

When the values of the second setting registers 132 and 152 match the values of the current value registers 131 and 151, the second comparison circuits 135 and 155 generate a comparison coincidence output to generate the AND elements 138a and 158a. Alternatively, the memory circuit S2 or S3 is set via 138b and 158b. The set output by the storage circuit S2 or S3 is the rising comparison output P1 · P2 or the falling comparison output P1 · P2 .

  The AND elements 138a and 158a enable the set command input to the storage circuit S2 when the logic level of the addition mode terminal UP of the first and second high-speed counters 130 and 150 is "H" and in the addition mode. It is a gate circuit to make.

  The AND elements 138b and 158b enable the set command input to the storage circuit S3 when the logic level of the subtraction mode terminal DN of the first and second high-speed counters 130 and 150 is "H" and the subtraction mode is in effect. It is a gate circuit to make.

The third comparison circuits 137 and 157 generate a comparison coincidence output when the values of the current value registers 131 and 151 coincide with the values of the zero registers 134 and 154 through the AND elements 139 and 159, respectively. The memory circuit S4 is set. The set outputs by the storage circuit S4 are the return outputs Q1 and Q2 .
The AND elements 139 and 159 enable the set command input to the storage circuit S4 when the logic level of the subtraction mode terminal DN of the first and second high-speed counters 130 and 150 is “H” and in the subtraction mode. It is a gate circuit to make.

  Note that the storage states of the storage circuits S1 to S4 are erased by a reset command from the microprocessor 120.

  FIG. 2B is a detailed logic circuit diagram of the first comparison circuits 136 and 156 according to Embodiment 1 of the present invention. The second comparison circuits 135 and 155 and the third comparison circuits 137 and 157 are similarly configured.

  In FIG. 2B, the first setting registers 133 and 153 store n-bit binary data in which the least significant bit is B0 and the most significant bit is Bn. The current value registers 131 and 151 store n-bit binary data in which the least significant bit is A0 and the most significant bit is An. The exclusive OR elements Ex0 to Exn to which the logic signal of each bit is input are configured by a logic circuit whose output logic level is “L” if the input logic levels match.

  The logical sum elements OR0 to ORn-1 are cascade-connected so as to sequentially logically sum the outputs of the exclusive logical sum elements Ex0 to Exn, and the output of the final stage logical sum element OR0 passes through the inverting logic element INV. Is input to the memory circuit S1.

  If the logic level of any bit of the comparison data An to A0 and Bn to B0 does not match, the output logic of the OR element OR0 becomes “H”, and a storage command for the storage circuit S1 is not generated.

  If the logical levels of all the bits of the comparison data An to A0 and Bn to B0 match, the output logic of the OR element OR0 becomes “L”, and a storage command for the storage circuit S1 is generated. However, at the time when the counting input to the first and second high-speed counters 130 and 150 is changed to the logic level “H” and the counting operation is performed, the output of the OR element OR0 becomes the logic level “H”. It has become.

  When the count input changes to “L”, the output logic of the OR element OR0 becomes “L”, and a storage command for the storage circuit S1 is generated. This is a delay determination means for avoiding the coincidence determination in the unstable state immediately after the count input changes to “H”.

  In the above description, the determination of the passage of ascending and descending passage is identified and stored by the difference between the up / down commands of the high speed counter. However, instead of this, it is also possible to determine that the passage is ascending if the count before the count-up output is activated, and that it is the descending pass if the match is after the count-up output is activated.

  In the first embodiment, each of the first and second high-speed counters 130 and 150 has the value of the current value registers 131 and 151 incremented by one count when the counting command changes to the logic level “H”. It increases or decreases, and always increases or decreases after reaching the comparison coincidence point. Therefore, the comparison determination can be based on a comparison match determination as to whether or not they match.

  On the other hand, in the case of the second embodiment to be described later, there is one in which the numerical value stored in the variation value register is added to the current value register by one counting operation. . When a plurality of values (a value larger than 1 which is the minimum unit) are increased / decreased in this way, in the process of increasing / decreasing the value of the current value register, it does not necessarily pass over the comparison coincidence point, and skips. A passing condition occurs.

  In such a case, it is necessary to make a size comparison determination such as “more than or less than the comparison matching point” or “over or below the comparison matching point”. Even in the case of the circuit configuration of FIG. It is possible to change to a determination method.

  Next, details of the operation and operation of the positioning control device according to the first embodiment will be described. FIG. 3 is a characteristic diagram of the positioning control device according to Embodiment 1 of the present invention. FIG. 3A shows the waveform of the reference clock signal CLK1 generated by the clock signal generation circuit 140. FIG.

  FIG. 3B shows the increase / decrease characteristics of the current value register 131 of the first high-speed counter 130. The high mountain height corresponds to the first setting value N1 stored in the first setting register 133, and the low mountain height corresponds to the second setting value stored in the second setting register 132. Corresponds to the value N2.

  FIG. 3C shows the waveform of the pulse output PLS which is an output signal of the alternating output circuit 142. The low speed cycle is T1 = 2 × N1 × τ, and the high speed cycle is T2 = 2 × N2 × τ (where τ is the cycle of the reference clock signal CLK1).

  FIG. 3D shows the increase / decrease characteristics of the value of the current value register 151 of the second high-speed counter 150. The setting value stored in the second setting register 152 is indicated by M2, and the setting value stored in the first setting register 153 is indicated by M1.

  FIG. 3E shows an operation in which the horizontal axis represents time, the vertical axis represents the frequency of output pulses corresponding to the operation speed (that is, the reciprocal of the pulse period), and the cumulative number of pulses generated corresponding to the amount of movement is represented as the area. The speed characteristic is shown.

When the rising comparison output P2 is activated to change the logic level to “H”, the operation is switched from the low speed operation to the high speed operation by the action of the selection switching circuit 141. When the count-up output Q2 is activated and the logic level changes to “H”, the second high-speed counter 150 starts a subtraction operation. When the descending comparison output P2 is activated and the logic level becomes “H”, the high speed operation is switched to the low speed operation. Finally, the pulse generation is completed when the return output Q2 is activated and the logic level becomes “H”.

The total number N of pulse generations by the above series of operations is expressed by the following equation.
N = M2 (Number of low-speed operation pulses after starting)
+2 x (M1-M2) (number of high-speed operation pulses)
+ M2 (Number of low-speed operation pulses before stopping)
= 2 x M1

  Accordingly, the total number N is an even value, but by adding a bias of ± 1 to the current value register 151 at the start of operation, the total number of generated pulses can be made odd.

Next, a series of operations will be described using a flowchart. FIG. 4 is a flowchart showing a series of operations of the positioning control device according to Embodiment 1 of the present invention.
In FIG. 4, step 400 is a step in which the microprocessor 120 starts a pulse output operation. A subsequent step 401 is a step of determining whether or not an operation command is input from the command input signal 108. If an operation command has not been input, a determination of NO is made and the operation end process 402 is entered. On the other hand, if an operation command is input, a determination of YES is made and the process proceeds to step 403.

  In step 402, another control is executed, and the process returns to the operation start step 400 again within a predetermined time. On the other hand, Step 403 is a step of determining whether or not the initial flag is set in Step 410a described later. If the initial flag is not set, a determination of YES is made and the process proceeds to step 405. On the other hand, if the initial flag is already set, a NO determination is made and the process proceeds to step 404.

  When the power is turned on, the initial flag and the first and second high-speed counters 130 and 150 are reset. Therefore, in the operation immediately after the power is turned on, step 403 makes a determination of YES.

Step 404 is a step of determining whether or not a series of pulse outputs are completed by operating the return output Q2 of the second high-speed counter 150. If not completed, a determination of NO is made and the process proceeds to step 420. On the other hand, if completed, a determination of YES is made and the process proceeds to step 405. Step 405 is a step of giving a reset command RST to the first and second high-speed counters 130 and 150 to stop the operation of each counter.

  In the subsequent step 406, the first setting value N1, which is a half of the low speed cycle, is stored in the first setting register 133 of the first high speed counter 130, and the second setting register 132 is stored. This is a step of storing the second set value N2, which is a value of 1/2 of the high-speed cycle.

  In the subsequent step 407, it is determined whether the target total number of pulse generation is an odd number or an even number, and if it is an even number, a determination of YES is made and the process proceeds to step 408a. This is a determination step that moves to step 408b.

  Step 408a sets the current value register 151 of the second high-speed counter 150 to zero, sets the setting value M2 of the second setting register 152 to the number of low-speed movement pulses, and sets the setting value M1 of the first setting register 153. Is set to 1/2 of the target total number N.

  Step 408b sets the value of the current value register 151 of the second high-speed counter 150 to minus 1 (or plus 1), sets the setting value M2 of the second setting register 152 to the number of low-speed movement pulses, and sets the first setting. This is a step of setting the set value M1 of the register 153 to ½ of an even number N−1 (or N + 1) before and after the target total number.

  The process block 409 composed of the above-described steps 406 to 408b serves as a conversion setting means, and the microprocessor 120 calculates and sets values that allow the first and second high-speed counters 130 and 150 to operate easily. It is like that. For example, two-speed operation can be easily performed by setting a cycle that is the reciprocal of the pulse frequency without using the pulse frequency as a target value of the operation speed.

  Step 410a is executed subsequent to step 408a or 408b, specifies the direction by setting the rotation direction command DIR to logic "H" or "L", and gives the start command by setting the start command ST / SP to logic "H". The reset command RST is set to logic “L” to release the reset, and the initial flag is set.

As a result, the pulse output circuit unit 100b generates a pulse output in step 410b. A subsequent step 411 is a step of determining whether or not the return output Q2 of the second high-speed counter 150 is activated and the total number of generated pulses has reached the target value N. If pulse generation is complete, a determination of YES is made and the process proceeds to step 415. On the other hand, if it is not completed, NO is determined and the process proceeds to Step 412.

Step 412 is a step of determining whether or not a predetermined time has elapsed since the start of pulse generation. If it is not exceeded, a determination of NO is made and the operation end process 402 is entered. On the other hand, if the time is exceeded, the process proceeds to step 413 to notify the abnormality, and then proceeds to the operation end process 402.
In step 415, the initial flag set in step 410a is reset, and thereafter, the process proceeds to operation end step 402.

  Step 420 is a step of determining whether or not the forward rotation limit switch 107, the reverse rotation limit switch 105, or the forced stop command switch is activated. When it is necessary to perform an emergency stop, a determination of YES is made and the process proceeds to step 421. On the other hand, when an emergency stop is not required, a NO determination is made and the process proceeds to step 411.

  In step 421, the logic level of the start command ST / SP is set to “L” to stop pulse generation, the initial flag set in step 410a is reset, and then the operation end step 402 is entered.

  The above operation will be generally described. When the first operation, the restart after the operation is completed, or the first operation after the emergency stop, the conversion setting means 409 sets control constants (parameters) for the first and second setting registers. Each time the generation of a series of pulse outputs is completed, resetting by the conversion setting means 409 is performed. Therefore, the microprocessor 120 only needs to transmit the control constant for the next pulse generation while the pulse generation is stopped, so that the interrupt high-speed processing related to the pulse generation operation is unnecessary.

  In the above description, the microprocessor 120 supplies the rotation direction command output DIR and the start command ST / SP to the output selection circuit 143. Further, the output selection circuit 143 outputs the rotation direction command DIR to the driver 101 as it is, and outputs the output signal of the alternating output circuit 142 as the forward / reverse pulse output FRP when the start command ST / SP becomes logic “H”. As shown in FIG.

  Instead, the microprocessor 120 supplies the normal selection pulse output command F / SP and the reverse rotation pulse output command R / SP to the output selection circuit 143, and the output selection circuit 143 outputs the normal rotation pulse output command F / SP. When / SP is logic “H”, the forward rotation pulse output FP is generated, and when reverse rotation pulse output command R / SP is the logic “H”, the reverse rotation pulse output RP is generated, and the forward rotation pulse output command F Pulse generation may be stopped when both / SP and reverse pulse output command R / SP are logic "L".

  As is clear from the above description, the positioning control device according to the first embodiment is based on the setting command information from the microprocessor 120, and the positioning control provided with the pulse output circuit unit 100b that generates a pulse output for positioning control. Device 100. The pulse output circuit unit 100b includes at least first and second high-speed counters 130 and 150, and a program memory 121 that cooperates with the microprocessor 120 includes a control program that serves as a conversion setting unit 409. ing.

  The first high-speed counter 130 variably sets a target pulse output cycle, and includes a current value register 131 that stores a count current value of the clock signal CLK1, and first and second setting registers 133. 132, and first and second comparison circuits 136 and 135.

  The second high-speed counter 150 generates a number of generated pulses and generates a speed switching command signal (corresponding to a reset timing command given to the selection switching circuit), and stores a current value in which an elapsed state of the number of generated pulses is stored. The register 151 includes first and second setting registers 153 and 152, and first and second comparison circuits 156 and 155.

  The conversion setting means 409 acts before the operation of the first and second high-speed counters 130 and 150, and sets the target number of pulse generations for the second high-speed counter 150. A transition characteristic of a pulse output cycle that becomes a target operation speed pattern is set for the second high-speed counter. That is, the conversion setting unit 409 determines a parameter for specifying a desired operation speed pattern, and sets the determined parameter in a register in the pulse output circuit unit 100b.

  In the first comparison circuits 136 and 156 provided in the first and second high-speed counters 130 and 150, the values of the current value registers 131 and 151 are set to be equal to or larger than the setting values of the second setting registers 132 and 152. The count-up outputs Q1 and Q2 are generated when they coincide with the set values of the first setting registers 133 and 153, or when the coincidence points are exceeded or exceeded.

The second comparison circuits 135 and 155 provided in the first and second high-speed counters 130 and 150 are connected to the second comparison circuits 135 and 155 in the process in which the current value registers 131 and 151 are increasing or decreasing. When the set values match the set values of the setting registers 132 and 152 or pass the coincidence state, at least one of the rising comparison outputs P1 and P2 or the falling comparison outputs P1 and P2 is generated.

The pulse output circuit unit 100b responds to the generation of the count-up outputs Q1 and Q2 and the generation of at least one of the rising comparison outputs P1 and P2 or the falling comparison outputs P1 and P2 , and changes the pulse output cycle. A pulse output PLS is generated according to an operation pattern based on the operation pattern. Further, the pulse output circuit unit 100b transmits a pulse generation completion signal M4 to the microprocessor 120 upon completion of pulse generation, and is designated without receiving a command from the microprocessor 120 in the period from the start of pulse generation to completion. A pulse output with the specified characteristics is generated.

  The first high-speed counter 130 counts the reference clock signal CLK1 with a predetermined period and generates a pulse output with a target period. The first setting register 133 of the first high-speed counter 130 stores the first setting value N1 corresponding to the target first pulse period T1 for low-speed operation, and the second setting register 132 The second set value N2 corresponding to the target second pulse period T2 for high speed operation is stored. A selection switching circuit 141 and an alternating output circuit 142 are connected to the first high-speed counter 130.

  The selection switching circuit 141 resets the current value register 131 when the count-up output Q1 of the first high-speed counter 130 is generated, and then restarts the counting of the reference clock signal CLK1 (corresponding to the first reset timing). Or, when the rising comparison output P1 of the first high-speed counter 130 is generated, the current value register 131 is reset and then the reference clock signal CLK1 is counted again (corresponding to the second reset timing). The first high-speed counter 130 operates as a ring counter.

  The alternating output circuit 142 inverts the output logic every time the count-up output Q1 or the rising comparison output P1 of the first high-speed counter 130 is generated, and the cycle τ of the reference clock signal CLK1 and the first or second set value N1 A circuit that generates a pulse output PLS having a period twice as long as the product of N2.

The second high-speed counter 150 counts the number of occurrences of the pulse output PLS of the alternating output circuit 142, and generates the return output Q2 when the generation of the target pulse is completed. The first setting register 153 of the second high-speed counter 150 stores a value M1 that is half the target pulse generation number N, and the second setting register 152 stores the target low-speed operation pulse generation number. M2 is stored.

The second high-speed counter 150 operates as an addition counter until the count-up output Q2 is generated after the counting operation is started, and operates as a subtraction counter after the count-up output Q2 is operated. Further, the second high speed counter 150 issues a command for selecting the first reset timing so that the selection switching circuit 141 is switched to the low speed side from when the counting operation is started until the rising comparison output P2 is generated. To do. Further, after the rising comparison output P2 is generated, the count-up output Q2 is generated, the counting direction is reversed, and until the falling comparison output P2 is generated, the second selection switch circuit 141 is switched to the high speed side. Command to select the reset timing. Further, from the generation of the falling comparison output P2 to the generation of the return output Q2 , a command for selecting the first reset timing is issued so as to switch the selection switching circuit 141 to the low speed side again.

The return output Q2 is set when the current value of the second high-speed counter 150 returns to zero. As the return output Q2 is set, the second high speed counter 150 stops the pulse generation of the first high speed counter 130 or the pulse output PLS of the alternating output circuit 142. Further, the second high-speed counter 150 transmits a pulse generation completion signal M4 to the microprocessor 120. The set state of the return output Q2 is reset by a reset command RST from the microprocessor 120.

  As described above, the positioning control device according to the first embodiment uses the first and second high-speed counters to generate a pulse output by two-stage speed operation of low speed start, high speed operation, and low speed stop. . Therefore, in simple positioning control using a stepping motor, there is a feature that high-speed operation and high-accuracy stop can be performed while preventing step-out.

  Further, when the target pulse generation number N generated by the pulse output circuit unit 100b is an odd number, the current value register 151 of the second high-speed counter 150 is set to minus 1 or plus 1 as an initial value, and the target pulse A half value of the even number before and after the number of occurrences is stored in the first setting register 153 as a setting value.

  In other words, the present value register is configured to be able to start operation by setting ± 1 as an initial value. Therefore, even if the target pulse generation number is an odd number, the two-stage speed operation can be performed using the rising comparison output, the count-up output, and the falling comparison output.

Further, the first and second comparison circuits 136, 135, 156, and 155 generate a binary logic output due to comparison match or comparison mismatch, and a predetermined delay from the time when the logic of the count input signal is inverted to the count state. The data is updated and stored in the storage circuits S1, S2, and S3 after a certain time. As a result, count-up outputs Q1 and Q2 and rising comparison outputs P1 and P2 or falling comparison outputs P1 and P2 are obtained.

  That is, the first and second comparison circuits store the comparison results after the logic is determined whether or not the comparison coincides. Therefore, for a high-speed counter in which the comparison numerical value does not pass over the coincidence point, a comparison result can be obtained by a simple comparison circuit, and at the count timing of the high-speed counter, comparison detection is avoided and erroneous detection is performed. There are features that can be prevented.

  Furthermore, when the first and second high-speed counters 130 and 150 are in the up-count mode, the rising comparison outputs P1 and P2 determine that the second comparison circuits 135 and 155 have passed the coincidence determination or the coincidence point. In this case, it becomes effective and is stored in the storage circuit S2 for ascending comparison determination.

The falling comparison outputs P1 , P2 , P2 , P4 indicate that the second comparison circuits 135 and 155 have passed the coincidence determination or coincidence point when the first and second high-speed counters 130 and 150 are in the down-count mode. It becomes effective when it is determined, and is stored in the storage circuit S3 for the downward comparison determination.

  Here, the storage state of each of the storage circuits S2 and S3 is erased by a reset command RST from the microprocessor 120.

  That is, the distinction between the rising comparison output and the falling comparison output is made according to whether the first and second high-speed counters are in the up-count mode or the down-count mode. Therefore, since the rising comparison output and the falling comparison output can be obtained using only the second comparison circuit, the comparison circuit is simplified.

  Further, the rising comparison outputs P1 and P2 are passed through the coincidence determination or coincidence point by the second comparison circuits 135 and 155 before the count-up outputs Q1 and Q2 of the first and second high-speed counters 130 and 150 are operated. It becomes effective when it is determined that it has been performed, and is stored in the storage circuit S2 for ascending comparison determination.

Decreasing comparison outputs P1 and P2 are determined that the second comparison circuits 135 and 155 pass the coincidence point or coincidence point after the count-up outputs Q1 and Q2 of the first and second high-speed counters 130 and 150 are activated. In this case, it becomes effective and is stored in the storage circuit S3 for the downward comparison determination.

  Here, the storage state of each of the storage circuits S2 and S3 is erased by a reset command RST from the microprocessor 120.

  That is, the distinction between the rising comparison output and the falling comparison output is made according to whether the count-up output of the first and second high-speed counters is before or after the operation. Therefore, since the rising comparison output and the falling comparison output can be obtained using only the second comparison circuit, the comparison circuit is simplified.

  Further, the microprocessor 120 is connected to a plurality of input sensors and a plurality of electric loads, and drives and controls the plurality of electric loads according to the operation state of the input sensors and the contents of the input / output control program stored in the program memory 121. Built in the CPU unit 100a of the programmable controller.

  The pulse output circuit unit 100b is built in an input / output unit connected to the microprocessor 120 by a bus, and includes an output selection circuit 143. The conversion setting means 409 is executed by a special instruction stored in the program memory 121 as a part of the input / output control program.

  The special command sets at least the operation constant including the transition characteristics of the pulse output cycle that becomes the target number of pulse generations and the target operation speed pattern, and the rotation direction command and start / stop command or forward rotation start / Stop command and reverse start / stop command are included.

  Based on the rotation direction command and the start / stop command, or the forward rotation start / stop command and the reverse rotation start / stop command, the output selection circuit 143 outputs the rotation direction command DIR and the forward / reverse rotation pulse output FRP or the forward rotation pulse output FP. A reverse pulse output RP is generated.

  After receiving the pulse generation completion signal M4 from the pulse output circuit unit 100b or when the generation of the pulse output PLS is interrupted and stopped by the operation stop command generated by the microprocessor 120, the microprocessor 120 outputs the pulse by the reset command RST. After the initialization of the circuit unit 100b, the next operation constant is set.

  Here, the microprocessor cooperating with the pulse output circuit unit constitutes the CPU unit of the programmable controller, and the positioning control constant is set by the microprocessor and the rotation direction command and the start command are supplied. It has become so. Therefore, there is a feature that high-speed and high-precision positioning control can be performed by sharing the functions of the microprocessor that performs the overall control and the pulse output circuit that generates the high-speed pulse output.

Embodiment 2. FIG.
FIG. 5 is a block diagram of a positioning control device according to Embodiment 2 of the present invention.
In FIG. 5, for example, a positioning control device 500 constituting a programmable controller is constituted by a CPU unit 500a and a pulse output circuit unit 500b which is a part of an input / output unit.

  The CPU unit 500a is supplied with a predetermined stabilization voltage Vcc via a power supply circuit 510 fed from an external power supply that is a commercial power supply of AC 100V to 240V, for example.

  Inside the CPU unit 500a, a microprocessor 520, a program memory 521, and a RAM memory 522 are provided. Here, the program memory 521 is, for example, a non-volatile flash memory, and stores an input / output control program created by the user. The specific address of the RAM memory 522 is occupied as the position information register 523.

  The pulse output circuit unit 500b is bus-connected to the microprocessor 520, and exchanges command / monitor signals.

  The servo amplifier 501 receives the forward pulse output FP or the reverse pulse output RP from the pulse output circuit unit 500b and drives the servo motor 502. When the servo motor 502 is driven, the workpiece 504 is moved in the forward direction or the reverse direction.

  The servo motor 502 is provided with an encoder 503 that generates a rotation pulse, and feeds back the amount of movement of the workpiece 504 to the servo amplifier 501.

  A command input signal 508 is connected to the microprocessor 520 via an interface circuit (not shown). For example, a forced stop command, a backward limit command by the reverse rotation limit switch 505, a forward limit command by the forward rotation limit switch 507, a manual forward command, Manual reverse command, home return command, automatic operation command, etc. are input.

  When a forced stop command, forward rotation limit command, or reverse rotation limit command is input, the pulse output circuit unit 500b immediately stops generating pulses. When a manual forward command or manual reverse command is given, a low-speed forward pulse output or reverse pulse output is generated. Furthermore, when an automatic operation command is given, the number of pulses commanded by the speed pattern based on the control program stored in the program memory 521 is generated and stopped.

  The near-point dog switch 506 that operates in the vicinity of the origin position is input as a near-point dog signal DOG to the pulse output circuit unit 500b. The zero phase signal generated by the encoder 503 is input to the pulse output circuit unit 500b as the zero point signal ZERO.

  In the second embodiment, the first front-stage high-speed counter 530 is used to gradually increase / decrease the target operation speed, and the generation pulse cycle is determined by the reciprocal of the target frequency. Two upstream high-speed counters 560 are used.

  The first previous high-speed counter 530 connected to the previous stage of the first high-speed counter 550 is configured to up-count the reference clock signal CLK1 generated by the clock signal generation circuit 540. In the first setting register 533, a value corresponding to ½ of the target step time ΔT that gradually increases and decreases is set from the microprocessor 520.

  When the current count value of the current value register 531 of the first front-stage high-speed counter 530 increases and reaches the set value N of the first setting register 533, a count-up output Q1 is generated, and the first front-stage high-speed counter 530 is reset. Accordingly, the output of the first alternating output circuit 542a is alternately inverted.

  As the first pre-stage high-speed counter 530 is reset and the value of the current value register 531 returns to zero, the count-up output Q1 is also reset and the counting of the reference clock signal CLK1 starts again. As a result, the generation period of the count-up output Q1 is equal to N × τ, which is the product of the set value N and the period τ of the reference clock signal. The period of the output pulse of the first alternating output circuit 542a is 2 × N × τ, which is twice that value, which corresponds to the step time ΔT.

  Therefore, the first pre-stage high-speed counter 530 serves as a step time generation means for a gradually increasing and decreasing pattern. In FIG. 5, a change in the current count value of the current value register 531 is indicated by a sawtooth waveform 541a.

  The first high-speed counter 550 connected to the next stage counts up or down using the output signal of the first alternating output circuit 542a as a count input. Further, the value of the gradually decreasing and increasing frequency Δf stored in the variation value register 551a is added to or subtracted from the current value register 551 by one up / down command.

  The first high speed counter 550 is for generating the speed pattern 541b. Accordingly, the value of the pulse frequency f1 corresponding to the target operating speed is set in the first setting register 553, and the value of the pulse frequency f2 corresponding to the low speed before stopping is set in the second setting register 552. The current value register 551 is set with the value of the pulse frequency f0 corresponding to the initial speed at the start of operation, and the variation value register 551a is set with the value of the gradually increasing and decreasing frequency Δf.

  However, normally, the same value is used for the low speed and the initial speed, and f2 = f0. As a result, every time a count input signal with a period ΔT is input to the count input terminal IN, the value of the current value register 551 is sequentially added with the incremental frequency Δf with the initial speed pulse frequency f0 as an initial value. When this added current value reaches the pulse frequency f1 corresponding to the target operation speed stored in the first setting register 553, a count-up output Q2 is generated, and an up command input is received by the output of the negative logic element 544. Stop. Therefore, even if the count input occurs, the value of the current value register 551 maintains a constant value.

  However, when a second high-speed counter 570 described later generates a deceleration start command, the first high-speed counter 550 starts a subtraction operation by the outputs of the logical sum element 546a and the gate element 546b. Each time a count input signal with a period ΔT is input to the count input terminal IN, the gradually decreasing frequency Δf is sequentially subtracted from the current value register 551.

Eventually, when the value of the current value register 551 becomes equal to or lower than the low speed frequency f2 (= f0) stored in the second setting register 552, the falling comparison output P2 becomes the logic level “H”. Thereby, the output of the gate element 546b is inverted to the logic level “L”, so that the subtraction operation is stopped, and the value of the current value register 551 maintains the value of the low speed frequency f2 (= f0). Yes.

  The second upstream high-speed counter 560 is configured to sequentially add the increment value stored in the variation value register 561a to the current value register 561 by the reference clock signal CLK1 generated by the clock signal generation circuit 540. A predetermined coefficient K (eg, K = 500,000) is set from the microprocessor 520 in the first setting register 563.

  In addition, the value of the current value register 551 of the first high-speed counter 550 is sequentially updated and stored in the variation value register 561a. Therefore, the increment value stored in the variation value register 561a is sequentially added to the current count value of the current value register 561 of the second pre-stage high-speed counter 560 by the ON / OFF operation of the reference clock signal CLK1. When the coefficient K stored in the first setting register 563 is reached, the count-up output Q3 is generated and the second pre-stage high-speed counter 560 is self-reset and repeats the same operation.

  As a result, the generation cycle of the count-up output Q3 becomes faster as the increment value stored in the variation value register 561a is larger. The output of the second alternating output circuit 542b is a pulse output with a period inversely proportional to the increment value stored in the variation value register 561a. This pulse output is output to the servo amplifier 501 through the output selection circuit 543 as a normal rotation pulse output FP or a reverse rotation pulse output RP.

  The output mode of the output selection circuit 543 is determined by the microprocessor 520 so that, for example, the normal rotation pulse output FP and the reverse rotation pulse output RP are output, or the normal rotation pulse FRP and the direction signal output DIR are output. It has become.

  The second high-speed counter 570 is a counter that counts up the output signal of the second alternating output circuit 542b and counts the number of pulse generations. The first setting register 573 of the second high-speed counter 570 stores the target pulse generation number, and the second setting register 572 stores the pulse generation number up to the deceleration start point.

  These set values are transmitted from the microprocessor 520 in advance.

  When the second high-speed counter 570 counts the number of generated pulses and eventually reaches the number of pulses up to the deceleration start point stored in the second setting register 572, the rising comparison output P4 becomes the logic level “H”. Then, the subtraction operation of the first high-speed counter 550 is started via the logical sum element 546a and the gate element 546b.

  The second high-speed counter 570 counts the number of pulse generations, and when the target pulse generation number stored in the first setting register 573 is reached, the count-up output Q4 becomes the logic level “H”. Then, the second high-speed counter 570 stops the operation of all the reversible counters, stops the generation of pulse output, and transmits a pulse generation completion signal M4 to the microprocessor 520.

  Note that the operation of the dotted line portions in FIG. 5 (portions indicated by reference numerals 570, 571, and 573) will be described with reference to FIG. FIG. 6 is another block diagram of the positioning control device according to Embodiment 2 of the present invention. The solid line portion in FIG. 5 is a connection circuit when the command input signal 508 for the microprocessor 520 is a manual advance, manual reverse, or automatic operation command. On the other hand, FIG. 6 shows a connection circuit when the command input signal 508 to the microprocessor 520 is an origin return command.

  In FIG. 6, the first pre-stage high-speed counter 530 operates in the same manner as in FIG. 5, and is set by the first setting register 533 while up-counting the reference clock signal CLK1 generated by the clock signal generation circuit 540. The repetitive operation corresponding to the gradually increasing and decreasing step time is performed. The change in the current count value of the current value register 531 changes to a sawtooth waveform 541a as shown in FIG.

  The first high-speed counter 550 is also a circuit that performs substantially the same operation as in FIG. 5 and generates a speed pattern as shown by a characteristic diagram 541c in FIG. However, in the case of FIG. 6, since the initial speed is not set for the current value register 551, the speed increase pattern gradually increases from zero.

  The first high-speed counter 550 starts the subtraction operation depending on the operation of the near-point dog signal DOG. The near-point dog signal DOG supplies a down command to the first high-speed counter 550 via the OR element 546a and the gate element 546b based on a switch signal that is turned ON before the machine origin. .

Further, at the deceleration completion stage, a constant speed corresponding to the slow operation speed (creep speed) stored in the second setting register 552 is maintained. This is because the down operation is stopped via the gate element 546b by the falling comparison output P2 .

  The second previous-stage high-speed counter 560 also performs exactly the same operation as in FIG. 5, and the current value of the previous-stage current value register 551 is sequentially transferred to the variation value register 561a. A pulse output having a period inversely proportional to the frequency corresponding to the operation speed is obtained from the output terminal of the second alternating output circuit 542b.

  The second high-speed counter 570 is a counter that counts up the zero-phase signal generated by the encoder 503 provided in the servo motor 502. The count signal input is an output signal of the AND element 546c to which the output of the count start determination circuit 547 and the zero point signal ZERO are input.

  The counting start determination circuit 547 includes a holding circuit 548 and a gate element 549. The holding circuit 548 stores that the near-point dog signal DOG has changed from OFF to ON and the logic level has changed from “L” to “H”. Further, the output of the gate element 549 is configured such that the logic level becomes “H” when the proximity dog signal DOG changes from ON to OFF after the holding circuit 548 is set.

  As a result, the zero point signal ZERO is input to the count input terminal IN of the second high-speed counter 570 via the AND element 546c after the near point dog signal DOG once operates and then returns to the inoperative state. It has become.

  The relationship between the near-point dog signal DOG and the zero-point signal ZERO will be described later in detail with reference to FIG. 9, but generally, the following operation is performed. The near-point dog signal DOG once becomes the logic level “H” near the origin, and when the deceleration is almost completed, the near-point dog signal DOG again becomes the logic level “L”. Thereafter, the second high speed counter 570 starts counting the zero point signal ZERO.

  When the current count value in the current value register 571 of the second high-speed counter 570 reaches the value of the number of zero point signals stored in the first setting register 573 in advance, a count-up output Q4 is generated. Then, the second high speed counter 570 stops the operation of all the high speed counters and the generation of the pulse output, and generates the clear signal CLR via the output selection circuit 543. Further, the second high-speed counter 570 transmits a pulse generation completion signal M4 to the microprocessor 520.

  The clear signal CLR is used as a signal for initializing the servo amplifier. In FIG. 5, the second high-speed counter 570, which counts the number of generated pulses, is shared as a counter for counting the zero point signal ZERO in FIG. The number of use is suppressed.

  In the above description, the second setting registers 532 and 562 in the first and second pre-stage high-speed counters 530 and 560 and the second setting register 572 of the second high-speed counter 570 in FIG. It has become. However, in either case, the second setting register can be used so that the first setting register is not used. In this case, the rising comparison output is used instead of the count-up output.

  Next, details of the comparison circuit will be described. FIG. 7A is an overall configuration diagram of a comparison circuit for the first and second high-speed counters 550 and 570 according to Embodiment 1 of the present invention. The first pre-stage high speed counter 530 and the second pre-stage high speed counter 560 are similarly configured.

  The first comparison circuits 556 and 576 generate a comparison determination output and set the memory circuit S1 when the values of the first setting registers 553 and 573 are equal to or less than the values of the current value registers 551 and 571. . The set output by the storage circuit S1 is the count-up output Q2, Q4.

The second comparison circuits 555 and 575 compare the values when the values of the second setting registers 552 and 572 are equal to or smaller than the values of the current value registers 551 and 571 or when the value on the setting value side becomes large. A determination output is generated, and the memory circuit S2 or S3 is set via the AND elements 558a, 578a, 558b, and 578b. The set output by the storage circuit S2 or S3 is the rising comparison output P2 / P4 or the falling comparison output P2 / P4 .

  The AND elements 558a and 578a receive the set command input to the storage circuit S2 when the logic level of the addition mode terminal UP of the first and second high-speed counters 550 and 570 is “H” and the addition mode is in the addition mode. It is a gate circuit to enable.

  The AND elements 558b and 578b enable the set command input to the storage circuit S3 when the logic level of the subtraction mode terminal DN of the first and second high-speed counters 550 and 570 is “H” and in the subtraction mode. It is a gate circuit to make.

The third comparison circuits 557 and 577 generate a comparison determination output when the values of the current value registers 551 and 571 are equal to or less than the values of the zero registers 554 and 574, and pass through the AND elements 559 and 579. The memory circuit S4 is set. The set output by the storage circuit S4 is the return output Q2 and Q4 .

  The AND elements 559 and 579 enable the set command input to the storage circuit S4 when the logic level of the subtraction mode terminal DN of the first and second high-speed counters 550 and 570 is “H” and is in the subtraction mode. It is a gate circuit to make.

  FIG. 7B is a detailed logic circuit diagram of the first comparison circuits 556 and 576 in Embodiment 2 of the present invention. The second comparison circuits 555 and 575 and the third comparison circuits 557 and 577 are similarly configured.

  In FIG. 7B, the first setting registers 553 and 573 store n-bit binary data in which the least significant bit is B0 and the most significant bit is Bn. The current value registers 551 and 571 store n-bit binary data in which the least significant bit is A0 and the most significant bit is An. The output of the mixed OR element Lxn that inputs the inverted logic of Bn and An of each bit is logic “0” only when Bn = 1 and An = 0 (that is, when Bn> An). .

  The logical output X1 obtained by sequentially cascading the outputs of the mixed OR elements Lxn to Lx0 by the AND elements ADn-1 to AD0 and logically inverted by the negative OR element ORN in the final stage is a set numerical value B> Only when the current value is A, the logic level is “H”. Further, the logical output X2 obtained from the logical product output at the final stage via the gate element GAT has the logic level “H” when the set numerical value B ≦ the current numerical value A.

  However, when the counting input to the first and second high-speed counters 550 and 570 is changed to the logic level “H” and the counting operation is performed, the outputs of the logic outputs X1 and X2 are the logic level “L”. " The comparison determination signal becomes valid when the count input changes to “L”.

  This is a delay determination means for avoiding a comparative determination in an unstable state immediately after the count input changes to “H”.

  The comparison determination result by the logic output X2 is stored in the storage circuits S1, S2, and S4 when the count input becomes “L”. The inverted output of the logic output X2 is stored in the storage circuit S3 when the count input becomes “L”.

  In the above description, the determination of the passage of ascending and descending passage is identified and stored by the difference between the up / down commands of the high speed counter. However, instead of this, it is also possible to determine that the passage is ascending if the count before the count-up output is activated, and that it is the descending pass if the match is after the count-up output is activated.

  In the second embodiment, both the first high-speed counter 550 and the second previous-stage high-speed counter 560 have the values of the current value registers 551 and 561 at the time when the count command changes to the logic level “H”. It is a significant increase or a significant decrease, and does not always reach a comparison match. Therefore, a size comparison determination such as “more than or less than the comparison matching point” or “over or below the comparison matching point” is required.

  However, if the setting values for the first and second setting registers 553 and 552 of the first high-speed counter 550 are set to an integral multiple of the variation frequency Δf stored in the first variation register 551a, The first high-speed counter 550 can be based on a comparison coincidence determination method.

  Next, the details of the operation and operation of the positioning control device according to the second embodiment will be described. FIG. 8 is a characteristic diagram of the positioning control device corresponding to the configuration of FIG. 5 in the second embodiment of the present invention, and shows an operation speed pattern during normal operation. FIG. 9 is a characteristic diagram of the positioning control device corresponding to the configuration of FIG. 6 in the second embodiment of the present invention, and shows an operation speed pattern during the home return operation.

  In FIG. 8, the initial speed f0 corresponds to the initial value stored in the current value register 551, the operating speed f1 corresponds to the first set value stored in the first setting register 553, and the low speed f2 This corresponds to the second setting value stored in the second setting register 552. The acceleration / deceleration time ΔT corresponds to a value twice the variation time stored in the first setting register 533, and the variation value Δf is a variation frequency stored in the first variation register 551a. It corresponds to. Further, the target movement amount N corresponds to the total number of pulses generated stored in the first setting register 573, and the deceleration start Nd corresponds to the number of pulses generated up to the deceleration start point stored in the second setting register 572. is doing.

  The remaining movement amount ΔN after the start of deceleration is calculated by the microprocessor 520 based on the operation speed f1 and the deceleration gradient Δf / ΔT.

  On the other hand, in FIG. 9, the operating speed f1 corresponds to the first set value stored in the first setting register 553, and the slow speed f2 is set to the second set value stored in the second setting register 552. Equivalent to. The acceleration / deceleration time ΔT corresponds to a value twice the variation time stored in the first setting register 533, and the variation value Δf is a variation frequency stored in the first variation register 551a. It corresponds to.

  The deceleration start of the first high-speed counter 550 is started by the operation of the near point dog signal DOG. The pulse generation is completed when the number of occurrences of the zero point signal ZERO reaches a predetermined value after the near-point dog signal DOG has returned to the inoperative state when the operation speed has sufficiently decreased. Finally, a clear signal CLR is supplied to the servo amplifier 501.

  Next, a series of operations will be described using a flowchart. FIG. 10 is a flowchart showing a series of operations of the positioning control apparatus corresponding to the configurations of FIGS. 5 and 6 in the second embodiment of the present invention. Moreover, FIG. 11 is a flowchart which shows the detailed operation | movement regarding the one part process of FIG. 10 in Embodiment 2 of this invention.

  In FIG. 10, a process 700 is a step in which the microprocessor 520 starts a pulse output operation. A subsequent step 701 is a step of determining whether or not an operation command is input from the command input signal 508. If the operation command has not been input, a NO determination is made and the process proceeds to the operation end step 702. On the other hand, if an operation command is input, a determination of YES is made and the process proceeds to step 703.

  In step 702, another control is executed, and the process returns to the operation start step 700 again within a predetermined time. On the other hand, Step 703 is a step of determining whether or not the initial flag is set in Step 710a described later. If the initial flag is not set, a determination of YES is made and the process proceeds to step 705. On the other hand, if the initial flag is already set, a NO determination is made and the process proceeds to step 704.

  When the power is turned on, the initial flag and each high-speed counter are reset. Therefore, in the operation immediately after the power is turned on, step 703 determines YES.

  Step 704 is a step of determining whether or not a series of pulse outputs has been completed by operating the count-up output Q4 of the second high-speed counter 570. If not completed, NO is determined and the process proceeds to step 720. On the other hand, if completed, a determination of YES is made and the process proceeds to step 705.

  Step 705 is a step of giving a reset command RST to each high-speed counter and stopping the operation of each counter. A subsequent step 706 is a step of determining whether or not the operation command is an origin return command. If it is an origin return command, a determination of YES is made and the process proceeds to step 707a. On the other hand, if the origin is not returned, NO is determined and the process proceeds to Step 707b.

  In step 707a, the input / output circuit of the second high-speed counter 570 is configured as shown in FIG. 6, and then the process proceeds to step 708a. On the other hand, in step 707b, the input / output circuit of the second high-speed counter 570 is configured as shown in FIG. 5, and then the process proceeds to step 708b. In steps 708a and 708b, the circuit is changed by operating a gate circuit (not shown) for switching wiring.

  In step 708a, which serves as a conversion setting means in the return-to-origin operation, a value that is 1/2 of the variation time ΔT of the gradually increasing / gradually decreasing frequency is set in the first setting register 533 of the first preceding high-speed counter 530. The current value register 531 is set to zero.

  Further, the first setting value f1 that is the high speed operation speed is set in the first setting register 553 of the first high speed counter 550, and the slow speed operation speed before the stop is set in the second setting register 552. Is set, and the current value register 551 is set to zero. Furthermore, the first variation register 551a is set with a variation frequency Δf of gradually increasing / decreasing frequency, and the first setting register 563 of the second upstream high-speed counter 560 is set to, for example, 5 of the maximum operating speed fmax. A double value is set and zero is set in the current value register 561. Further, the number of zero point signals is set in the first setting register 573 of the second high-speed counter 570, and zero is set in the current value register 571.

  In step 708b, which is a conversion setting means in normal operation, a value of ½ of the variation time ΔT of the gradually increasing / gradually decreasing frequency is set in the first setting register 533 of the first front-stage high-speed counter 530, The current value register 531 is set to zero.

  Also, the first setting value f1 that is the high speed operation speed is set in the first setting register 553 of the first high speed counter 550, and the low speed operation speed before the stop is set in the second setting register 552. Is set, and the initial speed f0 at the start of operation is set in the current value register 551. Furthermore, the first variation register 551a is set with a variation frequency Δf of gradually increasing / decreasing frequency, and the first setting register 563 of the second upstream high-speed counter 560 is set to, for example, 5 of the maximum operating speed fmax. A double value is set and zero is set in the current value register 561. The total number N of target pulse generations is set in the first setting register 573 of the second high-speed counter 570, and the number of generated pulses up to the deceleration start point is set in the second setting register 572. The current value register 571 is set to zero.

  The process block 709 composed of the above-described processes 708a and 708b serves as conversion setting means, and the microprocessor 520 includes the first and second high-speed counters 550 and 570 and the first and second previous high-speed counters. The values set so that 530 and 560 can operate easily are set.

  Step 710a is executed following step 708a or 708b, and the logic of the forward rotation pulse output command F / SP is set to “H” or the logic of the reverse rotation pulse output command R / SP is set to “H”. Thereby, a rotation direction command and a start command are given, the reset command RST is set to logic “L”, the reset is released, and the initial flag is set.

  As a result, in step 710b, the pulse output circuit unit 100b generates a pulse output. A subsequent step 711 is a determination step for operating the count-up output Q4 of the second high-speed counter 570. If pulse generation is complete, a determination of YES is made and the process moves to process block 714. On the other hand, if it is not completed, a determination of NO is made and the process proceeds to step 712.

  Step 712 is a step of determining whether or not a predetermined time has elapsed since the start of pulse generation. If not, NO is determined and the process proceeds to the operation end step 702. On the other hand, if the time is exceeded, the process proceeds to step 713, the abnormality is notified, and then the operation end process 702 is performed.

  Step 720 is a step of determining whether the forward rotation limit switch 507, the reverse rotation limit switch 505, or the forced stop command switch is activated. When it is necessary to perform an emergency stop, a determination of YES is made and the process proceeds to step 721. On the other hand, when the emergency stop is unnecessary, the determination of NO is made and the process proceeds to Step 711.

  In step 721, the logic level of the forward pulse output command F / SP or the reverse pulse output command R / SP is set to “L” to stop pulse generation, and the initial flag set in step 710a is reset. The process proceeds to the operation end process 702.

  In FIG. 11 showing the details of the process block 714 described above, a process 800 is an operation start step of a subroutine that is activated when the determination of the process 711 is YES. Subsequent step 801 is a step that operates depending on whether or not the determination in step 706 is a return to origin. If it is the origin return mode, a determination of YES is made and the process proceeds to step 802. On the other hand, if it is not the origin return mode, NO is determined and the process proceeds to step 803.

In step 802, the coordinate value at the origin position is written and set in the position information register 523 provided in the RAM memory 522. In step 803, the value of the current value register 571 of the second high-speed counter 570 is read, and the read current value is algebraically added to the position information register 523 in accordance with the rotation direction command set in step 710a. Subsequent to step 802 or step 803, a subroutine operation end step 804 is performed, and then the process proceeds to step 715 in FIG.
In step 715, the initial flag set in step 710a is reset, and thereafter, the process proceeds to the operation end step 702.

  The above operations will be generally described. At the time of initial operation, at the time of restart after completion of operation, or at the time of initial operation after an emergency stop, the conversion setting means 709 sets control constants for each high-speed counter, and a series of pulse outputs. Each time the occurrence of occurrence is completed, resetting by the conversion setting unit 709 is performed. Therefore, since the microprocessor 520 only needs to transmit the control constant for the next pulse generation while the pulse generation is stopped, the high-speed interrupt processing related to the pulse generation operation is unnecessary.

  In the above description, the microprocessor 520 supplies the forward selection pulse output command F / SP and the reverse rotation pulse output command R / SP to the output selection circuit 543. Further, the output selection circuit 543 generates the normal rotation pulse output FP when the normal rotation pulse output command F / SP is logic “H”, and when the reverse rotation pulse output command R / SP is logic “H”. In addition, the reverse rotation pulse output RP is generated, and the pulse generation is stopped when both the normal rotation pulse output command F / SP and the reverse rotation pulse output command R / SP are logic “L”.

  Instead, the microprocessor 520 supplies the rotation direction command output DIR and the start command ST / SP to the output selection circuit 543, and the output selection circuit 543 outputs the rotation direction command DIR to the servo amplifier 501 as it is. When the start command ST / SP becomes logic “H”, the output signal of the second alternating output circuit 542b may be supplied to the servo amplifier 501 as the forward / reverse pulse output FRP.

  As a command input signal 508 to the microprocessor 520, as a control operation when the manual forward command button is kept pressed or when the manual reverse command button is kept pressed, the control input is gradually increased immediately after the command button is pushed. A control program is applied that increases to the target speed based on the speed characteristics and stops based on the gradually decreasing speed characteristics when the command button is pressed. Even if the command button is kept pressed, it automatically stops when the forward rotation limit switch or the reverse rotation limit switch operates.

  If the command button is stopped before the forward rotation limit switch or the reverse rotation limit switch is activated, the vehicle thereafter decelerates and stops with a gradually decreasing speed pattern opposite to that at the start.

  As is apparent from the above description, the positioning control apparatus according to the second embodiment is based on the setting command information from the microprocessor 520, and the positioning control including the pulse output circuit unit 500b that generates a pulse output for positioning control. Device 500. The pulse output circuit unit 500b includes at least first and second high-speed counters 550 and 570, and a program memory 521 that cooperates with the microprocessor 520 includes a control program that serves as a conversion setting unit 709. ing.

  The first high-speed counter 550 variably sets a target pulse output frequency. The first high-speed counter 550 includes a current value register 551 that stores a current count value of the divided clock signal CLK2, and first and second settings. The registers 553 and 552 and first and second comparison circuits 556 and 555 are configured.

  The second high-speed counter 570 includes a current value register 571 that stores an elapsed state of the number of pulse generations, first and second setting registers 573 and 572, and first and second comparison circuits 576 and 575. It is configured.

  The conversion setting means 709 acts before the operation of the first and second high-speed counters 550 and 570, and sets the target number of pulse generations for the second high-speed counter 570. A transition characteristic of a pulse output frequency that becomes a target operation speed pattern is set for the second high-speed counter.

  In the first comparison circuits 556 and 576 provided in the first and second high-speed counters 550 and 570, the values of the current value registers 551 and 571 are set to be larger than the setting values of the second setting registers 552 and 572. The count-up outputs Q2 and Q4 are generated when the set values match the set values of the first setting registers 553 and 573, or when the coincidence points are exceeded or exceeded.

The second comparison circuits 555 and 575 provided in the first and second high-speed counters 550 and 570 have the second comparison circuits 555 and 575 in the process in which the values of the current value registers 551 and 571 are increasing or decreasing. When the set values match the set values of the setting registers 552 and 572, or pass the coincidence state, at least one of the rising comparison outputs P2 and P4 or the falling comparison outputs P2 and P4 is generated.

The pulse output circuit unit 500b operates in response to the generation of at least one of the count-up outputs Q2 and Q4 and the rising comparison outputs P2 and P4 or the falling comparison outputs P2 and P4. To generate a pulse output PLS. Further, the pulse output circuit unit 500b transmits a pulse generation completion signal M4 to the microprocessor 520 when the pulse generation is completed, and does not receive a command from the microprocessor 520 in the period from the start of the pulse generation to the completion. A pulse output with the specified characteristics is generated.

  The first high-speed counter 550 is for generating a frequency transition pattern of an output pulse that becomes a gradual increase / decrease speed pattern from low speed to high speed or from high speed to low speed, and the first variation value register 551a is stored in the first variation value register 551a. In addition, a first preceding high-speed counter 530 is connected.

  The first front-stage high-speed counter 530 counts the reference clock signal CLK1 having a predetermined cycle, and also uses the first alternating output circuit 542a to divide the variable clock signal CLK2 (set in the first setting register 533). This is a circuit for generating a count input signal output from the first alternating output circuit 542a in a cycle of a target gradually increasing and decreasing step time ΔT. The first or second setting register 533 or 532 of the first pre-stage high-speed counter 530 stores a half value of the required variation time ΔT corresponding to a predetermined variation value Δf of a gradually increasing / decreasing frequency. Each time the up output Q1 or the rising comparison output P1 is generated and the current value register 531 is reset, the output logic of the first alternating output circuit 542a is inverted.

  The first variation value register 551a operates when an addition or subtraction count input is given to the first high-speed counter 550, and is stored in the first variation value register 551a with respect to the current value register 551. It is a numerical value register for adding or subtracting the variation value Δf of the frequency that is present.

  The first high speed counter 550 counts the variable frequency divided clock signal CLK2 generated by the first preceding high speed counter 530. The first setting register 553 of the first high-speed counter 550 stores a first setting value f1 corresponding to the target first pulse frequency for high-speed operation, and the second setting register 552 stores The second set value f2 corresponding to the target second pulse frequency for low speed operation before stopping is stored, and the current value register 551 stores the third pulse for low speed operation at the start of target operation. A third set value f0 corresponding to the frequency is stored as an initial value, and a frequency variation value Δf is stored in the first variation value register 551a.

The current value of the first high-speed counter 550 gradually increases from the third set value f0 with the start of counting, and the addition operation stops with the occurrence of the count-up output Q2, and the first set value f1 To last. On the other hand, when the deceleration start command is given, it gradually decreases, and the subtraction operation is stopped when the descending comparison output P2 is generated, and the second set value f2 is maintained.

  The second high speed counter 570 counts pulses having a period proportional to the reciprocal of the value of the current value register 551 of the first high speed counter 550. Furthermore, the target setting number N of pulses is set in the first setting register 573 of the second high-speed counter 570, and the pulse setting number Nd up to the deceleration start point is set in the second setting register 572. Is set.

  The subtraction operation of the first high-speed counter 550 is started when the rising comparison output P4 of the second high-speed counter 570 is generated, and the first high-speed counter 550 is generated when the count-up output Q4 is generated. The pulse generation is stopped, and a pulse generation completion signal M4 is transmitted to the microprocessor 520.

  As described above, the positioning control device according to the second embodiment is configured so that the increase / decrease variation value of the frequency stored in the variation value register is added to or subtracted from the current value register. The current value of the first high-speed counter is increased or decreased by a clock signal having a variable period corresponding to the gradual increase / decrease characteristics.

  In particular, the deceleration start timing is automatically determined based on the information of the deceleration start point preset from the microprocessor for the second high-speed counter. Accordingly, there is a feature that it is possible to easily generate a gradually increasing / decreasing speed pattern using the rising comparison output, the count-up output, and the falling comparison output.

  Furthermore, the second high speed counter 570 includes a second preceding high speed counter 560 for obtaining the reciprocal of the current value of the first high speed counter 550. The second upstream high-speed counter 560 includes a second variation value register 561a and a second alternating output circuit 542b. A predetermined coefficient K is set in the first setting register 563 or the second setting register 562 of the second upstream high-speed counter 560.

  The second variation value register 561a stores the value of the current value register 551 of the first high-speed counter 550 that becomes the target frequency. The second variation value register 561a operates when an addition count input is given to the second previous-stage high-speed counter 560, so that the second variation value register 561a has the second variation value register 561a with respect to the current value register 561 of the second previous-stage high-speed counter 560. The value of the target frequency stored in the second variation value register 561a is added.

  The second alternating output circuit 542b outputs the count-up output Q3 or the rising comparison output P3 of the second preceding high-speed counter 560 every time the current value of the second preceding high-speed counter 560 is reset. The logic is inverted, and a pulse output PLS having a cycle twice the quotient obtained by dividing the predetermined coefficient K by the value of the second variation value register 561a is generated. The second high-speed counter 570 counts the output signal of the second alternating output circuit 542b.

  In other words, the current value register of the second pre-stage high-speed counter is configured to add the target frequency stored in the variation value register, and the accumulated addition value exceeds the predetermined coefficient value to increase the first frequency. When the second high-speed counter is initialized and restarted, a pulse output having a period inversely proportional to the target frequency is generated. Therefore, there is a feature that adjustment of a pulse period that changes every moment according to a target speed pattern can be executed on the pulse output circuit side to reduce the control burden on the microprocessor.

  Further, the first and second high-speed counters 550 and 570 are connected to positioning input / output signals that respond to the origin return command. The input signal for position determination includes a near point dog signal DOG and a zero point signal ZERO. The near-point dog signal DOG operates near the origin, and returns to operation at a position near the origin. The zero point signal ZERO is provided in the servo motor 502 driven by the pulse output PLS, and is input as a Z-phase signal that generates one pulse output per one rotation of the servo motor 502.

  The positioning output signal is a clear signal CLR for resetting the positioning deviation residual pulse of the servo amplifier 501 that drives the servo motor 502 when the home search is completed.

  The second high-speed counter 570 does not count the pulse output PLS that is the output of the second alternating output circuit 542b when an origin return command is given. Instead, the intermittent pulse signal, which is the zero point signal ZERO, is counted along with the return of the operation of the near point dog signal DOG, and the generation of the pulse output PLS is stopped when the number of zero point signals reaches a predetermined set value. To do. Then, a pulse generation completion signal M4 is transmitted to the microprocessor 520, and a clear signal CLR is supplied to the servo amplifier 501.

  The first high speed counter 550 counts the variable frequency divided clock signal CLK2 generated by the first preceding high speed counter 530. The first setting register 553 of the first high-speed counter 550 stores the first setting value f1 corresponding to the target first pulse frequency for the origin return operation, and the second setting register stores The second set value f2 corresponding to the target second pulse frequency for slow speed operation is stored, and the current value register 551 corresponds to the target third pulse frequency for low speed operation at the start of operation. The third set value f0 is stored as an initial value, and the frequency variation value Δf is stored in the first variation value register 551a.

The current value of the first high-speed counter 550 gradually increases from the third set value f0 with the start of counting, and the addition operation is stopped when the count-up output Q2 is generated. Continue f1. On the other hand, the current value of the first high-speed counter 550 gradually decreases when the deceleration start command is given, and the subtraction operation is stopped when the descending comparison output P2 is generated, and the second set value f2 is set. continue. The deceleration start command is generated by the operation of the near point dog signal DOG that operates when approaching a position near the target origin.

  That is, when an origin return command is given, the second high-speed counter does not count generated pulses, counts the number of zero point signals after the near-point dog signal has returned to operation, and the number of zero point signals is predetermined. The operation is completed when the value is reached. Further, when the near-point dog signal is activated, the first high-speed counter starts a subtraction operation, and stops after entering the slow speed operation state. Therefore, the second high-speed counter has a feature that the normal operation control and the origin return control are combined, and the number of necessary counters can be reduced.

  Further, the RAM memory 522 that cooperates with the microprocessor 520 includes a position information register 523 that stores absolute position information, and the program memory 521 includes a current position initialization unit 802 and an algebra addition unit 803. .

  Here, the current position initialization means 802 is means for writing and storing predetermined origin position information in the position information register 523 when the origin return operation is completed. The algebra addition means 803 reads the value of the current value register 571 of the second high speed counter 570 at the time when one positioning control by the speed pattern is completed, and the position information register according to the commanded rotation direction. This is means for algebraically adding the current movement amount to 523.

  The microprocessor 520 instructs the relative movement amount and movement direction calculated as the deviation between the next target position and the contents of the position information register 523 as setting information for the counter circuit 500b.

  That is, the microprocessor always keeps track of the current position using the position information register. Therefore, since a setting command based on the relative movement amount can always be given to the pulse output circuit unit, it is not necessary to store the absolute position on the pulse output circuit unit side, and a simple pulse output circuit unit can be obtained. There are features.

Further, the first and second comparison circuits 556, 555, 576, and 575 generate a binary logic output that is larger or smaller than or equal to or less than or equal to or greater than or less than the coincidence point at the comparison coincidence point. Furthermore, the count-up outputs Q2, Q4 and the rising comparison output P2,. P4 or descending comparison outputs P2 and P4 are obtained.

  That is, the first and second comparison circuits generate large and small binary logic outputs with the comparison coincidence as a boundary, and store the comparison results after the logic is determined. Therefore, there is a feature that a comparison result can be obtained even when the comparison numerical value passes over the coincidence point, and at the counting timing of the high-speed counter, comparison determination can be avoided and erroneous detection can be prevented.

Further, the first and second setting values f1 and f2 stored in the first and second setting registers 553 and 552 of the first high-speed counter 550 are numerical values stored in the first variation value register 551a. Is an integer multiple of. The first and second comparison circuits provided in the first front-stage high-speed counter 530, the first high-speed counter 550, and the second high-speed counter 570 generate a binary logic output based on comparison match or comparison mismatch. Further, the count-up outputs Q1, Q2, Q4 and the rising comparison output are obtained by updating and storing in the storage circuits S1, S2, S3 after a predetermined delay time from the time when the logic of the count input signal is inverted to the count state. P1 · P2 · P4 or descending comparison outputs P1 , P2, and P4 are obtained.

  That is, the first and second setting values stored in the first and second setting registers of the first high-speed counter are values that are integer multiples of the numerical value stored in the first variation value register. Yes. Therefore, since the comparison coincidence point is always passed in the process of gradually increasing / decreasing the current count value, there is a feature that the count-up output, the rising comparison output, and the falling comparison output can be obtained by a simple comparison circuit system.

It is a block diagram of the positioning control apparatus in Embodiment 1 of this invention. It is a whole block diagram of the comparison circuit with respect to the 1st, 2nd high-speed counter in Embodiment 1 of this invention. FIG. 3 is a detailed logic circuit diagram of a first comparison circuit in the first embodiment of the present invention. It is a characteristic diagram of the positioning control apparatus in Embodiment 1 of this invention. It is a flowchart which shows a series of operation | movement of the positioning control apparatus in Embodiment 1 of this invention. It is a block diagram of the positioning control apparatus in Embodiment 2 of this invention. It is another block diagram of the positioning control apparatus in Embodiment 2 of this invention. It is a whole block diagram of the comparison circuit with respect to the 1st, 2nd high-speed counter in Embodiment 1 of this invention. It is a detailed logic circuit diagram of the 1st comparison circuit in Embodiment 2 of this invention. It is a characteristic diagram of the positioning control apparatus corresponding to the structure of FIG. 5 in Embodiment 2 of this invention. It is a characteristic diagram of the positioning control apparatus corresponding to the structure of FIG. 6 in Embodiment 2 of this invention. It is a flowchart which shows a series of operation | movement of the positioning control apparatus corresponding to the structure of FIG. 5, FIG. 6 in Embodiment 2 of this invention. It is a flowchart which shows the detailed operation | movement regarding the one part process of FIG. 10 in Embodiment 2 of this invention.

Explanation of symbols

100 Positioning Control Device, 100a CPU Unit, 100b Pulse Output Circuit Unit, 120 Microprocessor, 121 Program Memory, 122 RAM Memory, 130 First High Speed Counter, 131 Current Value Register, 132 Second Setting Register, 133 First Setting register, 135 second comparison circuit, 136 first comparison circuit, 141 selection switching circuit, 142 alternating output circuit, 143 output selection circuit, 150 second high-speed counter, 151 current value register, 152 second setting register 153, first setting register, 155 second comparison circuit, 156 first comparison circuit, 409 conversion setting means, 500 positioning control device, 500a CPU unit, 500b pulse output circuit unit, 501 servo amplifier, 502 servo motor, 503 Encoder, 52 0 Microprocessor, 521 Program memory, 522 RAM memory, 523 Position information register, 530 First previous stage high-speed counter, 531 Current value register, 532 Second setting register, 533 First setting register, 535 Second comparison circuit 536 first comparison circuit, 542a first alternating output circuit, 542b second alternating output circuit, 543 output selection circuit, 550 first high-speed counter, 551 current value register, 551a first variation register, 552 Second setting register, 553 First setting register, 555 Second comparison circuit, 556 First comparison circuit, 560 Second previous high-speed counter, 561 Current value register, 561a Second variation register, 562 2 setting register, 563 1st setting register, 565 2nd comparison circuit, 566 1 Comparison circuit, 570 second high-speed counter, 571 current value register, 572 second setting register, 573 first setting register, 575 second comparison circuit, 576 first comparison circuit, 709 conversion setting means, 802 Current position initialization means, 803 algebra addition means, Q1-Q4 count up output, Q1 - Q4 return output, P1 - P4 rise comparison output, P1 - P4 fall comparison output, DIR rotation direction command output, FRP forward / reverse rotation pulse output, FP Forward rotation pulse output, RP reverse rotation pulse output, M4 pulse generation completion signal, CLR clear signal, ZERO zero point signal, DOG near point dog signal, CLK1 reference clock signal, CLK2 divided clock signal.

Claims (14)

A positioning control device including a pulse output circuit unit that generates a pulse output for positioning control according to a desired operation speed pattern,
Further comprising conversion setting means for determining a parameter for specifying the desired operation speed pattern based on a target number of pulse generations and a transition characteristic of a pulse output period or frequency,
The pulse output circuit unit includes a current value register in which a count current value of an input signal is stored, a first setting register in which a first parameter among the parameters determined by the conversion setting unit is set, and A comparison result between the second setting register in which a value equal to or less than the first parameter is set as the second parameter among the parameters specified by the conversion setting means, and the comparison result between the current value register and the first setting register. A first high-speed counter and a second high-speed counter each having a first comparison circuit for outputting and a second comparison circuit for outputting a comparison result between the current value register and the second setting register. ,
The first high-speed counter receives a reference clock signal having a predetermined cycle or a divided signal of the reference clock signal, and the reference clock signal or the current count value of the divided signal is stored in a current value register.
The second high-speed counter has the pulse output for positioning control as an input, and the progress of the number of generated pulses is stored in a current value register,
In the first comparison circuit provided in the first high-speed counter and the second high-speed counter, a value of the current value register matches a set value of the first setting register, A count-up output is generated when the match point is exceeded,
The second comparison circuit provided in the first high-speed counter and the second high-speed counter is configured so that the value of the current value register is the first value in the process in which the value of the current value register is increasing or decreasing. When the value coincides with the set value of the setting register 2 or passes through the coincidence state, at least one of the rising comparison output and the falling comparison output is generated,
The pulse output circuit unit is responsive to generation of the count-up output by the first high-speed counter and generation of at least one of the rising comparison output or the falling comparison output by the second high-speed counter. A positioning control device that generates a pulse output based on the desired operation speed pattern based on the target number of pulse generations and the transition characteristics. The positioning control device according to claim 1,
The conversion setting means functions by executing a control program stored in a program memory cooperating with a microprocessor,
The microprocessor, after transmitting the parameter determined by the conversion setting means to the pulse output circuit unit, transmits a pulse output start command according to the desired operation speed pattern to the pulse output circuit unit,
The first high-speed counter and the second high-speed counter in the pulse output circuit unit start counting operations when receiving the start command,
The second high-speed counter transmits a pulse generation completion signal to the microprocessor upon completion of pulse output based on the desired operation speed pattern. The positioning control device according to claim 2,
In the first high-speed counter, a setting value corresponding to a target first pulse cycle for low-speed operation is set by the conversion setting means as a first parameter of the first high-speed counter, and is set in the first setting register. The set value corresponding to the target second pulse cycle for high-speed operation is set by the conversion setting means as the second parameter of the first high-speed counter and stored in the second setting register. And the selection switching circuit and the alternating output circuit are connected,
The selection switching circuit resets the current value register of the first high-speed counter when the count-up output of the first high-speed counter is generated, and then restarts counting the reference clock signal. Or a second reset timing for restarting counting of the reference clock signal after resetting the current value register of the first high-speed counter when the rising comparison output of the first high-speed counter is generated. Is a circuit that switches by receiving a reset timing command, and operates the first high-speed counter as a ring counter,
The alternating output circuit inverts the output logic every time the count-up output or the rising comparison output of the first high-speed counter is generated, and the cycle of the reference clock signal and the first parameter of the first high-speed counter or A circuit for generating a pulse output having a period twice the product of the second parameter;
In the second high-speed counter, a value that is half of the target pulse generation number is set by the conversion setting means as the first parameter of the second high-speed counter and stored in the first setting register. The number of low-speed operation pulses generated is set by the conversion setting means as the second parameter of the second high-speed counter and stored in the second setting register, and the count-up output is generated after the counting operation is started. In order to switch the selection switching circuit to the low speed side from the start of the counting operation until the rising comparison output is generated. A reset timing command for selecting the first reset timing is transmitted to the selection switching circuit, and the rising comparison output is generated. After the count-up output is generated and the counting direction is reversed, a reset timing command for selecting the second reset timing is issued until the selection switching circuit is switched to the high speed side until the falling comparison output is generated. The selection timing command is transmitted to the selection switching circuit and selects the first reset timing to switch the selection switching circuit to the low speed side again until the return output is generated after the falling comparison output is generated. Sent to the switching circuit,
The second high-speed counter sets the return output when the current value returns to zero, and when the return output is set, the first high-speed counter generates a pulse or the alternating output circuit pulse. The positioning control device characterized in that the output is stopped, the pulse generation completion signal is transmitted to the microprocessor, and the set state of the return output is reset by a reset command from the microprocessor. In the positioning control device according to claim 3,
When the target number of pulse generations is an odd number, the conversion setting means uses a value that is half of the even number before and after the target number of pulse generations as the first parameter of the second high-speed counter. A positioning control device characterized in that, in addition to setting in the first setting register, minus 1 or plus 1 is set as an initial value in a current value register of the second high-speed counter. The positioning control device according to claim 2,
A first pre-stage connected to the first high-speed counter so that the first high-speed counter generates a frequency transition pattern of an output pulse that becomes a gradually increasing / decreasing rate pattern from low speed to high speed or from high speed to low speed. A high-speed counter,
A first alternating output circuit connected between the first high-speed counter and the first pre-stage high-speed counter;
The first front-stage high-speed counter is a circuit that counts a reference clock signal having a predetermined period and generates a count input signal that defines a gradually increasing and decreasing period via the first alternating output circuit. A half value of the required variation time corresponding to the variation value of the gradually decreasing frequency is set by the conversion setting means as the first parameter or the second parameter of the first front-stage high-speed counter, and the first setting register or the second Counter circuit that generates the count input signal by inverting the output logic of the first alternating output circuit each time the current value register is reset by generating a count-up output or a rising comparison output And
The first high-speed counter further includes a first variation value register, and counts the count input signal from the first alternating output circuit, and is a first high-speed driving target. The first set value corresponding to the pulse frequency of the first is set by the conversion setting means as the first parameter of the first high-speed counter and is stored in the first setting register for the target low-speed operation before stopping. The second set value corresponding to the second pulse frequency is set by the conversion setting means as the second parameter of the first high-speed counter and stored in the second setting register. The third set value corresponding to the third pulse frequency for low-speed operation is set as an initial value by the conversion setting means and stored in the current value register, and the frequency change in the period of gradual increase and decrease. The value is set by the conversion setting means, stored in the first variation value register, and acts when the count input signal is given from the first alternating output circuit to the first high-speed counter. By adding or subtracting the variation value of the frequency stored in the first variation value register with respect to the current value register, the current value of the first high-speed counter is changed as the counting starts. Gradually increases from the third set value, the addition operation stops with the occurrence of the count-up output, the first set value is maintained, gradually decreases when the deceleration start command is given, and the descending The subtraction operation is stopped with the occurrence of the comparison output, and the second set value is maintained.
The second high-speed counter counts pulses having a period proportional to the reciprocal of the value of the current value register of the first high-speed counter, and the target number of generated pulses is the second high-speed counter. The first parameter is set by the conversion setting means and stored in the first setting register, and the number of pulses generated up to the deceleration start point is set by the conversion setting means as the second parameter of the second high-speed counter. Stored in the second setting register, starts the subtraction operation of the first high-speed counter with the generation of the rising comparison output, and generates the pulse of the first high-speed counter with the generation of the count-up output. And a pulse generation completion signal is transmitted to the microprocessor. The positioning control device according to claim 5,
A second preceding high-speed counter connected to the second high-speed counter to obtain the reciprocal of the current value of the first high-speed counter;
A second alternating output circuit connected between the second high-speed counter and the second previous high-speed counter;
The second pre-stage high-speed counter has a second variation value register in which the value of the current value register of the first high-speed counter serving as a target frequency is stored, and counts a reference clock signal having a predetermined period. The predetermined coefficient is set by the conversion setting means as the first parameter or the second parameter of the second preceding high-speed counter and stored in the first setting register or the second setting register, and the second preceding stage The reference clock signal of the predetermined period input to the high-speed counter acts as an addition count input, and the second variation value register with respect to the current value register of the second preceding high-speed counter according to the addition count input Each time the target frequency value stored in is added, the count-up output or the rising comparison output is generated and the current value register is reset. The output logic of the second alternating output circuit is inverted, and a pulse output having a period twice the quotient obtained by dividing the predetermined coefficient by the value of the second variation value register is generated from the second alternating output circuit. Let
The positioning control apparatus, wherein the second high-speed counter counts an output signal of the second alternating output circuit. The positioning control device according to claim 6,
In the first high-speed counter, a near-point dog signal that operates near the origin and returns to operation near the origin is connected as an input signal for positioning.
The second high-speed counter is provided in the servo motor driven by the near-point dog signal and the pulse output, and receives a Z-phase signal that generates one pulse output per rotation of the servo motor. The zero point signal is connected as the positioning input signal, and when the home search is completed, the clear signal for resetting the positioning deviation residual pulse of the servo amplifier that drives the servo motor is connected as the positioning output signal. And
The second high-speed counter does not count the pulse output which is the output of the second alternating output circuit when an origin return command is given, and the zero point signal is accompanied by the return of the operation of the near point dog signal. The intermittent pulse signal is counted, and when the counted zero point signal number reaches a predetermined set value set by the conversion setting means, the generation of the pulse output is stopped and the pulse generation completion signal is sent to the microprocessor. And supplying the clear signal to the servo amplifier,
The first high-speed counter counts the count input signal from the first alternating output circuit, and is a first set value corresponding to a target first pulse frequency for home return operation. Is set as the first parameter of the first high-speed counter by the conversion setting means and stored in the first setting register, and the second set value corresponding to the target second pulse frequency for slow speed operation Is set by the conversion setting means as the second parameter of the first high-speed counter and stored in the second setting register, and the second parameter corresponding to the third pulse frequency for low-speed operation at the start of target operation 3 is set as an initial value by the conversion setting means and stored in the current value register, and a variation value of the frequency is set by the conversion setting means and the first variation value register is set. The current value of the first high-speed counter gradually increases from the third set value as the counting starts, and the addition operation stops when the count-up output occurs. The first set value is maintained, and gradually decreases due to a deceleration start command generated by the operation of a near-point dog signal that operates when approaching a position near the target origin, and the descending comparison output is generated Accordingly, the subtraction operation is stopped to maintain the second set value. The positioning control device according to claim 7,
The microprocessor has a position information register in which absolute position information is stored as a cooperating RAM memory, and further includes a current position initialization unit and an algebra addition unit that function by executing the control program,
The current position initialization means writes and stores predetermined origin position information in the position information register at the time when the origin return operation is completed,
The algebra adding means reads the current value register value of the second high-speed counter at the time when one positioning control by the speed pattern is completed, and stores it in the position information register according to the commanded rotation direction. Add the amount of movement this time to the algebra,
The conversion setting means commands a relative movement amount and a movement direction calculated as a deviation between a next target position and the contents of the position information register as setting information for the pulse output circuit unit. apparatus. The positioning control device according to claim 2,
The first comparison circuit and the second comparison circuit generate a binary logic output that is greater than or less than a match point or less than or equal to a match point and less than or less than a match point. Positioning control characterized in that the count-up output and the rising comparison output or the falling comparison output can be obtained by updating and storing in a storage circuit after a predetermined delay time from the time when the logic is inverted to the counting state. apparatus. In the positioning control device according to claim 3 or 4,
The first comparison circuit and the second comparison circuit generate a binary logic output based on comparison coincidence or comparison disagreement, and after a predetermined delay time from the time when the logic of the count input signal is inverted to the count state. The positioning control device, wherein the count-up output and the rising comparison output or the falling comparison output are obtained by updating and storing in a storage circuit. The positioning control device according to claim 5,
The conversion setting means converts the first setting value and the second setting value set in the first setting register and the second setting register of the first high-speed counter into the first change value. Set as an integer multiple of the variation value of the frequency set in the minute value register,
The first comparison circuit and the second comparison circuit provided in each of the first front-stage high-speed counter, the first high-speed counter, and the second high-speed counter have binarization logic based on comparison match or comparison mismatch. The count-up output and the rising comparison output or the falling comparison output are generated by generating an output and updating and storing in the memory circuit after a predetermined delay time from the time when the logic of the counting input signal is inverted to the counting state. A positioning control device characterized by being obtained. The positioning control device according to claim 2,
Each of the second comparison circuits provided in the first high-speed counter and the second high-speed counter is configured so that the corresponding first high-speed counter or the second high-speed counter is in the up-count mode. When it is determined that the second comparison circuit has passed the coincidence determination or the coincidence point, the ascending comparison output is validated and stored in the ascending comparison determining storage circuit, and the corresponding first high-speed counter or the first When the second high-speed counter is in the down-count mode and the second comparison circuit determines that the coincidence determination or the coincidence point has been passed, the falling comparison output is validated and stored in the descent comparison determination storage circuit. A positioning control device that erases the storage state of each of the storage circuits in response to a reset command from the microprocessor. The positioning control device according to claim 2,
Each of the second comparison circuits provided in the first high-speed counter and the second high-speed counter is set before the corresponding count-up output of the first high-speed counter or the second high-speed counter is activated. If the second comparison circuit determines that the second comparison circuit has matched or passed the coincidence point, the rising comparison output is validated and stored in the storage circuit for rising comparison determination, and the corresponding first high-speed counter or When it is determined that the second comparison circuit has passed the coincidence determination or the coincidence point after the count-up output of the second high-speed counter is activated, the falling comparison output is validated and stored in the storage circuit for the downward comparison determination And a storage control device that erases the storage state of each of the storage circuits in response to a reset command from the microprocessor. The positioning control device according to claim 2,
The microprocessor is connected to a plurality of input sensors and a plurality of electric loads, and is a programmable controller that drives and controls the plurality of electric loads according to the operation state of the input sensors and the contents of a control program stored in the program memory. Built in the CPU unit,
The pulse output circuit unit is built in an input / output unit bus-connected to the microprocessor, and further includes an output selection circuit,
The conversion setting means is executed by a special command stored in the program memory as a part of the control program, and the special command includes at least a pulse having a target pulse generation number and a target operation speed pattern. Set operation constants including output cycle or frequency transition characteristics, and include rotation direction command and start / stop command or forward rotation start / stop command and reverse rotation start / stop command,
The output selection circuit is configured to output a rotation direction command and forward / reverse rotation pulse output or forward rotation pulse output and reverse rotation pulse output based on the rotation direction command and start / stop command or forward rotation start / stop command and reverse rotation start / stop command. Occur and
The microprocessor receives the pulse generation completion signal from the pulse output circuit unit, or when the generation of pulse output is interrupted and stopped by an operation stop command generated by the microprocessor, the pulse output circuit is generated by a reset command. Positioning control device that performs the next parameter setting after initializing the part.

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