JP2009071968A - Electricity accumulating unit, image forming apparatus, and charge control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an electricity accumulating unit arranged to sharply reduce the number of components used for notifying a charge control circuit of the bypass state of each electricity accumulating cell, and can reduce the cost. <P>SOLUTION: An electricity accumulating unit comprises: a cell bank where a plurality of chargeable/dischargeable electricity accumulating cells are connected in series; a charge control circuit for performing charge control of the cell bank; and a plurality of bypass circuits for detecting the charging voltage of each individual electricity accumulating cell and bypassing the charging current for such electricity accumulating cells as having a charging voltage exceeding a predetermined value, wherein the accumulating unit further comprises: a first determination means for determining that any of the plurality of bypass circuits have performed bypass operation and notifying the charge control circuit of the determination; and a second determination means for determining that the plurality of bypass circuits performed bypass operation entirely and notifying the charge control circuit of the determination. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power storage device in which a plurality of chargeable / dischargeable power storage cells are connected in series, a copier that uses the power of the power storage device, a printer, a facsimile, or an image forming apparatus that combines these functions. And a method for controlling charging of the power storage device.

  As a chargeable / dischargeable storage cell, an electric double layer capacitor has a large capacity and excellent charge / discharge cycle characteristics, but has a low withstand voltage. A plurality of multilayer capacitors are connected in series to increase the breakdown voltage.

  When connecting multiple electric double layer capacitors in series, in order to reduce the number of electric double layer capacitors used as much as possible, they are charged to the limit voltage that does not exceed the withstand voltage standard value. When charging / discharging with a capacitor bank consisting of multiple multi-layer capacitors, there are variations in characteristics such as capacitance and leakage resistance between each electric double layer capacitor. Differences occur, and individual charging voltages may increase beyond the withstand voltage. This leads to a deterioration of the lifetime.

  Therefore, in the charge control of this capacitor bank, the charging voltage of each electric double layer capacitor is controlled so as not to exceed the withstand voltage, that is, all the electric double layer capacitors can be charged evenly, A method of maximizing the capacity of each electric double layer capacitor is employed.

  That is, for each electric double layer capacitor, a bypass circuit is arranged, and when charging up to the reference voltage, measures are taken to prevent overcharging of the electric double layer capacitor by bypassing the charging current. Then, the charge control circuit monitors the operating state of each bypass circuit through the photocoupler so that it can detect the bypass state of any of the plurality of electric double layer capacitors and the bypass state of all the electric double layer capacitors. This is a method of performing charge control corresponding to each. A specific example is shown below.

  For example, in Patent Document 1, in order to solve the problem that the voltage between both ends of each electric double layer capacitor varies depending on the characteristic variation described above, two photocouplers are installed for one electric double layer capacitor, The coupler is used to control the magnitude of the charging current that is bypassed by each bypass circuit according to the judgment on the side of the charging control circuit, and the other photocoupler transmits the operating state to the charging control circuit by the corresponding bypass circuit. Techniques used for the above are disclosed. The phototransistors of the other photocoupler are connected in parallel to the charge control circuit, respectively, so that the charge control circuit has a bypass state of any of the plurality of electric double layer capacitors and a bypass state of all the electric double layer capacitors. Can be detected.

  Also, for example, in Patent Document 2, two photocouplers are installed for one electric double layer capacitor, and the light-emitting diodes of both photocouplers have the same bypass circuit that controls light emission / non-light emission. The phototransistors of one photocoupler are connected in parallel to the charge control circuit, the phototransistors of the other photocoupler are connected in series with each other, and both ends of the series circuit are connected to the charge control circuit. A technique is disclosed in which a charge control circuit can detect any bypass state of a plurality of electric double layer capacitors and bypass states of all electric double layer capacitors.

Japanese Patent No. 3491676 JP 2005-253289 A

  However, in the technologies disclosed in Patent Documents 1 and 2, the presence or absence of the bypass state of each electric double layer capacitor is individually transmitted to the charge control circuit through a photocoupler, and the charge control circuit includes a plurality of electric double layer capacitors. Because it is configured to detect any bypass state and the bypass state of all electric double layer capacitors, a photocoupler that individually notifies the presence or absence of the bypass state as the number of electric double layer capacitors used increases There is a problem that the cost increases because the number of

  The present invention has been made in view of the above, and has a configuration in which the number of components used to notify the charge control circuit of the bypass state of each power storage cell can be greatly reduced, and the power storage device capable of reducing costs and the power storage An object of the present invention is to obtain an image forming apparatus using the apparatus and a charge control method.

  In order to achieve the above-described object, the present invention provides a cell bank in which a plurality of chargeable / dischargeable storage cells are connected in series, a charge control circuit that performs charge control for the cell bank, and charging of each of the storage cells. In a power storage device including a plurality of bypass circuits that bypass a charging current in a power storage cell that detects a voltage and exceeds a predetermined value, the charge control circuit detects that any of the plurality of bypass circuits has performed a bypass operation And a second detection means for detecting that all of the plurality of bypass circuits have performed a bypass operation and notifying the charge control circuit. .

  According to the present invention, only two detection means, that is, a means for detecting that any one of the energy storage cells is in the bypass state and a means for detecting that all the energy storage cells are in the bypass state are provided. The number of components required when notifying the state of the cell bank to the charge control circuit is two regardless of the number of the storage cells, and the number of components can be greatly reduced, and the cost can be reduced.

  Further, in the control of constant current charging and intermittent charging, the charging control circuit does not need to determine the state of each storage cell in the cell bank, and simply performs charging control according to two signals notified from the cell bank side. Therefore, the control mode can be simplified. From this point, there is an effect that the cost can be similarly reduced.

  Exemplary embodiments of a power storage device, an image forming apparatus, and a charge control method according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
1 is a block diagram showing a configuration of a power storage device according to Embodiment 1 of the present invention. FIG. 1 shows a configuration example of a power storage device using an electric double layer capacitor (hereinafter referred to as “capacitor cell”) as a chargeable / dischargeable power storage cell.

  In FIG. 1, the capacitor bank 9 has a configuration in which, for example, 18 capacitor cells C1 to C18 are connected in series. In the series circuit of 18 capacitor cells C1 to C18, the capacitor cell C1 side is the positive electrode end, and the capacitor cell The C18 side is the negative electrode end.

  The charge control circuit 7 converts and generates DC power from the AC power supply AC, and outputs a predetermined DC voltage between the positive terminal and the negative terminal.

  The positive end of the capacitor bank 9 is directly connected to the positive end of the charge control circuit 7, the negative end of the capacitor bank 9 is connected to the ground (GND), and the charge control circuit 7 is connected via the charge current detection circuit 6. Is connected to the negative electrode end of. That is, the charging current detection circuit 6 detects the charging current 13 that is fed back and supplies it to the charging control circuit 7. A capacitor bank voltage detection circuit 5 is connected between the positive terminal and the negative terminal of the charging control circuit 7. The capacitor bank voltage detection circuit 5 supplies the detected voltage (charge voltage) 12 of the capacitor bank 9 to the charge control circuit 7.

  Now, the bypass circuit 1 is provided in each of the 18 capacitor cells C1 to C18 of the capacitor bank 9. Each bypass circuit 1 is composed of a single cell full charge detection circuit 1a and a parallel circuit of a series circuit of a switching circuit 1b and a resistor R6, and both ends of the parallel circuit are connected to both ends of a corresponding one capacitor cell. ing. The switching circuit 1b performs one of an ON operation and an OFF operation according to the value of the detection signal of the single cell full charge detection circuit 1a.

  Specifically, the switching circuit 1b performs an OFF operation until the single cell full charge detection circuit 1a detects a single cell full charge voltage (for example, 2.5 V), and the single cell full charge detection circuit 1a operates as a single cell. When a full charge voltage is detected, an ON operation is performed. As a result, the series circuit of the switching circuit 1b and the resistor R6 short-circuits both ends of the corresponding capacitor cell. In the case of the capacitor cell C1, the resistance value of the resistor R6 is determined in the charging current to the capacitor cell C1. The charging current flows through the bypass A by the series circuit of the switching circuit 1b and the resistor R6. Then, a voltage corresponding to the bypass current flowing through the bypass path A appears at the connection end between the switching circuit 1b and the resistor R6. That is, the presence or absence of voltage generation at the connection end of the switching circuit 1b and the resistor R6 is an index indicating the presence or absence of the bypass operation of the bypass circuit.

  The anode of the light emitting diode 4a of the photocoupler 4 is connected to the other end of the resistor R11 whose one end is connected to the positive electrode end side of the capacitor bank 9, and switching is performed between the cathode of the light emitting diode 4a and the ground (GND). A circuit 3 is provided. The cathodes of the 18 diodes D21 to D38 are connected in parallel to the control terminal of the switching circuit 3. The anodes of the 18 diodes D21 to D38 are connected to the switching circuit 1b in each of the 18 bypass circuits 1. And the resistor R6 are connected in a one-to-one relationship.

  On the other hand, the phototransistor 4b of the photocoupler 4 has a collector electrode connected to another fixed power source via a resistor R12, and an emitter electrode connected to the ground (GND). A single cell full charge signal 10 is output to the charge control circuit 7 from the connection end of the collector electrode of the phototransistor 4b of the photocoupler 4 and the resistor R12.

  That is, the photocoupler 4 corresponds to the first photocoupler, the switching circuit 3 corresponds to the first switching circuit, and the whole of them constitutes the first detection means.

  In the configuration of the photocoupler 4 and the switching circuit 3, when all of the 18 bypass circuits 1 are not performing the bypass operation, the switching circuit 3 performs the OFF operation. Does not flow and does not emit light. Therefore, the phototransistor 4b of the photocoupler 4 does not perform the ON operation, and the connection terminal between the collector electrode and the resistor R12 becomes a high potential by another fixed power source.

  On the other hand, if any one of the 18 bypass circuits 1 performs the bypass operation, the switching circuit 3 performs the ON operation. Therefore, the light-emitting diode 4a performs the light-emission operation with the current flowing, and the photocoupler 4 The phototransistor 4b is turned on. As a result, the connection end of the collector electrode of the phototransistor 4b and the resistor R12 becomes a low potential of the ground potential.

  In short, the potential at the connection end of the collector electrode of the phototransistor 4b of the photocoupler 4 and the resistor R12 is a fixed high potential level when all of the 18 bypass circuits 1 are not in the bypass state. If any one of the bypass circuits 1 performs the bypass operation, the low potential level is changed, and then the low potential level is continued as long as any one of the 18 bypass circuits 1 is in the bypass state. . This is the content of the single cell full charge signal 10, and when all of the 18 bypass circuits 1 are in the bypass state, they are at the low potential level.

  A series circuit of 18 switching circuits 2 is provided between the other end of the resistor R8 having one end connected to the positive electrode end side of the capacitor bank 9 and the negative electrode end side of the capacitor bank 9. The eighteen switching circuits 2 have a one-to-one relationship with the eighteen bypass circuits 1, and whether or not voltage is generated at the connection end of the switching circuit 1b and the resistor R6 is input as a control signal. The series circuit of the 18 switching circuits 2 corresponds to a switching circuit group. Hereinafter, the series circuit of the 18 switching circuits 2 is abbreviated as a switching circuit group 2.

  The anode of the light emitting diode 14a of the photocoupler 14 is connected to the other end of the resistor R13, one end of which is connected to the positive end of the capacitor bank 9, and switching is performed between the cathode of the light emitting diode 14a and the ground (GND). A circuit 8 is provided. The control terminal of the switching circuit 8 is connected to the connection terminal between the positive terminal of the capacitor bank 9 of the switching circuit group 2 and the other end of the resistor R8.

  On the other hand, the phototransistor 14b of the photocoupler 14 has a collector electrode connected to another fixed power source via a resistor R14, and an emitter electrode connected to ground (GND). The all-cell full charge signal 11 for the charge control circuit 7 is output from the connection end of the collector electrode of the phototransistor 14b of the photocoupler 14 and the resistor R14.

  That is, the photocoupler 14 corresponds to the second photocoupler, the switching circuit 8 corresponds to the second switching circuit, and the whole including the series circuit (switching circuit group) of the 18 switching circuits 2 is the first. 2 detection means.

  In the configuration of the resistor R8, the switching circuit group 2, the photocoupler 14, and the switching circuit 8, when all of the 18 bypass circuits 1 are not performing the bypass operation, the switching circuit 8 is connected to the control terminal. Since the positive terminal potential of the capacitor bank 9 is applied, the ON operation is performed. As a result, the light-emitting diode 14a performs a light-emitting operation when a current flows, so that the phototransistor 14b of the photocoupler 14 performs an ON operation, and the connection terminal between the collector electrode and the resistor R14 has a low ground potential. .

  On the other hand, when all of the 18 bypass circuits 1 perform the bypass operation, the switching circuit 8 performs the OFF operation because the switching circuit group 2 performs the ON operation so that the ground potential is applied to the control terminal. It is like that. As a result, the light emitting diode 14a does not emit light and does not perform the light emitting operation, so the phototransistor 14b of the photocoupler 14 does not perform the ON operation. Become potential.

  In short, the potential of the connection end of the collector electrode of the phototransistor 14b of the photocoupler 14 and the resistor R14 is at a low potential level when all of the 18 bypass circuits 1 are not in the bypass state, and 18 potentials. When all of the bypass circuits 1 are in the bypass state, the high potential level is changed. After that, as long as all of the 18 bypass circuits 1 are in the bypass state, the high potential level is maintained and the 18 bypass circuits 1 are maintained. When even one of these is not in the bypass state, the potential level becomes low. This is the content of the all-cell full charge signal 11.

  In FIG. 1, the all-cell full charge signal 11 at the connection end between the collector electrode of the phototransistor 14 b of the photocoupler 14 and the resistor R <b> 14 has a potential level opposite to that of the single cell full charge signal 10. In order to make the determination mode in the charge control circuit 7 the same as the single cell full charge signal 10, the signal is inverted by the inverter 15 and then input to the charge control circuit 7.

  The charge control circuit 7 receives the charge voltage detection signal 12, the charge current detection signal 13, the single cell full charge signal 10, and the all cell full charge signal 11, and charges the capacitor bank 9 with constant current charging and constant power by program control. Charging, intermittent constant voltage charging, or intermittent constant current charging is selected and performed to charge each capacitor cell of the capacitor bank 9 evenly.

  Next, the entire circuit for generating one single cell full charge signal 10 and one all cell full charge signal 11 to be supplied to the charge control circuit 7 from the charge state of each capacitor cell of the capacitor bank 9 is an equalizing circuit. The specific configuration will be described. FIG. 2 is a circuit diagram illustrating a specific configuration example of the equalization circuit in the power storage device illustrated in FIG. 1.

  In FIG. 2, 18 bypass circuits 1 are each configured by a transistor Q1, a resistor R1 to R5, a shunt regulator X1, and a resistor R6 shown in FIG. 1, to which the diode D1 shown in FIG. 1 is connected. Has been. The single cell full charge detection circuit 1a shown in FIG. 1 is realized by a voltage dividing circuit including resistors R1 and R2 and a shunt regulator X1. The switching circuit 1b shown in FIG. 1 is realized by the transistor Q1 to which the diode D1 is connected.

  In the example of the capacitor cell C1, since the resistors R1 and R2 are connected in series between both terminals of the capacitor cell C1, the series circuit of the resistors R1 and R2 divides the terminal voltage of the capacitor cell C1. It is a voltage dividing circuit that presses. Since the divided voltage of the voltage dividing circuit including the resistors R1 and R2 is input to the control terminal of the shunt regulator X1, the shunt regulator X1 is turned on when the terminal voltage of the capacitor cell C1 is charged to a predetermined voltage. To do.

  When the shunt regulator X1 is turned on, a base current flows through the resistor R4 to the base electrode of the transistor Q1, and the transistor Q1 is turned on. When the transistor Q1 is turned on, the charging current of the capacitor cell C1 determined by the resistance value of the resistor R6 flows through the bypass path A.

  In addition, each switching circuit in the switching circuit group 2 shown in FIG. 1 includes a transistor Q2 and a resistor R7. That is, when a current flows through the resistor R6 and a drop voltage is generated, the transistor Q2 is configured to be turned on when a base current is supplied through the resistor R7.

  Further, the switching circuit 3 shown in FIG. 1 includes a transistor Q3 and resistors R9 and R10 connected in series between the base electrode of the transistor Q3 and the ground, and a connection terminal of the resistors R9 and R10. In addition, the cathodes of 18 diodes D21 to D38 are connected in parallel. As a result, the transistor Q3 performs the ON operation when any one of the 18 bypass circuits 1 is in a bypass state, so that the transistor Q3 is charged from the connection terminal between the collector electrode of the phototransistor 4b of the photocoupler 4 and the resistor R12. When the single cell full charge signal 10 output to the control circuit 7 falls from the high potential level to the low potential level, the charge control circuit 7 can be notified of the occurrence of the bypass state.

  The switching circuit 8 shown in FIG. 1 includes a transistor Q4, resistors R25 and R26, and a Zener diode Z1. The resistor 26 is provided between the base electrode of the transistor Q4 and the ground. The resistor R25 has one end connected to the base electrode of the transistor Q4 and the other end connected to the anode of the Zener diode Z1. The cathode of the Zener diode Z1 is connected to the connection end between the positive end of the capacitor bank 9 and the other end of the resistor R8 in the series circuit of 18 transistors Q2. The Zener voltage of the Zener diode Z1 is higher than the total ON voltage when all of the 18 transistors Q2 are in the ON operation state.

  According to this configuration, when all of the 18 transistors Q2 are not in the ON operation state, the transistor Q4 performs the ON operation because the base potential rises to near the positive side voltage of the capacitor bank 9. The photocoupler 14 is turned on, and the potential at the connection end of the collector electrode of the phototransistor 14b and the resistor R14 becomes a low potential level.

  When all of the 18 transistors Q2 are in the ON operation state, the total ON voltage of the 18 serially connected transistors Q2 is applied to the cathode of the Zener diode Z1, but the Zener diode Z1 does not operate. Since the base potential of Q4 is pulled to the ground potential by the resistor 26, the OFF operation can be surely performed. As a result, the potential at the connection end of the collector electrode of the phototransistor 14b of the photocoupler 14 and the resistor R14 is changed from a low potential level to a high potential level by another fixed power source.

  Therefore, the all-cell full charge signal 11 output from the output terminal of the inverter 15 to the charge control circuit 7 rises from the low potential level to the high potential level, so that the charge control circuit 7 It can be notified that all the capacitor cells are fully charged.

  Next, the charge control operation performed by the charge control circuit 7 by program control will be described along FIG. 3 with reference to FIGS. FIG. 3 is a flowchart illustrating a charge control operation in the power storage device shown in FIG. Note that a step indicating a processing procedure is abbreviated as ST.

  3, in ST1, the charge control circuit 7 performs a control operation at an initial stage of starting the charge control operation for the power storage device. That is, because the capacitor bank 9 is not used and left for a long time, or the stored power is discharged by self-discharge, the charge control circuit 7 performs the initial operation of confirming the voltage of the capacitor bank voltage detection circuit 5. When it is determined from the output charging voltage detection signal 12 that the charging voltage of the capacitor bank 9 is equal to or lower than the lower limit voltage that can be used, for example, charging with a constant current of about 10 A is performed.

  The charge control circuit 7 monitors the charge voltage detection signal 12 output from the capacitor bank voltage detection circuit 5 for this constant current charge control (ST1), so that the voltage across the capacitor bank 9 becomes a specified charge voltage (for example, about 28V) (ST2: No), and when the voltage across the capacitor bank 9 reaches a specified charging voltage (for example, about 28V) (ST2: Yes), switch to charge control with constant power. Implement (ST3).

  As a result, the potential of each capacitor cell in the capacitor bank 9 rises. Therefore, in the 18 bypass circuits 1, the charging voltage of the capacitor cell corresponding to the single cell full charge detection circuit 1a is a predetermined value (for example, 2.. 5V) is detected and the switching circuit 1b is turned on to enter a bypass state. The switching circuit 3 is turned on and the photocoupler 4 falls from the high potential level to the low potential level. The cell full charge signal 10 is output.

  Therefore, the charge control circuit 7 performs the constant power charge control (ST3) while monitoring the level change of the single cell full charge signal 10 output from the photocoupler 4 (ST4: No), and the single cell full charge signal 10 Falls from the high potential level to the low potential level (ST4: Yes), this time, for example, switching to charge control with a constant current of about 2 A is performed (ST5).

  As a result, in the 18 bypass circuits 1, the bypass operation transitions in a direction in which all the bypass circuits 1 are in the bypass state, and in the final state in which all the bypass circuits 1 are in the bypass state, the switching circuit group 2 is turned on. Thus, the switching circuit 8 is turned off, and the all-cell full charge signal 11 that falls from the high potential level to the low potential level is output from the inverter 15 that inverts the output of the photocoupler 14.

  Therefore, the charge control circuit 7 performs the constant current charge control (ST5) while monitoring the level change of the all-cell full charge signal 11 output from the inverter 15 that inverts the output of the photocoupler 14 (ST6: No). ) When the all-cell full charge signal 12 falls from the high potential level to the low potential level (ST6: Yes), this time, the intermittent charge control in which the charge control period and the stop period alternate are performed within a certain period. Switch to the operation to be performed (ST7).

  Then, after performing the intermittent charge control (ST5), the charge control circuit 7 monitors the change of the charge voltage detection signal 12 from the capacitor bank voltage detection circuit 5, and the voltage across the capacitor bank 9 is used (discharged). Even if the stored power decreases due to the above, until the voltage across the capacitor bank 9 falls below the lower limit voltage that can be used (ST8: No), the decrease in the voltage across the capacitor bank 9 is silent. When it falls below the usable lower limit voltage (ST8: Yes), the process returns to ST1 and starts again from the charge control with the first constant current of about 10A.

  As described above, according to the first embodiment, when the single-cell full charge signal is generated, the switching circuit 3 that receives a so-called logical sum of the bypass operations of all the bypass circuits 1 is turned on, whereby the photocoupler 4 is turned on. When the all-cell full-charge signal is generated, the switching circuit 8 is turned off in response to the fact that all the bypass circuits 1 perform the bypass operation and the switching circuit group is turned on. Is configured to operate OFF, so that the charge control circuit 7 can be set to a predetermined value only by preparing two detection means including a photocoupler and a switching circuit for driving the photocoupler regardless of the number of capacitor cells to be used. The charge control operation can be performed.

  In short, the number of photocouplers that are means for transmitting the bypass operation presence / absence of all bypass circuits 1 to the charge control circuit 7 can be reduced to two regardless of the number of bypass circuits 1, and the number of parts can be greatly reduced. it can. Then, the charge control circuit 7 monitors the bypass operation of all bypass circuits 1 and simply determines the single cell full charge signal and all cells without judging any bypass state and all bypass states. Since charging control may be performed according to the full charge signal, the charging control circuit 7 can simplify the control mode. As a result, the cost of the power storage device can be reduced.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a configuration of a power storage device according to Embodiment 2 of the present invention. In FIG. 4, components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1) are assigned the same reference numerals. Here, the description will focus on the parts related to the second embodiment.

  As shown in FIG. 4, the power storage device according to the second embodiment is the same as the first comparator in place of the switching circuit 3 and the photocoupler 4 in the configuration shown in FIG. 1 (first embodiment). 16, and instead of the switching circuit 8 and the photocoupler 14, a comparator 17 that is a second comparator is provided.

  The series circuit of the resistors R15 and R17 is provided between the positive terminal and the negative terminal (ground) of the capacitor bank 9, and the positive phase input terminal (+) of the comparator 16 is connected to the connection terminal of the resistors R15 and R17. It is connected. That is, the reference voltage to the positive phase input terminal (+) of the comparator 16 is supplied from the connection terminals of the resistors R15 and R17 that divide the charging voltage of the capacitor bank 9. The resistance values of the resistors R15 and R17 are set to predetermined values so that the divided voltage output to the connection end is lower than the charging voltage (2.5 V) of one capacitor cell. .

  A series circuit of resistors R15 and R17 is provided between the negative phase input terminal (−) of the comparator 16 and the ground (GND). Eighteen diodes D21 are connected to the connection terminals of the resistors R15 and R17. The cathodes of D38 are connected in parallel. That is, the potential of the negative-phase input terminal (−) of the comparator 16 is at the low potential level of the ground potential when none of the 18 bypass circuits 1 is in the bypass state, but any of the 18 bypass circuits 1 is. In the bypass state, the voltage drop at the resistor R6 is applied to the connection ends of the resistors R15 and R17, and the voltage rises toward the high potential level. Since the reference voltage of the positive phase input terminal (+) of the comparator 16 is lower than the charging voltage (2.5 V) of one capacitor cell as described above, any one of the 18 bypass circuits 1 is bypassed. In this state, the potential of the negative phase input terminal (−) of the comparator 16 becomes higher than the reference voltage of the positive phase input terminal (+) of the comparator 16, so that the comparator 16 can reliably detect the occurrence of the bypass state. .

  The output terminal of the comparator 16 is connected to the input terminal of the single cell full charge signal 10 of the charge control circuit 7, but is connected to another fixed power source via the resistor R19. That is, the output terminal of the comparator 16 is at a high potential level by another fixed power source when the potential of the negative phase input terminal (−) is lower than the reference voltage of the positive phase input terminal (+). When it becomes higher than the reference voltage of the input terminal (+), it becomes a low potential level. This is the content of the single cell full charge signal 10 output from the comparator 16.

  Next, the series circuit of the resistors R20 and R22 is provided between the positive terminal and the negative terminal (ground) of the capacitor bank 9, and the positive phase input terminal (+) of the comparator 17 is connected to the resistors R20 and R22. Connected to the connection end. That is, the reference voltage to the positive phase input terminal (+) of the comparator 17 is supplied from the connection terminal of the resistors R20 and R22 that divide the charging voltage of the capacitor bank 9.

  Further, a series circuit of resistors R21 and R23 is provided between the negative phase input terminal (−) of the comparator 17 and the ground (GND), and the switching circuit group 2 is connected to the connection terminal of the resistors R21 and R23. The connection end of the positive end of the capacitor bank 9 and the resistor R8 is connected. With this configuration, the potential of the negative phase input terminal (−) of the comparator 17 is pulled to the ground potential through the resistor R23 when the switching circuit group 2 is in the ON operation state, but the switching circuit group 2 is in the OFF operation state. In this case, the charging voltage of the capacitor bank 9 is divided by a series circuit of resistors R8 and R23. Therefore, the resistance values of the resistors R8 and R23 are obtained by dividing the divided voltage output to the connection end of the resistors R20 and R22, that is, the reference voltage to the positive phase input end (+). Is set to a predetermined value so as to be higher.

  The output terminal of the comparator 17 is connected to the input terminal of the all-cell full charge signal 11 of the charge control circuit 7, but is connected to another fixed power source via the resistor R24. That is, the output terminal of the comparator 17 is at a high potential level by another fixed power source when the potential of the negative phase input terminal (−) is lower than the reference voltage of the positive phase input terminal (+). When it becomes higher than the reference voltage of the input terminal (+), it becomes a low potential level. This is the content of the all-cell full charge signal 11 output from the comparator 17.

  Next, FIG. 5 is a circuit diagram illustrating a specific configuration example of the equalization circuit in the power storage device illustrated in FIG. 4. As shown in FIG. 5, the equalization circuit in the power storage device shown in FIG. 4 is the same as the equalization circuit shown in FIG. 2, but instead of the photocoupler 4, the transistor Q3, and the resistors R9 to R12, the comparator 16 and the resistor R15. To R18, and instead of the photocoupler 14, transistor Q4, resistors R13, R14, R25, and R26, a comparator 17 and resistors R20 to R24 are provided. These are the configurations shown in FIG. 4, and the other configurations are the same as those of the equalization circuit shown in FIG.

  Next, FIG. 6 is a flowchart illustrating a charge control operation in the power storage device shown in FIG. In FIG. 6, procedures that are equivalent to the processing procedures shown in FIG. 3 are denoted with the same reference numerals. Here, a processing procedure according to the second embodiment will be described.

  In FIG. 6, when the constant power charge control (ST3) is performed, the potential of each capacitor cell in the capacitor bank 9 rises. Therefore, in the 18 bypass circuits 1, a single cell full charge detection circuit 1a is provided. By detecting that the charging voltage of the corresponding capacitor cell exceeds a predetermined value (for example, 2.5 V) and the switching circuit 1b is turned on, a bypass state occurs. Then, in the comparator 16, since the potential of the negative phase input terminal (+) exceeds the reference voltage supplied to the positive phase input terminal (+), the single cell fullness falling from the high voltage level to the low voltage level from the output terminal. The charging signal 10 is output.

  Therefore, the charge control circuit 7 performs the constant power charge control (ST3) while monitoring the level change of the single cell full charge signal 10 output from the comparator 16 (ST11: No), and the single cell full charge signal 10 is When falling from the high potential level to the low potential level (ST11: Yes), this time, for example, switching to charge control with a constant current of about 2 A is performed (ST5).

  As a result, in the 18 bypass circuits 1, the bypass operation transitions in a direction in which all of the bypass circuits 1 are in the bypass state. In the final state in which all of the bypass circuits 1 are in the bypass state, the negative phase input terminal (+ ) Exceeds the reference voltage supplied to the positive phase input terminal (+), so that the all-cell full charge signal 11 falling from the high potential level to the low potential level is output from the output terminal of the comparator 17. Occur.

  Therefore, the charge control circuit 7 performs the constant current charge control (ST5) while monitoring the level change of the all-cell full-charge signal 11 output from the comparator 17 (ST12: No), and the all-cell full-charge signal 12 is When falling from the high potential level to the low potential level (ST12: Yes), this time, switching to the operation in which the intermittent charge control in which the charge control period and the stop period alternate are performed within a certain period (ST7).

  As described above, according to the second embodiment, when the single cell full charge signal is generated, the comparator 16 that receives a so-called logical sum of the bypass operations of all the bypass circuits 1 is configured to invert the output level. In the generation of the charging signal, the comparator 17 inverts the output level in response to the fact that all the bypass circuits 1 perform the bypass operation and the switching circuit group is turned on, so that it is independent of the number of capacitor cells to be used. Two comparators configured by one comparator 16 that detects any one bypass operation of all bypass circuits 1, a switching circuit group 2 that detects the bypass operations of all bypass circuits 1, and one comparator 16 The charge control circuit 7 can perform a predetermined charge control operation only by preparing a detection means. .

  In short, the number of comparators that are means for transmitting the bypass operation presence / absence of all bypass circuits 1 to the charge control circuit 7 can be reduced to two regardless of the number of bypass circuits 1, and as in the first embodiment, The number of parts can be greatly reduced. Then, as in the first embodiment, the charge control circuit 7 monitors the presence / absence of the bypass operation of all bypass circuits 1, and simply determines any bypass state and all bypass states, Since the charge control may be performed according to the single cell full charge signal and the all cell full charge signal, the charge control circuit 7 can simplify the control mode. As a result, the cost of the power storage device can be reduced.

  Here, in order to supplement the description in FIGS. 3 and 5, the charge control performed in the power storage device shown in Embodiments 1 and 2 will be described again with reference to FIG. 7. FIG. 7 is a diagram for explaining a charge / discharge sequence of the capacitor bank in the power storage device shown in FIGS. 1 and 4. FIG. 7 also shows the relationship between the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 and the charging current 13 detected by the charging current detection circuit 6.

  As shown in FIG. 7, the charging control of the capacitor bank 9 is performed in the order of (1) constant current charging, (2) constant power charging, (3) constant current charging, and (4) intermittent charging. When the discharge 26 is performed and the charging voltage is reduced to the usable lower limit voltage 27, the recharging 28 is controlled.

  The first constant current charging (1) is performed using, for example, a constant current of about 10 A when the capacitor bank 9 is left for a long period of time or when the power stored in the capacitor bank 9 is discharged by self-discharge. Is done. FIG. 7 shows a case where charging is performed from a state in which the capacitor bank 9 is 0V. This constant current charging (1) is performed until the charging voltage 12 reaches a predetermined value 21 (for example, about 28V). Meanwhile, the charging current 13 is constant at about 10A.

  The next constant power charging (2) is performed by switching when the charging voltage 12 reaches a predetermined value 21 (for example, about 28 V) in the constant current charging (1). This constant power charge (2) is performed until the voltage of the capacitor bank 9 rises, the charge voltage 12 reaches the full charge voltage 22, and the generation of the single cell full charge 23 is notified. In the meantime, the charging current 13 gradually decreases.

  When the next constant current charge (3) is notified of the occurrence of the single cell full charge 23, it is switched and executed. Since this constant current charging (3) is performed using, for example, a constant current of about 2A, when switching, the charging current 13 suddenly drops to a constant value of about 2A. In the bypass circuit 1 that has performed the bypass operation, the charging current flows through the bypass path A. Therefore, the charging operation is not performed in the capacitor cell corresponding to the bypass circuit 1 that has performed the bypass operation. This state is continued until all the bypass circuits 1 perform the bypass operation. Meanwhile, the charging current 13 is a constant value of about 2A.

  When the next intermittent charge (4) is notified of the occurrence of the full charge 25 of all the cells, it is switched and executed. In this intermittent charging (4), charging control is repeated in a certain period with a charging stop period in between. Therefore, the charging current 13 in the certain period flows intermittently. A period 24 in which constant current charging (3) and intermittent charging (4) are performed is an operation period of the bypass circuit 1.

  When the intermittent charge (4) within a certain period is completed, the charge control circuit 7 stops the charge control operation and monitors the transition of the charge voltage 12. For example, when the power storage device is a DC power supply that supplies power to the fixing heater of the image forming apparatus, the charging voltage 12 of the capacitor bank 9 is lowered by the discharge 26 in the process of changing at the full charge voltage 22, and the fixing roller When reaching the lower limit voltage 27 that can be effectively used in the heating unit, the charging control circuit 7 starts recharging 28 from the first constant current charging (1).

  Hereinafter, two application examples of the power storage device described in Embodiments 1 and 2 to an image forming apparatus will be described.

Embodiment 3 FIG.
FIG. 8 is a block diagram showing a configuration example of an image forming apparatus using the power storage device shown in FIGS. 1 and 4 as a main power source of the fixing device as the third embodiment of the present invention. In FIG. 8, reference numeral 29 denotes the power storage device shown in the first and second embodiments.

  The power storage device 29 includes a charge control circuit 30, a capacitor bank 9 including 18 capacitor cells C1 to C18, and an equalization circuit 31 interposed therebetween. The equalization circuit 31 has the configuration shown in FIGS. 2 and 5. In FIG. 8, the bypass circuit 1 is taken out from the equalization circuit 31 and is shown as the bypass circuit 31a. The charge control circuit 7 shown in FIGS. 1 and 4 has a configuration including various circuits from the AC power supply 38 to the smoothing capacitor C40.

  The charge control circuit 30 includes an output voltage generation circuit 32 that outputs a charge voltage to the capacitor bank 9, an output control circuit 33 that controls the output voltage of the output voltage generation circuit 32, and the capacitor bank shown in FIGS. The voltage detection circuit 5, the resistor R31 functioning as the charging current detection circuit 6 shown in FIGS. 1 and 4, and a diode 36 are provided.

  The capacitor bank voltage detection circuit 5 includes a series circuit of resistors R32 and R33. One end of the series circuit is connected to the positive terminal of the capacitor bank 9, and the positive terminal of the output control circuit 33 is connected via the diode 36. The other end of the series circuit is connected to the negative end of the output control circuit 33 via the resistor R31 and to the negative end of the capacitor bank 9. As a result, the capacitor bank voltage detection circuit 5 shows a voltage obtained by dividing the charge voltage of the capacitor bank 9 at the connection end of the series circuit of the resistors R32 and R33, and the divided voltage is used as the detected charge voltage 12. This is given to the output control circuit 33.

  The voltage drop due to the feedback current appearing in the resistor 31 inserted in the charging current feedback path is supplied to the output control circuit 33 as the detected charging current 13. The single-cell full charge signal 10 and the all-cell full charge signal 11 shown in FIGS. 1 and 4 are input from the equalization circuit 31 to the output control circuit 33.

  The output voltage generation circuit 32 includes a high-frequency transformer 34, a switching circuit (FET) 35, a rectifier circuit S composed of two series-parallel diodes, a choke coil L, and a smoothing capacitor C41.

  The output control circuit 33 is not shown in addition to the CPU 33a, a serial controller (SIC) 33b, an A / D converter 33c, a charging current detection circuit 33d, and a PWM generation circuit 33e connected to the CPU 33a via an internal bus. ROM, RAM, termer, interrupt control circuit, and input / output port. The PWM generation circuit 33e is used for control of constant voltage output, constant current charging, and constant power charging.

  In the path from the AC power supply 38 to the smoothing capacitor C40, the following operation is performed. That is, the AC voltage from the AC power supply 38 is input to the full-wave rectifier circuit 41 via the main power switch 39 and the filter 40 and is full-wave rectified. The DC voltage output from the full-wave rectifier circuit 41 is input to the charging control circuit 30 after the ripple component and the like are removed by the smoothing capacitor C40.

  In the output voltage generation circuit 32 in the charge control circuit 30, one end of the primary coil 34a of the high-frequency transformer 34 provided on the DC input side from the full-wave rectifier circuit 41 is connected to one end of the smoothing capacitor C40 and the full-wave rectifier circuit 41. The other end of the primary coil 34a is connected to the negative end of the full-wave rectifier circuit 41 together with the other end of the smoothing capacitor C40 via the FET 35 which is a switching circuit. The PWM signal is input to the gate electrode of the FET 35 from the PWM generation circuit 33e in the output control circuit 33. The PWM generation circuit 33e in the output control circuit 33 generates a PWM signal corresponding to constant voltage output, constant current charging, and constant power charging under the control of the CPU 33a.

  In this configuration, the FET 35 performs an ON / OFF switching operation in accordance with a PWM signal corresponding to a constant voltage output, a constant current charge, and a constant power charge input to the gate electrode from the PWM generation circuit 33e. Since a switching current flows through the primary coil 34a, a switching voltage is induced in the secondary coil 34b. In short, if the conduction period of the switching frequency in the FET 35 is changed, the switching voltage (that is, the output voltage) induced in the secondary coil 34b can be controlled.

  The switching voltage induced in the secondary coil 34b of the high-frequency transformer 34 is rectified by the rectifier circuit S, smoothed by the choke coil L and the smoothing capacitor C41, and converted into a DC output. This DC output is applied to both ends of the capacitor bank 9 through the diode 36 and the resistor R31.

  In this embodiment, the capacitor bank 9 has a characteristic that each of the 18 capacitor cells C1 to C18 can store up to 2.5 V when fully charged. Therefore, when the 18 capacitor cells C1 to C18 are fully charged, the capacitor bank 9 is charged to a voltage of 45V. Note that the storage capacity of the capacitor bank 9 is a capacity that can prevent a temperature drop during continuous copying of the target image forming apparatus, or a capacity that can achieve a required fixing start-up time.

  The charging voltage 12 of the capacitor bank 9 detected by the capacitor bank voltage detection circuit 5 is input to the CPU 33a via the A / D converter 33c in the output control circuit 33. Although it is also input to the engine control unit 42 in parallel, it will be described later. The charging current 13 detected by the resistor 31 is input to the CPU 33a via the A / D converter 33c.

  The operation of the equalization circuit 31 will be briefly described. If the capacitor cell C1 is taken as an example of the capacitor cell of the capacitor bank 9, when the capacitor cell C1 is charged to the fully charged voltage 2.5V, the corresponding bypass circuit 31a bypasses the charging current. The bypass circuit connected in parallel to the other capacitor cells also performs the same operation, so that the charging voltage of each capacitor cell is equalized.

  The equalization circuit 31 detects the full charge of any capacitor cell, and outputs the single cell full charge signal 10 to the CPU 33a in the output control circuit 33 when the bypass circuit operates. Thereafter, the equalization circuit 31 detects the full charge of all the capacitor cells, and outputs all the cell full charge signals 11 to the CPU 33a in the output control circuit 33 when all the bypass circuits are operated.

  The CPU 33a in the output control circuit 33 monitors the charging voltage 12 and charging current 13 input from the A / D converter 33c, the single cell full charge signal 10 and the all cell full charge signal 11 input from the equalization circuit 31, and An instruction is given to the PWM generation circuit 33e based on the monitoring result, and the output voltage to the capacitor bank 9 is controlled by changing the ON duty of the PWM signal at the time of constant voltage output, constant current charge, and constant power charge. .

  Specifically, when the detected charging voltage 12 of the capacitor bank 9 input from the capacitor bank voltage detecting circuit 5 is lower than a preset value, the CPU 33a reduces the voltage drop (charging current 13) at the resistor R31. ) Are detected one by one, an instruction is given to the PWM signal generation circuit 33e, and a PWM signal for setting a constant current charge corresponding to the voltage drop (charging current 13) in the resistor R31 is set to the gate electrode of the FET 35. To output.

  As a PWM signal for setting a preset constant current charge, a table in which the relationship between the voltage drop at the resistor R31 (charging current 13) and the ON duty of the PWM signal is created in advance may be used. It may be calculated by calculation.

  Further, the PWM signal may be controlled so as to obtain a preset charging current by referring only to the voltage drop (charging current 13) at the resistor R31.

  Further, when the capacitor bank 9 is not charged, in order to prevent a large inrush current from flowing into the capacitor bank 9, the PWM signal is initially set to lower the output voltage and gradually increase the output voltage. May be output.

  Next, when the charging voltage 12 of the capacitor bank 9 becomes equal to or higher than a preset value (28 V or higher in this embodiment), the CPU 33a performs the constant power charging, the charging current 13 of the capacitor bank 9, The charging voltage 12 of the bank 9 is taken in step by step, and the PWM signal is calculated and determined in order to perform preset constant power charging from the charging current 13 of the capacitor bank 9 and the charging voltage 12 of the capacitor bank 9, This is given to the PWM signal generation circuit 33e to output a PWM signal for performing preset constant power charging (about 260 W) to the gate electrode of the FET 6.

  Next, when the CPU 33a receives the all-cell full charge signal 11 from the equalization circuit 31, the CPU 33a controls the PWM generation circuit 33e so that the PWM signal output to the gate electrode of the FET 6 is constant voltage charge or intermittent charge for a certain period. Then, a signal for stopping the charging operation is output to the gate electrode of the FET 6.

  Next, the engine control unit 42 includes a CPU 42a, a serial controller (SCI) 42d, an input / output port 42c, an A / D converter 42b, an NV-RAM 42e, a ROM 43f, a RAM 43g, a timer, and a timer connected to the CPU 42a via an internal bus. It comprises an interrupt control circuit (INT) 43i and the like.

  In this embodiment, an AC fixing heater 43 as a heating unit of the fixing device and a DC fixing heater 44 as an auxiliary heater at the time of start-up and when the temperature drops during continuous copying are provided. Connected to the A / D port 43b are temperature detection circuits 45 and 46 for detecting the surface temperature (fixing temperature) of the fixing roller 61 of the fixing device 60 shown in FIG.

  The temperature detection circuit 45 includes a DC heater thermistor 45a provided between another fixed power source and ground (GND) and a resistor R36 connected in series thereto, and corresponds to the DC fixing heater 44. It is a circuit which detects the temperature of the measurement area to be. The temperature detected by the temperature detection circuit 45 is input to the output control circuit 33 and the CPU 42a via the A / D converter 42b in the engine control unit 42.

  The temperature detection circuit 46 includes an AC heater thermistor 46 a provided between another fixed power source and ground (GND) and a resistor R 37 connected in series thereto, and corresponds to the AC fixing heater 43. It is a circuit which detects the temperature of the measurement area to be. The temperature detected by the temperature detection circuit 46 is input to the CPU 42a via the A / D converter 42b in the engine control unit 42.

  The input / output port 43c is provided with an input port, an output port, and five ports (port 1 to port 5). A sensor 50 and a switch circuit 51 necessary for image formation are connected to the input port, and a load 49 such as a motor, solenoid, and clutch necessary for image formation is connected to the output port. ing. The five ports (port 1 to port 5) will be described later.

  The serial controller (SCI) 42d is connected to the serial controller (SCI) 33b in the output control circuit 33, and the CPU 42a transmits and receives signals via the CPU 33a in the output control circuit 33 and the serial controllers (SCI) of each other. Can be done.

  When the CPU 42a receives the charging voltage 12 of the capacitor bank 9 from the capacitor bank voltage detection circuit 5, the CPU 42a determines whether or not the power discharge of the capacitor bank 9 is possible. Notify the CPU 33a. Further, the CPU 42a notifies the CPU 33a in the output control circuit 33 of the voltage value supplied to the DC fixing heater 44 or the pattern for starting up the fixing device 60 by the communication means described above.

  Next, the AC heater control circuit 52 will be described. When the main power is turned on and during normal copy operation, power is supplied to the AC fixing heater 43 to perform the copy operation. When the temperature detection circuit 46 detects a temperature equal to or lower than a preset temperature, the CPU 42a sends a signal for turning on the triac (registered trademark) TR of the phototriac (registered trademark) drive circuit 53 from the port 4 of the input / output port 43c. Output. As a result, AC power is supplied from the AC power source to the fixing heater 43. When the temperature detection circuit 46 detects a temperature equal to or higher than a preset temperature, the CPU 42a outputs a signal for turning off the triac TR to the phototriac drive circuit 53 from the port 4 of the input / output port 42c. Thereby, the AC power supply from the AC power source to the AC fixing heater 30 is stopped.

  Next, an operation for supplying DC power to the DC fixing heater 44 will be described. The CPU 42a checks the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 when the main power source is turned on, and then supplies the stored power of the capacitor bank 9 to the DC fixing heater 44 in the port of the input / output port 42c. 1 outputs a signal for turning on the FET 48, which is a discharge circuit, and outputs a signal for closing the relay 47 from the port 2 of the input / output port 42c. As a result, the power stored in the capacitor bank 9 is supplied to the DC fixing heater 44.

  Alternatively, when the temperature of the fixing heating unit decreases during continuous copying and reaches a temperature at which an unfixed image is generated, the CPU 42a displays the all-cell full charge signal 11 notified from the CPU 33a of the output control circuit 33 or the capacitor bank voltage. After confirming the charging voltage 12 detected by the detection circuit 5, in order to supply the power stored in the capacitor bank 9 to the DC fixing heater 44, a signal for closing the relay 47 is output from the port 2 of the input / output port 42c. A signal for turning on the FET 48 is output from the port 1 of the output port 42c. As a result, the power stored in the capacitor bank 9 is supplied to the DC fixing heater 44.

  When the temperature detection circuit 45 detects the temperature of the fixing heating unit and detects a temperature equal to or higher than a preset temperature, the CPU 42a stops the power discharge of the capacitor bank 9 to stop the power discharge of the input / output port 42c. Then, a signal for opening the relay 24 is output, and a signal for turning off the FET 48 is output from the port 1 of the input / output port 42c.

  In addition, when supplying the power stored in the capacitor bank 9 to the fixing heater 44, discharging is not performed below a lower limit voltage that can be effectively used for heating the fixing roller. As a result, the time for recharging can be shortened.

  Next, the control circuit 55 is a CPU 55a for controlling the entire image forming apparatus, a serial controller (SCI) 55b connected to the CPU 55a via an internal bus, a ROM, a RAM, a work memory for image development used in a printer, and a written image. Frame memory for temporarily storing the image data, an ASIC equipped with a function for controlling the CPU periphery, an interface circuit thereof, and the like.

  An operation unit control circuit 56 is connected to the CPU 55a via the SCI 55b. The operation unit control circuit 56 includes an input unit that allows a user to input a system setting by operating a panel, a display device that displays a setting content state of the system to the user, and a control unit that controls the input unit. I have. The SCI 55b is connected to the SCI 42d in the engine control unit 42, and the CPU 55a can communicate with the CPU 42a in the engine control unit 42 through the mutual SCI.

  Next, FIG. 9 is a cross-sectional view showing a configuration of a fixing device provided in the image forming apparatus shown in FIG. As shown in FIG. 9, the fixing device 60 includes a fixing roller 61 that is a fixing member, a pressure roller 62 that is a pressure member, and a pressure roller 62 (not shown) that is fixed to the fixing roller 61. There is a pressurizing means to press against. Although not shown, the fixing roller 61 and the pressure roller 62 are each driven to rotate by a driving mechanism.

    Further, the fixing device 60 is provided with two fixing heaters (AC fixing heater 43 and DC fixing heater 44) and thermistors 45a and 46a for detecting the surface temperature of the fixing roller 61. The two fixing heaters 43 and 44 are disposed inside the fixing roller 61, and heat the fixing roller 61 from the inside to supply heat to the fixing roller 61.

  The surface temperature detection thermistors 45a and 46a are provided in contact with the surface of the fixing roller 61, respectively, and detect the surface temperature (fixing temperature) of the fixing roller 61. The thermistor 46 a is disposed in the measurement region corresponding to the AC fixing heater 43, and the surface temperature detection thermistor 45 a is disposed in the measurement region corresponding to the DC fixing heater 44.

  The AC fixing heater 43 and the DC fixing heater 44 are heaters that are turned ON to heat the fixing roller 61 when the temperature of the fixing roller 61 does not reach the target temperature. Further, the DC fixing heater 44 stores the power storage unit when the main power of the image forming apparatus is turned on or when the image forming apparatus starts up from the off mode for energy saving until copying is possible, that is, when the fixing apparatus 60 is warmed up. An auxiliary heater is used to start up the fixing device using electric power.

  As described above, in the fixing device 60, when the sheet 64 carrying the toner image 63 passes through the nip portion between the fixing roller 61 and the pressure roller 62, the fixing roller 61 and the pressure roller 62 heat and press the sheet. Is done. As a result, the toner image 63 is fixed on the sheet 64.

  Next, with reference to FIG. 10, the charging control operation performed in the image forming apparatus shown in FIG. 8 will be described. FIG. 10 is a flowchart for explaining the charge control operation performed by the output control circuit in the image forming apparatus shown in FIG.

  In FIG. 10, the CPU 33a in the output control circuit 33 sets the charge permission flag to “1” when the charge permission signal is sent from the CPU 42a in the engine control unit 42. When starting, it is first confirmed whether or not the charge permission flag is “1” (ST21). As a result, when the charge permission flag is not “1” (ST21: No), since the charge permission signal is not sent from the CPU 42a, the charge control is not performed and the present charge control process is terminated. When the flag is “1” (ST21: Yes), the charging control is performed according to the charging permission signal sent from the CPU 42a, and the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 reaches 45V. It is confirmed whether or not (ST22).

  When the charge voltage 12 detected by the capacitor bank voltage detection circuit 5 has reached 45 V (ST22: No), the CPU 33a transmits a full charge voltage signal to the CPU 42a in the engine control unit 42 (ST23). This charging control process is terminated. On the other hand, when the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 has not reached 45V (ST22: Yes), the charging operation in-progress signal is sent to the CPU 42a in the engine control unit 42 in order to perform the charging operation next time. Transmit (ST24) and monitor whether or not the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 is 28V or less (ST25).

  As a result, when the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 is 28 V or less (ST25: Yes), the CPU 33a stores power using the charging current detection circuit 33d in order to perform the constant current charging operation. (ST26), the PWM generation circuit 33e is controlled to the gate electrode of the switching circuit (FET 35), and the charging current detected for carrying out the constant current charging operation is detected. The corresponding PWM signal is output (ST27), and the process returns to ST25 again. When the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 is 28V or less (ST25: Yes), the CPU 33a thereafter continues until the charging voltage detected by the capacitor bank voltage detection circuit 5 exceeds 28V (ST25: No). ), ST25 to ST26 to ST27 to ST25 are repeatedly performed to perform a constant current charging operation.

  Then, as a result of repeating the constant current charging operation, the CPU 33a, when the charging voltage 12 detected by the capacitor bank voltage detection circuit 5 exceeds 28V (ST25: No), this time, in order to perform the constant power charging operation Then, the charging current 13 and the charging voltage 12 of the power storage unit (capacitor bank 9) are detected (ST28), the PWM generation circuit 33e is controlled, and the constant power charging is performed on the gate electrode of the FET 35 which is a switching circuit. Therefore, a PWM signal corresponding to the detected charging current 13 and charging voltage 12 is output (ST29), and the input of the single cell full charge signal 10 from the equalization circuit 31 is monitored (ST30).

  As a result, when the single cell full charge signal 10 is not input from the equalization circuit 31 (ST30: No), the charge control circuit 30 and “timer 1” that detects an abnormality in the equalization circuit 31 are counted up. (ST31). That is, the CPU 33a repeatedly performs the above-described constant power charging operation (processing of ST28 to ST31) until the “timer 1” counts a preset time N (ST32: Yes). When “timer 1” counts a preset time N (ST32: Yes), the PWM signal generation circuit 33e is controlled to stop the charging operation to stop the PWM signal output (ST33). The abnormality of the charging unit is output to the CPU 42a of the engine control unit 42 (ST34), and this charging control process is terminated.

  On the other hand, when the single-cell full charge signal 10 is input from the equalization circuit 31 in ST30 (ST30: Yes), the CPU 33a controls the PWM signal generation circuit 33e to apply to the gate electrode of the switching circuit (FET35). A PWM signal for performing the above-described constant current charging operation is output (ST27), and the charge control circuit 30 is again subjected to constant current charging (ST35).

  When the constant current charging is performed (ST35), the CPU 33a monitors the input of the all-cell full charge signal 11 from the equalization circuit 31 (ST36). If the all-cell full charge signal 11 is not input (ST36: No), “timer 2” that detects an abnormality in the charge control circuit 30 and the equalization circuit 31 is counted up (ST37). That is, until the “timer 2” counts the preset time N (ST38: Yes), the CPU 33a receives the single cell full charge signal 10 from the equalization circuit 31 (ST30: Yes). The constant current charging is repeatedly performed (ST35) while confirming the above, and in the process, when the "timer 2" counts a preset time N (ST38: Yes), in order to stop the charging operation, ST33 , ST34 is performed, and this charging control process is terminated.

  On the other hand, when the all-cell full charge signal 11 is input from the equalization circuit 31 in ST36 (ST36: Yes), the CPU 33a transmits the input all-cell full charge signal 11 to the CPU 42a of the engine control unit 42 (ST39). ), The PWM signal generation circuit 33e is controlled to output a PWM signal having a pattern for performing intermittent constant current charging or intermittent constant voltage charging for a certain period to the gate electrode of the switching circuit (FET 35) (ST40). The charging control process is terminated after the period.

  In intermittent constant current charging, the PWM signal generation circuit 33e alternately repeats an operation for outputting a constant current charging PWM signal for a certain period of time and an operation for stopping the output of the PWM signal for a certain period of time within a certain period. Is done.

  In intermittent constant voltage charging, the PWM signal generation circuit 33e alternately repeats an operation for outputting a constant voltage charging PWM signal for a certain period of time and an operation for stopping the output of the PWM signal for a certain period of time within a certain period. Is done.

  Next, with reference to FIG. 11, a temperature control operation at the time of fixing start-up performed in the image forming apparatus shown in FIG. 8 will be described. FIG. 11 is a flowchart for explaining the temperature control operation at the time of fixing start-up performed by the engine control unit in the image forming apparatus shown in FIG.

  In FIG. 11, large-capacity power is stored in the capacitor bank 9 and discharged from the capacitor bank 9 at the time of start-up. Thereafter, when the heating part temperature exceeds a preset temperature, or the charging voltage ( When the discharge voltage 12 is lower than 21 V, a series of processing procedures for stopping the discharge of the capacitor bank 9, supplying power only to the AC fixing heater 43, and controlling the temperature of the fixing heating unit to a predetermined temperature is performed. It is shown. The reason why the discharging is stopped when the charging voltage (discharging voltage) 12 is lower than 21 V is that there is no heat generation effect even if the stored power of a voltage lower than this is supplied to the fixing heating unit.

  In FIG. 11, the CPU 42a in the engine control unit 42 sets the start flag to “1” when the main power is turned on or when the energy saving mode is canceled. First, whether or not the start flag is set to “1”. (ST51). If the start flag is not set to “1” (ST51: No), the fixing start-up process is terminated. On the other hand, when the start flag is set to “1” (ST51: Yea), whether or not a full charge signal is transmitted from the CPU 33a in the output control circuit 33, or is input to the A / D port 42b. It is confirmed whether or not the charging voltage 12 of the capacitor bank 9 is 41 V or more (ST52).

  When the determination result in ST52 is affirmative (Yes), the CPU 42a detects each temperature input from the temperature detection circuits 45 and 46 to the A / D port 42b, and the heating unit temperature is set to a preset temperature (for example, 170 ° C.) or less (ST53). As a result, when the heating part temperature is set to, for example, 170 ° C. or lower (ST53: Yes), the detected heating part temperature needs to use the power stored in the capacitor bank in order to shorten the fixing start-up time. The CPU 42a next checks whether or not the charging voltage 12 is 21 V or higher (ST54).

  When the charging voltage 12 is 21 V or higher (ST54: Yes), the CPU 42a outputs an output stop signal of the PWM signal to the CPU 33a of the output control circuit 33 (ST55) and prohibits the charging operation. A charge prohibition signal is transmitted (ST56).

  In parallel, the CPU 42a outputs a signal for causing the relay 47 to perform a closing operation from the port 2 of the input / output port 42c in order to supply the stored power of the capacitor bank 9 to the DC fixing heater 44 (ST57). A signal for turning on the discharge circuit (FET 48) is output from the port 1 of the output port 42c (ST58).

  In the process of ST58, if the discharge circuit (FET 48) is turned on after a certain period of time after the relay 47 performs the closing operation, contact welding of the relay can be prevented.

  Then, the CPU 42a outputs a signal for turning on the AC fixing heater 43 from the port 4 of the input / output port 42c (ST59), returns to the processing of the previous ST53, and again from the temperature detection circuits 45, 46 to the A Each temperature input to the / D port 42b is detected, and it is checked whether or not the heating unit temperature is equal to or lower than a preset temperature (for example, 170 ° C.).

  As a result, as long as the heating part temperature is equal to or lower than a preset temperature (for example, 170 ° C.) (ST53: Yes) and the charging voltage 12 is 21 V or more (ST54: Yes), the above-described processing of ST55 to ST59 ( (Charge stop process, DC to AC switching process of electric power supplied to the heating unit) and the process of returning to ST53 is repeated.

  In the process, when the heating unit temperature is equal to or lower than a preset temperature (for example, 170 ° C.) (ST53: Yes), but the charging voltage 12 is not 21 V or more (ST54: No), DC power is supplied to the fixing heating unit. Even if supplied, it does not provide an effective power supply to the fixing and heating unit. Therefore, in order to stop the discharge, in ST61 to ST64, the same processing as ST55 to ST59 (charging stop processing, the power supplied to the heating unit) (Switching process from DC to AC) is performed, and the process returns to ST53.

  Further, when the determination is made by returning to ST53, when the heating unit temperature is equal to or higher than a preset temperature (for example, 170 ° C.) (ST53: No), the CPU 42a sends the temperature detection circuits 45 and 46 to the A / D port 42b. Each temperature input to is detected, and it is checked whether or not the heating part temperature is equal to or lower than a preset temperature (for example, 178 ° C.). The determination process in ST60 is also performed when the determination result in ST52 is negative (No).

  As a result, when the heating unit temperature is equal to or lower than a preset temperature (for example, 178 ° C.) (ST60: Yes), in ST61 to ST64, the same processing as ST55 to ST59 (charging stop processing, heating unit) (Switching process of supplied power from DC to AC) is performed, and the process returns to ST53.

  In this way, control is performed in which the power supply to the fixing heating unit is switched from the supply of both the stored power and AC power of the capacitor bank 9 to only AC power.

  In ST60, when the heating part temperature exceeds a preset temperature (for example, 178 ° C.) (ST60: No), the CPU 42a sets each temperature input from the temperature detection circuits 45 and 46 to the A / D port 42b. It is detected and it is investigated whether the heating part temperature is a preset reload temperature (for example, 180 ° C.) (ST65).

  When the detected heating part temperature has not reached the reload temperature (180 ° C.) (ST65: No), the process returns to ST53 and the power supply to the AC fixing heater 43 is continued. When the detected heating part temperature reaches the reload temperature (180 ° C.) (ST65: Yes), the CPU 42a resets the rising flag (ST66) and sets the fixing reload flag (ST76).

  In parallel, the CPU 42a outputs a signal for turning off the discharge circuit (FET 48) from the port 1 of the input / output port 42c (ST68). A signal for turning off the AC fixing heater 43 is output from the port 4 of the input / output port 42c. Then, in order to perform the charging operation, the CPU 42a transmits a charging permission signal to the CPU 33a in the output control circuit 33 (ST70), and ends the fixing start-up process.

  According to the third embodiment, since the power storage device with reduced cost is used, an image forming apparatus with reduced manufacturing cost can be provided. By using the stored power of the power storage device as the power of the heating unit of the fixing device, it is possible to shorten the rise time of the image forming apparatus and improve productivity. In addition, since the discharge is performed up to the lower limit voltage that can be effectively used for the heating unit of the fixing roller, and the discharge is not performed below the lower limit voltage, it is possible to shorten the recharge control and reduce wasteful power consumption.

Embodiment 4 FIG.
FIG. 12 is a block diagram showing a configuration example of an image forming apparatus using the power storage device shown in FIGS. 1 and 4 as an auxiliary power source of a fixing device as a fourth embodiment of the present invention. In the fourth embodiment, there is shown a configuration example in the case where the supply of power to the load is insufficient for the supply of AC power, and the shortage of power is switched to the supply from the power storage device.

  In the case of an image forming apparatus in a high-speed field, since a large amount of electric power is used for the fixing and heating unit, when a commonly used AC100V, 15A rated commercial power supply is used, a shortage may occur. Further, when the main power switch is turned on, it takes a long time to reach a fixing temperature at which the image forming apparatus can be used.

  Therefore, as shown in FIG. 12, the power storage device 70 is prepared as an auxiliary power source, and the power shortage described above is supplied from the power storage device 70 to the load.

  In FIG. 12, the power storage device 70 has the configuration shown in the first and second embodiments, and shows a charge control circuit 71, a power storage unit 72, and a stored voltage detection circuit 73. The power storage unit 72 includes a capacitor bank and an equalization circuit as main components.

  The AC power source 75 is supplied to the AC / DC converter 76 and the fixing heating unit temperature control circuit 78. The AC / DC converter 76 is a circuit that generates a DC constant voltage from the AC voltage. The output of the AC / DC converter 76 is supplied to the image forming apparatus control circuit 77 and the charge control circuit 71, and is also supplied to the load 81 via the switching circuit 79. The load 81 is a power system load such as various motors, solenoids, and clutches for performing an image forming operation.

  The charge control circuit 71 confirms the charge voltage detected by the charge voltage detection circuit 73 based on an instruction from the image forming apparatus control circuit 77 and controls charging to the power storage unit 72. The stored power of the charged power storage unit 72 is input to the constant voltage generation circuit 80. The constant voltage generation circuit 80 has a step-up / down converter function that generates a constant voltage (for example, 24 V) even when the voltage of the power storage unit 72 decreases due to discharge. The output of the constant voltage generation circuit 80 is input to the switching circuit 79.

  The fixing heating unit temperature control circuit 78 detects the heating unit temperature with a temperature detection element 83 provided in the fixing heating unit 82, and when the detected temperature is lower than a preset temperature, the fixing heating unit 82 is supplied with an AC power source. When the detected temperature is higher than a preset temperature, the power supply from the AC power supply is cut off.

  In this case, in a situation where the changeover switch 79 selects the output of the AC / DC converter 76 and supplies power to the load 81, the image forming apparatus control circuit 77 uses the fixing heating unit temperature control circuit 78 for fixing heating. Even when the preset power is supplied to the unit 82, when the temperature of the fixing heating unit 82 is lower than the preset temperature, the load switch 81 is selected by causing the changeover switch 79 to select the power storage device 70 side. Measures are taken to supply DC power and supply excess AC power to the fixing heating unit 82.

  Thus, in normal times, when the power supply to the fixing heating unit 82 is 80% duty power supply, the changeover switch 79 is switched to the power storage device 70 side to perform 100% duty power supply. Can do.

  According to the fourth embodiment, since the power storage device designed to reduce costs is used, an image forming apparatus with reduced manufacturing costs can be provided. When the power supplied from the AC power source to the heating unit of the fixing device is insufficient, the power supply from the AC power source to the load is switched to the supply from the power storage device, and the surplus AC power is used for the heating unit power of the fixing device. Therefore, the rise time of the image forming apparatus can be shortened.

  In each of the above embodiments, an electric double layer capacitor has been shown as a power storage cell. However, the present invention is not limited to this, and a lithium battery can be similarly used as the power storage cell.

  As described above, the power storage device according to the present invention is useful for cost reduction regardless of the number of power storage cells, and is particularly used as an auxiliary power source for an image forming apparatus to shorten the rise time of the device. Suitable for

It is a block diagram which shows the structure of the electrical storage apparatus by Embodiment 1 of this invention. FIG. 2 is a circuit diagram illustrating a specific configuration example of an equalization circuit in the power storage device illustrated in FIG. 1. 4 is a flowchart for explaining a charge control operation in the power storage device shown in FIG. 1. It is a block diagram which shows the structure of the electrical storage apparatus by Embodiment 2 of this invention. FIG. 5 is a circuit diagram illustrating a specific configuration example of an equalization circuit in the power storage device illustrated in FIG. 4. 5 is a flowchart for explaining a charge control operation in the power storage device shown in FIG. It is a figure explaining the charging / discharging sequence of the capacitor bank in the electrical storage apparatus shown in FIG. FIG. 5 is a block diagram illustrating a configuration example of an image forming apparatus that uses the power storage device illustrated in FIGS. 1 and 4 as a main power source of a fixing device as a third embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a configuration of a fixing device included in the image forming apparatus illustrated in FIG. 8. 9 is a flowchart for explaining a charge control operation performed by an output control circuit in the image forming apparatus shown in FIG. 8. 9 is a flowchart for explaining a temperature control operation at the time of fixing start-up performed by an engine control unit in the image forming apparatus shown in FIG. 8. FIG. 6 is a block diagram illustrating a configuration example of an image forming apparatus that uses the power storage device illustrated in FIGS. 1 and 4 as an auxiliary power source of a fixing device as a fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bypass circuit 1a Single cell full charge detection circuit 1b Switching circuit A Bypass path 2 Switching circuit which comprises the switching circuit group in connection with detection of full charge of all cells 3 Switching circuit in connection with detection of single cell full charge (1st switching circuit )
4 Photocoupler that detects and outputs a full charge of a single cell (first photocoupler)
5 Capacitor bank voltage detection circuit 6 Charging current detection circuit 7 Charge control circuit 8 Switching circuit related to detection of full charge of all cells (second switching circuit)
9 Capacitor banks C1 to C18 Electric double layer capacitors (capacitor cells)
10 single cell full charge signal 11 all cell full charge signal 12 charge voltage detection signal 13 charge current detection signal 14 photocoupler that detects and outputs full charge of all cells (second photocoupler)
15 Inverter 16 Comparator for detecting and outputting full charge of a single cell (first comparator)
17 Comparator (second comparator) that detects and outputs full charge of all cells
DESCRIPTION OF SYMBOLS 29 Power storage device 30 Charge control circuit 31 Equalization circuit 32 Output voltage generation circuit 33 Output control circuit 34 High frequency transformer 35 Switching circuit (FET)
S rectifier circuit L choke coil C40, C41 smoothing capacitor 36 diode 38 AC power supply 39 main power switch 40 filter 41 full wave rectifier 42 engine control unit 43 AC fixing heater 44 DC fixing heater 45, 46 temperature detection circuit 45a, 46a temperature detection Element (Thermistor)
47 Relay 48 Discharge circuit (FET)
49 Load 50 Sensor 51 Switch circuit 52 AC heater control circuit 53 Phototriac driver circuit 55 Control circuit 56 Operation unit control circuit 57 Full-wave rectifier 58 DC / DC converter 60 Fixing device 61 Fixing roller 62 Pressure roller 63 Toner 64 Sheet 70 Power storage Device 71 Charge control circuit 72 Power storage unit 73 Charging voltage detection circuit 75 Commercial power supply 76 AC / DC converter 77 Image forming device control circuit 78 Temperature control circuit for fixing heating unit 79 Switching circuit 80 Constant voltage generation circuit 81 Load 82 Fixing heating unit 83 Temperature detection element

Claims (8)

A cell bank in which a plurality of chargeable / dischargeable storage cells are connected in series, a charge control circuit that performs charge control for the cell bank, and a charge current in a storage cell that detects a charge voltage of each of the storage cells and exceeds a predetermined value In a power storage device comprising a plurality of bypass circuits for bypassing
First detecting means for detecting that any of the plurality of bypass circuits has performed a bypass operation and notifying the charge control circuit;
Second detection means for detecting that all of the plurality of bypass circuits have performed a bypass operation and notifying the charge control circuit;
A power storage device comprising: The first detection means includes
If any of the plurality of bypass circuits is not performing a bypass operation, either the ON operation or the OFF operation is performed. If any of the plurality of bypass circuits performs a bypass operation, the bypass operation is bypassed. A first switching circuit that performs either the ON operation or the OFF operation based on the charged current;
When the first switching circuit is performing one of an ON operation and an OFF operation, one level signal of a binary level is output to the charge control circuit, and the first switching circuit is turned on. And a first photocoupler that outputs the other level signal of the binary level to the charge control circuit when the other operation is performed.
Consists of
The second detection means includes
Each switching circuit of the plurality of switching circuits connected in series between both ends of the cell bank in a one-to-one relationship with the plurality of bypass circuits performs an OFF operation when the corresponding bypass circuit is not performing a bypass operation. A switching circuit group that performs an ON operation based on the bypassed charging current when the corresponding bypass circuit performs a bypass operation;
If the potential of the connection end of the switching circuit group to the high potential side of the cell bank is in a high potential state, either the ON operation or the OFF operation is performed, and if it is in the low potential state, the ON operation is performed. A second switching circuit for performing the other operation of the OFF operation;
When the second switching circuit is performing one of an ON operation and an OFF operation, one level signal of a binary level is output to the charge control circuit, and the second switching circuit is turned on. And a second photocoupler that outputs the other level signal of the binary level to the charge control circuit when the other operation is performed.
Composed of,
The power storage device according to claim 1. The first detection means includes
When none of the plurality of bypass circuits performs a bypass operation, one level signal of a binary level is output to the charge control circuit, and when any of the plurality of bypass circuits performs a bypass operation A first comparator that outputs the other level signal of the binary level to the charge control circuit;
Consists of
The second detection means includes
Each switching circuit of the plurality of switching circuits connected in series between both ends of the cell bank in a one-to-one relationship with the plurality of bypass circuits performs an OFF operation when the corresponding bypass circuit is not performing a bypass operation. A switching circuit group that performs an ON operation based on the bypassed charging current when the corresponding bypass circuit performs a bypass operation;
When the potential at the connection end of the switching circuit group to the high potential side of the cell bank is in a high potential state, one level signal of a binary level is output to the charge control circuit, and in the low potential state A second comparator for outputting the other level signal of the binary level to the charge control circuit;
Composed of,
The power storage device according to claim 1.   The power storage device according to claim 1, wherein the power storage cell is an electric double layer capacitor or a lithium battery.   An image forming apparatus comprising a fixing device, wherein the power storage device according to claim 1 is provided in the apparatus main body.   The image forming apparatus according to claim 5, wherein when the storage voltage of the power storage device is lowered to a predetermined value, power supply from the power storage device to the heating unit of the fixing device is stopped.   The image forming apparatus according to claim 5, wherein when the power supply to the heating unit of the fixing device is insufficient, the power supply to the load is switched to the supply from the power storage device. The power storage device according to claim 1, wherein the charge control circuit is a charge control step.
Detecting the charging voltage of the cell bank;
When the detected charging voltage does not exceed a predetermined voltage value, performing a first constant current charging;
When the detected charging voltage exceeds a predetermined voltage value, the step of switching from the first constant current charging to the constant power charging,
In the process of performing the constant power charging, when a detection notification is input from the first detection means for detecting that any of the plurality of bypass circuits has performed a bypass operation, the first Performing a second constant current charge with a constant current smaller than a constant current used in the constant current charge;
In the process of performing the second constant current charging, when a detection notification is input from the second detection unit that detects that all of the plurality of bypass circuits have performed a bypass operation, A step of switching from constant current charging of 2 to intermittent charging;
A charge control method for a power storage device, comprising:

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