JP2009071756A - Image processing circuit, and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase processing speed in an entire image processing circuit by reducing the amount of data used for expansion processing in an expansion/reduction circuit. <P>SOLUTION: In the expansion/reduction circuit 24, an expansion/reduction section 2400 reads pixel data in a prescribed range in the order of a main scanning direction from pixel data composing an original image stored in an external memory 30. Each time the pixel data in a prescribed range are read, a plurality of pixel data are calculated at least in a vertical scanning direction in the pixel data that can be calculated from the read pixel data by using the read pixel data and compose an expansion image for output to a FIFO memory 2410. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing circuit and an image processing apparatus, and more particularly to a technique for performing an image enlargement / reduction process.

  In an image processing apparatus such as a printer, an image scanner, or a copier, a technique for enlarging or reducing an input image is known. Image processing such as enlargement and reduction is executed by, for example, a dedicated circuit or a program executed by a CPU (Central Processing Unit). For example, in Patent Document 1, image data enlargement processing is performed by an ASIC (Application Specific IC).

JP 2006-45837 A

  In an image processing apparatus that executes scan processing and print processing, a control device for performing image processing has, for example, a system configuration as shown in FIG. As shown in the figure, the control device includes a CCD sensor 10, an image data processing unit 20 (shading correction circuit 22, interline correction circuit 23, enlargement / reduction circuit 24, image processing circuit 25, printer output circuit 26), An external memory 30 and a printer 40 are included. The external memory 30 is configured by, for example, a DDR-SDRAM (Double Data Rate SDRAM).

  The operation of each of the above devices and the flow of image data will be described. First, when a scanner signal is input through the CCD sensor 10, photoelectric conversion and A / D conversion are performed and stored in the external memory 30 as image data. When the shading correction circuit 22 receives the image data output from the external memory 30, the shading correction circuit 22 corrects shading caused by variations in sensitivity of the CCD sensor 10 that reads the document and the light distribution characteristics of the lamp for illuminating the document. Output to the circuit 23. The inter-line correction circuit 23 synchronizes image data read at different timings by the line sensor (CCD sensor 10) for each RGB color at the same position on the document so as to be data at the same position on the document, and corrects the correction. The subsequent image data is output to the external memory 30. When receiving the image data output from the external memory 30, the enlargement / reduction circuit 24 performs enlargement / reduction processing on the input image and outputs the enlarged image or the reduced image to the external memory 30 as described later. Upon receiving the image data output from the external memory 30, the image processing circuit 25 performs filter processing such as MTF correction, sharpening, and smoothing, for example. In addition, color conversion processing from RGB colors to CMYK colors, halftoning, and the like are performed, and output to the external memory 30 as print data. The printer output circuit 26 reads the print data from the external memory 30 and outputs it to the printer 40. The printer 40 performs print processing by driving a print head or the like using print data.

  As described above, between the above devices and the external memory 30, reading of image data necessary for processing of each device and writing of image data after the processing, that is, data input / output frequently occur. Each device performs processing using data processed by the preceding device. For this reason, if data input / output increases between any of the devices and the external memory 30, processing of other devices is delayed, leading to a decrease in processing speed of the entire image data processing.

  Incidentally, in the conventional enlargement / reduction circuit, the enlargement / reduction process is executed as follows.

  FIG. 6 is a diagram for explaining an algorithm for enlargement / reduction processing. The pixel value of the target pixel D ′ is calculated by two-dimensional interpolation using the pixel values of the pixels D0, D1, D2, and D3 of the input image located around the target pixel D ′. That is, two pixels are used from two lines of the input image, and arbitrary target pixel data located within the range surrounded by the four pixels is calculated. Specifically, D ′ = D0 × (1−dx) × (1−dy) + D1 × dx × (1−dy) + D2 × (1−dx) × dy + D3 × dx × dy).

  FIG. 7 is a diagram for explaining enlargement processing in a conventional enlargement / reduction circuit. This figure shows an example of enlarging input image data to 400%. In the enlargement process, as shown in FIGS. 7A to 7D, pixel data after enlargement in the main scanning direction (pixel data constituting the image after enlargement) is calculated for each line constituting the image after enlargement. Is done. Specifically, first, the enlargement / reduction circuit calculates four consecutive enlarged pixel data on the same line, and the four pixels located around the enlarged pixel data (dotted square corners). Read pixel data of input image (input pixel data). Further, four pieces of enlarged pixel data are calculated using the read input pixel data. Similarly, the enlargement / reduction circuit repeatedly reads the four input pixel data from the input image data while shifting the pixels one pixel at a time in the main scanning direction, and calculates the enlarged pixel data. When the processing for one line is completed, the same processing is performed for the next line adjacent in the sub-scanning direction.

  As described above, in the enlargement process in the conventional enlargement / reduction circuit, the input pixel data in a predetermined range is repeatedly read for each line constituting the enlarged image, and the post-enlargement pixel data is calculated. Therefore, the amount of data read from the external memory 30 by the enlargement / reduction circuit 24 increases in proportion to the enlargement magnification, that is, according to the number of pixels in the sub-scanning direction of the enlarged image. As the amount of data input / output between the enlargement / reduction circuit 24 and the external memory 30 increases, the overall speed of image data processing decreases.

  An object of the present invention is to provide a technique for improving the overall speed of image data processing by reducing the amount of data used in enlargement processing.

  In order to solve the above problems, one embodiment of the present invention is an image processing circuit that outputs pixel data that forms an enlarged image using pixel data that forms an original image, and the pixel data that forms the original image A pixel image of a predetermined range is read in the order of the main scanning direction, and an enlarged image that can be calculated from the read pixel data using the read pixel data each time the pixel data of the predetermined range is read Among the pixel data to be processed, a plurality of pixel data are calculated and output at least in the sub-scanning direction.

  The image processing circuit calculates all of the pixel data constituting the enlarged image that can be calculated from the read pixel data using the read pixel data each time the predetermined range of pixel data is read. However, it can also be configured to output.

  An image processing circuit that outputs pixel data constituting an enlarged image using pixel data constituting an original image, and is arranged in two lines in the main scanning direction from the pixel data constituting the original image. All the pixel data on the plurality of lines constituting the enlarged image that can be calculated by interpolation calculation using the pixel data each time a plurality of pixel data straddling are read and the pixel data is read in the sub-scanning direction And an enlargement processing unit that calculates and outputs each column of pixel data.

  In addition, the image processing circuit has a region for storing each pixel data output from the enlargement processing unit for a corresponding number of pixels for each corresponding line, and pixel data having a predetermined number of pixels. For each line in which is stored, a FIFO memory for outputting pixel data.

  Further, the above-described image processing circuit can be mounted on an image processing apparatus together with an image memory to which the image processing circuit is connected.

  An embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the control device for performing image processing has a system configuration as shown in FIG. 1 as described above, for example.

  Hereinafter, a characteristic operation of the enlargement process in the enlargement / reduction circuit according to the present embodiment will be described.

  FIG. 2 is a diagram for explaining enlargement processing in the enlargement / reduction circuit. This figure shows an example of enlarging input image data to 400%. In the enlargement process, as shown in FIGS. 2A to 2D, the enlarged pixel data is calculated in units of blocks for each of a plurality of lines constituting the enlarged image. Specifically, first, the enlargement / reduction circuit 24 calculates four input pixels located around the enlarged pixel data (dotted square corners) in order to calculate the enlarged pixel data on the four lines. Read data. Also, using the read input pixel data, four enlarged pixel data are calculated on each of the four lines. Similarly, the enlargement / reduction circuit 24 repeatedly reads four input pixel data from the input image data while shifting the input pixel data by one pixel at a time in the main scanning direction, and reads the enlarged pixel data in units of blocks (4 pixels × 4 lines). calculate. When the processing for four lines is completed, the same processing is performed for the next four adjacent lines in the sub-scanning direction.

  As described above, in the enlargement process in the enlargement / reduction circuit of the present embodiment, the input pixel data in a predetermined range is repeatedly read for each of a plurality of lines constituting the enlarged image, and the post-enlargement pixel data is processed in block units. Calculate. That is, input pixel data in a predetermined range is read, and as much enlarged pixel data as possible is output from the input pixel data.

  Next, the configuration of the enlargement / reduction circuit in which the above enlargement process operates will be described.

  FIG. 3 is a block diagram showing the configuration of the enlargement / reduction circuit. As shown in the figure, the enlargement / reduction circuit 24 includes an enlargement / reduction unit 2400, a FIFO memory 2410, an output buffer 2420, and a signal line connecting them.

  As described with reference to FIG. 2, the enlargement / reduction unit 2400 calculates 4-line enlarged pixel data using the 2-line input pixel data output from the external memory 30. In addition, the calculated post-enlargement pixel data for each of the four lines is output to the FIFO memory via the corresponding signal lines RGB1 to RGB4. The enlargement / reduction unit 2400 includes, for example, a horizontal interpolator and a vertical interpolator.

  The FIFO memory 2410 is a device for temporarily buffering the enlarged pixel data output from the enlargement / reduction unit 2400, and includes, for example, an SRAM or a dual port SRAM. Pixel data input via the signal lines RGB1 to RGB4 are written in areas 2411 to 2414, respectively. The pixel data written in the areas 2411 to 2414 is output to the output buffer 2420 in the order of writing.

  The configuration of the FIFO memory 2410 will be specifically described with reference to FIG. FIG. 4A shows the arrangement of the pixel data of the image data after the enlargement process in the enlargement / reduction unit 2400. As shown in FIG. 4B, each of the areas 2411 to 2414 of the FIFO memory 2410 can store 16 bytes of pixel data (16 pixels if 1 byte of pixel data). Each region 2411 to 2414 is configured as a ring buffer. Each pixel of the image data (FIG. 4A) is divided into RGB pixel data and stored in the FIFO memory. For example, pixel data at the pixel position (1, 1) is divided into pixel data R (1, 1), G (1, 1), and B (1, 1) and stored in the region 2411.

  Returning to FIG. 3, the output buffer 2420 buffers a predetermined amount of pixel data output from each of the areas 2411 to 2414 of the FIFO memory 2410, and outputs the pixel data to the external memory 30. Here, the output buffer 2420 is 16 bytes in size. That is, for each line (regions 2411 to 2412), the pixel data after the enlargement process is collected into 16 bytes and output to the external memory 30.

  Next, with reference to a timing chart shown in FIG. 5, an operation of transferring the pixel data after the enlargement process from the enlargement / reduction unit 2400 to the FIFO memory 2410 will be described.

  As shown in this figure, when the START pulse is generated in the enlargement / reduction unit 2400, the above-described enlargement processing is performed until the END pulse is generated. Then, four pixels (four pixel data in the sub-scanning direction) of the four lines after the enlargement process are output to the regions 2411 to 2414 via the signal lines RGB1 to RGB4. An END pulse is generated when H_counter = n (the number of pixels in the main scanning direction of pixel data after enlargement processing). The value of n is set by the CPU.

  The embodiment of the present invention has been described above. According to the present embodiment, the amount of data used by the enlargement / reduction circuit can be reduced, and the overall speed of image data processing can be improved. That is, read access to the external memory can be reduced by increasing the number of post-expansion pixel data calculated using input pixel data in a predetermined range. This increases the external memory access bus bandwidth that can be used by other circuits that perform various processes. Further, since the processing time of the enlargement process in the enlargement / reduction circuit is shortened, the processing speed of the entire control apparatus that performs image data processing is improved. Further, by adopting a configuration in which the enlargement process is performed in units of blocks, pipeline processing in units of blocks can be performed in the entire control apparatus, so that the time until a print result is obtained is shortened.

  The present invention has been described in connection with exemplary embodiments. Obviously, many alternatives, modifications, and variations will be apparent to practitioners skilled in this art. Accordingly, the above-described embodiments of the present invention are intended to illustrate and not limit the gist and scope of the present invention.

The block diagram which shows the system configuration | structure of the control apparatus which performs image data processing. The figure for demonstrating the expansion process in an expansion / contraction circuit. The block diagram which shows the structure of an expansion / contraction circuit. The figure for demonstrating the structure of a FIFO memory, and arrangement | positioning of pixel data. FIG. 6 is a timing chart illustrating an operation of transferring pixel data after enlargement processing. The figure for demonstrating the algorithm of an enlargement / reduction process. The figure for demonstrating the expansion process in the conventional expansion / contraction circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... CCD sensor, 20 ... Image data processing part, 22 ... Shading correction circuit, 23 ... Interline correction circuit, 24 ... Enlargement / reduction circuit, 25 ... Image processing circuit, 26 ... Printer output circuit, 30 ... External memory, 40 ... Printer, 2400 ... Enlargement / reduction unit, 2410 ... FIFO memory, 2411 ... Area, 2412 ... Area, 2413 ... -Area, 2414 ... Area, 2420 ... Output buffer

Claims (5)

An image processing circuit that outputs pixel data constituting an enlarged image using pixel data constituting an original image,
Read pixel data in a predetermined range from the pixel data constituting the original image in the order of the main scanning direction,
Each time pixel data in a predetermined range is read, using the read pixel data, a plurality of pixel data in at least the sub-scanning direction are calculated out of the pixel data constituting the enlarged image that can be calculated from the read pixel data. Output,
An image processing circuit. The image processing circuit according to claim 1,
Every time pixel data of a predetermined range is read, using the read pixel data, all the pixel data constituting the enlarged image that can be calculated from the read pixel data is calculated and output.
An image processing circuit. An image processing circuit that outputs pixel data constituting an enlarged image using pixel data constituting an original image,
From the pixel data constituting the original image, a plurality of pixel data extending over two lines can be read in the order of the main scanning direction, and every time the pixel data is read, the pixel data can be calculated by an interpolation operation using the pixel data. An enlargement processing unit that calculates and outputs all of the pixel data on a plurality of lines constituting the enlarged image for each column of pixel data in the sub-scanning direction;
An image processing circuit. The image processing circuit according to claim 3,
Each pixel data output from the enlargement processing unit has a region for storing a predetermined number of pixels for each corresponding line, and pixel data is stored for each line in which pixel data of a predetermined number of pixels is stored. Having a FIFO memory to output,
An image processing circuit.   An image processing device comprising: the image processing circuit according to claim 1; and an image memory to which the image processing circuit is connected.

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