JP2009065641A - Electronic device, and information apparatus, communications apparatus, av apparatus, and mobile apparatus using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the signal waveform distortion along the transmission line in an electronic device. <P>SOLUTION: An electronic device includes a transmitting circuit Tx5A, a receiving circuit Rx5B, a first conductor 1A, and a second conductor of a return path being a grounded line. The first conductor 1A is surrounded by a dielectric. A plurality of resistive elements Rg5C are connected in parallel between the first conductor 1A and the second conductor. The first conductor 1A transfers therethrough a transmission signal from the transmitting circuit Tx5A. The length of the line of the first conductor 1A is set to be greater than or equal to one half of the product between the inverse of the signal transfer rate of the first conductor 1A and the velocity of light traveling through the dielectric. The resistive elements Rg5C are provided on the line of the first conductor 1A for every unit distance being equal to one half of the product between the transmission signal transfer rate of the first conductor 1A and the velocity of light traveling through the dielectric. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic device, and more particularly, to communication within an integrated circuit in the electronic device and between the integrated circuits, and to a technology for speeding up and reducing area and power consumption using a transmission line.

  Conventionally, as a high-speed communication method in an integrated circuit including a semiconductor in an electronic device and between integrated circuits, there is a method of using a transmission line between a transmission circuit and a reception circuit. This transmission line uses a device element that can form the same impedance value as the characteristic impedance of the line made of a conductor. When the transmission line is of a single signal line type, this device element is connected between a conductor line for transmitting a signal in the vicinity of the receiving circuit and the return path. When the transmission line is a differential transmission system, the transmission line is connected between two conductor lines.

   By such a method, the reflection coefficient of the signal propagating through the conductor line is suppressed to 0 as much as possible, and a more reliable voltage waveform of the signal is generated in the vicinity of the receiving circuit and received by the receiving circuit. Such a technique is described in Non-Patent Document 1.

  In the transmission line, the frequency of the actually transmitted signal is not always the same, and the reflection coefficient of the signal cannot be zero due to intersymbol interference (ISI).

In order to solve this, conventionally, the duobinary transmission technique described in Non-Patent Document 2, the pre-emphasis technique described in Non-Patent Document 3, the return zero (RZ) technique described in Non-Patent Document 4, The equalizer technology described in Patent Document 5 and Non-Patent Document 6 is used.
All distributed constant circuits for board designers Chapter 6 and Chapter 9 by Yuzo Sakurai IEEE International Solid-State Circuits Conference 2005 Session 3.6 “12Gb / s Duobinary Signaling with × 2 Oversampled Edge Equalization” P.297 “A 3-Gb / s / ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects” published in IEEE Journal of Solid-State Circuits, volume 41, Number 1, JANUARY 2006 P.772 "Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication" published in IEEE Journal of Solid-State Circuits volume 41, Number 4, APRIL 2006 P.872 “A Fully Integrated 10Gbp / s Receiver with Adaptive Optical Dispersion Equalizer in 0.13um CMOS” published in IEEE Journal of Solid-State Circuits volume 42 Number 4 April 2007 P.881 “A 5mW 6Gbp / s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions” published in IEEE Journal of Solid-State Circuits volume 42 Number 4 April 2007 JP-A-7-297678

  However, in any of the non-patent documents 2 to 6, an extra circuit must be added to the transmission circuit and the reception circuit, respectively, due to the configuration of the technology employed by them. There was a growing problem.

  In addition, the reflection coefficient of the signal does not become zero due to manufacturing variations of device elements themselves placed near the receiving circuit of the transmission line, changes in device temperature, fluctuations in applied voltage value, and the like. In order to solve this problem, conventionally, as shown in Patent Document 1, there is a method of realizing an impedance value in which a signal waveform is difficult to be reflected in the vicinity of the receiving end with a MOS resistance element (hereinafter referred to as a terminating resistor).

  In this method, the value of the termination resistor can be adjusted by CMOS circuit technology. Specifically, the same amount of current is passed through the reference resistance value and the replica CMOS termination resistance value, and the voltage values obtained by integrating the resistance value and the current value are compared, and the reference resistance value and the replica CMOS termination value are compared. The feedback system is configured to adjust the gate voltage value of the replica CMOS so that the resistance value becomes the same. In this method, the gate voltage value of the replica CMOS is also applied to the gate of the CMOS termination resistor circuit, and the termination resistor is finally set to have the same value as the reference resistor.

  However, in the method of Patent Document 1, the reference resistor must be placed outside the semiconductor integrated circuit. This is because if the reference resistance is built in the semiconductor integrated circuit, the termination resistance varies due to process variations and temperature variations, and impedance matching cannot be adjusted accurately. Therefore, the voltage waveform of the signal in the vicinity of the receiving circuit has a problem that the phase is disturbed and uncertain data reception occurs.

  In order to solve the above problems, an electronic device according to the present invention includes at least one transmission means, at least one reception means, at least two conductors, and surrounding the conductors. A plurality of resistive elements connected in parallel between the dielectric and at least one first conductor of the conductors and at least one second conductor excluding the first conductor The first conductor transmits a signal, and the length of the line of the first conductor is the reciprocal of the signal transfer rate of the first conductor and the dielectric. The resistive element has a length that is at least half of the product of the speed of light traveling, and the resistance element is half of the product of the signal transfer rate of the first conductor and the speed of light traveling through the dielectric. At least one or more are arranged on the line of the first conductor for each distance.

  Thereby, in this invention, the signal distortion which transmits a transmission line decreases, and it can transmit at higher speed.

  Preferably, there is an aspect in which the potential of the second conductor is forcibly fixed from the outside. Thereby, the radiation direction of the electromagnetic wave along the first conductor is concentrated, and the signal can be propagated at a higher speed.

  Preferably, the forced potential of the second conductor may be maintained at the same potential during the signal transmission operation. Thereby, the impedance of the first conductor becomes a function of the frequency component of the transmitted signal, signal distortion is reduced, and transmission can be performed at higher speed.

  Preferably, there is an aspect in which the second conductor transmits a signal complementary to the signal of the first conductor. Thereby, it becomes strong with respect to the common mode noise from another conductor.

  Preferably, the line of the first conductor has a branched structure, and the resistive element is arranged at a branching location. As a result, the straightness of propagation of the electromagnetic wave from the branch point to each branched transmission line is improved, and the high speed of signal transmission can be maintained.

  Preferably, there is an aspect in which the transmission circuit or the reception circuit is provided in the line of the first conductor. Thereby, since it is not necessary to prepare a plurality of transmission lines, the area can be reduced.

  Preferably, there is an aspect in which the resistance element is included in the reception circuit or the transmission circuit. As a result, it is not necessary to separately arrange the transmission / reception circuit and the resistance element, so that the layout overhead can be reduced and the area can be reduced.

  Preferably, there is an aspect in which information on a reception position is transmitted from the transmission circuit. As a result, it can be determined whether or not the receiving circuit receives a signal. When the signal is not received, the receiving circuit is stopped so that the output signal of the receiving circuit is not propagated.

  Preferably, there is an aspect in which transmission position information is transmitted from the transmission circuit to the reception circuit. Since the voltage amplitude value of the signal reaching the receiving circuit is known in advance, the sensitivity of the receiving circuit can be adjusted.

  Preferably, there is an aspect in which the reception circuit adjusts reception sensitivity according to information on a position of the transmission circuit. Thereby, the sensitivity of the receiving circuit can be adjusted, and the reliability of signal transmission is improved.

  Preferably, there is an aspect in which a minimum signal transfer rate of the conductor is zero. This eliminates the need for a circuit that modulates a signal transmitted from the transmission circuit, thereby realizing a reduction in area.

  Preferably, the electronic device further includes integration means for integrating the resistance value of the first conductor and the resistance value of the resistance element, and comparison means for comparing the integrated value obtained by the integration means with a certain reference value. There is a mode in which the resistance value of the resistance element is adjusted so that the integrated value and the reference value are the same. Thereby, the amplitude variation width of the eye of the transmission line can transmit an undistorted signal that does not depend on temperature.

  Preferably, there is an aspect in which the reference value is an inductance value per unit capacity of the first conductor. As a result, the amplitude variation width of the eye of the transmission line can transmit an undistorted signal that does not depend on the shape variation of the wiring after the process manufacture.

  Preferably, there is an aspect in which the reference value is variable in accordance with a conductor and a shape of an interlayer film surrounding the conductor. Thereby, the amplitude fluctuation width of the eye of the transmission line can transmit an undistorted signal that does not depend on the shape of the wiring after the process manufacture.

  Preferably, the reference value has an aspect in which the integrating means is a multiplier.

  Preferably, there is an aspect in which a product of a resistance value of the resistance element and a current value of a constant current source is input.

  Preferably, the multiplier has an aspect in which a product of a resistance value of a conductor imitating the conductor and a current value of a constant current source is input.

  Preferably, the first conductor is a transmission signal line in a semiconductor integrated circuit.

  Preferably, the semiconductor integrated circuit further includes a power switch having a function of whether or not to supply power to the FET in the semiconductor integrated circuit from the outside, and the power switch is connected to a power line from an external power source. There is a mode in which the second conductor connected to the first conductor in the circuit through a resistor is the power supply line. Thereby, the radiation direction of the electromagnetic wave along the first conductor is concentrated, and the signal can be propagated at a higher speed.

  Preferably, there is a mode in which the first conductor is connected to a different processing unit.

  Preferably, there is an aspect in which the first conductor is connected to a plurality of the same processing units.

  Preferably, there is an aspect in which the first conductor is connected to a plurality of processing elements constituting the reconfigurable core.

  Preferably, there is an aspect in which the signal of the first conductor is transmitted from the transmission circuit via a circuit that receives electromagnetic waves.

  Preferably, the first conductor is covered with a silicon compound, and the resistive element has an aspect in which the silicon compound is polycrystalline.

  Preferably, the connection between the conductor and the transmission signal line of the semiconductor integrated circuit is through a conductor having a cross-sectional area larger than that of the conductor.

  Preferably, the resistive element is configured by at least one or more FETs, the source and the drain of which are connected to another conductor, and the gate is applied with a voltage from another conductor. .

  Preferably, the voltage range of the signal line connected to the gate may be a voltage range in which the source / drain current of the FET exhibits a linear region when the first conductor transmits a signal.

  Preferably, the voltage range of the signal line connected to the gate may be a voltage range in which the source / drain current of the FET indicates a cutoff region when the first conductor does not transmit a signal.

  Preferably, the voltage value of the substrate of the FET is variable independently of its source voltage, drain voltage, and gate voltage.

  Preferably, there is an aspect in which a cross-sectional portion of the conductor to which the first conductor and the resistance element are connected is not less than an interval at which another conductor is inserted.

  Preferably, at least one of the conductors connected to the first conductor and the resistance element is wired in parallel with the first conductor.

  Preferably, there is an aspect in which the second conductor is located between a semiconductor constituting the substrate and the first conductor.

  Preferably, the second conductor is composed of a plurality of wiring layers, and the third lowermost layer and the third lowermost layer overlap each other.

  Preferably, there are a communication device including a semiconductor integrated circuit including the electronic device, an information reproducing device, an image display device, an electronic control device, and a moving body including the electronic control device.

  As described above, according to the electronic device of the present invention, when a signal is propagated using a conductor line, the voltage waveform of the signal can be propagated to the receiving end without distortion. In addition, the area can be reduced and the power consumption can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
This embodiment will be described using a transmission line 1A1 including a conductor 1A as shown in FIG.

Here, the conductor 1A is defined as a substance having an electrical resistivity [ohm · m] of 10 ⁻⁵ or less. Further, the conductor 1A is used for a signal line for transmitting information. The transmission line 1A1 is defined as a mechanism of the present embodiment for propagating electromagnetic waves along the transmission line 1A1. An unsigned transmission line is a broad transmission line and does not refer only to the mechanism of the transmission line 1A1 of this embodiment. A track is synonymous with wiring. The conductor 1A is surrounded by a dielectric material. Here, the expression “surrounded” means that it is roughly surrounded, and not all of it is surrounded by a dielectric material. This is because air or the like may exist in a minute amount between the dielectric materials depending on the process of manufacturing this mechanism. In FIG. 1, z is the distance [m] from the left starting point of the line of the conductor 1A, t is the time [s], and R is the resistance value per unit length of the line of the conductor 1A [ohm / m. ], G is a conductance value [S / m] per unit length of the line of the conductor 1A, C is a capacitance [F / m] per unit length of the line of the conductor 1A, and L is a value of the conductor 1A. An inductance value [H / m] per unit length of the line. The line length of the conductor 1A is zo [m].

When considering an equivalent circuit of the transmission line 1A1, the voltage V (z, t) and the current I (z, t) at the point z are

となる。

Equation (1) is

It becomes.

となる。 Equation (3) is

It becomes.

From the equations (2) and (4), the telegraph equations as shown in the following equations (5) and (6) are expressed.

ｖは、信号の伝播速度である。 When a sine wave is considered as the transmission signal, the voltage amplitude V (z) at a certain distance z in the line of the conductor 1A on the S plane (Laplace transform) is obtained by solving the equations (5) and (6): It can be expressed by equation (7), and γ is called a propagation constant, a real part α of γ is called an attenuation constant, and an imaginary part β is called a phase constant.

v is the propagation speed of the signal.

In the equation (7), the condition for signal propagation without distortion is that the phase constant α does not depend on the frequency, and the phase difference β must be proportional to the operating frequency of the signal. If these two conditions are put in another expression, the characteristic impedance of the conductor line must be a positive real number. In order for the impedance to be a positive real number, the phase angles must be equal.

の時、

ここで、ｃ_ｏは、光の真空中の速度であり、

である。 That means

time,

Where c _o is the speed of light in vacuum,

It is.

  Further, ω is an angular frequency ω (2πf: f is a signal frequency [Hz]), and εr is a dielectric constant of a dielectric surrounding the transmission line.

  The condition for signal propagation without distortion (no distortion condition) has been mathematically proven by 1888 Heavy Side.

  In the present embodiment, under the condition using the telegraph equation (when the signal wavelength to be transmitted is close to the length of the conductor line, it is treated as a distributed constant), the above (within the range of the line length of the conductor 1A ( 10) The resistance element Rg having a resistance value that is the reciprocal of the conductance value that can be realized by the equation is composed of a conductor (first conductor) 1A and a return path conductor 1B (second conductor) (conductor 1B Then, it is an ideal plane for the conductor 1 A. When a conductor material substantially the same as the conductor 1 A is used for the conductor 1 B and a signal having a phase opposite to that of the signal is transmitted to the line of the conductor 1 B, It is a differential transmission system, and impedance is defined as 2Zo). Since the electric potential of the conductor 1B is fixed from the outside, the radiation direction of the electromagnetic wave has a straight traveling property, and a signal is propagated at a higher speed. Further, by making the potential of the conductor 1B out of phase with the transmission signal, it becomes strong against common mode noise from other conductors. The arrangement interval of the resistance elements Rg is determined as follows according to the line length of the conductor and the maximum operating frequency of the transmission signal.

Here, the operating frequency f [Hz] of the transmission signal has the following relationship with the data transfer rate d [bps / wire] of one [wire] transmission signal.

で表される。 If the operating frequency of the transmission signal is f [Hz], the wavelength of the signal transmitted through the transmission line 1A1 is

It is represented by

μｒは透磁率である。 here,

μr is the magnetic permeability.

  Since the signal resonates when the conductor line length is λ / 4, in order to eliminate the influence of the radiation source of electromagnetic noise (no problem if the transmission power is small), this resistance element Rg is applied to the transmission line. Must be placed at intervals of 4 or less. Of course, the narrower the interval between the inserted resistance elements Rg, the more ideal undistorted signal voltage waveform can be generated.

That is, the insertion number N of the resistance element Rg can be expressed by the following equation.

The value of each resistance element Rg can be expressed by the following equation.

  For example, when the dielectric constant εr = 4 and μr = 1, the interval between the resistance elements Rg arranged on the transmission line 1A1 should be 3.75 [mm] or less when the maximum frequency of the transmission signal is 10 [GHz]. It is. If silicon Si is used for the substrate, the resistance element Rg can be reduced in area by using a MOSFET having a higher resistivity than the conductor, polysilicon, or a diffusion layer region. By using an element made of a substance having a higher resistivity than the conductor or an organic FET, it can be realized in a small area. That is, the transmission line 1A1 in which the resistance element Rg of this embodiment is arranged so as to satisfy the expressions (18) and (19) can reduce the distortion of the signal waveform of the transmission line 1A1. The present embodiment is the first proposal for disposing resistive elements for each distance on the transmission line. This is because the conventional loading transmission line is assumed to be a cable such as a thick copper wire, and the resistance of the copper wire is very small per unit length, so it is impossible to insert a resistance element. Because. Hereinafter, the reason why there is no transmission line system that satisfies the equations (18) and (19) for the resistance element will be described with reference to historical points and specific examples.

  In the past, there is a fact that some element is arranged at each point of the transmission line, and this is called a caulking cable. 1894 M.C. A configuration has been proposed in which an inductance is inserted at a certain distance by a pure pin to reduce the attenuation constant. However, this is not effective for a signal waveform of several hundred kHz or more because noise is generated. Since then, Matsumae et al. Have proposed a no-brain cable, and a coaxial cable has also been proposed. At present, coaxial cables are used for most transmission lines, and transmission lines having the same structure are used for boards and the like in order to achieve impedance matching with the coaxial cable.

である。 Consider whether the transmission line 1A1 of the present embodiment can be realized with a copper wire of a coaxial cable. Assuming that the impedance Z of the coaxial cable is 50 [ohm] and the resistance is R = 0.1 [ohm / m], and the length is 1 [m], the reciprocal of the conductance is

It is.

If a resistance element Rg having a reciprocal of conductance is inserted in units of 2.5 [mm], one resistance value is obtained from the equations (18) and (19):

  That is, the resistance value that is the reciprocal of the inductance value becomes very large.

  The conductance value including the dielectric loss of the dielectric surrounding the conductor is 0.18 [S / m] @ 10 GHz or less for the board FR4 substrate, and 0.1 [S / m] @ for the semiconductor such as SiO 2. 10 GHz or less. Therefore, even with a dielectric loss alone, with a wiring length of 2.5 [mm], 1 / G = 2222 [ohm] to 4000 [ohm], and a more insulative resistance of 10000000 [ohm] cannot be inserted. This is because it has been impossible to realize because of a large amount of leakage current.

である。転送信号の最大周波数を５［ＧＨｚ］とし、２．５ｍｍ間隔で抵抗素子Ｒｇを配置すると、抵抗素子Ｒｇ１箇所当たりの抵抗値は、

となる。 On the other hand, this configuration considers a transmission line that transmits a transmission signal to a very thin conductor line. The wiring resistance between the coaxial cable and the integrated circuit device differs by about 100 times or more per unit length. For example, when the resistance of the conductor 1A is 50 ohms with a length of 10 mm, the resistance value of the resistance element Rg inserted into the transmission line 1A1 is

It is. When the maximum frequency of the transfer signal is 5 [GHz] and the resistance elements Rg are arranged at intervals of 2.5 mm, the resistance value per one position of the resistance element Rg is:

It becomes.

  This resistance value is a range of applicable resistance values even if the leakage current of the dielectric loss described above is taken into consideration. Therefore, the resistance element Rg has a relatively reasonable value, and can be realized.

が１：１００位の場合は、減衰定数と位相差定数は、先の電信方程式（５）、（６）から近似を行い、減衰定数αと位相差定数βは、下記の式で表せる。
ωＬ＞＞Ｒ、Ｇ≒０より、

Next, the effect of the configuration of the present transmission line being able to transmit without distortion in a wide frequency band of the transmission signal will be described in comparison with the prior art. Conventionally, a ratio of a resistance value R [ohm / m] per unit length of a conductor line and an inductance value L [H / m] multiplied by an angular frequency ω.

Is approximately 1: 100, the attenuation constant and the phase difference constant are approximated from the previous telegraph equations (5) and (6), and the attenuation constant α and the phase difference constant β can be expressed by the following equations.
From ωL >> R, G≈0,

と表され、終端抵抗は、（２７）式の値をとることにより、反射係数は０とできる。 In the method using the conventional termination resistor, the impedance Z of the conductor is in a frequency band where the resistance of the conductor is negligible.

The termination coefficient can take a reflection coefficient of 0 by taking the value of equation (27).

In the frequency band of the transmission signal as described above, there is no problem in generating and receiving a more reliable waveform, but the transmission signal in which the ratio of the expression (24) is in the range of about 1: 0.01 to 1:10. In the frequency band, the approximation is performed from the previous telegraph equations (5) and (6), and the attenuation constant α and the phase constant β can be expressed by the following equations.
From ωL << R, G ≒ 0,

  When a conventional termination resistor is used and the resistance value of the termination resistor is set to the same value as the impedance Z (Equation (27)) of the conductor, the attenuation constant changes due to the fluctuation of the angular frequency, and the waveform near the receiving circuit is disturbed. In order to solve this problem, conventionally, a pre-emphasis technique, an equalizer technique, and the like must be added to the transmission circuit and the reception circuit, respectively, which increases the area and power of each circuit.

  On the other hand, in the transmission line 1A1 of this embodiment, as can be seen from the equations (11), (12), and (13), the attenuation constant, the phase constant, and the characteristic impedance do not change regardless of the frequency band of the transmission signal. FIG. 34 shows graphs when the present loading type is applied and when it is not applied. The horizontal axis represents frequency, and the vertical axis represents characteristic impedance. As can be seen from FIG. 34, when this embodiment is applied, the characteristic impedance does not depend on the frequency. Therefore, there is an advantage that a complicated pre-emphasis technique, an RZ technique, and an equalizer technique need not be installed in the conventional transmission circuit, and the area and power of the transmission circuit and the reception circuit can be greatly reduced.

  In the above description, the resistance element Rg is formulated by fixing one on the return path for the sake of simplicity. However, the resistance element Rg does not necessarily have to be connected to the return path, and the voltage is fixed externally. Even if it is connected to the other conductor, substantially the same effect can be exhibited.

  FIG. 5 shows a circuit diagram using a CMOS transistor having a gate length of 45 nm as the resistance element Rg, the transmission circuit, and the reception circuit satisfying the expressions (17) and (18).

  The transmission circuit (transmission means) is Tx5A, and a signal to be transmitted is input to the gate of the NMOS transistor Tx5AN1, and the drain of the NMOS transistor Tx5AN1 is connected to the conductor 1A of the transmission line 1A1. The gate length of the MOS transistor is 45 nm, and the gate width is 39 times 0.51 μm.

  The receiving circuit (receiving means) is Rx5B, the conductor 1A of the transmission line 1A1 is connected to the gate of the NMOS transistor Rx5BN1, and the drain of the NMOS transistor Rx5BN1 is connected to the input terminal of the inverter Rx5BINV1 and the drain of the PMOS transistor Rx5BP2. Has been. The source of the PMOS transistor Rx5BP2 is connected to the drain of the PMOS transistor Rx5BP1, and the gates of the PMOS transistors Rx5BP2 and Rx5BP1 are grounded via the node Rx5BPG. The gate length of the NMOS transistor Rx5BN1 is 45 nm, and the gate width is four times 0.4 μm. The gate length of the PMOS transistors Rx5BP2 and Rx5BP1 is 45 nm, and the gate width is 12 times 0.92 μm. The size of the inverter Rx5BINV1 is such that the gate width of both MOS transistors is 45 nm, the gate width of the PMOS transistor is 0.92 μm, and the gate width of the NMOS transistor is 0.4 μm.

  The resistance element is Rg5C, the gate of the PMOS transistor Rg5CP1 is grounded, the drain is connected to the conductor 1A of the transmission line 1A1, and the resistance is determined by the relationship between Vds and Ids at a constant voltage Vgs, Operates in the linear region. The gate length of the PMOS transistor Rg5CP1 is 45 nm and the gate width is 16 times 0.92 μm.

The transistor pitch is 0.18 μm, the upper limit of the vertical length parallel to the gate width of the PMOS region is 1 μm, the upper limit of the vertical length parallel to the gate width of the NMOS region is 0.6 μm, When the layout cell is created, the horizontal length of the receiving circuit Rx5B is 0.18 μm × (39 + 2), and the area of the transmitting circuit Tx5A is
0.18 μm × (39 + 2) × 0.6 μm = 4.4 [μm ² ] −− (25)
It is.

In the same way, the area of the receiving circuit Rx5B is
0.18 μm × (24 + 1 + 2) × 1.0 μm
+0.18 μm × (4 + 1 + 2) × 0.6 μm
= 5.6 [μm ² ]-(26)
It is. The transmission circuit, the reception circuit, and the resistance circuit each occupy one MOS area, and by combining them, there is no need to separately arrange the transmission / reception circuit and the resistance element, thus reducing the layout overhead. Therefore, the area can be reduced.

  The quantitative values of these effects can be easily understood by quoting past papers on the area of the pre-emphasis circuit and the area of the equalizer and comparing them with simple inverters and simple circuits operating on one channel. For example, in a conventional paper, as a transmission circuit with a pre-emphasis function, Non-Patent Document 3 (IEEE Journal of Solid-State Circuits, volume 41, Number 1, JANUARY 2006, P.297 “A 3-Gb / s / ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects "Fig. 9 and Fig. 11).

  Non-Patent Document 4 (P. 772 “Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip published by IEEE Journal of Solid-State Circuits volume 41, Number 4, APRIL 2006) Fig. 10) of "Communication".

  Non-Patent Document 5 (P.872 “A Fully Integrated 10 Gbp / s Receiver with Adaptive Optical Dispersion Equalizer in 0.13um CMOS, published in IEEE Journal of Solid-State Circuits volume 42 Number 4 April 2007) Fig. 13 Equalizer and Non-Patent Document 6 (P.881 “A 5mW 6Gbp / s Quarter-Rate Sampling Receiver with a 2-Tap DFE published in IEEE Journal of Solid-State Circuits volume 42 Number 4 April 2007 Refer to “Using Soft Decisions”, FIG. 16, 2-Tap DFE).

  The advantage of this distortion-free transmission line is that a transmission / reception circuit can be placed at any point on the conductor line, and a plurality of reception circuits can receive an appropriate distortion-free waveform at any point. Can also be applied.

  FIG. 2A shows an embodiment of the arrangement of the transmission line 1A1, the transmission / reception circuit, and the resistance element of the present embodiment in the integrated circuit device. 2A is an integrated circuit device. The wiring length of the conductor 1A of the transmission line 1A1 is 10 mm, and L / C = 2500. The conductor 1B has a plain structure.

TRxN (N = 1 to 6) includes a transmission circuit, a reception circuit, and a resistance element Rg (Rg = 375 ohm) inserted between the conductor 1A and the conductor 1B. 2 (b) is ^{2 11-1} PRBS from TRX0 (Pseudorandom Binary (Bit) Sequence : pseudo random number bit string) case of transmitting, FIG. 2 (c), ^{2 11-1} PRBS from TRX3 signal pattern 2 shows the eye pattern of the signal waveform of each receiving end (each node in0, out1, out2, out3, out4, out5, out6 of the transmission line 1A1 in FIG. 2A) for which a transient analysis was simulated. . It can be seen that an effective eye pattern can be secured without distortion at any receiving end. As a result, it is not necessary to prepare a plurality of transmission lines in which the transmission circuit and the reception circuit have a one-to-one configuration, so that the area can be reduced. In FIG. 2D, the termination resistance (50Ω) is inserted between the node in0 and the conductor 1B and between the node out6 and the conductor 1B in FIG. An eye pattern is shown. As can be seen from FIG. 2D, it can be seen that the rise of the signal waveform is steeper than the eye pattern of FIG. Thus, by inserting termination resistors having the same degree as the characteristic impedance of the conductor 1A at both ends of the conductor 1A and the conductor 1B, reflection of the signal waveform at both ends can be suppressed. Therefore, since interference between the traveling wave and the reflected wave does not occur, the rising of the waveform can be made steeper, and higher speed transmission can be realized.

  FIG. 3A is an example in which the transmission line 1A1 method of the present embodiment is applied to the entire electronic device. 3A is the entire electronic device. Reference numeral 3B denotes an integrated circuit (IC chip). The integrated circuit 3B1 is composed of a heterogeneous multiprocessor (cores 3C1, 3C2, 3C3). 3B2 is also composed of heterogeneous multiprocessors (cores 3C4 and 3C5). In particular, 3C5 is a reconfigurable core and is composed of PE (processing elements) 3C5A to 3C5D equipped with the same logic circuit. Reference numerals 3B3 to 3B9 denote memory ICs each including a transmission / reception circuit 3D, a resistance element 3E, and a memory. 3B1A and 3B2A are interfaces between the memories 3B3 to 3B9 and the multiprocessors 3B1 and 3B2, and are cores called memory control units. FIG. 3B shows an example of the interface functions of the memory control units 3B1A and 3B2A. In the figure, data and commands (address, enable signal, etc.) are exchanged via the memories 3B3 to 3B9 and the physical layer interface 3B1A1. Between the physical layer interface 3B1A1 and the internal buses of the multiprocessors 3B1, 3B2, as indicated by arrows in FIG. 3B, a transaction processing unit, a command queue unit, a port arbitration unit, a write queue unit, and a read The order of data reception and data transmission from the external memory is controlled in consideration of power consumption and transfer efficiency via a queue unit or the like. The conductors 1A and 1B are connected to the transmission / reception circuit 3D for interfacing with the integrated circuits and the logic circuit in the core in the integrated circuit, respectively. The resistance element 3E is connected between the conductors 1A and 1B. It is connected. The radio signal via the antenna is transmitted / received by the transmission / reception circuit 3D1. The memory ICs 3B3 to 3B9 are not particularly specified in which position on the transmission line, and when there is no transmission / reception circuit having a resistance element within λ / 4, the memory ICs 3B3 to 3B9 are like transmission lines connecting the integrated circuits 3B1 and 3B2. In addition, the resistive elements 3E are respectively disposed within λ / 4. Further, when the dielectric constants of the dielectric materials surrounding the transmission line are different between the integrated circuits and in the integrated circuits, the resistive element 3E is disposed within λ / 4 according to the dielectric constant. By adopting such a configuration, conventionally, an integrated circuit (IC chip) has conventionally had an I / O circuit (including PAD (including area PAD)), an ESD protection, a drive circuit, etc. that interface the outside and inside of the integrated circuit. However, there is an advantage that a transmission line that controls the internal and external interfaces of the integrated circuit can be directly connected. This eliminates the need for an I / O circuit and allows not only high-speed transmission, but also reduction of the area of the entire electronic device and integrated circuit, and consequently reduction of parasitic capacitance, thereby reducing power consumption. Memory cores in the integrated circuit can be reduced by high-speed transmission. Therefore, it is possible to reduce power consumption including useless leakage current of a core such as a memory having a low activation rate. In addition, it is desirable to arrange | position a resistive element in the location branched into two from the track | line of one conductor. This improves the straightness of propagation of the electromagnetic wave from the branch point to each branched line, and can maintain the high speed of signal transmission.

  Although the conductor 1A has been described with respect to data and commands centering on the wiring connection, it is advantageous to take the same configuration as the clocks of the processors 3B1 and 3B2. For example, when switching the clock frequency to improve the efficiency of the applications of the processors 3B1 and 3B2, if the configuration of this embodiment is used, there is no inter-symbol interference, so that an effective clock is propagated from the next cycle after frequency switching. It becomes possible to do.

  The transmission line system of the present embodiment is not limited to the electronic device shown in FIG. 3A, but also a sensor such as an image sensor, a display system device such as a PDP, a liquid crystal or an organic EL, an FPGA, and the like. The present invention can also be applied to an internal interface of an integrated circuit and an interface between integrated circuits.

  FIG. 4 shows a cross-sectional view of the electronic device 3A. Integrated circuits 3B1 and 3B3 to 3B9 are arranged above and below the dielectric film 1, and the transmission line 1A1 in the dielectric film 1 and the transmission lines 1A1 of the integrated circuits 3B1, 3B3 to 3B9 are connected via a PAD. Similarly, integrated circuits 3B3 to 3B9 and 3B2 are disposed above and below the dielectric film 2, and the transmission line 1A1 in the dielectric film 2 and the transmission line 1A1 of the integrated circuits 3B2 to 3B9 are connected via a PAD. .

  It is desirable that this PAD is equal to or thicker than the wiring width of the conductor of the transmission line 1A1 in view of improving the manufacturing yield. This is because the probability of occurrence of cracks in the conductor and dielectric materials can be reduced by positioning between chips.

  FIG. 9 shows a physical arrangement of the transmission / reception circuit of the core 31B1 in the integrated circuit 3B1 as viewed from above. The resistance element Rg constituting the transmission line 1A1 and the power cutoff switch cell 9A in the core 31B1. Whether or not the power cut-off switch cell 9A cuts off the power supply line (here, LVDD) made of the conductor used in the core 31B1 from the power supply line GVDD made of the conductor laid in the integrated circuit 3B1. It is a switch that controls. In some power cutoff switch cells 9A, a diode is inserted in parallel with the switch in order to fix the potential of the power supply line LVDD and hold the data information inside the core 31B1. The power cut-off switch cell 9A is composed of a MOS transistor to stabilize the power supply voltage value of the power supply line LVDD inside the core 31B1 when conducting, and the gate of the MOS transistor monitors the voltage of the power supply line LVDD. Some are also connected to a signal from a signal processing circuit having a function of stabilizing the voltage. Since it is necessary to always connect the resistance element Rg connected to the conductor 1A to the power supply line whose potential is fixed from the outside, the resistance element Rg is not connected to the power supply line LVDD in the core 31B1, but to the power supply line GVDD. Connecting.

  The power supply lines GVDD and LVDD may be longitudinal lines in the drawing. Also, the conductor 1A layer and the GVDD and LVDD conductor layers may be the same layer or different.

  By adopting such a configuration, in this embodiment, the potential of the resistance element Rg is fixed even when the core 31B1 is in the cut-off state. Therefore, the attenuation constant of the transmission line including the conductor 1A and the resistance element Rg α is a function of the frequency component of the transmitted signal, signal distortion is reduced, and stable transmission at higher speed is possible.

  FIG. 10 is a cross section of the transmission line 1A1 in the integrated circuit 3B1. The transmission line 1A1 is composed of polysilicon that forms the resistance element Rg through the conductor N + 1 from the conductor N + 1 having a different layer through the conductor N and again through the conductor N + 1. It is connected. In this way, by changing the transmission line 1A1 from a conductor in a certain layer to a conductor in a lower lower layer and returning to the conductor in a certain layer, the surface area of the conductor in any layer of the transmission line 1A1 Even if the value is large, it is possible to reduce the probability of device breakdown when performing CMP or the like in manufacturing. Compared to the conventional termination resistor alone, the resistance insertion interval is close, so that the charge of the conductor 1A is easily distributed to other conductors and the substrate, and the device breakdown occurrence probability is greatly improved.

  FIG. 11A shows a physical arrangement when the transmission line 1A1 in the integrated circuit 3B1 is viewed from above (on the opposite side to the back surface of the substrate on which the integrated circuit 3B1 is formed). There are conductors named GND on both sides of the conductor 1A. Furthermore, there are conductors VDD-B and VDD-A outside the conductor GND. In this example, since these conductors use metal, they may be called metal in the same meaning as the conductor. Further, in a layer below the conductor 1A of the transmission line 1A1, there are a conductor called a lower layer N metal and a conductor called a lower layer N-1 metal. Although the conductor layers of the lower layer N metal and the lower layer N-1 metal are different, the structure is such that the lower silicon substrate cannot be seen when viewed from above. In other words, when projected onto a plane, they overlap or are flush. VDD-B and VDD-A are conductors whose potentials are intentionally controlled, and GND is fixed at the potential from the outside when the integrated circuit 3B1 is operated. By adopting such a configuration, the main return path of the transmission line 1A1 is a GND lower layer N metal and a lower layer N-1 metal, and a substance that is intermediate between a conductor or a dielectric depending on the frequency such as silicon. By not using the return path, the transmission signal can always be transmitted stably via the transmission line 1A.

  In addition, there is a long conductor in the lateral direction between the conductor 1A of the transmission line 1A1 and the conductors of the lower layer N metal and the lower layer N-1 metal. Transmission of electromagnetic waves is effective and stable transmission is possible.

  FIG. 11B shows the arrangement of the conductor 1A and the conductor 1B in the case where the power layer of the core 3B15 has a physical shape separated from other cores for the purpose of power cutoff control, power supply voltage variable control, and the like. . Regarding the case where the conductor 1A is wired across the different power sources (separated structures), the conductor 1B may be separated in the case of a single-ended transmission system. It is desirable to insert a stitching capacitor 1ab between the separated conductors 1B. Due to the stitching capacity, electrons flowing in the conductor 1B serving as a return path of the conductor 1A flow through the stitching capacity without passing through a large loop. That is, since the impedance of the conductor 1B can be formed low, the distortion component of the characteristic impedance of the conductor 1A is reduced, and the signal can be transmitted at higher speed.

  FIG. 16 is a cross section of the transmission line 1A1 in the integrated circuit 3B1. From the bottom, there are a substrate, a plurality of conductor N-1 layers, a conductor N layer, and a conductor N + 1 layer, and on the right side of the conductor 1A among the conductor N + 1 layers, VDD1, VDD2, VDD3, and VDD4 in the same layer. Each track is lined up in parallel. The conductor N layer does not exist between the VDD 9 of the conductor N-1 layer and the conductor 1A. In the conductor N layer, VDD5, VDD6, VDD7, and VDD8 lines are arranged in parallel. The numerical value described below the conductor N-1 layer is the distance from the center of the conductor 1A, and its unit is μm. Although omitted on the left side of the conductor 1A, the conductors are lined up symmetrically about the right side and the conductor 1A. In this way, by separating the wiring distance adjacent to the conductor 1A and eliminating the conductor layer for the upper and lower layers, a conductor 1A line having a large inductance value can be formed, and the attenuation constant α is reduced. It becomes possible to receive with a more stable waveform.

  The transmission / reception circuit unit connected via the conductor 1A of the transmission line 1A1 such as the integrated circuit 3B1 shown in FIG. 3A will be described. Transmission / reception is transmitted from the core 3C1 and received by the core 3C3, transmitted from the core 3C1 and received by the core 3C2, transmitted from the core 3C3, simultaneously received by the cores 3C0, 3C1 and 3C2, and simultaneously transmitted from the cores 3C1 and 3C3. Many-to-many communication such as reception can be performed by the core 3C2. In addition, information on where to receive from the transmission side and information on the location on the transmission side are sent in advance before transmitting actual data to the transmission line 1A1. The sending means may be transmitted via the transmission line 1A1, or may be transmitted by another signal line. Based on the information and the distance of the transmission line 1A1 between receptions prepared in advance on the receiving side and the attenuation constant, the voltage amplitude information at the receiving end is collated with a reference table or the like, and the gate voltage of the node Rx5BPG shown in FIG. 5 is adjusted. In addition, it is possible to adjust the gain of the receiving circuit so as to obtain the transmission signal information more reliably.

  Further, when a request is made from the transmission side to the reception circuit, the gate voltage of the node Rx5BPG is set to the same value as the source voltage of the PMOS transistor Rx5BP2, so that no data is propagated from the reception circuit into each core. Power consumption can be realized.

  In addition, when there is no signal propagation, the resistance element Rg composed of a MOS transistor or the like can cut off the current path of the transmission line 1A1 and reduce power by fixing the gate voltage and turning it off. It is.

  Another method is to prepare a high-speed AD converter near the receiving end, monitor the amplitude voltage value of the signal propagating through the transmission line 1A1, and adjust the sensitivity of the receiving circuit according to the voltage value. In this case, there is no need for information on from which transmission point the signal is transmitted from the transmission side, and the latency can be reduced.

  Incidentally, when data is received from a plurality of transmission circuits via a plurality of lines, malfunction of data reception can be further reduced by using the source synchronous technology. The source synchronous technique is a technique for transmitting data and a strobe signal from a transmission side to a reception side. If there is a margin in the transmission rate, sending a strobe signal at a transfer rate twice that of the data transfer rate will not interfere with the timing of taking the output data of the receiving circuit with a flip-flop (hereinafter referred to as FF). Usually, in order to make full use of the performance of the transmission line, the data transfer rate is the highest transfer rate that can be guaranteed. Therefore, the strobe signal transfer rate cannot be twice the maximum data transfer rate, and is equal to the maximum data transfer rate. Therefore, in order to take the output data of the receiving circuit with the FF, the clock frequency of the FF needs to be twice the transfer rate of the strobe signal. To generate a double clock frequency, a strobe signal is input to the reception circuit Rx5B, and a signal is input from the output out of the reception circuit Rx5B to the Delay locked loop (DLL) circuit 12A as shown in FIG. Signals having different phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees are output from the delay elements of the DLL circuit 12A. By inputting the four 90 ° phase-shifted signals to each input terminal of the double frequency generation circuit 13A as shown in FIG. 13A, the output becomes a double frequency.

  FIG. 13B shows a simulation waveform of the double frequency generation circuit 13A. It can be seen that the output signal has a frequency twice that of the input signal. As the output OUT of the receiving circuit Rx5B, the receiving circuit Rx5B as shown in FIG. 5 is used, and the output signal OUT is received again by a device as shown below, so that high speed and area efficiency can be improved. An FF with a multi-input selector function described in a patent document (International Publication No. 2007/046368 pamphlet) is used as the basic FF in this proposal.

  Next, the case where the strobe signal is differential will be described. FIG. 23 shows a differential frequency divider 23. A differential pair of strobe signals is input to the terminal names ck and ckb described in the differential frequency divider 23, respectively, and signals having phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees are generated. The counter output signal of FIG. 14 is generated using these signal lines. For example, when accuracy is not achieved such as when the flip-flop 26I31 causes metastable or the like, the phase adjustment circuit 24 as shown in FIG. For example, by inputting the 0 degree and 90 degree clocks of the output signal of the differential frequency dividing circuit 23 in FIG. 23, half the phase, that is, 45 degree clock output is possible. When the phase (45 degrees) is generated, a circuit delay occurs. Therefore, the output signal of the reference phase (0 degrees) is input with a 0 degree clock at both inputs in FIG. This is possible by outputting the following clock. By connecting a circuit as shown in FIG. 24 to the output of the differential frequency divider 23, the phase difference of the counter output of FIG. 14 is set to 0 degree, 90 degrees, 180 degrees, 270 degrees, and 45 degrees. , 135 degrees, 225 degrees, and 315 degrees. Which set is used may be switched according to power supply voltage fluctuations and temperature fluctuations of the semiconductor integrated circuit. As a switching method, it is only necessary to check whether or not dummy data can be transmitted / received in a state before the original data access, and to select a set switching control signal so that a set obtained by the check can be obtained. In this example, two sets of examples are shown. However, if the resolution of the phase degree is increased, more accurate transmission / reception is possible.

  FIG. 14 is a diagram showing a FIFO circuit 26K in the core 26A of the receiving unit when the source synchronous method is adopted.

  The FIFO circuit 26K includes a counter 26L1 that counts the number of data transfers with the output signal OUT2 [3: 0] of the double frequency generation circuit 13A described in FIG. 13A, and a counter 26L2 that counts the number of core clocks with the core clock. FF 26I31 [3: 0] with multi-input selector and FF circuit 26I32 with multi-input selector described in a patent document (Pamphlet of International Publication No. 2007/046368). The four signals output from the counter 26L1 are digital signals, and the rising and falling edges of these signals appear every ¼ of the transfer rate of the strobe signal. The four signals output from the counter 26L2 to count are digital signals, and the periods indicating Hi do not overlap each other, and appear every ¼ of the transfer rate of the core clock signal. The FF 26I31 [3: 0] with multi-input selector receives data from the output OUT [3: 0] of the receiving circuit, and the bus switching control signal is input to the port S [3: 0] of the FF 26I31 with multi-input selector. The input data is selected by the signal of the port S [3: 0]. One of the four output signals is input from the counter 26L1 to the clock of the FF 26I31 [3: 0], one of the four is enabled, and the FF 26I31 with multi-input selector is enabled. Only 3: 0] is captured. The output of each FF 26I31 with multi-input selector [3: 0] is one of four data in the FF circuit 26I32 with multi-input selector using the output signal from the counter 26L2 as the selection signal S [3: 0]. The selected data is taken into the multi-input selector-equipped FF circuit 26I32 by the core clock. In the case of the source synchronous method, if a data transfer strobe is used instead of the core clock, the timing margin of data transfer does not depend on the clock skew between the core and the data transfer strobe, and an interface with more stable data reception operation can be obtained. Can be built. If the cycle of data transfer is shorter than the operating cycle of the core, the output of the FF circuit with multi-input selector 26I31 is transferred as it is to the core logic without going through the FF circuit with multi-input selector 26I32. In this case, the number of FIFO stages (FF 26I31 [3: 0] with multi-input selector) is set by “core operation cycle / data transfer cycle”. If the data transfer cycle is shorter than the limit value of the operation cycle of the FF, it is very effective for stable reception operation, and the number of transmission lines (the number of buses) that interface between cores can be reduced. There is an effect that the area can be reduced.

  When the data transfer cycle is longer than the limit value of the operation cycle of the FF, another FIFO circuit configuration uses a circuit in which the multi-input FF of FIG. 31 described in the patent document (International Publication No. 2007/046368) is improved. Can be configured. This circuit is shown in FIG. FIG. 15 shows a configuration in which the receiving circuit output OUT [3: 0] is input to the data and the bus switching signal is input to the data selection signal S [3: 0], which is described in the patent document (International Publication No. 2007/046368 pamphlet). There are three differences from FIG.

  The first is to input the output of the counter 26L1 instead of the control signal S [3; 0] of the dynamic circuit 28A1C. Here, the four signals output from the counter 26L1 are digital signals, and unlike the specification shown in FIG. 14, the periods indicating “Hi” do not overlap each other and are ¼ of the strobe signal transfer rate. Appears every time. As the clock CLK, the data transfer strobe 4to1 signal of the bus selected from the output signals [3: 0] of the double frequency generation circuit 13A described in FIGS. 12 and 13 is used. In FIG. 14, it is specified that the receiving destination is the core 26A. However, the receiving destination is not particularly limited, and the relay point of the hierarchical bus structure may have a FIFO 26K structure.

  When the FIFO 26K is used as a relay point of the hierarchical bus structure, the transmission destination of the reception circuit output and the Q output of 26I32 may be a transmission / reception form such as one-to-many or many-to-one. Each relay point may have a plurality of FIFOs 26K. An example is shown in FIG. In FIG. 25, the memory control unit receives data and commands from the four FIFOs 26K (a, b, c, d) in the chip, and receives them from the FIFO 26K (e) to be transmitted to the external memory and the external memory. The memory control unit has a FIFO 26K (i) that transmits data and commands to the four FIFOs 26K (f, g, h, i) in the chip. As shown in FIG. 25, it is desirable to generate a many-to-one strobe signal from a one-to-many stove signal.

  Second, there are a plurality of dynamic circuits 28A1 (28A1C-A, 28A1C-B, 28A1C-C, 28A1C-D).

  Third, there are a plurality of hold circuits 90 (90A1, 90A2, 90A3, 90A4), and the output from each hold circuit is used as the output of the dynamic FF circuit.

  The internal signal connection between the internal dynamic circuit and the hold circuit in FIG. 15 is based on the output of the dynamic circuit 28A1 (A1C-2-A, N4-A, N4B-A (the inverted signal of N4 is N4B)). Input to the hold circuits (90A1, 90A2, 90A3, 90A4) and outputs (A1C-2-A to D, N4-A to D) of the dynamic circuits (28A1C-A, 28A1C-B, 28A1C-C, 28A1C-D) , N4B-A to D) are connected to the input signal ports of the respective hold circuits (90A1, 90A2, 90A3, 90A4) on a one-to-one basis. By using the FF of FIG. 15 instead of the FF 26I31 with multi-input selector shown in FIG. 14 [3: 0], the number of elements can be greatly reduced, so that there is a significant area reduction effect. If the timing constraint of the signal output from the counter 26L1 does not adversely affect the data holding of each hold circuit (90A1, 90A2, 90A3, 90A4), the dynamic circuit (28A1C-A, 28A1C-B, 28A1C- C, 28A1C-D) can also be bypassed. In this case, the dynamic circuits (28A1C-A, 28A1C-B, 28A1C-C, 28A1C-D) can be removed, and the area can be further reduced.

  Note that four NMOS transistors are prepared at the output out node of the receiving circuit Rx5B shown in FIG. 5, the drain of the NMOS transistor is connected to the output node, and the inverted signal of Q [3: 0] is connected to the gate of each NMOS transistor. By connecting, the output waveform of the receiving circuit Rx5B can be reliably transmitted to the next FF without being attenuated in the high frequency region. These four NMOS transistors have different current capabilities.

(Second Embodiment)
In the present embodiment, a correction method is proposed in which the eye pattern of the signal waveform hardly fluctuates with respect to temperature fluctuation.

  As described in the first embodiment, the characteristic impedance Z of the line is expressed by equation (22) in a frequency band where the resistance of the line can be ignored. It hardly depends on temperature in the frequency band where dielectric loss and surface effect can be ignored. For example, in the case of a termination resistance type transmission line, if the characteristic impedance of the line is 50 ohms, the termination resistance is preferably 50 ohms. In FIG. 1 shown in Patent Document 1, if the reference resistor is formed of a copper wiring and the wiring is built in the integrated circuit, the value of the reference resistance fluctuates due to the temperature variation of the integrated circuit, and the temperature becomes −40 Since the temperature is in the range of from 125 ° C. to 125 ° C., the value of the termination resistance is also twice different. In other words, due to temperature fluctuations, impedance mismatch between the transmission line and the termination resistor occurs, and signal reflection occurs, making it difficult to realize high-speed transmission over a wide temperature range.

である。（２．１）式を変形すると、

となる。 A method for correcting the resistance value of the resistance element Rg in the transmission system of this embodiment will be described.
When a resistance element having a reciprocal number of G having the relationship shown in the equation (11) is expressed as a function of temperature T,

It is. When (2.1) is transformed,

It becomes.

  That is, the product of the resistance of the resistance element Rg and the conductor constituting the transmission line 1A1 is a value obtained by dividing the inductance of the conductor by the capacitance, in other words, a high-frequency signal that can ignore the resistance component of the conductor. This is the square of the impedance of the conductor. Since both the inductance L and the capacitance C have very little temperature fluctuation, when the resistance value Rg of the transmission line 1A1 fluctuates due to temperature fluctuation, the resistance value of the resistance element Rg is equal to the product of the resistance element and the resistance of the conductor. If it correct | amends to, distortion of the signal waveform by the temperature fluctuation of transmission line 1A1 can be reduced.

  In order to minimize distortion due to branching, the configuration shown in FIG. FIG. 26A is a view of the chip as viewed from above. The main conductor 1A is divided into three branches at a point 26AA shown in the figure, and one of the branch destinations is a point 26AB. This is an example of a structure that is bifurcated again. If the characteristic impedance of the main conductor 1A is Zo at the point where it is branched into three, the wiring structure is changed once so that the characteristic impedance becomes Zo / 4, or a resistor that makes Zo / 4 is connected. FIG. 26B shows a specific example of the wiring cross-sectional structure. In FIG. 26A, a conductor 1A (main trunk line) further branched among the three branches is inserted with a resistor corresponding to the characteristic impedance Zo / 4, and one side of the resistor is connected to the conductor 1A having the characteristic impedance Zo. An example of returning is also shown. Further, when the length of the branch line is shorter than ¼ of the wavelength of the transmission signal, it is desirable that the characteristic impedance is set to Zo / 4 as it is. The symbol Rl in the figure may be a termination resistor or a transmission resistor. These are preferably matched with the characteristic impedance of the conductor 1A.

  Further, the distinction between the main line and the branch line is preferably defined according to the activation rate of the connected ports as described below, considering power consumption and energy consumption.

  FIGS. 27A and 27B show voltage waveforms and current consumption values at each end when a waveform is input from a port having different characteristic impedances with a conductor branched into four branches. It can be seen that the power consumption is different.

Input from a port having characteristic impedance Zo consumes less current than when input from a port having characteristic impedance Zo / 4. Therefore,
1. When a port with a high activation rate is connected, the port is placed on a port with low power consumption, that is, a main line with high characteristic impedance.
2. Ports with a low activation rate are placed on ports with high power consumption. That is, it arrange | positions to a branch line.

  By doing so, the power of the chip can be reduced.

  FIG. 6 shows a specific circuit of the resistance correction method in the transmission system of this embodiment. 6A is a current source, and here, a current Io flows. 6B is also a current source, and a current equivalent to that of the current source 6A flows here. Although not necessarily the same, it is preferable that the current mirror circuit is configured by a current mirror circuit using a bias voltage configured by a band gap reference circuit or the like. This is because a more ideal current source can be realized in which the current value of the current source is hardly affected by temperature and power supply voltage fluctuations. 6E is a resistance element formed of the same conductor material as the conductor forming the transmission line, one is connected to the ground, the other is connected to the current source 6B, and its node is 6A1. . 6F is a resistance element formed of the same device as the proposed resistance element Rg, and the resistance value can be made variable by a control signal. One end of the resistance element 6F is connected to the ground, the other end is connected to the current source 6A, and its node is 6B1. Reference numeral 6C denotes a multiplier (multiplication means) that multiplies the voltage values of the nodes 6A1 and 6B1 and outputs the result to the output node 6C1. Reference numeral 6D denotes a comparator (comparison means) that compares the reference voltage Vref with the voltage at the node 6C1 and outputs the magnitude value to the node 6D1. The resistance element 6F and the resistance element Rg of the transmission line can be made variable by the node 6D1. If the voltage value of the node 6C1 is higher than the reference voltage, the resistance of the resistance element 6F is lowered. If the voltage value of the node 6C1 is lower than the reference voltage, the feedback system increases the resistance value of the resistance element 6F. Here, the reference voltage Vref is set to a value linear to the value of L / C of the transmission line.

  A specific circuit diagram of the multiplier 6C is shown in FIG. This is a CMOS type Gilbird analog multiplier 6CA. A differential signal 6B1 is input to bias1. A differential signal 6A1 is input to bias2. When such an analog multiplier is used, the responsiveness of the feedback system is good and the number of elements is small, so that it is possible to control the resistance value of the resistance element Rg better with less noise.

  FIG. 8 shows a circuit diagram of an example of variable control of the resistance elements 6F and Rg. The resistance value is adjusted by connecting the NMOS transistor 8A and the resistance element 8C in parallel to form a resistor, and connecting the gate of the NMOS transistor 8A to the node 6D1. The substrate of the NMOS transistor 8A is connected to the node 8B, and the substrate is controlled so as to have the same current characteristics regardless of the process variation, temperature variation, and voltage variation of the NMOS transistor 8A.

  These substrate control methods are also described in patent documents (Japanese Patent Application Laid-Open No. 2004-165649, Japanese Patent No. 3838655), and FIG. 17 shows a supplementary example. FIG. 17 shows a substrate control method when the resistance element Rg is formed by a PMOS transistor, and the core has a power cutoff switch on the NMOS transistor side, the substrate of the NMOS transistor is fixed at 17V3, and the source of the NMOS transistor A method for controlling the potential will be described.

  Reference numeral 17G denotes a power supply control circuit. Reference numeral 17A-1 denotes an NMOS transistor manufactured in the same manner as the NMOS transistor in the core. The gate and drain of the NMOS transistor are connected to the current source 17Io2 and further connected to the input terminal of the operational amplifier Op-amp17C. It is connected. The reference voltage of the operational amplifier Op-amp 17C is the power supply voltage 17V2 inside the core. The operational amplifier Op-amp 17C adjusts the source voltage of the NMOS transistor 17A-1 via the signal line 17Vref32 so that the saturation current of the NMOS transistor 17A-1 becomes constant. The signal line 17Verf32 is connected to the pad PAD3 via the analog switch SW7A4, and is connected to the power supply (not grounded) of the NMOS transistor in the core via the analog switch SW7A6. The power line of the NMOS transistor is connected to the output terminal of the fuse box Fuse whose output voltage value is adjusted by an external signal from the pad PAD2 via the analog switch SW7A2. The output of the fuse box Fuse is connected to the pad PAD3 via the analog switch SW7A8. The fuse box includes a volatile memory, a nonvolatile memory, and a fuse.

  In FIG. 17, 17P is a substrate control circuit of a PMOS transistor, 17A-2 is a PMOS transistor formed by the same manufacture as the PMOS transistor in the core, and the gate and drain are connected to the current source 17Io1. Furthermore, it is connected to the input terminal of the operational amplifier Op-amp 17B. The reference voltage of the operational amplifier Op-amp 17B is the power supply voltage 17V1 inside the core. The operational amplifier Op-amp 17B adjusts the substrate voltage of the PMOS transistor 17A-2 via the signal line 17Vref31 so that the saturation current of the PMOS transistor 17A-2 becomes constant. The signal line 17Verf31 is connected to the pad PAD1 via the analog switch SW7A3, and is connected to the PMOS transistor substrate in the core via the analog switch SW7A5. The PMOS transistor substrate is connected to the output terminal of the fuse box Fuse controlled by an external signal from the pad PAD2 via the analog switch SW7A1. The output of the fuse box Fuse is connected to the pad PAD1 via the analog switch SW7A7. These power supply control and board control can be realized in two or more ways of using the switches SW7A1 to SW7A8. Here, two effective methods will be described.

  One is a method in which the switches SW7A1 and SW7A2 are turned off and the switches SW7A5 and SW7A6 are turned on to adaptively control the power supply and the substrate inside the core. This can respond to instantaneous fluctuations of process deterioration, temperature fluctuation, and voltage fluctuation, and can be controlled with high accuracy.

  The other is that before the core operates, the switches SW7A3, SW7A4 are made conductive and the switches SW7A2, 8, SW7A3, 7 are made nonconductive, that is, the pad PAD1, 3 outputs the information of the voltage 17Vref31 and 17Vref32 of the signal line, adjusts the fuse box Fuse from the outside via the pad PAD2 so as to be the same value as the voltage value, and then switches SW7A3, 5, SW7A4, 6 is in a non-conductive state, the switches SW7A2, 8, SW7A3, 7 are in a conductive state, and the power supplied to the power supply control circuit 17G and the substrate control circuit 17P is cut off. This can adjust for variations in process manufacturing. For temperature fluctuations and voltage fluctuations, the temperature detection circuit detects the information that the chip temperature has changed, and within a certain range, the core is not stopped. And operate the substrate control circuit. Similarly, the voltage fluctuation is controlled by the voltage fluctuation detection circuit. Regarding the voltage, the core is stopped and the power supply and the substrate control circuit are operated when an external command for changing the power supply voltage and the substrate voltage value inside the core is issued. Although less accurate than adaptive, it is a more robust method and does not consume the power of the control circuits 17P and 17G during the core operation, thus reducing power consumption.

  Returning to the description of FIG. 6, an A-D converter may be inserted between the nodes 6A1 and 6B1, and a digital multiplier may be used instead of the multiplier 6C. The comparator 6D may also be a digital comparator. In that case, the node 6C1 and the reference voltage Vref are represented as digital values by a plurality of bit strings. The variable resistance element 6F and the resistance element Rg may also be configured by connecting MOS transistors or the like in parallel, and the MOS transistor may be switch-controlled with a digital value using the node 6D1 as a bus.

  For the reference voltage Vref, if the accuracy is improved, the CR time constant of the capacitance value C and resistance value R of the conductor 1A constituting the transmission line 1A1 and the dielectric constant of the dielectric material surrounding the conductor 1A Thus, the reference voltage Vref is determined. If the time constant CR is applied to the transmission line 1A1 with a voltage waveform that gradually changes to the transmission line 1A1 without considering the distributed constant, and its arrival time is measured using a DLL or the like built in an integrated circuit, A time constant is determined. The resistance value R is calculated from a current source and a voltage value in a DC state. Thereby, the capacity C is calculated. Further, the inductance L value of the conductor 1A is calculated by the equation (13). By setting this value to the reference voltage Vref before the signal propagates through the transmission line 1A1 at high speed, an accurate resistance value of the caustic resistance corresponding to the process variation and temperature variation of the transmission line 1A1 in the on-chip can be obtained. realizable. As a result, the waveform amplitude is constant even at high speed transmission at any temperature and process condition, and stable signal transmission is possible.

Further, whether to control these adaptively or with a Fuse box or the like can be realized by preparing an analog switch, a Fuse box and a pad PAD, and a power cutoff circuit of a feedback system as described in FIG.
The effects of this proposed method are described below.

When the conductance, that is, the reciprocal of the resistance value of the resistance element Rg, fluctuates by Δ, it is expressed as shown in Equation (2.3).

となる。 When the attenuation constant α given by the previous equations (11) and (12) is expanded using the equation (2.3),

It becomes.

  When copper is used for the conductor 1A, the fluctuation of the resistance R is 1.343 times due to the temperature difference between 27 ° C. and 125 ° C. Substituting Z = 50 [ohm] and R = 50 [ohm] and taking into account the resistance variation from -40 ° C. to 125 ° C., the eye attenuation constant varies by 50%. Further, the characteristic impedance varies by 10%. Which is the main cause of distortion in the waveform is characteristic impedance. The fluctuation of the characteristic impedance affects the reflection of the signal waveform assuming that there is no temperature fluctuation in the termination resistor. Therefore, waveform distortion occurs. FIG. 33 is a graph in which the horizontal axis represents temperature and the vertical axis represents characteristic impedance when the correction method is not used (w / O) and when it is used (with). As can be seen from FIG. 33, using this embodiment, it can be seen that the characteristic impedance does not vary with temperature. That is, the waveform distortion can be reduced by this embodiment. Furthermore, if the reference voltage Vref is a voltage value reflecting the process variation value of the conductor 1A, the signal propagating through the transmission line 1A1 can have an undistorted signal waveform that does not depend on the process and temperature variation. Become. As described above, the distortion of the signal waveform can be further reduced by adding a small circuit scale to the transmission line 1A1.

(Application example of embodiment)
FIG. 18 shows an overview of a communication device provided with an electronic device according to the present invention. The mobile phone 500 includes a baseband LSI 501 and an application LSI 502. The baseband LSI 501 and the application LSI 502 are semiconductor integrated circuits having the electronic device according to the present invention. Since the electronic device according to the present invention can transmit information at a higher speed than before and can operate with less power consumption than in the past, the baseband LSI 501 and the application LSI 502 and the mobile phone 500 including these can also be reduced in power consumption. Operation is possible. Further, for the semiconductor integrated circuit provided in the mobile phone 500 other than the baseband LSI 501 and the application LSI 502, the logic circuit provided in the semiconductor integrated circuit is the electronic device according to the present invention, which is similar to the above. The effect of can be obtained.

  The periphery of chips 501 and 502 in FIG. 18 is a chip such as an integrated chip such as an analog chip or a digital chip in the mobile phone device system of FIG. 28, and includes an antenna, a power IC memory, a camera, an LCD, and the like. It is connected to the.

  Note that the communication device including the electronic device according to the present invention should not be limited to a mobile phone, but includes, for example, a transmitter / receiver in a communication system, a modem device that performs data transmission, and the like. It is a waste. That is, according to the present invention, it is possible to obtain the effect of reducing power consumption for any communication device regardless of whether it is wired / wireless, optical communication / electrical communication, or digital method / analog method.

  FIG. 19 shows an overview of an information reproducing apparatus provided with an electronic device according to the present invention. The optical disk device 510 includes a media signal processing LSI 511 that processes a signal read from the optical disk, and an error correction / servo processing LSI 512 that performs error correction of the signal and servo control of the optical pickup. The media signal processing LSI 511 and the error correction / servo processing LSI 512 are semiconductor integrated circuits having the electronic device according to the present invention. Since the electronic apparatus according to the present invention can transmit information at a higher speed than before and can operate with less power consumption than before, the media signal processing LSI 511, the error correction / servo processing LSI 512, and the optical disk apparatus 510 including them are also included. Further, low power operation is possible. Further, regarding the semiconductor integrated circuit provided in the optical disk device 510 other than the media signal processing LSI 511 and the error correction / servo processing LSI 512, the logic circuit provided in the semiconductor integrated circuit is the electronic device according to the present invention. Thus, the same effect as described above can be obtained.

  Chips 511 and 512 in FIG. 19 are, for example, FEP and FE + BE integrated chips in the disk re-recording apparatus shown in FIG. 29, and are HD, Flash AV IO Sub field (AV IO SUBF), and HA (head amplifier). ), LDD or the like.

  Note that the information reproducing apparatus provided with the electronic device according to the present invention should not be limited to the optical disk apparatus. In addition to this, for example, an information recording / reproducing apparatus incorporating a magnetic disk or information using a semiconductor memory as a medium. It includes a recording / reproducing device. That is, according to the present invention, the effect of reducing power consumption can be obtained for any information reproducing apparatus (which may include an information recording function) regardless of the type of media on which information is recorded.

  FIG. 20 shows an overview of an image display device provided with the electronic device according to the present invention. The television receiver 520 includes an image / sound processing LSI 521 that processes image signals and sound signals, and a display / sound source control LSI 522 that controls devices such as a display screen and speakers. The image / sound processing LSI 521 and the display / sound source control LSI 522 are semiconductor integrated circuits having the electronic device according to the present invention. Since the electronic device according to the present invention can transmit information at a higher speed than before and can operate with less power consumption than before, the image / sound processing LSI 521, the display / sound source control LSI 522, and the television receiver including the same. 520 also enables low power operation. Further, regarding the semiconductor integrated circuit provided in the television receiver 520 other than the image / sound processing LSI 521 and the display / sound source control LSI 522, the logic circuit provided in the semiconductor integrated circuit is the electronic device according to the present invention. By doing so, the same effect as described above can be obtained.

  The chips 521 and 522 in FIG. 20 are, for example, the demodulator and DTV-SOC of the digital TV apparatus shown in FIG. The periphery is connected to a terrestrial digital tuner, a satellite digital tuner, a B-CAS card, an SD, a memory, a Sub-Field, a Scan Driver, and the like.

  FIG. 31 shows a diagram comprehensively showing the configuration and interface in the chip used in FIGS. 28, 29 and 30. FIG. FIG. 31 shows an example of a heterogeneous processor and its periphery. Data is communicated between the memory control unit and each core (AV / IO, CPU, signal processing, stream IO) by the conductors 1A and 1B of the present invention. AV / IO is a functional block for image and sound control. The CPU is a functional block of the user interface. The signal processing is a functional block such as image or audio compression / decompression. The stream IO is a functional block that takes in image data and audio data from the outside and manages the security of the data.

  The present invention can be applied to other than heterogeneous processors. FIG. 32 shows an example in which 64 multi-cores are mounted. In the figure, the external memory and the memory control unit supply 25 conductors 1A and 1B of the present invention from the memory control unit to each core when accessed at 1 TByte / s.

  The image display device provided with the electronic device according to the present invention should not be limited to a television receiver, but also includes, for example, a device for displaying streaming data distributed through an electric communication line. Is included. That is, according to the present invention, it is possible to obtain the effect of reducing power consumption for any image display apparatus regardless of the information transmission method.

  FIG. 21 shows an overview of an electronic device provided with the electronic device according to the present invention. The digital camera 530 includes a signal processing LSI 531 which is a semiconductor integrated circuit having the electronic device according to the present invention. Since the electronic device according to the present invention can operate with less power consumption than before, the signal processing LSI 531 and the digital camera 530 including the same can also operate at low power. Further, for the semiconductor integrated circuit provided in the digital camera 530 other than the signal processing LSI 531, the logic circuit provided in the semiconductor integrated circuit is the electronic device according to the present invention, so that the same effect as described above can be obtained. Obtainable.

  The electronic device provided with the electronic device according to the present invention should not be limited to a digital camera. In addition to this, for example, various devices such as various sensor devices and electronic computers generally include a semiconductor integrated circuit in general. Is included. According to the present invention, the effect of reducing power consumption can be obtained for all electronic devices.

  FIG. 22 shows an overview of an electronic control device including the electronic device of the present invention and a moving body including the electronic control device. The automobile 540 includes an electronic control device 550. The electronic control device 550 is a semiconductor integrated circuit having the electronic device according to the present invention, and includes an engine / transmission control LSI 551 that controls an engine, a transmission, and the like of the automobile 540. In addition, the automobile 540 includes a navigation device 541. Similarly to the electronic control device 550, the navigation device 541 also includes a navigation LSI 542 that is a semiconductor integrated circuit having the electronic device according to the present invention.

  Since the electronic device according to the present invention can operate with less power consumption than before, the engine / transmission control LSI 551 and the electronic control device 540 including the same can also operate at low power. Similarly, the navigation LSI 542 and the navigation device 541 including the navigation LSI 542 can also operate at low power. Further, for the semiconductor integrated circuit provided in the electronic control device 550 other than the engine / transmission control LSI 551, the logic circuit provided in the semiconductor integrated circuit is the electronic device according to the present invention. The effect of can be obtained. The same can be said for the navigation device 541. The power consumption of the automobile 540 can also be reduced by reducing the power consumption of the electronic control unit 550.

  Note that the electronic control device including the electronic device according to the present invention should not be limited to the one that controls the engine and the transmission, and other than this, for example, a semiconductor integrated circuit such as a motor control device may be used. It includes all devices that control the power source. According to the present invention, an effect of reducing power consumption can be obtained for such an electronic control device.

  In addition, the mobile body provided with the electronic device according to the present invention should not be limited to an automobile. Besides this, for example, an electronic control that controls an engine or a motor that is a power source, such as a train or an airplane. Includes all equipment with devices. According to the present invention, the effect of reducing power consumption can be obtained for such a moving body.

  As described above, the electronic device of the present invention has little signal deterioration particularly when a signal is transmitted, and the transmission circuit receiving circuit requires a small area. For example, it is useful for notebook PCs, cellular phones, portable music players, and the like.

It is a figure which shows the transmission line which concerns on this invention. It is a figure which shows the transmission-and-reception circuit of the transmission line, and arrangement | positioning of a resistor. It is a figure which shows the simulation waveform at the time of transmitting a pseudo random number bit string from TRX0 in the circuit of Fig.2 (a). It is a figure which shows the simulation waveform at the time of transmitting a pseudo random number bit sequence from TRX3 in the circuit of Fig.2 (a). The figure which shows the eye pattern of each node at the time of inserting termination resistance (50 ohm) between the node of in0 of FIG. 2A and the conductor 1B, and between the node of out6 and the conductor 1B. It is. It is a schematic block diagram of the electronic device containing the transmission line. It is a figure which shows an example of the function of the interface of memory control part 3B1A, 3B2A. It is sectional drawing of the transmission line of the same electronic device. It is a figure which shows the transmission circuit, receiving circuit, and resistance circuit of the transmission line of the same electronic device. It is a figure which shows the resistance adjustment circuit of the transmission line of the same electronic device. It is a figure which shows the integrating circuit with which the resistance adjustment circuit is equipped. It is a figure which shows the detail of the resistance of the transmission line of the same electronic device. It is a physical layout figure of the transmission line of the electronic device. It is a physical layout showing a section of the transmission line. It is the physical layout which looked at the transmission line from the upper part. It is a figure which shows embodiment of this invention in case the global power supply layer of a core is isolate | separated from others. It is a schematic block diagram of the internal structure of the DLL circuit of the same electronic device. It is a figure which shows schematic structure of the 2nd frequency generation circuit of the same electronic device. It is a figure which shows the simulation waveform of the double frequency generation circuit. It is a schematic block diagram of the source synchronous receiving part of the same electronic device. It is the schematic of the other internal structure of the receiving part of the same electronic device. It is sectional drawing of the transmission line in the integrated circuit of the same electronic device. It is the schematic which shows the internal structure of the board | substrate control circuit and power supply control circuit of the same electronic device. It is a general-view figure of the communication apparatus provided with the same electronic device. It is a general-view figure of the information reproduction apparatus provided with the same electronic device. It is a general-view figure of the image display apparatus provided with the same electronic device. It is a general-view figure of the electronic device provided with the same electronic device. It is a general-view figure of the electronic control apparatus provided with the same electronic device, and the moving body provided with the electronic control device. It is a figure which shows a differential type | mold frequency divider circuit. It is a figure which shows a phase adjustment circuit. It is a figure which shows the example of application in case FIFO26K is used as a relay point of a hierarchical bus structure. It is a figure which shows the detailed drawing of the branch of 1 A of conductors. It is a figure which shows the specific example of wiring cross-section. It is a figure which shows the voltage waveform and current consumption value in each edge part at the time of inputting a waveform from one of the ports in which each characteristic impedance differs in the conductor branched into four. It is a figure which shows the voltage waveform and consumption current value in each edge part at the time of inputting a waveform from the other one of the ports in which each characteristic impedance differs in the conductor branched into four. It is a figure which shows the type | system | group of a mobile telephone apparatus. It is a figure which shows the integrated chip | tip of FEP and FE + BE of a disk re-recording apparatus. It is a figure which shows the demodulation of a digital TV apparatus, and DTV-SOC. It is a figure which shows an example of the structure of the heterogeneous processor to which this invention is applied, and its periphery. It is the figure which applied this invention when 64 multi-cores are mounted. It is a figure in which the horizontal axis of the case where this correction method is not used (w / O) and the case where it is used (with) is temperature, and the vertical axis is a graph of characteristic impedance. It is a figure which shows graph 2D addition when not applying with the case where this loading type is applied.

Explanation of symbols

1A1 Transmission line 1A Conductor 1B Conductor (return path)
Tx5A transmission circuit (transmission means)
Rx5B receiving circuit (receiving means)
Rg, Rg5C Resistance element 6C Multiplier (integrating means)
6D comparator (comparison means)

Claims (39)

At least one transmission means;
At least one receiving means;
At least two conductors;
A dielectric surrounding the conductor;
A plurality of resistive elements connected in parallel between at least one first conductor of the conductors and at least one or more second conductors excluding the first conductor;
The first conductor transmits a signal;
The length of the line of the first conductor is at least half the value of the product of the reciprocal of the signal transfer rate of the first conductor and the speed of light traveling through the dielectric,
The resistance element is at least one on the line of the first conductor for every half of the product of the signal transfer rate of the first conductor and the speed of light traveling in the dielectric. An electronic device characterized by being arranged as described above. The electronic device according to claim 1.
The electronic device, wherein the second conductor is forcibly fixed from the outside. The electronic device according to claim 2.
The electronic device characterized in that the forced potential of the second conductor maintains the same potential when the conductor performs a signal transmission operation. The electronic device according to claim 1.
The electronic device, wherein the second conductor transmits a signal complementary to the signal of the first conductor. The electronic device according to claim 1.
The line of the first conductor has a branched structure, and the resistance element is arranged at the branch point. The electronic device according to claim 1.
An electronic apparatus comprising the transmission circuit or the reception circuit in a line of the first conductor. The electronic device according to claim 6.
The electronic device comprising the resistance element in the receiving circuit or the transmitting circuit. The electronic device according to claim 6.
An electronic apparatus, wherein information on a reception position is transmitted from the transmission circuit. The electronic device according to claim 6.
An electronic apparatus comprising: transmitting position information from the transmitting circuit to the receiving circuit. The electronic device according to claim 6.
The electronic device, wherein the reception circuit adjusts reception sensitivity according to information on a position of the transmission circuit. The electronic device according to claim 1.
The electronic device, wherein a minimum signal transfer rate of the conductor is zero. The electronic device according to claim 1.
And an integrating means for integrating the resistance value of the first conductor and the resistance value of the resistance element;
Comparing means for comparing the integrated value obtained by the integrating means with a reference value,
An electronic device, wherein the resistance value of the resistance element is adjusted so that the integrated value and the reference value are the same. The electronic device according to claim 12.
The electronic device according to claim 1, wherein the reference value is an inductance value per unit capacity of the first conductor. The electronic device according to claim 12.
The electronic device according to claim 1, wherein the reference value is variable in accordance with a conductor and a shape of an interlayer film surrounding the conductor. The electronic device according to claim 12.
The electronic device is characterized in that the integrating means is a multiplier. The electronic device according to claim 15.
The electronic device, wherein the multiplier receives a product of a resistance value of the resistance element and a current value of a constant current source. The electronic device according to claim 15.
The electronic device, wherein the multiplier receives a product of a resistance value of a conductor imitating the conductor and a current value of a constant current source. The electronic device according to claim 1.
The electronic device, wherein the first conductor is a transmission signal line in a semiconductor integrated circuit. The electronic device according to claim 18.
Furthermore, a power switch having a function of whether to supply power from the outside to the FET in the semiconductor integrated circuit,
The power switch is connected to a power line from an external power source,
The electronic device, wherein the second conductor connected to the first conductor in the semiconductor integrated circuit via a resistor is the power line. The electronic device according to claim 1.
The electronic device, wherein the first conductor is connected to a different processing unit. The electronic device according to claim 1.
The electronic device, wherein the first conductor is connected to a plurality of the same processing units. The electronic device according to claim 1.
The electronic device, wherein the first conductor is connected to a plurality of processing elements that constitute a reconfigurable core. The electronic device according to claim 1.
The electronic device, wherein the signal of the first conductor is transmitted from the transmission circuit through a circuit that receives electromagnetic waves. The electronic device according to claim 1.
The first conductor is covered with a silicon compound;
In the resistance element, the silicon compound is polycrystalline. The electronic device according to claim 1.
The electronic device is characterized in that the conductor and the transmission signal line of the semiconductor integrated circuit are connected via a conductor having a cross-sectional area larger than that of the conductor. The electronic device according to claim 1.
The resistive element is composed of at least one FET,
An electronic device, wherein the source and the drain are connected to different conductors, respectively, and the gate is supplied with a voltage from another conductor. The electronic device according to any one of claims 1 to 14,
The voltage range of the signal line connected to the gate is a voltage range in which the source / drain current of the FET exhibits a linear region when the first conductor transmits a signal. 28. The electronic device of claim 27.
The voltage range of the signal line connected to the gate is a voltage range in which the source / drain current of the FET indicates a cutoff region when the first conductor does not transmit a signal. The electronic device of claim 28.
The voltage value of the substrate of the FET is variable independently of its source voltage, drain voltage, and gate voltage. The electronic device according to claim 1.
The electronic device, wherein a cross-sectional portion of the conductor to which the first conductor and the resistance element are connected is not less than an interval at which another conductor is inserted. The electronic device according to claim 1.
At least one of the conductors connected to the first conductor and the resistance element is wired in parallel with the first conductor. The electronic device according to claim 1.
The electronic device, wherein the second conductor is positioned between a semiconductor constituting the substrate and the first conductor. The electronic device of claim 32.
The second conductor is composed of a plurality of wiring layers, and the lowest layer and the third layer from the lowest layer overlap each other. A communication device comprising a semiconductor integrated circuit having the electronic device according to claim 1. An information reproducing apparatus comprising a semiconductor integrated circuit having the electronic device according to claim 1. An image display device comprising a semiconductor integrated circuit having the electronic device according to claim 1. An electronic device comprising a semiconductor integrated circuit having the electronic device according to claim 1. An electronic control device comprising a semiconductor integrated circuit having the electronic device according to claim 1. A moving body comprising the electronic control device according to claim 38.

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