JP2009065420A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain reduction of layout area, and lower power consumption by reducing the number of comparators used for a quantizer. <P>SOLUTION: The quantizer 10 provided in an A/D converter compares an input signal with preset reference voltage in comparators 13-16. A control circuit 17 outputs a boundary of temperature codes between "0" and "1" of output of the comparators 13-16 as "1". For example, when "1" is output from an AND circuit D4 of the control circuit 17, switches SW4, SW9, SW14, SW19 become ON, respectively, and thus, divided voltage of nodes n4, n5, n6, n7 is output to the comparators 13-16 as the reference voltage, respectively. Thus, only the optimal reference voltage near the boundary of the temperature codes suitable for an input level of the input signal is supplied to the comparators 13-16, and even in the case of a small number of comparators 13-16, highly accurate quantization becomes possible. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technology for improving the performance of an A / D (Analog / Digital) converter, and in particular, a technology effective for reducing a layout area and reducing power consumption in a quantizer provided in the A / D converter. About.

  Some semiconductor integrated circuit devices include an A / D converter that converts an analog input signal into a digital signal. As one of the A / D converters, for example, a delta-sigma A / D converter is known.

  The delta-sigma A / D converter includes, for example, an integration circuit, a quantizer, and a quantization error feedback circuit (D / A (Digital / Analog) converter).

  In the above-described configuration circuit, when the integration of the input and the output of the quantizer coincides, the output is output from the quantizer when there is a difference between them, and the difference is attempted to be canceled. Therefore, in the ΔΣ modulation, the value of the quantizer varies depending on the magnitude of the input signal.

  The integrator has a high gain for signals having a low frequency and, conversely, a low gain for signals having a high frequency. Since the comparator is passed after the integration, the followability with respect to the low frequency signal is higher than that of the high frequency signal, and the quantization error is fed back to the signal directly without being integrated.

  However, the inventor has found that the analog signal digital conversion technique using the A / D converter as described above has the following problems.

The value of the quantizer used in the A / D converter using this ΔΣ modulation is determined by the number of comparators constituting the quantizer, and is usually put to practical use with a value of 2 ⁿ⁻¹ . . If the value of the quantizer is increased, sampling can be performed more finely and quantization noise can be reduced.

  However, when high-accuracy ΔΣ modulation is to be obtained by increasing the number of quantizers, the number of comparators increases, resulting in an increase in layout area and power consumption. Further, when a mismatch occurs in the D / A converter, there is a problem that a non-linear component is added to the circuit and a high frequency is generated.

  An object of the present invention is to provide a technique capable of reducing a layout area in an A / D converter and reducing power consumption by reducing the number of comparators used in a quantizer. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device including an A / D converter that converts an analog signal into a digital signal, and the A / D converter is an integrator that integrates a differential signal between an input signal and a feedback signal. A quantizer that converts the signal output from the integrator into a digital signal and quantizes the signal, and a D / A converter that converts the digital signal output from the quantizer into an analog signal and feeds back the analog signal. The quantizer compares a reference voltage output unit that generates a plurality of reference voltages with a reference voltage generated by the reference voltage output unit and an input signal, and outputs the comparison result as a thermometer code. A plurality of comparators, and a reference voltage supply control unit that selects an arbitrary reference voltage corresponding to the input level of the input signal based on the thermometer code output from the comparator and supplies the reference voltage to each of the comparators. It is equipped .

  According to the present invention, the reference voltage supply control unit selects an arbitrary reference voltage generated by the reference voltage output unit based on the selection control signal, and outputs the selected reference voltage to the comparator. A selection control unit that detects a boundary of an output thermometer code, generates a selection control signal that supplies a reference voltage near the boundary of the thermometer code to a comparator, and outputs the selection control signal to a reference voltage selection unit; is there.

  Furthermore, in the present invention, the quantizer comprises a flash A / D conversion circuit.

  In the present invention, the A / D converter comprises a delta-sigma modulation circuit.

  Furthermore, the outline | summary of the other invention of this application is shown briefly.

  The present invention is a semiconductor integrated circuit device including an A / D converter that converts an analog signal into a digital signal, and the A / D converter is an integrator that integrates a differential signal between an input signal and a feedback signal. A quantizer that converts the signal output from the integrator into a digital signal and quantizes the signal, and a D / A converter that converts the digital signal output from the quantizer into an analog signal and feeds back the analog signal. The quantizer compares a reference voltage output unit that generates a plurality of reference voltages with a reference voltage generated by the reference voltage output unit and an input signal, and outputs the comparison result as a thermometer code. A comparator that is supplied with an arbitrary reference voltage corresponding to the input level of the input signal based on a plurality of comparators and a thermometer code output by the comparator, and is operated in comparison. Stop the device An operation control unit that generates an operation control signal and outputs the operation control signal to the comparator. The comparator includes an operation control terminal, and the operation state and the stop state are determined based on the operation control signal input to the operation control terminal. Is controlled.

  Further, according to the present invention, the operation control unit detects a boundary of a thermometer code output from the comparator, operates a comparator to which a reference voltage near the boundary of the thermometer code is supplied, and performs other comparisons. A control unit that generates and outputs a control signal for stopping the detector, and an operation control signal output unit that outputs an operation control signal to the comparator based on the control signal output from the control unit It is.

  Furthermore, in the present invention, the quantizer comprises a flash A / D conversion circuit.

  In the present invention, the A / D converter comprises a delta-sigma modulation circuit.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The number of comparators can be greatly reduced without reducing the accuracy of the quantizer.

  (2) Further, the layout area can be reduced by the above (1).

  (3) Furthermore, current consumption can be reduced by the above (1).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a block diagram of an A / D converter provided in the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 4 is an explanatory diagram illustrating a configuration example of a quantizer provided in the A / D converter, FIG. 4 is an explanatory diagram illustrating a connection configuration of a control switch unit provided in the quantizer in FIG. 3, and FIG. FIG. 6 is an explanatory diagram showing an example of operation in the quantizer of FIG. 3, FIG. 7 is an explanatory diagram following FIG. 6, and FIG. FIG. 9 is an explanatory diagram subsequent to FIG.

  In the first embodiment, the semiconductor integrated circuit device 1 includes, for example, a microcontroller, and is used for controlling an electronic system. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a CPU 2, a memory 3, a signal switching unit 4, an A / D converter 5, a control unit 6, a register 7, and the like.

  The CPU 2 manages all the controls in the semiconductor integrated circuit device 1. The memory 3 is composed of, for example, a nonvolatile semiconductor memory exemplified by a flash memory and stores data such as a control program.

  The signal switching unit 4 selects an analog signal input to an arbitrary external terminal based on a control signal output from the control unit 6 from analog signals input via a plurality of external terminals, and performs A / D conversion. Output to the device 5.

  The A / D converter 5 is, for example, a delta sigma type A / D converter, which converts an analog signal input via the signal switching unit 4 into a digital signal and outputs the digital signal. The control unit 6 controls the operation of the signal switching unit 4 and the A / D converter 5 based on the control of the CPU 2. The register 7 temporarily stores the digital signal converted by the A / D converter 5.

  The CPU 2, the memory 3, the control unit 6, and the register 7 are comprehensively connected via the bus B.

  FIG. 2 is a block diagram showing the configuration of the A / D converter 5.

  The A / D converter 5 includes a subtracter 8, an integrator 9, a quantizer 10, and a D / A (Digital / Analog) converter 11, as shown in the figure.

  One input portion of the subtracter 8 is connected so that an analog input signal which is an input signal of the A / D converter 5 is input. The output unit of the subtractor 8 is connected to the input unit of the integrator 9, and the output unit of the integrator 9 is connected to the input unit of the quantizer 10.

  The output unit of the quantizer 10 is connected to the input unit of the D / A converter 11, and the output unit of the D / A converter 11 is connected to the other input unit of the subtractor 8. Yes. The output unit of the quantizer 10 serves as the output unit of the A / D converter 5 and outputs an output signal of a digital signal.

  The subtracter 8 calculates the difference between the input signal and the analog signal output from the D / A converter 11. The integrator 9 integrates the calculation result of the subtracter 8. The quantizer 10 converts the input signal into a digital signal and quantizes it. The D / A converter 11 converts the digital signal output from the quantizer 10 into an analog signal.

  FIG. 3 is an explanatory diagram showing a configuration example of the quantizer 10.

  The quantizer 10 includes a reference voltage output circuit 12, comparators 13 to 16, and a control circuit 17. The reference voltage output circuit 12 includes a resistance unit RR and a control switch unit 18. Further, the control circuit 17 and the control switch unit 18 function as a reference voltage supply control unit.

  The resistor unit RR is provided with resistors R1 to R9, and the resistors R1 to R9 are connected in series between a positive (+) reference voltage VREFP and a negative (−) reference voltage VREFN. It has become.

  The control switch unit 18 that functions as a reference voltage selection unit includes a selection unit sel and switch units S1 to S4. The selection unit sel outputs a selection signal to each of the switch units S1 to S4 based on the control signal output from the control circuit 17.

  The switch unit S1 includes switches SW1 to SW5, and the switch unit S2 includes switches SW6 to SW10. The switch unit S3 includes switches SW11 to SW15, and the switch unit S4 includes switches SW16 to SW20.

  One connection portion of the switch SW1 is connected to a connection portion (node n1) between the resistors R1 and R2, and one connection portion of the switch SW2 is connected to a connection portion (node) between the resistors R2 and R3. n2) is connected.

  One connection portion of the switch SW3 is connected to a connection portion (node n3) between the resistors R3 and R4, and one connection portion of the switch SW4 is connected to a connection portion (node) between the resistors R4 and R5. n4) is connected. Also, a connection portion (node n5) between the resistor R5 and the resistor R6 is connected to one connection portion of the switch SW5.

  Similarly, nodes n2 to n5 are connected to one connection portion of the switches SW6 to SW9, respectively, and a connection portion (node n6) between the resistors R6 and R7 is connected to one connection portion of the switch SW10. It is connected.

  Nodes n3 to n6 are connected to one connection part of the switches SW11 to SW14, respectively, and a connection part (node n7) between the resistor R7 and the resistor R8 is connected to one connection part of the switch SW15. Yes.

  Further, nodes n4 to n7 are connected to one connection part of the switches SW16 to SW19, respectively, and a connection part (node n8) between the resistors R8 and R9 is connected to one connection part of the switch SW20. Has been.

  One input part of the comparator 13 is connected to the other connection part of the switches SW1 to SW5, and one input part of the comparator 14 is connected to the other connection part of the switches SW6 to SW10. Has been.

  Further, one input part of the comparator 15 is connected to the other connection part of the switches SW11 to SW15, and one input part of the comparator 16 is connected to the other connection part of the switches SW16 to SW20. Each is connected.

  Based on the selection signal output from the selection unit sel, the switch units S1 to S4 cause the arbitrary switches SW1 to SW5, SW6 to SW10, SW11 to SW15, and SW16 to SW20 to be in a conductive state, and are divided by the resistors R1 to R9. The compressed reference voltage is output to each of the comparators 13 to 16.

  Further, the other input parts of the comparators 13 to 16 are connected so that the output signal from the integrator 9 is inputted. The control circuit 17 functioning as a selection control unit includes AND circuits D1 to D5 and inverters Iv1 to Iv5.

  The reference potential VSS is connected to the input part of the inverter Iv1, and one input part of the AND circuit D1 is connected to the output part of the inverter Iv1. The other input section of the AND circuit D1 is connected to the output section of the comparator 13 and the input section of the inverter Iv2.

  One input portion of the AND circuit D2 is connected to the output portion of the inverter Iv2, and the output portion of the comparator 14 and the input portion of the inverter Iv3 are connected to the other input portion of the AND circuit D2. Each is connected.

  One input unit of the AND circuit D3 is connected to the output unit of the inverter Iv3, and the output unit of the comparator 15 and the input unit of the inverter Iv4 are connected to the other input unit of the AND circuit D3. Each is connected.

  Further, one input part of the AND circuit D4 is connected to the output part of the inverter Iv4, and the other input part of the AND circuit D4 is connected to the output part of the comparator 16 and the input of the inverter Iv5. Each part is connected.

  One input part of the AND circuit D5 is connected to the output part of the inverter Iv5, and the other input part of the AND circuit D5 is connected to the power supply voltage VDD. The output units of the comparators 13 to 16 are output units of the quantizer 10.

  The output units of the AND circuits D1 to D5 are connected to be output to the selection unit sel of the control switch unit 18, respectively.

  FIG. 4 is an explanatory diagram illustrating a connection configuration between the selection unit sel and the switch units S1 and S4 in the control switch unit 18.

  The selection unit sel includes AND circuits D6 to D9, an OR circuit OR, and an inverter Iv6. One input part of the AND circuits D6 to D9 and the input part of the inverter Iv6 are connected to receive a reset signal (Lo signal active). This reset signal is output from, for example, either the reset terminal of the semiconductor integrated circuit device 1 or the control unit 6.

  Further, one input part of the OR circuit OR is connected to the output part of the inverter Iv6, and the logic circuit of the control circuit 17 is connected to the other input parts of the AND circuits D6 to D9 and the OR circuit OR. Connection is performed so that signals output from the product circuits D1 to D5 are input.

  Control terminals provided on the switches SW1 to SW5 of the switch unit S1 and the switches SW16 to SW20 of the switch unit S4 are connected to the output circuits of the logical product circuits D6 to D9 and the logical sum circuit OR. Although FIG. 4 shows the switch units S1 and S4, the other switch units S2 and S3 have the same connection configuration.

  The signals output from the logical product circuits D6 to D9 and the logical sum circuit OR become selection signals of the selection unit sel, and are arbitrarily selected so that the switches SW1 to SW5 and the switches SW16 to SW20 are in a conductive state.

  Next, the operation of the quantizer 10 provided in the A / D converter 5 in the present embodiment will be described using the flowchart of FIG. 5 and the operation explanatory diagrams of FIGS.

  First, at the start of operation (step S101), a reference voltage is input to each of the comparators 13-16. When the reset signal (Lo signal) is input to the selection unit sel, the Lo signal is output from the AND circuits D6 to D9, and the Hi signal is output from the OR circuit OR.

  As a result, as shown in FIG. 6, the switches SW3, SW8, SW13, and SW18 at the center of the switch sections S1 to S4 are turned on (conductive state), respectively, and the nodes SW3, SW8, SW13, and SW18 are connected to the nodes n3 and n4. , N5, and n6 (FIG. 3) are output as reference voltages to the comparators 13 to 16, respectively.

  Thereafter, an input signal of the input level L1 (FIG. 6) is input, and the comparators 13 to 16 compare the input signal with a reference voltage. In this case, as shown in the lower timing chart of FIG. 6, the clock signal input to the comparators 13 to 16 is input with the reference voltage and the voltage comparison is performed during the Hi signal period.

  The outputs of the comparators 13 to 16 output by the thermometer code are input to the control circuit 17, and the control circuit 17 sets the boundary between the temperature codes of “0” and “1” of the outputs from the comparators 13 to 16. 1 "is output (for example, the logical product circuit D4 in FIG. 6).

  Subsequently, signal processing is started (step S102). Here, the signal “1” output from the AND circuit D4 of the control circuit 17 is input to the selection unit sel. As a result, the output of the AND circuit D7 becomes a Hi signal, and as shown in FIG. 7, selection signals are output to the switch sections S1 to S4 so that the switches SW4, SW9, SW14, and SW19 are turned on.

  The switches SW4, SW9, SW14, and SW19 are switched, for example, during the Lo signal period of the clock signal as shown in the timing chart at the bottom of FIG.

  As described above, when the switches SW4, SW9, SW14, and SW19 are switched, the divided voltages of the nodes n4, n5, n6, and n7 (FIG. 3) are output as reference voltages to the comparators 13 to 16, respectively. The

  Thereby, only the optimum reference voltage near the boundary of the thermometer code corresponding to the input level L1 of the input signal is supplied to the comparators 13 to 16, and even with a small number of comparators 13 to 16, High-precision quantization is possible. In this case, the reference voltages respectively input to the comparators 13 to 16 are reduced by a voltage corresponding to 1 LSB (Least Significant Bit).

  Thereafter, when a new input signal is input (step S103), the process returns to step S102, and when a new input signal is not input, the process ends. Here, when a new input signal of the input level L2 is inputted, new “0” and “1” thermometer codes are formed in the comparators 13 to 16, as shown in FIG.

  The temperature code formed in the comparators 13 to 16 is input to the control circuit 17, and the control circuit 17 sets the boundary between the temperature codes of the outputs “0” and “1” in the comparators 13 to 16 to “1”. Output (for example, AND circuit D2 in FIG. 8).

  Subsequently, the signal processing in step S102 is started. When the signal “1” output from the AND circuit D2 is input to the selection unit sel, the output of the AND circuit D8 of the selection unit sel becomes a Hi signal, and the switches SW2 and SW7 are switched as shown in FIG. , SW12, SW17 are turned on.

  The switching of the switches SW2, SW7, SW12, and SW17 is performed, for example, during the Lo signal period of the clock signal as shown in the timing chart at the bottom of FIG.

  When these switches SW2, SW7, SW12, and SW17 are turned on, the divided voltages of the nodes n2, n3, n4, and n5 (FIG. 3) are output to the comparators 13 to 16 as reference voltages, respectively.

  As described above, it is possible to supply the optimum reference voltages to the comparators 13 to 16 in accordance with the input level of the input signal.

  Thereby, according to the first embodiment, since the number of comparators provided in the quantizer 10 can be reduced, the current consumption of the quantizer 10 can be reduced while reducing the layout area. be able to.

  Therefore, it is possible to reduce the size and power consumption of the semiconductor integrated circuit device 1 without degrading the performance of the semiconductor integrated circuit device 1.

(Embodiment 2)
FIG. 10 is an explanatory diagram illustrating a configuration example of a quantizer according to the second embodiment of the present invention, FIG. 11 is an explanatory diagram illustrating a configuration example of the comparator provided in FIG. 10, and FIG. FIG. 13 is an explanatory diagram following FIG. 12, FIG. 14 is an explanatory diagram following FIG. 13, FIG. 15 is an explanatory diagram following FIG. 14, and FIG. It is explanatory drawing which shows the comparison range of other quantizers.

  In the second embodiment, the A / D converter 5 includes a subtractor 8, an integrator 9, a quantizer 10, and a D / A converter 11 as in the first embodiment. The difference from the first embodiment is the configuration of the quantizer 10.

  As illustrated in FIG. 10, the quantizer 10 includes a reference voltage output circuit 19, a sleep control unit 20, comparators 21 to 28, a control circuit 29, and an encoder 30.

  The reference voltage output circuit 19 is provided with resistors R1 to R9, and these resistors R1 to R9 are connected in series between a positive (+) side reference voltage VREFP and a negative (−) side reference voltage VREFN. It becomes the composition.

  The sleep control unit 20 functioning as an operation control signal output unit is composed of NOR circuits 31 to 38 and AND circuits 39 to 45, and controls the sleep state / operation state of the comparators 21 to 28. Generate a control signal.

  The negative OR circuits 31 to 38 are each provided with five input sections (first input section to fifth input section), and the output sections of the negative OR circuits 31 to 38 are provided in the comparators 21 to 28. Connected to a sleep terminal slp that functions as an operation control terminal. The signals output from these NOR circuits 31 to 38 become control signals for controlling the sleep state / operating state of the comparators 21 to 28.

  A connection portion (node n1) between the resistors R1 and R2 is connected to one input portion of the comparator 21, and a connection portion between the resistors R2 and R3 is connected to one input portion of the comparator 22. (Node n2) is connected.

  One input portion of the comparator 23 is connected to a connection portion (node n3) between the resistors R3 and R4, and one input portion of the comparator 24 is connected to a connection portion between the resistors R4 and R5. Connected to (node n4).

  Similarly, one input portion of each of the comparators 25 to 28 has a connection portion between the resistors R5 and R6 (node n5), a connection portion between the resistors R6 and R7 (node n6), a resistor R7 and a resistor R8, Are connected to each other (node n7) and the connection between the resistor R8 and the resistor R9 (node n8). Further, the other input parts of the comparators 21 to 28 are connected so that the output signal from the integrator 9 is inputted.

  The output parts of the logical product circuit 42 are connected to the first input parts of the negative logical sum circuits 31 to 34, respectively, and the output of the logical product circuit 41 is connected to the first input parts of the negative logical sum circuits 35 to 38, respectively. Each part is connected.

  The output parts of the logical product circuit 43 are connected to the second input parts of the negative logical sum circuits 31 to 34, respectively, and the output of the logical product circuit 40 is connected to the second input parts of the negative logical sum circuits 35 to 38, respectively. Each part is connected.

  Further, the output parts of the logical product circuit 39 are connected to the third input parts of the negative logical sum circuits 31, 36 to 38, respectively, and the fourth input parts of the negative logical sum circuits 31, 32, 37, 38 are connected to the third input parts. Are connected to the output of the AND circuit 45.

  The output part of the logical product circuit 44 is connected to the fifth input part of the negative logical sum circuits 31 and 38 and the third input part of the negative logical sum circuits 32 and 33, respectively. The fifth input unit of the negative OR circuit 32, the fourth and fifth input units of the negative OR circuits 33 and 36, the third to fifth input units of the negative OR circuits 34 and 35, and the negative logic A reference potential VSS is connected to each of the fifth input portions of the sum circuit 37.

  The control circuit 29 that functions as a control unit includes AND circuits 46 to 52 and inverters 53 to 59. Input portions of the inverters 53 to 59 are connected to output portions of the comparators 21 to 27, respectively.

  The other inputs of the AND circuits 46 to 52 are connected to the outputs of the comparators 22 to 28, respectively, and one of the AND circuits 46 to 52 is connected to the outputs of the inverters 53 to 59. Input sections are connected to each other.

  The output units of these AND circuits 46 to 52 are connected to the input unit of the encoder 30. The encoder 30 encodes the signals output from the AND circuits 46 to 52 into parallel bit data and outputs the parallel bit data.

  Further, the other input section of the AND circuit 41 is connected to the output section of the AND circuit 46, and the other input section of the AND circuits 40 and 39 is connected to the output section of the AND circuits 47 and 48. Are connected to each other.

  Further, the other input parts of the AND circuits 44, 43 and 42 are connected to the output parts of the AND circuits 50, 51 and 52, respectively, and the AND circuit 45 is connected to the output part of the AND circuit 49. Is connected to the other input section.

  For example, a reset signal output from either the reset terminal of the semiconductor integrated circuit device 1 or the control unit 6 is connected to one input unit of the AND circuits 39 to 45.

  FIG. 11 is an explanatory diagram illustrating a configuration example of the comparator 21.

  The comparator 21 includes transistors Q1 to Q9, logical product circuits AND1 and AND2, negative logical sum circuits NOR1 and NOR2, and inverters Inv1 and Inv2. Transistors Q1, Q2, Q5 to Q7 are formed of, for example, a P-channel MOS (Metal Oxide Semiconductor), and transistors Q8, Q9 are formed of an N-channel MOS.

  A constant current source is connected to one connection portion of the transistors Q1 and Q2, and one connection portion of the transistors Q3 and Q4 is connected to the other connection of the transistors Q1 and Q2.

  The gate of the transistor Q1 is connected so that the reference voltage output from the reference voltage output circuit 19 is input, and the transistor Q2 is connected so that the output signal from the integrator 9 is input. Has been. The gates of the transistors Q3 and Q4 are sleep terminals slp, which are connected so that a control signal output from the sleep control unit 20 is input thereto.

  One connection portion of the transistor Q5 is connected so that the power supply voltage VCC is input, and one connection portion of the transistors Q6 and Q7 is connected to the other connection of the transistor Q5. The gate of the transistor Q5 is connected to receive a clock signal.

  One connection portion of the transistors Q8 and Q9 is connected to the other connection portion of the transistors Q6 and Q7, and the power supply voltage VEE is connected to each other. The other connection portion of the transistor Q7 is connected to the gate of the transistor Q6, and the other connection portion of the transistor Q6 is connected to the gate of the transistor Q7.

  The other connection portion of the transistor Q6 is connected to one input portion of the AND circuit AND1, and the other connection portion of the transistor Q7 is connected to one input portion of the AND circuit AND2.

  The other input sections of the AND circuits AND1 and AND2 are also connected to the sleep terminal slp so that a control signal output from the sleep control section 20 is input thereto. The output part of the AND circuit AND1 is connected to one input part of the NOR circuit NOR1, and the output part of the AND circuit AND2 is connected to the other input part of the NOR circuit NOR2. Yes.

  The output part of the NOR circuit NOR1 is connected to one input part of the NOR circuit NOR2 and the input part of the inverter Ivn1, respectively. The output part of the NOR circuit NOR2 is connected to a negative OR circuit. One input portion of NOR1 and the input portion of inverter Ivn2 are connected to each other. The output unit of the inverter Ivn2 is the output unit of the comparator 21.

  When a control signal (Lo signal) is output from the sleep control unit 20, the transistors Q3 and Q4 are turned off, and the outputs of the AND circuits AND1 and AND2 are fixed to the Lo signal, so that the comparator 21 enters the sleep state. Further, since the outputs of the AND circuits AND1 and AND2 are fixed to the Lo signal, the output signal in the comparator 21 when the control signal is input is held.

  In addition, although the structural example of the comparator 21 was shown in FIG. 11, it is the same structure also about the other comparators 22-28.

  Next, the operation of the quantizer 10 according to the second embodiment will be described with reference to a flowchart (FIG. 5), FIGS. 12 to 15, and an explanatory diagram showing a comparison range of the quantizer 10 of FIG.

  First, at the start of operation, all the comparators 21 to 28 in the quantizer 10 are turned on (step S101). In this case, a reset signal (Lo signal) is input, and as shown in FIG. 12, control signals (Hi signals) for turning on the comparators 21 to 28 are output from the NOR circuits 31 to 38, respectively.

  This process is performed during the Hi signal period of the clock signal input to the comparators 21 to 28, as shown in the timing chart at the bottom of FIG.

  In this state, for example, when an input signal of the input level L3 (FIG. 12) is input, the comparators 21 to 28 compare the input signal with a reference voltage, and a thermometer code corresponding to the input signal is output. Is done. Here, as shown in the state J1 of FIG. 16, all the comparators 21 to 28 are in an operating state.

  Subsequently, signal processing is performed (step S102). The thermometer codes that are the comparison results of the comparators 21 to 28 are output to the AND circuits 46 to 52 of the control circuit 29, respectively. Then, the control circuit 29 outputs the boundary of the thermometer code of the AND circuits 46 to 52 as “1”.

  Subsequently, the signal “1” output from the control circuit 29 is output to the sleep control unit 20. As shown in FIG. 13, the sleep control circuit 20 turns on the comparators 23 to 26 to which the reference voltage corresponding to the input level L3 of the input signal is input, and turns on the other comparators 21, 22, 27, and 28. A control signal for setting the sleep state is output. This process is performed during the Lo signal period of the clock signal input to the comparators 21 to 28, as shown in the lower timing chart of FIG.

  Thereby, the comparator group in the range shown in the state J2 of FIG. 16 according to the input level L3 of the input signal operates.

  Thereafter, when a new input signal is input (step S103), the process returns to step S102, and when a new input signal is not input, the process ends. For example, when a new input signal of the input level L4 is input, as shown in FIG. 14, the comparators 21 to 28 corresponding to the input level L4 output a new thermometer code of “1”. . The operation state of the comparator group at this time is the state J3 in FIG. 16, which is the same as the state J2.

  Then, the signal of “1”, which is the temperature code of the boundary output from the control circuit 29, is output to the sleep control unit 20, and a reference voltage corresponding to the input level L4 of the input signal is input as shown in FIG. The comparators 24 to 27 are turned on, and control signals for causing the other comparators 21 to 23 and 28 to be in the sleep state are output. As a result, the operation state of the comparator group becomes the state J4 in FIG. 16, and only the comparator group optimum for the input level L4 is turned ON.

  Thereby, according to the second embodiment, any of the comparators 21 to 28 can be selected and operated according to the input level of the input signal, so that the current consumption of the A / D converter 5 is reduced. be able to.

  Therefore, low power consumption can be realized without degrading the performance of the semiconductor integrated circuit device 1.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for an A / D converter provided in a semiconductor integrated circuit device or the like.

1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a block diagram of an A / D converter provided in the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing which shows the structural example of the quantizer provided in the A / D converter of FIG. It is explanatory drawing which shows the connection structure of the control switch part provided in the quantizer of FIG. It is a flowchart which shows the example of an operation process in the quantizer of FIG. It is explanatory drawing which shows the operation example in the quantizer of FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing which shows the structural example of the quantizer by Embodiment 2 of this invention. It is explanatory drawing which shows the structural example of the comparator provided in FIG. It is explanatory drawing which shows the operation example in the quantizer of FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing which shows the comparison range of the quantizer of FIG.

Explanation of symbols

1 Semiconductor Integrated Circuit Device 2 CPU
3 Memory 4 Signal Switching Unit 5 A / D Converter 6 Control Unit 7 Register 8 Subtractor 9 Integrator 10 Quantizer 11 D / A Converter 12 Reference Voltage Output Circuits 13 to 16 Comparator 17 Control Circuit 18 Control Switch Unit 19 Reference voltage output circuit 20 Sleep control unit 21-28 Comparator 29 Control circuit 30 Encoder 31-38 NAND circuit 39-45 AND circuit B Bus RR Resistance unit R1-R9 Resistance sel Selection unit S1-S4 Switch unit SW1 ˜SW20 switches D1 to D9 AND circuits AND1, AND2 AND circuits Iv1 to Iv6 inverter OR OR circuits Q1 to Q9 transistors NOR1, NOR2 NOT OR circuits Inv1, Inv2 inverter slp sleep terminal

Claims (8)

A semiconductor integrated circuit device including an A / D converter that converts an analog signal into a digital signal,
The A / D converter is
An integrator for integrating a difference signal between the input signal and the feedback signal;
A quantizer that converts the signal output from the integrator into a digital signal and quantizes the digital signal;
A D / A converter that converts the digital signal output from the quantizer into an analog signal and feeds back the analog signal;
The quantizer is
A reference voltage output unit for generating a plurality of reference voltages;
A plurality of comparators that compare the reference voltage generated by the reference voltage output unit and the input signal, and output the comparison result with a thermometer code;
A reference voltage supply control unit that selects an arbitrary reference voltage corresponding to an input level of an input signal based on a thermometer code output from the comparator and supplies the selected reference voltage to the comparator; Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1.
The reference voltage supply controller is
A reference voltage selection unit that selects an arbitrary reference voltage generated by the reference voltage output unit based on a selection control signal and outputs the selected reference voltage to the comparator;
Selection control for detecting a boundary of a thermometer code output from the comparator, generating a selection control signal for supplying a reference voltage near the boundary of the thermometer code to the comparator, and outputting the selection control signal to the reference voltage selection unit A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1 or 2,
2. The semiconductor integrated circuit device according to claim 1, wherein the quantizer comprises a flash type A / D conversion circuit. The semiconductor integrated circuit device according to any one of claims 1 to 3,
The A / D converter is
A semiconductor integrated circuit device which is a delta-sigma modulation circuit. A semiconductor integrated circuit device comprising an A / D converter for converting an analog signal into a digital signal,
The A / D converter is
An integrator for integrating a difference signal between the input signal and the feedback signal;
A quantizer that converts the signal output from the integrator into a digital signal and quantizes the digital signal;
A D / A converter that converts the digital signal output from the quantizer into an analog signal and feeds back the analog signal;
The quantizer is
A reference voltage output unit for generating a plurality of reference voltages;
A plurality of comparators that compare the reference voltage generated by the reference voltage output unit and the input signal, and output the comparison result with a thermometer code;
Based on the thermometer code output by the comparator, the comparator to which an arbitrary reference voltage corresponding to the input level of the input signal is supplied is selected and operated, and the operation of the unselected comparator is stopped. An operation control signal to be generated and output to the comparator,
The comparator is
A semiconductor integrated circuit device comprising an operation control terminal, wherein an operation state and a stop state are controlled based on an operation control signal input to the operation control terminal. The semiconductor integrated circuit device according to claim 5.
The operation controller is
A control signal for detecting a boundary of a thermometer code output from the comparator, operating the comparator supplied with a reference voltage in the vicinity of the boundary of the thermometer code, and stopping the other comparators A control unit for generating and outputting
A semiconductor integrated circuit device comprising: an operation control signal output unit that outputs an operation control signal to the comparator based on a control signal output from the control unit. The semiconductor integrated circuit device according to claim 5 or 6,
2. The semiconductor integrated circuit device according to claim 1, wherein the quantizer comprises a flash type A / D conversion circuit. The semiconductor integrated circuit device according to any one of claims 5 to 7,
The A / D converter is
A semiconductor integrated circuit device which is a delta-sigma modulation circuit.

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