JP2009064857A - Semiconductor integrated circuit and pattern layout method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of forming a TEG pattern by preventing that the monitoring result has an error without reducing the monitored items and without making the width of the scribing region larger by utilizing a dummy pattern. <P>SOLUTION: The semiconductor integrated circuit includes a plurality of function modules formed in a chip, and a functional dummy pattern 5 formed in the peripheral vacant region 3 of a predetermined function module 2 in the chip and having an aberration monitoring function, and the functional dummy pattern 5 is formed by that a band-shaped metal portion B and a band-shaped insulating film portion L are periodically repeated respectively in the plan view. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a functional dummy pattern and a pattern layout method thereof, and in particular, manufacturing of a microdevice such as a semiconductor element, a liquid crystal display element, an image pickup element (CCD: Charge-Coupled Device) and a thin film magnetic head. It relates to technology that can be applied.

  Conventionally, when manufacturing a semiconductor integrated circuit (LSI), a projection exposure apparatus that projects a pattern image of a photomask onto a substrate such as a wafer or a glass plate coated with a photoresist via a projection optical system. Is used.

  Many types of patterns are arranged in the LSI. In addition to various functional module patterns, other patterns such as a mark / scribe TEG pattern and a dummy pattern are arranged, and each plays an important role. The TEG (Test Elementary Group) is an element circuit that is prototyped for the purpose of verifying the transistor structure and circuit system, and grasping the performance.

  Dummy patterns are placed in extra space inside and outside of LSI chips and wafers to improve uniformity of LSI chip and wafer pattern occupancy in chemical mechanical polishing (CMP) and dry etching processes. It is. Since the dummy pattern 7 plays its role as long as its occupation ratio is within a predetermined range, its shape and size may be arbitrary, and therefore it is not necessary to have a complicated shape, as shown in FIG. Rectangular patterns of several sizes are prepared and arranged in the gaps between the functional modules 2 such as RAM and analog, and inside and outside the LSI product. In addition, the dummy pattern does not affect the function and performance of the LSI, but the effect of improving the uniformity can eliminate variations in the characteristics of each functional module and element of the LSI. This pattern is indispensable for ensuring reliability (Patent Document 1).

  A scribe area for dicing is provided at the periphery of the conventional LSI. Scribe TEG patterns such as side monitors, alignment marks, and resolution charts are arranged in the scribe area, and the finished condition when the LSI is manufactured is monitored by these TEG patterns. These TEG patterns do not affect the function and performance of the LSI in the past, but manage whether the manufacturing equipment is operating normally. If an abnormality occurs, the TEG patterns are inspected immediately. In order to prevent the spread of damage to other LSIs, or to relieve or redo if possible, this pattern is indispensable in the current LSI manufacturing process.

JP 2000-294730 A

  The scribe TEG pattern was not a big problem in the generation where there were few items to be monitored and the scribe TEG pattern could be sufficiently arranged if there was an area for the scribe region. However, in recent LSIs, since various types of functional modules such as memory, logic, analog, and sensor are formed on one chip, the types of elements such as transistors, diodes, resistors, capacitors, and inductors used are dramatically increased. Accordingly, the items to be monitored by the scribe TEG pattern are also increasing.

  Of course, in order to monitor many items, many scribe TEG patterns are required, but recently, it is not possible to arrange all the scribe TEG patterns only in the scribe area.

  For this reason, it is necessary to take measures such as reducing items to be monitored or expanding the width of the scribe area. In this case, the following problems 1-3 occur. 1. If the number of items to be monitored is reduced, process management becomes inadequate and process device abnormality detection is neglected. 2. When the width of the scribe region is increased, the area that can be used as a product is reduced, so that the number of products that can be taken from one wafer is reduced, and the manufacturing cost of the product is increased. 3. When the scribe TEG pattern is arranged in the scribe area, the position of the scribe TEG pattern (monitor position) is a position away from the position of the element to be monitored, and therefore an error is always included in the monitor result.

  In addition, some functional modules mounted on an LSI are easily affected by electromagnetic noise and electrical noise. Therefore, it is necessary to provide such a functional module with an electromagnetic noise cutoff circuit and an electrical noise cutoff circuit. However, if the functional module itself is equipped with an electromagnetic noise cutoff circuit or an electrical noise cutoff circuit, the functional module will become larger and it will be difficult to secure space in the chip. It wasn't.

  The present invention has been made in view of such a situation. First, by using a dummy pattern, it is possible to reduce the number of monitor items without increasing the width of the scribe area, and to obtain a monitor result. An object of the present invention is to provide a semiconductor integrated circuit capable of forming a TEG pattern while preventing errors from being included, and a layout design method thereof.

  Secondly, by using a dummy pattern, a semiconductor integrated circuit capable of taking electromagnetic noise blocking measures and electric noise blocking measures for functional modules without newly securing a space for blocking electromagnetic noise and electric noise. An object is to provide a layout design method.

  In order to solve the above-described problem, the first embodiment of the present invention has a plurality of functional modules formed in a chip and an empty area around a predetermined functional module in the chip and has an aberration monitoring function. The functional dummy pattern is formed by periodically repeating a band-shaped metal part and a band-shaped insulating film part in plan view.

  According to the semiconductor integrated circuit configured as described above, the functional dummy pattern having the aberration monitoring function is formed in the empty area around the predetermined functional module in the chip. A TEG pattern for monitoring an aberration can be formed without reducing monitor items for the aberration monitor and without increasing the width of the scribe area. In addition, since the functional dummy pattern is formed in an empty area around a predetermined functional module in the chip, it can be arranged around the functional module to be monitored (that is, immediately adjacent), and the monitor result has an error as in the conventional case. It can be prevented from being included.

Embodiment 1 FIG.
FIG. 1 shows an example of a floor plan of a semiconductor integrated circuit according to this embodiment. As shown in the figure, the semiconductor integrated circuit 10 according to this embodiment is formed in a chip shape, and the chip 1 has a plurality of functional modules 2 such as a memory (RAM, ROM), analog, logic, I / O and the like. A scribe region 4 in which a scribe TEG pattern is formed is formed on the periphery of the chip so as to surround these functional modules 2.

  An empty area 3 is generated between the functional modules 2. The empty area 3 is an area necessary for exchanging signals between the functional modules 2 or preventing signal interference, but is generally adjusted to be as small as possible. Yes. However, since this empty area 3 cannot be completely eliminated, it occurs to some extent.

  In this empty area 3, a functional dummy pattern 5 having a special function is formed. Thereby, the uniformity of the pattern occupancy ratio of the chip 1 (pattern occupancy ratio of the functional module 2 and the functional dummy pattern 5 combined) is improved. The empty area 3 is preferably optimized by prioritizing the size reduction of the chip 1 rather than forming the functional dummy pattern 5.

  Here, the functional dummy pattern 5 is formed as a functional dummy pattern having an aberration monitoring function. More specifically, as shown in FIG. 4, the functional dummy pattern 5 includes a strip-shaped metal portion (dark portion) B and a strip-shaped insulating film portion (bright portion) L that are periodically repeated with the same width. It is formed.

  In FIG. 4, this functional dummy pattern 5 is formed in the empty area 3 around the functional module (for example, SRAM module) 2 to be monitored for aberration, and the periodic direction is the horizontal direction (with the functional module 2 to be monitored for aberration). Functional dummy patterns 5a, 5b, and 5c in which the periodic pitch P is relatively large, medium, and small in the direction orthogonal to the opposite direction (y direction) (x direction), and the periodic direction is the vertical direction Functional dummy patterns 5d, 5e, and 5f that are changed in a direction parallel to the functional module 2 to be monitored for aberration (a direction parallel to the y-direction) and the periodic pitch P is relatively large, medium, and small. Illustrated.

  Each functional dummy pattern 5a-5f may be treated as one functional dummy pattern 5, or each of the functional dummy patterns 5a-5f (generally a plurality of functions with different periodic directions and periodic pitches). Functional dummy patterns) may be collectively handled as one functional dummy pattern 5.

  As for aberrations, there are cases where the behavior of aberrations differs in the horizontal and vertical directions, such as astigmatism and coma, so the functional dummy pattern 5 having the horizontal and vertical directions as described above is required. It is.

  Such a functional dummy pattern 5 is, for example, an empty area around a functional module (that is, a functional module in which lens aberration is a problem) 2 that utilizes the symmetry of the layout of flip-flops, differential elements, and the like, such as an SRAM. 3 is formed. At this time, the functional dummy pattern 5 is formed in the periphery (that is, immediately adjacent) of the functional module 2 by allowing the mask pattern to coexist in an empty area of the mask for the semiconductor integrated circuit 10.

  In this way, by forming the functional dummy pattern 5 in the empty area 3 in the chip 1, it is possible to directly check the causal relationship between the defect of the semiconductor integrated circuit 10 and the aberration of the optical system. For example, if an SRAM circuit or memory cell that requires pattern symmetry is transferred using an optical system that retains coma and astigmatism, the pattern finish becomes asymmetrical and circuit operation using flip-flops becomes unstable. However, if the functional dummy pattern 5 is immediately adjacent to the SRAM, the causal relationship between the two can be immediately quantified and measures can be taken. At the same time, the pattern occupancy in the chip 1 can be adjusted by the functional dummy pattern 5.

  According to the semiconductor integrated circuit 10 configured as described above, the functional dummy pattern 5 having the aberration monitoring function is formed in the empty area 3 around the predetermined functional module 2 in the chip 1. By using this, it is possible to form an aberration monitor TEG pattern without reducing the number of aberration monitor items and without increasing the width of the scribe region.

  Further, since the functional dummy pattern 5 is formed in the empty area 3 around the predetermined functional module 2 in the chip 1, it can be arranged around the functional module to be monitored, and the monitoring result includes an error as in the conventional case. Can be prevented.

  Further, since the functional dummy pattern 5 is formed by periodically repeating the band-shaped metal portion B and the band-shaped insulating film portion L in plan view, it has the function of an aberration monitor while functioning as a dummy pattern. Can be made.

Embodiment 2. FIG.
The semiconductor integrated circuit 10 according to this embodiment uses a functional dummy pattern 5B having an electric noise blocking function instead of the functional dummy pattern 5 having an aberration monitoring function in the first embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

  The functional dummy pattern 5B of this embodiment is composed of a first periodic pattern 5Ba and a second periodic pattern 5Bb as shown in FIG. In both the first and second periodic patterns 5Ba and 5Bb, the strip-shaped metal portion (dark portion) B and the strip-shaped insulating film portion (bright portion) L are periodically repeated with the same width (width ratio of 1: 1). Is formed. The periodic pitch P2 of the second periodic pattern 5Bb is set to a periodic pitch different from the periodic pitch P1 of the first periodic pattern 5Ba (that is, the spatial frequency ν2 of the second periodic pattern 5Bb is the first periodic pattern 5Bb). It is set to a spatial frequency different from the spatial frequency ν1 of the pattern 5Ba). Both the first and second periodic patterns 5Ba and 5Bb have their periodic directions aligned with the opposing direction (x direction) of the functional module (for example, an analog module) 2 that is the object of electrical noise interruption, and the functional module 2 and each other. Are arranged in parallel along the opposite direction.

  Each of the first and second periodic patterns 5Ba and 5Bb has a characteristic of passing only electrical noise having a frequency matching the spatial frequencies ν1 and ν2 (ν1 ≠ ν2) in the periodic direction. This functional dummy pattern 5B has such a periodic pattern 5Ba, 5Bb arranged in parallel along the facing direction of the functional module 2 that is the object of electrical noise interruption as shown in FIG. The electric noise propagating to 2 is completely cut off. From the definition of Fourier transform, when the metal part B and the insulating film part L have a periodic pattern with a width ratio of 1: 1, only odd-order harmonics are generated as high-order harmonics.

  The functional dummy pattern 5B is formed, for example, in the empty area 3 around the memory, analog, or high frequency element. Here, the functional dummy pattern 5B is formed immediately adjacent to the functional module 2 that is the object of electrical noise interruption by allowing the mask pattern to coexist in an empty area of the mask for the semiconductor integrated circuit 10.

  In this embodiment, for example, a case is assumed in which a soft error accompanying electric pulse noise due to cosmic rays (α rays or neutron rays) occurs. Generally, electric pulse noise is a white state including all frequency components when Fourier frequency decomposition is performed. Therefore, the electric pulse noise always has a noise component that matches the spatial frequency ν1 of a certain periodic dummy pattern. The noise component of ν1 passes through the periodic dummy pattern without being blocked. This causes a fatal error for analog and high frequency devices.

  However, if another periodic dummy pattern having a spatial frequency ν2 different from the noise component of ν1 is present near the periodic dummy pattern having the spatial frequency ν1, the periodic dummy pattern having the spatial frequency ν1 is passed. The noise component ν1 is blocked without passing through the periodic dummy pattern having the spatial frequency ν2. On the contrary, the noise component of ν2 is blocked without passing through the periodic dummy pattern having the spatial frequency ν1. Therefore, even if the electric pulse noise is white noise, there is no noise component that is ν1 and ν2 at the same time, and therefore the first and second periodic patterns 5Ba and 5Bb are arranged in parallel as in this embodiment. If placed, it can be completely blocked. Further, as the first and second periodic patterns 5Ba and 5Bb, if a one-to-one periodic pattern with a width ratio (width ratio between the metal part B and the insulating film part L) in which harmonics are generated only in odd order is selected. , The possibility that harmonics match each other is reduced. If two or more types of periodic patterns 5Ba and 5Bb having a width ratio of 1: 1 are arranged on the noise propagation path as in this embodiment, soft error propagation prevention and high-frequency noise interruption are achieved in analog and high-frequency elements. The pattern occupancy can be adjusted.

  A soft error is a phenomenon in which a memory chip or the like in an electronic device malfunctions for some reason. Unlike a "hard error" that causes fatal damage to the circuit, it is temporary and does not cause immediate failure. There are several possible causes for soft errors, but secondary cosmic rays reaching the ground are thought to be the major cause. Among the cosmic rays that reach the ground, α-rays with electric charges, etc., cause a memory error because they disturb the value of the amount of electric charge stored in the memory cells when they collide with the memory cells. In addition, neutron beams or the like having no electric charge destroy the substrate atoms when colliding with the silicon substrate of the memory, and cause memory errors due to the ions generated by the energy at that time.

  According to the semiconductor integrated circuit 10 configured as described above, the functional dummy pattern 5B having the electric noise blocking function is formed in the empty area 3 around the predetermined functional module 2 in the chip 1, so that the dummy By using the pattern, it is possible to take an electrical noise blocking measure for the functional module 2 without newly securing a space for blocking the electrical noise.

  The functional dummy pattern 5B has first and second periodic patterns 5Ba and 5Bb, and both the first and second periodic patterns 5Ba and 5Bb have a band-shaped metal portion B and a band-shaped insulating film in plan view. The portion L is formed by being periodically repeated with the same width, and the periodic pitch P2 of the second periodic pattern 5Bb is set to a periodic pitch different from the periodic pitch P1 of the first periodic pattern 5Ba. The second periodic patterns 5Ba and 5Bb are arranged in parallel along the opposing direction of the functional module 2 that is the target of electromagnetic noise shielding, and the periodic direction of each of the second periodic patterns 5Ba and 5Bb is matched with the opposing direction of the functional module 2 that is the subject of electromagnetic noise shielding. Therefore, it is possible to provide a function of blocking electric noise while functioning as a dummy pattern.

Embodiment 3 FIG.
The semiconductor integrated circuit 10 according to this embodiment uses a functional dummy pattern 5C having a magnetic noise blocking function instead of the functional dummy pattern 5 having an aberration monitoring function in the first embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

  As shown in FIG. 6, the functional dummy pattern 5C of this embodiment is configured by an annular pattern including one or a plurality of annular metal portions B in plan view. The portion L other than the metal portion B is formed of an insulating film. In FIG. 6, as an example of the functional dummy pattern 5 </ b> C, the functional dummy pattern 5 </ b> Ca is configured by one planar-view square annular metal portion B, and two concentric two-planar square annular metal portions B are configured. A dummy pattern 5Cb and a dummy pattern 5Cc composed of one rectangular metal portion B in plan view are shown.

  When the magnetic pulse noise C passes through the ring portion R, the functional dummy pattern 5C blocks the electromagnetic pulse noise C due to the Faraday electromagnetic induction effect generated in the metal portion B at that time.

  Note that Faraday's electromagnetic induction is a phenomenon in which a potential difference (voltage) occurs in a conductor that exists in an environment in which magnetic flux fluctuates. Further, according to Lenz's law, it is known that an electromotive force generated in a circuit is generated in such a direction that a magnetic flux generated by a current flowing through the circuit due to the electromotive force opposes a given magnetic flux change.

  For example, when the semiconductor integrated circuit 10 includes a magnetic sensor module, the functional dummy pattern 5C is formed in the empty area 3 around the functional module 2 other than the magnetic sensor module. In the empty area 3 around the magnetic sensor module, a dummy pattern having no magnetic noise blocking function is formed so as not to prevent the magnetic detection of the magnetic sensor module.

  There are mainly three types of magnetic sensors. MR (magneto-resistive) elements, MI (magneto-impedance) elements, and Hall elements. The MR element utilizes the MR effect of a soft metal magnetic material such as permalloy (NiFe) whose resistance value changes with an external magnetic field strength change, for example. The MI element utilizes the MI effect of an amorphous wire whose impedance changes when the external magnetic field changes. At that time, a pulse current is allowed to flow through the wire. The Hall element measures a change in an external magnetic field by detecting a potential difference generated by the Hall effect of a semiconductor.

  According to the semiconductor integrated circuit 10 configured as described above, the functional dummy pattern 5C having a magnetic noise blocking function is formed in the empty area 3 around the predetermined functional module 2 in the chip 1. By using the pattern, it is possible to take a magnetic noise blocking measure for the functional module 2 without newly securing a space for blocking the magnetic noise.

  Moreover, since the functional dummy pattern 5C is configured by an annular pattern including one or a plurality of annular metal portions B in plan view, the function dummy pattern 5C can have a function of blocking magnetic noise while functioning as a dummy pattern.

Embodiment 4 FIG.
The semiconductor integrated circuit 10 according to this embodiment uses a functional dummy pattern 5D having an alignment measurement function instead of the functional dummy pattern 5 having an aberration monitoring function in the first embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

  As shown in FIG. 7, the dummy pattern 5D of this embodiment is composed of a main scale pattern 5m and a sub-scale pattern 5n formed in the empty area 3 in the chip 1.

  Both the main scale pattern 5m and the sub-scale pattern 5n are formed by periodically repeating a band-shaped metal part (dark part) B and a band-shaped insulating film part (bright part) L, for example, with the same width in plan view. Yes. The periodic pitch P4 of the vernier pattern 5n is set to a periodic pitch different from the periodic pitch P3 of the main scale pattern 5m. The main scale pattern 5m and the sub-scale pattern 5n are formed adjacent to each other in a direction orthogonal to the periodic direction in plan view. In FIG. 7, the functional dummy pattern 5Da whose periodic direction is directed in the direction (y direction) orthogonal to the facing direction to the functional module (for example, SRAM module) 2 that is the alignment measurement target, and the function whose periodic direction is the alignment measurement target A functional dummy pattern 5Db oriented in the direction facing the module 2 (x direction) is illustrated.

  This functional dummy pattern 5D allows the mask pattern of the main scale pattern 5m to coexist in the empty area 3 on one of the masks for forming the functional module 2 to be subjected to alignment measurement, while the sub-scale The mask pattern of the pattern 5n is formed together with the functional module 2 to be subjected to the alignment measurement by coexisting in the empty area 3 on another mask among the masks for forming the functional module 2 to be subjected to the alignment measurement. Is done. Then, after the functional dummy pattern 5D is formed, by measuring the width of the main scale pattern 5m and the vernier pattern 5n in the periodic direction, the portion of the functional module 2 formed with the same mask as the main scale pattern 5m The alignment with another part of the functional module 2 formed with the same mask as the vernier pattern 5n can be appropriately measured.

  The functional dummy pattern 5D is formed, for example, in the empty area 3 around the functional module 2 where the overlay accuracy is a problem. For example, when measuring the alignment between the via and the metal wiring, for example, the mask pattern of the main scale pattern 5m is allowed to coexist in the vacant area 3 of the mask for forming the via, while the vacant of the mask for forming the metal wiring is used. The main scale pattern 5m and the vernier pattern 5n are formed together with the via and the metal wiring in the region 3 with the mask pattern of the vernier pattern 5n coexisting. Then, the alignment between the via and the metal wiring is measured by measuring the shift width in the periodic direction between the main scale pattern 5m and the vernier pattern 5n.

  In this functional dummy pattern 5D, as described above, the mask pattern of the main scale pattern 5m and the mask pattern of the vernier pattern 5n need to coexist in different masks, so that this functional dummy pattern 5D is formed. In each of the masks for forming the semiconductor integrated circuit 10, two or more masks need to have the empty area 3 in the same place.

  In this manner, by forming the functional dummy pattern 5D in the empty area 3 in the chip 1, it is possible to directly check whether or not there is a causal relationship between the defect of the semiconductor integrated circuit 10 and the alignment error. For example, if an alignment error occurs during the transfer of the formation process of vias and multilayer wiring that require high-precision overlay, the circuit operation becomes unstable, but there is a functional dummy around these vias and multiple wirings. If there is the pattern 5D, the causal relationship between the two can be immediately quantified and measures can be taken. At the same time, the pattern occupancy in the chip 1 can be adjusted by the functional dummy pattern 5D.

  According to the semiconductor integrated circuit 10 configured as described above, since the functional dummy pattern 5D having the alignment measurement function is formed in the empty area 3 in the chip 1, the alignment measurement is performed by using the dummy pattern. TEG patterns for alignment measurement can be formed without reducing the number of monitor items and without increasing the width of the scribe region.

  Further, since the functional dummy pattern 5D is formed in the empty area 3 around the predetermined functional module 2 in the chip 1, it can be arranged around the functional module 2 to be subjected to the alignment measurement, and the monitor result has a conventional error. Can be prevented from being included.

  The functional dummy pattern 5D has a main scale pattern 5m and a vernier pattern 5n. The main scale pattern 5m and the vernier pattern 5n are both a band-shaped metal portion B and a band-shaped insulating film portion L in plan view. Are periodically repeated with the same width, the periodic pitch P4 of the vernier pattern 5n is set to a different periodic pitch from the periodic pitch P3 of the main metric pattern 5m, and the main metric pattern 5m and the vernier pattern 5n are Since they are arranged adjacent to each other in the direction orthogonal to the periodic direction in plan view, it is possible to provide an alignment measurement function while functioning as a dummy pattern.

  In this embodiment, the main scale pattern 5m and the vernier pattern 5n are configured by a pattern in which the strip-shaped metal portion B and the strip-shaped insulating film portion L are periodically repeated. A metal vernier pattern for inspection or a rectangular pattern made of metal may be used.

  Vernier (vernier scale, vernier scale, Vernier Scale) is attached to calipers and the like and assists in reading numerical values below the minimum scale. In many cases, the scale is set at intervals of 9/10 or 19/20 of the main scale (main scale), and the zero point of the vernier is aligned with the measurement point, and the scale of the main scale and the vernier scale coincide. Can be measured in units of 1/10 or 1/20.

Embodiment 5 FIG.
The semiconductor integrated circuit 10 according to this embodiment uses a functional dummy pattern 5E having a timing measurement function instead of the functional dummy pattern 5 having an aberration monitoring function in the first embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

  As shown in FIG. 8, the functional dummy pattern 5E according to this embodiment is configured by a ring oscillator in which an inverter 5p is connected in an odd-numbered manner and input and output are connected in a loop.

  In the ring oscillator, for example, when an odd number of inverters are connected in cascade and input and output are connected in a loop, a logical value obtained by inverting the original input logical value is returned to the input, and the input is inverted. In this way, in the odd-numbered cascade connection loop circuit of the inverter, the inversion of the input is repeated indefinitely, so it is called a ring oscillator (ring oscillator). Since the oscillation period of the ring oscillator is considered to be the time for which the logical value goes around the loop, if the average delay time of the inverter is td, the oscillation period of the N-stage ring oscillator is given by T = 2 · td · N It is done. If the oscillation period is measured, the average delay time of the inverter can be obtained, so that it can be used for evaluation of the manufacturing process.

  The functional dummy pattern 5E is formed at a plurality of locations in the empty area 3 in the chip 1 (for example, an empty area 3a surrounded by analog modules and an empty area 3b surrounded by ROM / RAM). Note that the same functional dummy pattern 5E is formed at each location. This functional dummy pattern 5E is formed in the empty area 3 in the chip 1 by coexisting the mask pattern in the empty area 3 on the mask for forming the semiconductor integrated circuit 10.

  Since the ring oscillator cannot be formed with only one mask, in order for the mask pattern of this functional dummy pattern 5E to coexist in the empty area 3 on the mask for forming the semiconductor integrated circuit 10, of the masks. In all the masks other than the mask for forming the multilayer wiring, it is necessary that the empty area 3 exists in the same place.

  In this manner, by forming the functional dummy patterns 5E at a plurality of locations in the empty area 3 in the chip 1, it is possible to directly check the causal relationship between each location in the chip 1 and the signal propagation capability. . For example, the vacant area 3a generally surrounded by an analog module having a low pattern density and the vacant area 3b surrounded by a ROM / RAM having a high pattern density vary in the fine processing finish in the CMP process or the dry etching process. Occurs. Such process variations cause variations in the resistance and capacitance of the multilayer wiring. Therefore, if the functional dummy pattern 5E is formed in these empty spaces 3a and 3b, the causal relationship among process variations, resistance and capacitance fluctuations, and signal timing deviations can be immediately quantified, and measures should be taken. Can do. At the same time, the pattern occupancy in the chip 1 can be adjusted by the functional dummy pattern 5E.

  According to the semiconductor integrated circuit 10 configured as described above, a plurality of functional dummy patterns 5E having a timing measurement function are formed at a plurality of locations in the vacant area 3 in the chip 1. Therefore, the dummy patterns are used. Thus, a TEG pattern for timing measurement can be formed without reducing monitor items for timing measurement and without increasing the width of the scribe area.

  Since the functional dummy pattern 5E is composed of a ring oscillator, it can have a timing measurement function while functioning as a dummy pattern.

Embodiment 6 FIG.
This embodiment is a pattern layout method for laying out a pattern of the semiconductor integrated circuit 10 according to Embodiment 1-5. The pattern layout method for the semiconductor integrated circuit according to this embodiment will be described below with reference to FIGS.

  In step S1, a layout pattern of a semiconductor integrated circuit (in which a functional dummy module is not yet formed) 10s having a plurality of functional modules 2 mounted in the chip 1 as shown in FIG. Create design data.

  In step S2, a well-known hierarchical process and a well-known graphic operation are performed on the design data of the semiconductor integrated circuit 10s to create drawing data for each mask.

  In step S3, the occupation area of each functional module 2 is widened (oversized) by a predetermined width for each mask for the drawing data of the semiconductor integrated circuit 10s, and the occupation area of each functional module 2 after the widening process is obtained. Ask. In this way, an occupation area of each functional module 2 is obtained after securing a safe distance between adjacent functional modules 2, and the remaining area in the chip 1 of the semiconductor integrated circuit 10 s is set as an empty area 3. .

  In step S4, the empty area 3 in the chip 1 of the semiconductor integrated circuit 10 is obtained based on the result of step S3. At that time, each free area 3 is obtained by identifying how many masks the obtained free areas 3 are shared in common. As a result, it is possible to obtain the empty area 3 with only one mask, the empty area 3 common to a plurality of masks, and the like.

  In step S5, any one of the functional dummy patterns 5, 5B, 5C, 5D, 5E of the embodiment 1-5 is designed, and the design data is created.

  In step S6, a well-known hierarchical process and a well-known graphic operation are performed on the design data of the functional dummy pattern to create drawing data for each mask.

  In step S7, the functional dummy pattern occupation area is widened (oversized) by a predetermined width with respect to the drawing data of the functional dummy pattern for each mask, and the functional dummy pattern occupation area after the widening process is performed. As well as the number of masks used. The number of masks used for the functional dummy pattern is, for example, one for the functional dummy patterns 5, 5B, 5C, and two for the functional dummy pattern 5D, and the functional dummy pattern 5E. For example, there are three.

  In step S8, based on the occupation area after the widening process of the functional dummy pattern and the number of used masks, the free area 3 in which the functional dummy pattern can be formed is extracted from the free areas 3 obtained in step 4. . More specifically, the empty space 3 obtained in step 4 is free for the masks larger than the occupied area of the functional dummy pattern after the widening process and more than the number of masks used for the functional dummy pattern. The free space 3 is extracted.

  Then, an appropriate number of functional dummy patterns are arranged in the extracted empty area 3. More specifically, the mask pattern of the functional dummy pattern coexists in the empty area 3 on a predetermined mask among the masks sharing the extracted empty area 3 among the masks for the semiconductor integrated circuit 10s. Let Thereby, a functional dummy pattern can be appropriately formed in the periphery (immediately adjacent) of each functional module 2 mounted on the semiconductor integrated circuit 10s.

  For example, in the case of the functional dummy pattern 5 of the first embodiment, the mask pattern of the functional module 2 to be measured among the masks sharing the extracted empty area 3 among the masks for the semiconductor integrated circuit 10s. The mask pattern of the functional dummy pattern 5 is allowed to coexist in the vacant area 3 on one of the masks in which is formed. Further, in the case of the functional dummy patterns 5B and 5C of the second and third embodiments, the functional module to be subjected to noise blocking among the respective masks sharing the extracted empty area 3 among the respective masks for the semiconductor integrated circuit 10s. The mask patterns of the functional dummy patterns 5B and 5C are made to coexist in the empty area 3 on one of the masks on which the mask pattern for 2 is formed. In the case of the functional dummy pattern 5D of the fourth embodiment, the mask pattern of one part of the alignment measurement target among the masks sharing the extracted empty area 3 among the masks for the semiconductor integrated circuit 10s. A mask pattern of the main scale pattern 5m of the functional dummy pattern 5D is allowed to coexist in the empty area 3 on the mask in which the mask pattern is formed, and the empty area 3 on the mask in which the mask pattern of the other part to be measured for alignment is formed. In addition, the mask pattern of the vernier pattern 5n of the functional dummy pattern 5D is allowed to coexist. In the case of the functional dummy pattern 5E according to the fifth embodiment, a specific functional module (for example, an analog module or a RAM) among the masks sharing the extracted empty area 3 among the masks for the semiconductor integrated circuit 10s. / ROM) The mask pattern of the functional dummy pattern 5D is allowed to coexist in the empty areas 3a and 3b on the respective masks sharing the empty areas 3a and 3b surrounded by the ROM 2.

  Note that the formation of the TEG pattern of the same monitor item as the functional dummy pattern formed in the empty area 3 is canceled in the scribe area 4 at the periphery of the chip 4.

  In step S9, based on the drawing data of the semiconductor integrated circuit 10s and the drawing data of the functional dummy pattern based on the result of step S8, a plurality of functional modules 2 and functional dummy patterns 5, as shown in FIG. Drawing data of each mask of the semiconductor integrated circuit 10 on which 5B, 5C, 5D, or 5E is mounted is created. In this way, the pattern of the semiconductor integrated circuit 10 is laid out.

  According to the layout method of the semiconductor integrated circuit described above, the empty area in which the functional dummy pattern can be formed from the empty area 3 of the semiconductor integrated circuit 10s based on the occupation area of the functional dummy pattern and the number of masks used. 3 and a functional dummy pattern is arranged in the extracted empty area 3, thereby forming a plurality of functional modules 2 in the chip 1 and forming a functional dummy pattern in the empty area 3 in the chip 1. Since the drawing data for each mask of the semiconductor integrated circuit 10 is created, the pattern of the semiconductor integrated circuit 10 of the first to fifth embodiments can be appropriately laid out.

  Further, as a common effect to the first to sixth embodiments, the functional dummy patterns 5, 5B, 5C, 5D, and 5E are formed by utilizing the vacant region 3, so that the chip area is increased and the cost is reduced as compared with the conventional case. Without incurring an increase, more TEG patterns can be mounted and finer process monitoring than in the past can be achieved.

  Further, since the functional dummy patterns 5, 5B, 5C, 5D, and 5E are formed in the empty area 3 in the chip 1, the occupation ratio of the chip 1 can be ensured and the variation in the finish of the fine pattern can be suppressed.

  Further, since the TEG pattern formed as the functional dummy patterns 5, 5B, 5C, 5D, 5E in the empty area 3 in the chip 1 can be deleted from the scribe area 4 on the chip periphery, the scribe area 4 is reduced accordingly. As a result, the number of LSI chips that can be produced from one wafer can be increased, and the manufacturing cost per chip can be reduced.

  Further, the TEG pattern formed as the functional dummy patterns 5, 5B, 5C, 5D, and 5E in the empty area 3 in the chip 1 has characteristics of the functional module 2 at a position closer to the functional module 2 to be monitored than before. Therefore, the error due to the mounting position of the conventional TEG pattern can be reduced, and a highly accurate process monitor can be performed.

5 is a diagram showing an example of a floor plan of a semiconductor integrated circuit according to Embodiment 1-4. FIG. FIG. 10 illustrates a pattern layout method for a semiconductor integrated circuit according to a sixth embodiment. FIG. 16 is a diagram showing an example of a floor plan of a semiconductor integrated circuit in which a plurality of functional modules before a functional dummy pattern is formed in the sixth embodiment. FIG. 3 is an example of a functional dummy pattern having an aberration monitoring function in the first embodiment. It is an example figure of the functional dummy pattern which has an electrical noise interruption | blocking function in Embodiment 2. FIG. FIG. 11 is an example of a functional dummy pattern having a magnetic noise blocking function in the third embodiment. It is an example figure of the functional dummy pattern which has an alignment measurement function in Embodiment 4. It is the figure which showed an example of the functional dummy pattern which has an example of the floorplan of the semiconductor integrated circuit which concerns on Embodiment 5, and a timing measurement function. It is an example figure of the dummy pattern of a prior art example.

Explanation of symbols

  1 chip, 2 functional module, 3 free area in chip, 4 scribe area, 5, 5B, 5C, 5D, 5E functional dummy pattern, 5Ba first periodic pattern, 5Bb second periodic pattern, 5m main scale pattern 5n vernier pattern, 10 semiconductor integrated circuit, B metal part, L insulating film part, P, P1, P2, P3, P4 periodic pitch.

Claims (9)

A plurality of functional modules formed in the chip;
A functional dummy pattern formed in an empty area around a predetermined functional module in the chip and having an aberration monitoring function;
2. The semiconductor integrated circuit according to claim 1, wherein the functional dummy pattern is formed by periodically repeating a band-shaped metal portion and a band-shaped insulating film portion in plan view. A plurality of functional modules formed in the chip;
A functional dummy pattern formed in an empty area around a predetermined functional module in the chip and having an electrical noise blocking function;
The functional dummy pattern has first and second periodic patterns;
Both the first and second periodic patterns are formed by periodically repeating a band-shaped metal part and a band-shaped insulating film part with the same width in plan view,
The periodic pitch of the second periodic pattern is set to a periodic pitch different from the periodic pitch of the first periodic pattern,
The first and second periodic patterns have their periodic directions aligned with the direction facing the predetermined functional module, and are arranged in parallel along the direction facing the predetermined functional module. A semiconductor integrated circuit. A plurality of functional modules formed in the chip;
A functional dummy pattern that is disposed in an empty area around a predetermined functional module in the chip and has a magnetic noise blocking function;
2. The semiconductor integrated circuit according to claim 1, wherein the functional dummy pattern is formed of an annular pattern including one or a plurality of planar metal parts in plan view. A plurality of functional modules formed in the chip;
A functional dummy pattern formed in an empty area around a predetermined functional module in the chip and having an alignment measurement function;
Both of the functional dummy patterns have a metal main scale pattern and a sub-scale pattern. Both the main scale pattern and the vernier pattern are formed by periodically repeating a band-shaped metal part and a band-shaped insulating film part with the same width in plan view,
The periodic pitch of the vernier pattern is set to a periodic pitch different from the periodic pitch of the main scale pattern,
The semiconductor integrated circuit according to claim 4, wherein the main scale pattern and the vernier pattern are arranged adjacent to each other in a direction orthogonal to the periodic direction in plan view.   In the functional dummy pattern, the mask pattern of the main scale pattern coexists in the vacant area on one of the masks for forming the predetermined functional module, and the mask pattern of the vernier pattern is the mask pattern of the vernier pattern 5. The method according to claim 4, wherein the predetermined functional module is formed together with the predetermined functional module by coexisting in the empty area on another one of the masks for forming the predetermined functional module. The semiconductor integrated circuit as described. A plurality of functional modules formed in the chip;
A plurality of functional dummy patterns that are formed in a plurality of vacant areas in the chip and have a timing measurement function,
Each of the plurality of functional dummy patterns is constituted by a ring oscillator. A pattern layout method for laying out a pattern of a semiconductor integrated circuit according to claim 1,
(A) creating drawing data for each mask of a semiconductor integrated circuit having a plurality of functional modules mounted in a chip;
(B) obtaining a free area in the chip for the drawing data of the semiconductor integrated circuit;
(C) creating drawing data for each mask of the functional dummy pattern;
(D) obtaining an occupation area of the functional dummy pattern and the number of masks used based on the drawing data of the functional dummy pattern;
(E) extracting a vacant area where the functional dummy pattern can be formed from the vacant areas determined in step (b) based on the occupied area of the functional dummy pattern and the number of masks used; ,
(F) By disposing the functional dummy pattern in the empty area extracted in the step (e), the plurality of functional modules are formed in the chip and the functional dummy in the empty area in the chip. Creating drawing data for each mask of the semiconductor integrated circuit on which the pattern is formed;
A pattern layout method for a semiconductor integrated circuit, comprising:   In the step (f), the functionality is added to the vacant region on a predetermined mask among the masks sharing the vacant region extracted in the step (e) among the masks for the semiconductor integrated circuit. By making the mask pattern of the dummy pattern coexist, the drawing data of each mask of the semiconductor integrated circuit in which the plurality of functional modules are formed in the chip and the functional dummy pattern is formed in the empty area in the chip can be obtained. 9. The pattern layout method for a semiconductor integrated circuit according to claim 8, wherein the pattern layout method is created.

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