JP2009064112A - Code transfer method to memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic code transfer method to a high-speed memory, improving execution operation speed by dynamically detecting a function having high access frequency or a function having a very long execution time, arranging a memory resource to the memory capable of dynamically operating at high speed, and performing transfer. <P>SOLUTION: This code transfer method to the memory in a system having memories each having different access speed has steps: for totaling use frequency of a previously designated code during operation of the system to generate statistical information; for detecting the high-use-frequency code from the statistical information; and for transferring the detected code to the memory having the higher access speed than the memory recording the detected code, and performing the arrangement. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for allocating memory resources to a plurality of memory areas having different access speeds.

  Conventionally, in order to effectively allocate memory resources (source code) to a limited memory area and operate it, a user creates a vector file in advance, and a compiler or linker stores memory in the memory area based on the vector file. Resources are allocated.

  For example, if there are multiple memory resources that you want to operate at high speed, but the memory capacity of the memory area that can be operated at high speed is less than the program capacity of the memory resource, the user can select a memory resource with relatively high access frequency and operate at high speed A vector file is created so that it can be allocated to the appropriate memory area.

  In addition, memory resources once allocated by a vector file are difficult to change the memory area during program execution. Therefore, frequently accessed data and instructions are held in the cache area using the CPU's cache function to achieve high speed. Is being implemented.

  According to Patent Document 1, the simulator unit models a processor system having at least two memory areas with different access speeds and simulates a program. Based on the simulation results, the resource allocation unit assigns the data area used for program execution to the high-speed memory area and the low-speed memory area so that the target execution speed of the program can be maintained without placing data in the high-speed memory area as much as possible. The optimum memory allocation to be distributed to the memory area is determined. There has been proposed a method for automatically optimizing memory allocation in the system as described above through simulation of a system model to support memory resource optimization.

  Patent Document 2 proposes an arithmetic device capable of performing a function operation at high speed by making the function table programmable, and supporting a plurality of function operations by rewriting the contents of the function table.

  According to Patent Document 3, a library address list table is provided in an application code (program), and a procedure for registering a library address in this table is provided to dynamically link the library.

According to Patent Document 4, there is proposed a language processing apparatus capable of assigning a variable to a high-speed memory when there is a variable that can be assigned to a high-speed memory area.
According to Patent Document 5, when data in a cache memory is replaced without being fully used, the original data can be prohibited from being registered in the cache memory thereafter, so that the use efficiency of the cache memory is improved and the miss rate is increased. There are proposals to reduce this.

  However, when the program is statically arranged in a memory capable of high-speed operation in an apparatus such as Patent Document 1, it is not guaranteed that the actual operation is optimal in this memory arrangement. Similarly, even when a highly frequent program is detected by simulation, there is a problem that it is difficult to ensure that the simulation result is optimal due to changes in actual operating conditions.

The CPU cache function is for data access and instruction access.
In the case of a memory in which the program code itself is placed at a slow location, most of the control time is occupied by the memory read of the program code placed in the slow memory.

In Patent Documents 1 to 5, memory resources that are frequently used are not stored in a memory that can dynamically operate at high speed according to the frequency of use.
JP 2004-70862 A Japanese Patent Laid-Open No. 09-022343 Japanese Patent Laid-Open No. 10-254711 JP 2000-339173 A JP 05-274225 A

  The present invention has been made in view of the above circumstances, and dynamically detects a function having a high access frequency or a function having a long execution time, and dynamically allocates a memory resource to a memory capable of operating at high speed. An object of the present invention is to provide a dynamic code transfer method to a high-speed memory which improves the execution operation speed by transferring.

  A method of transferring code to a memory in a system including memories with different access speeds, which is one aspect of the present invention, and generates statistical information by aggregating the frequency of use of predetermined codes during operation of the system. The code that is frequently used is detected from the statistical information, and the detected code is transferred to a memory having a higher access speed than the memory in which the detected code is recorded.

  With the above configuration, it is possible to improve the execution operation speed by dynamically detecting a function with high access frequency or a function with a long execution time, and allocating and transferring memory resources to a memory capable of dynamic operation at high speed. it can.

  Preferably, the statistical information includes the number of activations or the number of runnings, and the number of times of activation is recorded every time a predetermined code is activated, and the number of travelings is recorded each time the code is executed. May be recorded.

  Preferably, the number of times of activation and a preset number of times of activation threshold are compared to detect whether or not the number of times of activation is equal to or greater than the threshold value of the number of times of activation, or the number of runnings is compared with a preset number of times of running threshold The code having a high use frequency may be detected by detecting whether or not it is equal to or greater than a running number threshold.

  Preferably, when transferring the detected code to a memory having a high access speed, it is determined whether the detected code is stored in a free area of the high speed memory without the detected code in the high speed memory, and the high speed The transfer may be performed when the detected code can be transferred to the memory.

  Preferably, if there is no free area in the high-speed memory, a code already registered in the high-speed memory may be deleted to secure a free area, and the detected code may be transferred.

  The present invention dynamically detects a function with a high access frequency or a function with a long execution time, and dynamically allocates and transfers memory resources to a memory capable of high-speed operation, thereby improving the operation speed of the system. Can do.

(Principle explanation)
In a system including a plurality of memories having different access speeds, a code having a high operation frequency is detected, and a code having a high operation frequency is dynamically arranged in a memory capable of high-speed operation even when the system is in operation.

  Here, the code is an executable code created by compiling and linking the source code programmed by the user, such as a function registered in the library or a code specified by the user. It is.

The code is detected by determining whether the code is in the entry table.
The entry table includes entry key information indicating the address and memory size where a part or all of the code that actually wants to dynamically change the memory allocation is stored, the number of times the code is activated, and the stack It is comprised by the statistical information which shows the driving | running number of.

  When dynamically allocating code to a memory capable of high-speed operation, statistical information is collected and aggregated periodically by the user setting the start, end, and period in advance at an arbitrary timing. .

When the code registered in the entry table is activated, the statistical information collects and records the number of activations and the number of runnings corresponding to the code registered in the entry table.
Thereafter, it is detected that the number of times of activation of the statistical information has exceeded a preset number of activations threshold, or that the number of travelings has exceeded a preset number of runnings of statistical information.

  If the memory that can be operated at high speed has free space in the memory that can be operated at high speed and the code recorded in the statistical information aggregation table etc. can be arranged, Transfer the corresponding code to a memory capable of high-speed operation.

  The code arranged in the memory capable of high-speed operation rewrites the address of the entry key information in the entry table in order to operate the code in the memory capable of high-speed operation from the next activation. In addition, information for managing which code is arranged in the memory capable of high-speed operation is also updated.

  In addition, even if a code exceeding the threshold for the number of activations and the number of runnings to be placed in the memory capable of high-speed operation is newly generated, if sufficient capacity cannot be secured in the memory capable of high-speed operation at the placement destination, Returns the entry table of the code placed in the memory capable of high-speed operation to the initial value. Then, after securing a sufficient free space in a memory capable of high-speed operation, a new code is arranged.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Example 1
(Constitution)
FIG. 1 is a diagram showing a configuration of a system in which memories having different access speeds are mixed. The system shown in FIG. 1 includes a circuit including a CPU 101, a memory 102 capable of high-speed operation, and a flash memory 103. The CPU 101, the memory 102 that can operate at high speed, and the flash memory 103 are connected via a bus line 104.

The CPU 101 reads a code from a memory area in which a plurality of codes generated by a compiler and a linker are recorded, and operates based on the contents of the code.
The CPU 101 also provides a memory (register or the like) for storing the start address of the entry table, and activates a code (function code or the like) using the entry key information in the entry table.

Software for analyzing statistical information is managed by an OS (Operating System), and uses high-speed memory management information as data for controlling the high-speed memory 102.
The high-speed memory management information is composed of the activation count threshold, the running count threshold, and the priority of statistical items. These pieces of information can be changed by the user.

The CPU 101 is provided with a memory (register or the like) that determines whether or not to collect statistical information. In the case of collecting statistical information, the statistical information is collected when a dynamically allocated code is activated.
In the memory 102 capable of high-speed operation, a code designated by the vector file is statically recorded when the power is turned on or reset. During operation, a code with high access frequency is detected, and the detected code is dynamically transferred to the memory 102 capable of high-speed operation. Hereinafter, the memory 102 capable of high-speed operation is simply referred to as a high-speed memory.

  The flash memory 103 is a memory having a slower access speed than the high-speed memory 102. In the flash memory 103, the code specified by the vector file is statically recorded when the power is turned on or reset.

In FIG. 1, the flash memory 103 is shown as a memory having a slower access speed than the high-speed memory 102, but the present invention is not limited to the flash memory.
The statistical information totaling process operates according to the periodic task of the OS. The statistical information collected by the CPU 101 is searched, and the high-speed memory management information is used to determine whether the threshold value is exceeded. When a function exceeding the threshold is detected, it is stored in the statistical information aggregation table. Also, the statistical information on the entry table is cleared.

The created statistical information aggregation table is used to control transfer to the high-speed memory 102 executed by the high-speed memory update process.
In the high-speed memory update process, it is determined whether or not the high-speed memory management information can be arranged in the high-speed memory 102. For example, when a plurality of codes are to be transferred in the same cycle, the statistical item priority is determined, and control is performed in order of priority.

  At this time, if the newly detected function can be placed by returning the placed code with the least amount of frequency information and no free space in the high-speed memory, the address of the code with less frequency information is restored. Implement control.

When the memory capacity in which the detected code can be arranged can be secured, the detected code is transferred (copied) to the high-speed memory 102.
When returning an infrequent placement code or placing a newly detected code, the entry table and the high-speed memory management information table are updated so that the placement in the high-speed memory 102 can be used effectively. Perform relocation.

(Compiler and linker)
In the system shown in FIG. 1, when compiling the code programmed by the user, the code necessary for allocating the code in the low-speed memory such as the flash memory 103 to the high-speed memory 102 during operation is provided. Add and compile.

In other words, the entry key information indicating the address and memory size of the code whose memory allocation is to be dynamically changed and the transfer code are embedded in the code programmed by the user and compiled. For example, entry key information and a transfer code may be incorporated using an extended language.

In addition, the compiler generates an entry table shown in FIG. 2 for a plurality of codes designated by a user that is dynamically arranged.
The entry table shown in FIG. 2 has a plurality of entry areas including an entry index value area, a code head address / size area, a startup count storage area, and a travel count storage area.

  The entry index value area stores a number corresponding to a code name of a code that is desired to be operated at high speed. For example, a programmed code name, function name, etc. (entry key information) are recorded.

The start address / size area is an area in which the start address and size (entry key information) of the code corresponding to the entry index value are recorded.
The activation count storage area records the number of times (statistical information) the code corresponding to the entry index value is activated.

The number-of-runs storage area records the number of times (statistical information) transferred to the stack when the code corresponding to the entry index value is activated.
For example, the compiler performs conventional assembler expansion for statically placed code, but for dynamically placed code, the activation destination is obtained from the entry key information, and the activated code is Implement assembler deployment.

The linker secures an entry table area in the memory area. Also, code that does not require high-speed operation is linked as before.
(Description of operation)
FIG. 3 shows the processing sequence of the present invention and the operation will be described. The processing sequence illustrated in FIG. 3 illustrates operations of the application 31, the OS 32, and the CPU 101 (hardware).

  The application 31 notifies the OS 32 of the statistical information start, stop, and collection period, and enables the collection of statistical information by manipulating the collection register to determine whether or not to collect the statistical information to the CPU 101 at an arbitrary timing. . The OS 32 that has received the start of collection instructs the CPU 101 using the collection register and starts the statistical information collection process (statistical information collection process start 35).

When a code registered in the entry table is detected during execution of the application, the OS 32 is notified as indicated by an operation start instruction 33 in FIG.
When the OS 32 receives the notification, it notifies the CPU 101 of a notification for setting the collection register provided in the CPU 101 as shown in the collection register setting 34 of FIG.

Upon receiving the notification, the CPU 101 counts the number of activations and the number of travels and records them in the activation number storage area and the travel number storage area of the entry table.
Next, in order to periodically total the contents of the entry table, a totaling period process start 37 controlled by the periodic task generation 36 in FIG. 3 is executed.

FIG. 4 is a diagram showing a processing flow for collecting statistical information.
When the code is activated, the number of runs during the code run is counted in the stack area, and when the code ends, the number of runs in the stack and the number of activations are stored in the entry table.

  In step S41, it is determined whether to collect statistical information. It is determined whether or not the code to be executed is the same as the entry index value recorded in the entry index value area of the entry table. If the code matches the code recorded in the entry index value, the process proceeds to step S42. If they do not match, the code does not need to be placed in the high-speed memory 102, and the process proceeds to step S47.

In step S42, the code is activated and executed.
In step S43, the number of running codes being executed is counted and stored in the stack area.
In step S44, the execution of the code ends.

In step S45, 1 is added (incremented) and recorded each time the code corresponding to the activation count storage area in which the activation count of the code is recorded is activated.
In step S46, the number of travels recorded in the stack area is collected and registered in the travel number storage area.

In step S47, a code not recorded in the entry table is activated, and in step S48, the execution of the code is completed.
FIG. 5 shows an example in which the running number is recorded in the stack area.

  FIG. 5A shows a case where the function code A, function code B, and function code C included in the code have a nested structure. The traveling number of the function code A is the sum of the traveling numbers of the first half process and the second half process on both sides of the function code B. The traveling number of the function code B is the sum of the traveling numbers of the first half process and the second half process on both sides of the function code C. The traveling number of the function code C is the traveling number in the function code C.

FIG. 5B is a diagram showing how the traveling number is recorded in the stack area in the structure shown in FIG.
The memory area shown in FIG. 5B includes areas used by the function codes A to C. Each area includes a user stack area 51, a stack running count storage area 52, an old frame pointer storage area 53, and a return program counter. The storage area 54 is configured.

  The user stack area 51 is an area for saving data necessary for shifting to each function code. When the currently executing function code is completed, the data saved in the user stack area 51 is restored again.

  The stack travel count storage area 52 is an area for collecting the travel count. For example, the number of running of each function code is counted in the order of the first half processing of the function code A as shown in FIG. 5A, the first half processing of the function B, the processing of the function C, the second half processing of the function B, and the second half processing of the function A. And save. Note that the stack travel count storage area 52 may use a part of the user stack area 51.

The old frame pointer storage area 53 stores the contents indicated by the frame pointer of each function code.
The return program counter storage area 54 is an area for recording the return value of the program counter.

  When the first half of the function code A processing is started, the number of travels is recorded in the stack travel number storage area 52 for the function code A. Next, when the function code B during execution of the function code A is called, the function code B is activated. The number of travels of the first half of the function code B is recorded in the stack travel number storage area 52 for the function code B.

When the function code C is called while the function code B is being executed, the function code C is activated. The travel number of the function code C process is recorded in the stack travel count storage area 52 for the function code C.
Next, when the processing of the function code C is completed, the processing returns to the processing of the function code B, and the number of runnings of the function code B latter half processing is stored in the stack running number storage area 52 for the function code B function code B. It is added to the number and recorded.

  When the processing of the function code B is completed, the processing returns to the processing of the function code A. When the second half processing of the function code A is started, the running number of the second processing of the function code A is stored in the function code A It is added to the number of travels in the first half process and recorded.

  Then, as described in step S46, the number of travels recorded in the stack travel count storage area 52 of each function code is added and registered for each function code in the travel count storage area of the entry table.

FIG. 6 is a diagram showing a processing flow of a totaling periodic process instructed to start execution by generating a periodic task controlled by the OS.
In step S61, the number of activations and the number of travelings recorded in the activation number storage area and the traveling number storage area of the entry table corresponding to the code (for example, function code) are detected. In addition, since the number of times of running is one step at the assembler level, the execution time can be calculated if the number of running of each code is known. Therefore, the running time of each code may be used for detection.

  In step S62, whether the statistical information activation count exceeds the preset activation count threshold in the high-speed memory management information shown in FIG. 7 or whether the statistical information activation count exceeds the preset statistical information running count threshold. judge. When it exceeds the range of the activation number threshold or the running number threshold, the process proceeds to step S63. If not, the process proceeds to step S61 to search for the next code.

  In step S63, the entry key information and statistical information of the code exceeding the range of the activation number threshold or the running number threshold are stored in the statistical information aggregation table. The statistical information aggregation table has an area for storing entry key information and statistical information.

In step S64, the statistical information in the entry table of the corresponding code is cleared.
In step S65, it is determined whether or not all codes registered in the entry key table have been searched. If completed, the process proceeds to step S66. If not all codes have been searched, the process proceeds to step S61.

  In step S66, it is determined whether there is data in the statistical information tabulation table. If there is data including entry key information and statistical information of the stored code, the process proceeds to step S67.

In step S67, the high-speed memory update process shown in FIG. 8 is performed.
FIG. 7A is a diagram showing the structure of a memory area that stores high-speed memory management information. In the high-speed memory management information, an area for managing the usage state of the high-speed memory 102 and a setting value for controlling a code registered in the entry table are recorded.

  The high-speed memory management information includes a high-speed memory maximum size, a high-speed memory remaining size, a cycle time, a cycle count, a startup count threshold, a startup count priority, a running count threshold, a running count priority, and high-speed memory storage information.

The maximum size that can use the high-speed memory 102 is recorded in the high-speed memory maximum size.
As the high-speed memory remaining size, the remaining memory capacity of the memory currently used in the high-speed memory 102 is recorded.

As the cycle time, the start-up time of the counting cycle process is recorded. The number of cycles records how many times the aggregation process has been executed.
The activation count threshold is a value set in advance by the user in order to compare with the activation count recorded in the entry table. In addition, an activation frequency threshold may be provided for each code registered in the entry table.

  The travel number threshold is a value set in advance by the user in order to compare with the travel number recorded in the entry table. Moreover, you may provide a driving | running | working number threshold value for every code registered into the entry table.

  The activation number priority and the traveling number priority select whether to start executing the code arrangement in the high-speed memory 102 based on the number of activations or based on the number of travelings. For example, the priority is determined using a flag. A flag is set when priority is given to the number of activations, and no flag is set when priority is given to the number of runs. In addition, when code placement in the high-speed memory 102 is executed when the number of activations and the number of runnings exceed the above-mentioned number of activations threshold and the number of runnings threshold, a flag is provided for the number of activations and the number of runnings, and two flags are set. It can be considered to be effective.

The high-speed memory storage information includes high-speed memory storage code key information corresponding to each code, an initial code address value, a high-speed memory address value, and high-speed memory storage statistical information.
In the high-speed memory storage code key information, entry key information of a code registered in the high-speed memory 102 is stored.

As the initial code address value, a head address when it is arranged in the low-speed memory (flash memory 103) before being arranged in the high-speed memory 102 is recorded.
As the high-speed memory address value, the head address of the code arranged in the high-speed memory 102 is recorded.

In the high-speed memory storage statistical information, the number of activations and the number of runnings are recorded.
FIG. 7B shows the statistical information tabulation table, which records entry key information and statistical information of the detected frequently used codes.

  For example, it is possible to easily search for an old code by recording in the order of recording in ascending order of address number in the memory area. Further, the order of registration in the entry key information may be recorded.

  FIG. 8 is a diagram showing a control flow for arranging codes in the high-speed memory 102. FIG. 9 is a diagram showing that the function code B among the function codes A to C in the flash memory 103 is transferred to the high-speed memory 102.

In step S81, it is determined whether the code has already been arranged in the high-speed memory 102.
For example, the determination is made based on the entry key information recorded in the statistical information aggregation table.

If the code recorded in the entry table and the number of activations or the number of runnings exceeds the set number of activations threshold or the running number threshold has already been placed in the high-speed memory 102, the process proceeds to step S82. To do. If not yet arranged, the process proceeds to step S83. In FIG. 9, the function code B is detected.

  In step S82, it is determined whether or not there is a free area larger than the capacity of the code to be arranged in the high speed memory 102. If there is an empty area, the process proceeds to step S86. If there is no free area, the process proceeds to step S83. In the case of FIG. 9, the memory capacity of the function code B is compared with the free area.

  In step S <b> 83, it is determined whether an empty area can be secured in the high speed memory 102 by deleting the oldest code arranged in the high speed memory 102. If a free area cannot be secured even after deletion, the process exits this flow. If the memory area can be secured, the process proceeds to step S84. Here, the detection of the oldest code is determined by searching the order of entry key information recorded in the statistical information aggregation table.

  In step S84, the number of activations and the number of runnings in the statistical information of the entry table corresponding to the oldest code are cleared. Further, the entry key information in the entry table corresponding to the oldest code is updated with reference to the initial code address of the high-speed memory management information.

  In step S85, the high-speed memory storage information of the high-speed memory management information corresponding to the code updated in step S84 is updated. That is, the high-speed memory address corresponding to the updated code is cleared. Also, the remaining high-speed memory size is updated.

Also, the entry key information and statistical information corresponding to the oldest code recorded in the statistical information totaling table are deleted.
In step S <b> 86, the code placed in the high speed memory 102 is transferred to an empty area of the high speed memory 102. In FIG. 9, the function code B is transferred.

  In step S87, the start address of the high-speed memory 102 in which the code that has been detected that the number of times of starting or the number of runnings exceeds the set number of times of starting threshold or the number of runnings is set is reflected in the entry key information of the entry table.

  In step S88, the start address of the high-speed memory 102 in which the detected code is arranged is reflected in the high-speed memory address of the high-speed memory management information. Also, the remaining high-speed memory size is updated.

Note that the control processing shown in the flow of the above embodiment can be realized by causing a computer to execute a program in which an instruction for performing the control processing is described.
If this program is stored in a storage medium such as a CD-ROM, the control process can be realized by installing the program in a computer. Further, this program may be downloaded to a computer via a communication network.
The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

(Appendix 1)
A code transfer method to a memory in a system including memories having different access speeds,
During the operation of the system, the usage frequency of the code specified in advance is aggregated to generate statistical information,
Detect the code that is frequently used from the statistical information,
Transferring and arranging the detected code in a memory having a higher access speed than the memory in which the detected code is recorded;
A code transfer method to a memory.
(Appendix 2)
The statistical information includes the number of activations or the number of runs,
Record the number of activations every time a pre-specified code is activated,
Record the number of runs each time the code is executed in the number of runs.
The method for transferring a code to a memory according to appendix 1, wherein:
(Appendix 3)
Detection of the code that is used frequently is
The number of activations is compared with a preset number of activations threshold to detect whether the number of activations is equal to or greater than the number of activations threshold, or the number of travelings is compared with a preset number of runnings threshold The code transfer method to the memory according to appendix 2, wherein the code that is frequently used is detected by detecting whether or not the above is true.
(Appendix 4)
When transferring the detected code to a memory having a high access speed,
Determining whether or not the detected code is already present in the high-speed memory and the detected code can be recorded in an empty area of the high-speed memory, and transferring when the detected code can be transferred to the high-speed memory The method for transferring a code to a memory according to appendix 1, wherein:
(Appendix 5)
6. If there is no free area in the high-speed memory, the code already registered in the high-speed memory is deleted, a free area is secured, and the detected code is transferred. Code transfer method.
(Claim 6)
On the computer,
During the operation of a system having memories with different access speeds, a process of generating statistical information by summing up the frequency of use of codes specified in advance;
A process of detecting the code frequently used from the statistical information;
A process of transferring and arranging the detected code in a memory having a faster access speed than the memory in which the detected code is recorded;
Code transfer program to execute.
(Appendix 7)
The code transfer method to the memory according to appendix 2, wherein priority is given to the number of activations or the number of runnings.

It is a figure which shows the system configuration example by embodiment of this invention. It is a figure which shows the structure of an entry table. It is a flowchart which shows the process performed by an application. It is a flowchart which shows the process of collection control of statistical information. It is a flowchart which shows count control of the number of driving | running | working of statistical information. It is a flowchart which shows the process control of the totaling period process of statistical information. It is a figure which shows the structure of high-speed memory management information. It is a flowchart which shows the process which stores a code in a high-speed memory. It is a figure which transfers a code from low speed memory to high speed memory.

Explanation of symbols

101 CPU
102 High-speed memory (memory capable of high-speed operation)
103 Flash memory 31 Application 32 OS
33 Start instruction 34 Collection register setting 35 Statistics information collection process start 36 Periodic task generation 37 Aggregation period process start

Claims (6)

A code transfer method to a memory in a system including memories having different access speeds,
During the operation of the system, the usage frequency of the code specified in advance is aggregated to generate statistical information,
Detect the code that is frequently used from the statistical information,
Transferring and arranging the detected code in a memory having a higher access speed than the memory in which the detected code is recorded;
A code transfer method to a memory. The statistical information includes the number of activations or the number of runs,
The number of activations is recorded each time a pre-specified code is activated,
The number of runs is recorded every time the code is executed,
The method for transferring code to a memory according to claim 1. Detection of the code that is used frequently is
The number of activations is compared with a preset number of activations threshold to detect whether the number of activations is equal to or greater than the number of activations threshold, or the number of travelings is compared with a preset number of runnings threshold 3. The code transfer method to the memory according to claim 2, wherein the code that is used frequently is detected by detecting whether or not the above is true. When transferring the detected code to a high-speed memory having a high access speed,
Determining whether there is no detected code in the high-speed memory and the detected code can be recorded in an empty area of the high-speed memory, and performing transfer when the detected code can be transferred to the high-speed memory. The method of transferring code to a memory according to claim 1.   6. The memory according to claim 5, wherein if there is no free area in the high-speed memory, a code already registered in the high-speed memory is deleted to secure a free area, and the detected code is transferred. Code transfer method. On the computer,
During the operation of a system having memories with different access speeds, a process of generating statistical information by summing up the frequency of use of codes specified in advance;
A process of detecting the code frequently used from the statistical information;
A process of transferring and arranging the detected code in a memory having a faster access speed than the memory in which the detected code is recorded;
Code transfer program to execute.

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