JP2009059892A - Semiconductor magnetoresistance element and its designing method - Google Patents

Semiconductor magnetoresistance element and its designing method Download PDF

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JP2009059892A
JP2009059892A JP2007225806A JP2007225806A JP2009059892A JP 2009059892 A JP2009059892 A JP 2009059892A JP 2007225806 A JP2007225806 A JP 2007225806A JP 2007225806 A JP2007225806 A JP 2007225806A JP 2009059892 A JP2009059892 A JP 2009059892A
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JP5314261B2 (en
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Tetsushi Yamada
哲史 山田
Hiromasa Gotou
広将 後藤
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Asahi Kasei Electronics Co Ltd
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<P>PROBLEM TO BE SOLVED: To achieve a magnetoresistance change rate as high as in a case of a conventional large width W even when a width W of a semiconductor operating layer in a direction orthogonal to a length direction of the magnetoresistance element, that is, a direction between electrodes is reduced. <P>SOLUTION: The semiconductor magentoresistance element includes a thin film semiconductor operating layer formed on a substrate, input-output electrodes arranged at least on two end parts on the semiconductor operating layer, and a plurality of short-circuit electrodes arranged at constant intervals in an extending direction of a semiconductor layer extending in a right angle direction with respect to the extending direction of the semiconductor layer extending between the input-output electrodes on the semiconductor operating layer between the input-output electrodes. When the width of the semiconductor operating layer in the right angle direction with respect to the extending direction of the semiconductor layer extending between the input-output electrodes is not more than 60 μm, a length of the short-circuit electrode in the extending direction of the semiconductor layer is not more than 5 μm, the width of the semiconductor operating layer is W, and a distance between the plurality of the short-circuit electrodes at the constant interval is L, L/W which is a ratio of L and W is not more than 0.3. It is preferable that the L/W is not less than 0.1, and the length of the short-circuit electrode is not less than 2 μm. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、外部磁場強度を検知する磁気センサに関し、より詳細には、外部磁場強度を検知する磁気抵抗素子およびその設計方法に関する。   The present invention relates to a magnetic sensor that detects external magnetic field strength, and more particularly to a magnetoresistive element that detects external magnetic field strength and a design method thereof.

外部磁場強度を検知する磁気センサは光学式のものに比べ、特に汚れや埃などの影響を受ける用途においてその優位性がある。磁気センサの代表的なものとして、ホール素子や磁気抵抗素子があげられる。一般に磁気抵抗素子は、歯車回転速度を検出するセンサや紙幣磁気パターンを検出するセンサなどに使われている。   A magnetic sensor that detects the intensity of an external magnetic field is superior to an optical sensor particularly in applications that are affected by dirt, dust, and the like. Typical examples of magnetic sensors include Hall elements and magnetoresistive elements. In general, the magnetoresistive element is used for a sensor for detecting a gear rotation speed, a sensor for detecting a bill magnetic pattern, and the like.

図1(a)、(b)は、磁気抵抗素子の構造例の一つを示している。図1(a)は上面図で、図1(b)が断面図である。なお、これらの図は説明のための図であり、図1(a)と図1(b)の間には、寸法的に1:1の対応関係はない。図において、符号1は基板、符号2は半導体動作層、符号3は磁気抵抗素子としての入出力電極、符号4は短絡電極を示している。ここで、符号2の半導体動作層は、電極間方向に延在し、短絡電極の長軸方向は、電極間方向と直交する形で配置される。また、符号Lは、短絡電極間の電極間方向と平行な方向の距離であり、入出力電極と短絡電極間の距離でもある。符号Leは、同じ電極間方向の短絡電極の長さ、符号Wは、半導体動作層の、電極間方向(言い換えれば、半導体動作層の延在する方向)と直交する方向の幅である。   FIGS. 1A and 1B show one example of the structure of the magnetoresistive element. 1A is a top view and FIG. 1B is a cross-sectional view. Note that these figures are for explanation, and there is no 1: 1 correspondence between FIG. 1 (a) and FIG. 1 (b) in terms of dimensions. In the figure, reference numeral 1 denotes a substrate, reference numeral 2 denotes a semiconductor operation layer, reference numeral 3 denotes an input / output electrode as a magnetoresistive element, and reference numeral 4 denotes a short-circuit electrode. Here, the semiconductor operation layer denoted by reference numeral 2 extends in the inter-electrode direction, and the long-axis direction of the short-circuit electrode is arranged in a form orthogonal to the inter-electrode direction. Symbol L is a distance in a direction parallel to the inter-electrode direction between the short-circuit electrodes, and is also a distance between the input / output electrodes and the short-circuit electrodes. The symbol Le is the length of the short-circuit electrode in the same interelectrode direction, and the symbol W is the width of the semiconductor operation layer in the direction orthogonal to the interelectrode direction (in other words, the direction in which the semiconductor operation layer extends).

素子の感磁面(図1(a)の場合では、紙面と平行な面)に垂直に磁場を印加すると、磁場がない場合のキャリアの水平方向の進行方向が、外部磁場強度およびその向きに応じて、ローレンツ力によって(図1(a)の場合には、短絡電極の長さ方向に相当する、上方にあるいは下方向に)曲げられて、素子全体のキャリアの行路が、磁場がない場合に較べて長くなる。しかしながら、一般的には、曲げられて半導体層の側端部に達するとそれ以上曲げられることはない。このことは磁場によって曲げられて側端部に達するまでの距離以上に半導体層が長い場合、その距離以上の部分は、基本的には、磁場の影響を、曲げられる部分に比べると、受けにくくなる。図1では、そのために、半導体層の長さ方向の一定の距離毎に短絡電極4が設けられている。この短絡電極4には、磁場によって曲げられたキャリアの行路を元に戻す効果、すなわち、キャリアのリセット効果がある。つまり、例えば、図1(a)の半導体動作層の上部に集まったキャリアは、短絡電極4によって、短絡電極全体に理論的には均一に分散する、すなわち、上方に曲げられた場合に、図1(a)の下部にもその一部が移動することになる。言い換えれば、図における短絡電極の右端部とその右側の半導体動作層との関係は、左側の入出力電極とその右側の半導体動作層と関係と同じになる。この短絡電極によるキャリア密度のリセット効果を利用して、キャリアが曲げられる部分を数多く設けることにより、つまり、磁場の検出感度の高い部分をシリーズに構成することが可能になる。このように構成することによって、磁気の大きさに応じて出力端子間の抵抗が高くなるという磁気抵抗効果を所望のインピーダンス範囲で得ることができるようになる。つまり、図1の磁気抵抗素子は、磁場強度に応じて素子抵抗が変化し、磁気センサとして機能することになる。理論的には、短絡電極間距離Lと半導体動作層の幅Wの比であるL/Wが小さいほど、磁気変化に対する磁気抵抗変化率が大きくなる。   When a magnetic field is applied perpendicular to the magnetosensitive surface of the element (in the case of FIG. 1A, a plane parallel to the paper surface), the horizontal traveling direction of the carrier in the absence of the magnetic field depends on the external magnetic field strength and its direction. Accordingly, the carrier path of the entire element is bent by the Lorentz force (in the case of FIG. 1A, corresponding to the length direction of the short-circuit electrode, upward or downward), and there is no magnetic field. Longer than In general, however, when the bent side reaches the side edge of the semiconductor layer, it is not further bent. This means that if the semiconductor layer is longer than the distance until it reaches the side edge after being bent by the magnetic field, the part beyond that distance is basically less susceptible to the influence of the magnetic field than the bent part. Become. In FIG. 1, for this purpose, the short-circuit electrode 4 is provided at every constant distance in the length direction of the semiconductor layer. The short-circuit electrode 4 has an effect of returning the carrier path bent by the magnetic field, that is, a carrier reset effect. That is, for example, when the carriers collected on the upper part of the semiconductor operation layer in FIG. 1A are theoretically uniformly distributed over the entire short-circuit electrode by the short-circuit electrode 4, that is, when bent upward, A part of it also moves to the lower part of 1 (a). In other words, the relationship between the right end portion of the short-circuit electrode and the semiconductor operation layer on the right side thereof in the drawing is the same as the relationship between the left input / output electrode and the semiconductor operation layer on the right side. By utilizing the reset effect of the carrier density by the short-circuit electrode, it is possible to provide a number of portions where the carriers are bent, that is, it is possible to configure a portion having a high magnetic field detection sensitivity in series. With this configuration, it is possible to obtain a magnetoresistive effect that the resistance between the output terminals increases in accordance with the magnitude of magnetism in a desired impedance range. That is, the magnetoresistive element of FIG. 1 functions as a magnetic sensor, with the element resistance changing according to the magnetic field strength. Theoretically, the smaller the L / W, which is the ratio of the distance L between the short-circuit electrodes and the width W of the semiconductor operation layer, is, the greater the magnetoresistance change rate with respect to the magnetic change.

また、この短絡電極が形成されている部分は、半導体磁気抵抗素子のキャリア密度のリセットに効果があるのみで、素子の磁気抵抗変化には寄与しないと考えている。図1(c)には磁気抵抗効果の典型例を示す。外部磁場強度が増加するに従い磁気抵抗変化率が増加することが分かる。   In addition, it is considered that the portion where the short-circuit electrode is formed is only effective in resetting the carrier density of the semiconductor magnetoresistive element and does not contribute to the change in magnetoresistance of the element. FIG. 1C shows a typical example of the magnetoresistive effect. It can be seen that the magnetoresistance change rate increases as the external magnetic field strength increases.

図2は、図1(b)の磁気抵抗素子断面に示している一組の半導体動作層と短絡電極の等価回路を示す図である。ここで、R1は主に磁気抵抗効果を発動する半導体動作層の抵抗、R2は短絡電極直下の半導体動作層の抵抗、Rmは短絡電極の抵抗、Rcは半導体動作層と短絡電極との接触抵抗である。 FIG. 2 is a diagram showing an equivalent circuit of a pair of semiconductor operation layers and a short-circuit electrode shown in the magnetoresistive element cross section of FIG. Here, R 1 is a resistance of the semiconductor operation layer that mainly activates the magnetoresistive effect, R 2 is a resistance of the semiconductor operation layer immediately below the short-circuit electrode, Rm is a resistance of the short-circuit electrode, and Rc is a resistance between the semiconductor operation layer and the short-circuit electrode. Contact resistance.

以下、接触抵抗と短絡電極の直列抵抗成分をRs、RsとR2との並列抵抗成分をRpとする。RsとRpは以下のように表すことができる。 Hereinafter, the series resistance component of the contact resistance and the short-circuit electrode is Rs, and the parallel resistance component of Rs and R 2 is Rp. Rs and Rp can be expressed as follows.

Figure 2009059892
Figure 2009059892

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従来、大きな磁気抵抗変化率を得るためには短絡電極によるリセット効果が十分であること、つまり、より多くのキャリアを短絡電極に作用させることが必要であると考えられてきた。そのためには、RsとR2の比であるRs/R2を小さくする必要があり、特に接触抵抗Rcを小さくするために、以下の2つの方法が取られてきた。 Conventionally, in order to obtain a large rate of change in magnetoresistance, it has been considered that the reset effect by the short-circuit electrode is sufficient, that is, it is necessary to cause more carriers to act on the short-circuit electrode. For this purpose, it is necessary to reduce Rs / R 2 , which is the ratio of Rs to R 2 , and in particular, the following two methods have been taken to reduce the contact resistance Rc.

1つ目は、アニールやインプラにより半導体動作層と短絡電極の界面状態を改善する方法である。2つ目は、短絡電極の長さLeを大きくする方法である。   The first is a method of improving the interface state between the semiconductor operating layer and the short-circuit electrode by annealing or implantation. The second method is to increase the length Le of the short-circuit electrode.

通常、短絡電極と半導体動作層との接触面積が大きいほど接触抵抗Rcは小さいので、短絡電極の長さLeを大きくとることで、Rs/R2を小さくでき、より多くのキャリアを短絡電極に作用させることができる。実デバイスではどちらも実施され、半導体動作層の幅Wが100μm程度の場合の短絡電極の長さLeは数10μm程度になっている。この短絡電極の長さLeはキャリアのリセット効果を得るのに十分な長さであり、また、短絡電極の長さLeが大きいほどキャリアのリセット効果が大きいと考えられてきた。 Usually, the larger the contact area between the short-circuit electrode and the semiconductor operation layer, the smaller the contact resistance Rc. Therefore, by increasing the length Le of the short-circuit electrode, Rs / R 2 can be reduced, and more carriers are used as the short-circuit electrode. Can act. Both are implemented in the actual device, and the length Le of the short-circuit electrode when the width W of the semiconductor operation layer is about 100 μm is about several tens of μm. The length Le of the short-circuit electrode is long enough to obtain a carrier reset effect, and it has been considered that the carrier reset effect is larger as the length Le of the short-circuit electrode is larger.

また、磁気抵抗変化率は、ΔR/{n×(R1+Rp)}と表せるので、磁気抵抗効果の期待できないRpが小さい方が、磁気抵抗素子全体の磁気抵抗変化率に有利に働く。ここで、ΔRは印加磁場による素子抵抗の増加分、nは半導体動作層と短絡電極との対の数である。半導体動作層の幅Wと短絡電極間距離Lの比であるL/Wと短絡電極の長さLeを固定した場合、半導体動作層の幅Wが小さくなるにしたがって半導体動作層と短絡電極と接触面積が小さく、すなわち、接触抵抗Rcが大きくなり、それに伴ってRpも大きくなってしまう。つまり、半導体動作層の幅Wが小さくなると、磁気抵抗変化率も小さくなってしまう。 Further, since the magnetoresistance change rate can be expressed as ΔR / {n × (R 1 + Rp)}, the smaller the Rp that the magnetoresistance effect cannot be expected, the more advantageous the magnetoresistance change rate of the entire magnetoresistive element. Here, ΔR is an increase in element resistance due to the applied magnetic field, and n is the number of pairs of the semiconductor operation layer and the short-circuit electrode. When L / W, which is the ratio of the width W of the semiconductor operation layer to the distance L between the short circuit electrodes, and the length Le of the short circuit electrode are fixed, the contact between the semiconductor operation layer and the short circuit electrode decreases as the width W of the semiconductor operation layer decreases. The area is small, that is, the contact resistance Rc increases, and Rp increases accordingly. That is, when the width W of the semiconductor operation layer is reduced, the magnetoresistance change rate is also reduced.

以上より、従来は、大きな磁気抵抗変化率を得るための素子構造としては、より多くのキャリアをリセット効果のある短絡電極に作用させることと、全体抵抗に対するRpの占める割合が小さいこと、すなわち、短絡電極の長さLeが十分に大きいことと、半導体動作層の幅Wが大きいことが必要であると考えられてきた。   As described above, conventionally, as an element structure for obtaining a large magnetoresistance change rate, more carriers are caused to act on the short-circuit electrode having a reset effect, and the ratio of Rp to the total resistance is small. It has been considered necessary that the length Le of the short-circuit electrode is sufficiently large and the width W of the semiconductor operation layer is large.

半導体磁気抵抗素子の動作原理の詳細については、例えば非特許文献1に、半導体磁気抵抗素子の微細化技術については、例えば、特許文献1に紹介されている。   The details of the operation principle of the semiconductor magnetoresistive element are introduced in Non-Patent Document 1, for example, and the miniaturization technology of the semiconductor magnetoresistive element is introduced in Patent Document 1, for example.

H.WEISS著、片岡照榮訳、「磁電変換素子の構造と応用」、コロナ社、p.16−22H. WEISS, translated by Teruaki Kataoka, “Structure and Application of Magnetoelectric Conversion Elements”, Corona, p. 16-22 特開2001−68755号公報JP 2001-68755 A

半導体磁気抵抗素子を用いて高精度で歯車回転検出を行うためには、狭ピッチの歯車を使用する必要がある。一般に、歯車のピッチP(歯車の隣合う山−山、若しくは谷−谷の距離)はモジュールMを用いて、P=Mπ(mm)と定義される。   In order to detect gear rotation with high accuracy using a semiconductor magnetoresistive element, it is necessary to use a gear with a narrow pitch. In general, the pitch P of the gear (the distance between the adjacent crests and crests or the trough and trough of the gear) is defined as P = Mπ (mm) using the module M.

モジュールMの小さい歯車ほどピッチPは小さくなり、高精度の歯車回転検出が可能となる。例えば、10cm程度の車両位置検出精度で十分な鉄道の車軸用歯車はM=2〜3が、数百μm以下の高精度の歯車回転制御が必要な工作機械ではM=0.4〜0.8がICと組み合わされて使用されており、さらに精密制御が必要なものはM=0.2が使用されている。   The smaller the gear of the module M, the smaller the pitch P, and the gear rotation can be detected with high accuracy. For example, M = 2 to 3 is used for railway axle gears with sufficient vehicle position detection accuracy of about 10 cm, and M = 0.4 to 0 .0 for machine tools that require high-precision gear rotation control of several hundred μm or less. 8 is used in combination with the IC, and M = 0.2 is used for those requiring further precise control.

半導体磁気抵抗素子を用いて歯車の回転を検出する場合、通常、半導体磁気抵抗素子を歯車のピッチPの半分あるいはそれ以下の半導体動作層の幅とする。つまり、歯車のモジュールMが小さくなるほど半導体磁気抵抗素子の幅(図1(a)のWに相当)を小さくする必要がある。上述のM=0.2の場合に、このWは、0.2×π/2=0.314mm、すなわち、314μm以下となる。   When the rotation of a gear is detected using a semiconductor magnetoresistive element, the semiconductor magnetoresistive element is usually set to a width of the semiconductor operation layer that is half or less than the pitch P of the gear. That is, the smaller the gear module M, the smaller the width of the semiconductor magnetoresistive element (corresponding to W in FIG. 1A). When M = 0.2 described above, this W is 0.2 × π / 2 = 0.314 mm, that is, 314 μm or less.

しかしながら、半導体磁気抵抗素子には最適な形状、すなわち、短絡電極間距離Lと半導体動作層の幅Wの比であるL/Wに最適値があるので、歯車の狭ピッチ化にあわせてやみくもに半導体動作層の幅Wを小さくすることはできない。なぜならば、例えばL/Wの最適値が0.2で半導体動作層の幅Wが10μmとした場合、短絡電極間距離Lは、10μm×0.2=2μmとなり、ファインパターン形成に高度な技術を要する。   However, since there is an optimal value for the semiconductor magnetoresistive element, that is, L / W, which is the ratio of the distance L between the short-circuited electrodes and the width W of the semiconductor operation layer, it is difficult to understand as the gear pitch becomes narrower. The width W of the semiconductor operation layer cannot be reduced. This is because, for example, when the optimum value of L / W is 0.2 and the width W of the semiconductor operation layer is 10 μm, the distance L between the short-circuit electrodes is 10 μm × 0.2 = 2 μm, which is an advanced technique for fine pattern formation. Cost.

また、短絡電極の長さLeを一定にして半導体動作層の幅Wを小さくすると、接触抵抗Rcの増加のために、磁気抵抗効果のない抵抗成分Rpの全体抵抗に占める割合が大きくなり、磁気抵抗変化率が小さくなってしまうという問題があった。   Further, if the length Le of the semiconductor operation layer is reduced with the length Le of the short-circuited electrode being constant, the ratio of the resistance component Rp having no magnetoresistance effect to the total resistance increases due to the increase of the contact resistance Rc. There was a problem that the rate of resistance change would be small.

図3は、半導体動作層がGaAs基板上に形成されたInSb(膜厚:1μm、キャリア密度:7×1016(/cm3)、電子移動度:42000cm2/Vs)で、半導体動作層の幅Wが100μmと60μm、30μmの磁気抵抗効果を示した図である。素子のL/Wは0.2、短絡電極の長さLeは10μmの一定値としている。半導体動作層の幅Wが100μmから30μmになると、外部磁場0.2テスラで、磁気抵抗変化率が57%から43%に落ちている。これは、半導体動作層の幅Wが小さくなり接触抵抗Rcが大きくなった分、無磁場でのRpの抵抗が増加し、磁気抵抗変化率であるΔR/{n×(R1+Rp)}が小さくなってしまったと理解できる。 FIG. 3 shows an InSb (film thickness: 1 μm, carrier density: 7 × 10 16 (/ cm 3 ), electron mobility: 42000 cm 2 / Vs) formed on a GaAs substrate. It is the figure which showed the magnetoresistive effect whose width W is 100 micrometers, 60 micrometers, and 30 micrometers. The L / W of the element is a constant value of 0.2, and the length Le of the short-circuit electrode is 10 μm. When the width W of the semiconductor operation layer is changed from 100 μm to 30 μm, the magnetoresistance change rate is reduced from 57% to 43% at an external magnetic field of 0.2 Tesla. This is because the resistance of Rp in the absence of a magnetic field increases as the width W of the semiconductor operation layer decreases and the contact resistance Rc increases, so that ΔR / {n × (R 1 + Rp)} which is the magnetoresistance change rate is I can understand that it has become smaller.

このように、半導体動作層の幅Wが100μm程度以下の半導体磁気抵抗素子を設計するには、上述したような制約があり、また、半導体動作層の幅Wが100μm程度以上の場合に較べて、性能が劣化するという問題があった。したがって、半導体動作層の幅Wが100μm程度以下であっても、性能の劣化が少ない半導体磁気抵抗素子が求められていた。   As described above, the design of the semiconductor magnetoresistive element having the semiconductor operation layer width W of about 100 μm or less is limited as described above, and also compared with the case where the semiconductor operation layer width W is about 100 μm or more. There was a problem that the performance deteriorated. Accordingly, there has been a demand for a semiconductor magnetoresistive element with little deterioration in performance even when the width W of the semiconductor operation layer is about 100 μm or less.

本発明は、このような問題に鑑みてなされたもので、その目的とするところは、半導体動作層の幅Wが100μm程度以下の半導体磁気抵抗素子を、従来の設計手法に基づいて設計するよりも高性能な半導体磁気抵抗素子を提供することにあり、また、半導体動作層の幅Wが100μm程度以下の半導体磁気抵抗素子の効果的な設計手法を提供することにある。言い換えれば、半導体動作層の幅Wが100μm程度以下であっても、実質的に同等の性能の、あるいは性能劣化の少ない、半導体磁気抵抗素子を提供することにある。   The present invention has been made in view of such problems. The object of the present invention is to design a semiconductor magnetoresistive element having a semiconductor operation layer width W of about 100 μm or less based on a conventional design method. Is to provide a high-performance semiconductor magnetoresistive element, and to provide an effective design technique for a semiconductor magnetoresistive element having a semiconductor operating layer width W of about 100 μm or less. In other words, it is an object to provide a semiconductor magnetoresistive element having substantially the same performance or little performance deterioration even when the width W of the semiconductor operation layer is about 100 μm or less.

本発明は、このような目的を達成するために、請求項1に記載の発明は、基板上に形成された薄膜状半導体動作層と、当該半導体動作層上の少なくとも2つの端部に配置された入出力電極と、当該入出力電極間の前記半導体動作層上で、前記入出力電極間に延在する前記半導体層の延在方向と直角方向に延在する形で、前記半導体層の前記延在方向に一定間隔をおいて、配置された複数の短絡電極とを有する半導体磁気抵抗素子において、前記入出力電極間に延在する前記半導体層の延在方向と直角方向の前記半導体動作層の幅が60μm以下であり、前記短絡電極の、前記半導体層の延在方向の長さが5μm以下であり、前記半導体動作層の幅を前記W、前記一定間隔の複数の短絡電極間の距離をLとしたとき、LとWの比であるL/Wが0.3以下であることを特徴とするものである。   In order to achieve such an object, the present invention is arranged in a thin film semiconductor operation layer formed on a substrate and at least two ends on the semiconductor operation layer. In the form extending on the semiconductor operation layer between the input / output electrodes and the semiconductor operation layer between the input / output electrodes in a direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes. In a semiconductor magnetoresistive element having a plurality of short-circuit electrodes arranged at regular intervals in the extending direction, the semiconductor operation layer in a direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes The width of the semiconductor layer is 5 μm or less, the width of the semiconductor operation layer is W, and the distance between the plurality of short-circuited electrodes at a constant interval is 60 μm or less. When L is L, L / W, which is the ratio of L and W, is 0. .3 or less.

また、請求項2の発明は、請求項1に記載の半導体磁気抵抗素子であって、前記L/Wが0.1以上であることを特徴とするものである。   A second aspect of the present invention is the semiconductor magnetoresistive element according to the first aspect, wherein the L / W is 0.1 or more.

また、請求項3の発明は、請求項1または2に記載の半導体磁気抵抗素子であって、前記短絡電極の長さが2μm以上であることを特徴とするものである。   The invention of claim 3 is the semiconductor magnetoresistive element according to claim 1 or 2, wherein the length of the short-circuit electrode is 2 μm or more.

また、請求項4の発明は、請求項1乃至3のいずれかに記載の半導体磁気抵抗素子であって、前記半導体動作層の組成がInAsySb1-y(0≦y≦1)であることを特徴とするものである。 The invention according to claim 4 is the semiconductor magnetoresistive element according to any one of claims 1 to 3, wherein the composition of the semiconductor operation layer is InAs y Sb 1-y (0 ≦ y ≦ 1). It is characterized by this.

また、請求項5の発明は、請求項1乃至4のいずれかに記載の半導体磁気抵抗素子であって、前記半導体動作層にIV族元素、もしくは、VI族元素がドーピングされており、その電子密度が1×1016〜1×1018(cm-3)であることを特徴とするものである。 The invention according to claim 5 is the semiconductor magnetoresistive element according to any one of claims 1 to 4, wherein the semiconductor operation layer is doped with a group IV element or a group VI element, and the electron The density is 1 × 10 16 to 1 × 10 18 (cm −3 ).

また、請求項6の発明は、請求項1乃至5のいずれかに記載の半導体磁気抵抗素子であって、前記半導体動作層が作成される基板は、SiまたはGaAsであることを特徴とするものである。   A sixth aspect of the present invention is the semiconductor magnetoresistive element according to any one of the first to fifth aspects, wherein the substrate on which the semiconductor operation layer is formed is Si or GaAs. It is.

請求項7の発明は、半導体磁気抵抗素子の設計方法であって、基板上に形成された薄膜状半導体動作層と、当該半導体動作層上の少なくとも2つの端部に配置された入出力電極と、当該入出力電極間の前記半導体動作層上で、前記入出力電極間に延在する前記半導体層の延在方向と直角方向に延在する形で配置された複数の短絡電極とを有する半導体磁気抵抗素子の設計方法であって、前記入出力電極間に延在する前記半導体層の延在方向と直角方向の前記半導体動作層の幅を60μm以下とし、前記短絡電極の、前記半導体層の延在方向の長さを5μm以下とし、前記半導体動作層の前記幅をW、前記一定間隔の複数の短絡電極間の距離をLとしたとき、LとWの比であるL/Wが0.3以下とすることを特徴とする。   The invention of claim 7 is a method for designing a semiconductor magnetoresistive element, comprising a thin film semiconductor operation layer formed on a substrate, and input / output electrodes disposed at at least two ends on the semiconductor operation layer, And a plurality of short-circuit electrodes arranged on the semiconductor operation layer between the input / output electrodes so as to extend in a direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes. A method for designing a magnetoresistive element, wherein a width of the semiconductor operation layer in a direction perpendicular to an extending direction of the semiconductor layer extending between the input and output electrodes is set to 60 μm or less, and the short-circuit electrode of the semiconductor layer When the length in the extending direction is 5 μm or less, the width of the semiconductor operation layer is W, and the distance between the plurality of short-circuited electrodes at a constant interval is L, L / W as a ratio of L to W is 0. .3 or less.

また、請求項8の発明は、請求項7に記載の半導体磁気抵抗素子の設計方法であって、前記L/Wが0.1以上であることを特徴とする。   The invention of claim 8 is the method of designing a semiconductor magnetoresistive element according to claim 7, wherein the L / W is 0.1 or more.

また、請求項9の発明は、請求項7または8に記載の半導体磁気抵抗素子の設計方法であって、前記短絡電極の長さが2μm以上であることを特徴とする。   The invention of claim 9 is the method of designing a semiconductor magnetoresistive element according to claim 7 or 8, wherein the length of the short-circuit electrode is 2 μm or more.

また、請求項10の発明は、請求項7乃至9のいずれかに記載の半導体磁気抵抗素子の設計方法であって、前記半導体動作層の組成がInAsySb1-y(0≦y≦1)であることを特徴とする。 The invention of claim 10 is the semiconductor magnetoresistive element design method according to any one of claims 7 to 9, wherein the composition of the semiconductor operating layer is InAs y Sb 1-y (0 ≦ y ≦ 1). ).

また、請求項11の発明は、請求項7乃至10のいずれかに記載の半導体磁気抵抗素子の設計方法であって、前記半導体動作層にIV族元素、もしくは、VI族元素がドーピングされており、その電子密度が1×1016〜1×1018(cm-3)であることを特徴とする。 The invention of claim 11 is the method of designing a semiconductor magnetoresistive element according to any one of claims 7 to 10, wherein the semiconductor operation layer is doped with a group IV element or a group VI element. The electron density is 1 × 10 16 to 1 × 10 18 (cm −3 ).

また、請求項12の発明は、請求項7乃至11のいずれかに記載の半導体磁気抵抗素子の設計方法であって、前記半導体動作層が作成される基板は、SiまたはGaAsであることを特徴とする。   The invention of claim 12 is the method of designing a semiconductor magnetoresistive element according to any one of claims 7 to 11, wherein the substrate on which the semiconductor operation layer is formed is Si or GaAs. And

以上説明したように本発明によれば、半導体動作層の幅Wが100μm程度以下であっても、実質的に同等の性能の、あるいは性能劣化の少ない、半導体磁気抵抗素子を提供することができる。   As described above, according to the present invention, it is possible to provide a semiconductor magnetoresistive element having substantially the same performance or little performance deterioration even when the width W of the semiconductor operation layer is about 100 μm or less. .

以下、図面を参照して本発明の実施例について説明する。なお、各図における同じ符号は、同じものあるいは類似物を示している。   Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol in each figure has shown the same thing or the similar thing.

本発明者らは、磁場シミュレーションを用いて素子形状の最適化を目指して、上述した各パラメータの変化とその結果としての磁気抵抗効果との関係を求めることを試みた。この結果、短絡電極の長さLeを短く設計することで、半導体動作層の幅Wを小さく、すなわち、より小さなモジュールMの歯車に対応する大きさの磁気抵抗素子においても、従来の大きな半導体動作層の幅Wと同程度の高い磁気抵抗変化率を維持できることを発見した。   The present inventors have attempted to obtain the relationship between the change of each parameter described above and the resulting magnetoresistance effect, aiming at optimization of the element shape using magnetic field simulation. As a result, by designing the length Le of the short-circuit electrode to be short, the width W of the semiconductor operation layer is reduced, that is, even in a magnetoresistive element having a size corresponding to the gear of the smaller module M, the conventional large semiconductor operation It was discovered that the rate of change in magnetoresistance as high as the layer width W can be maintained.

背景技術において説明したように、大きな磁気抵抗変化率を得るためには、磁気抵抗効果の期待できないRpを小さくする必要がある。   As described in the background art, in order to obtain a large rate of change in magnetoresistance, it is necessary to reduce Rp where the magnetoresistance effect cannot be expected.

図4は、半導体動作層の幅Wが125μmの場合の無磁場におけるRp(磁気抵抗素子としての直列抵抗成分となる短絡電極を含む部分の抵抗)の短絡電極の長さ依存性の計算結果を示す図である。ここで、電極のシート抵抗として0.058Ω、半導体動作層と短絡電極が接している面積が1250μm2のときの接触抵抗値Rcとして0.3Ω、半導体動作層のシート抵抗として20Ωを使用した。また、接触抵抗Rcは半導体動作層と短絡電極との接する面積に反比例すると仮定している。つまり、短絡電極の長さLeが大きければ接触抵抗Rcは小さい。 FIG. 4 shows the calculation result of the short-circuit electrode length dependency of Rp (resistance of the portion including the short-circuit electrode serving as a series resistance component as a magnetoresistive element) in the absence of a magnetic field when the width W of the semiconductor operation layer is 125 μm. FIG. Here, 0.058Ω was used as the sheet resistance of the electrode, 0.3Ω was used as the contact resistance value Rc when the area where the semiconductor operating layer was in contact with the short-circuit electrode was 1250 μm 2 , and 20Ω was used as the sheet resistance of the semiconductor operating layer. The contact resistance Rc is assumed to be inversely proportional to the area where the semiconductor operating layer and the short-circuit electrode are in contact. That is, if the length Le of the short-circuit electrode is large, the contact resistance Rc is small.

図4で短絡電極の長さLeが7μm以上の領域では、短絡電極と半導体動作層の接触面積が大きくなるため接触抵抗Rcは小さくなり、Rpの抵抗値は小さくなる。従来の半導体磁気抵抗素子はこの領域を使用していた。この領域の抵抗値の関係は、R2>Rsである。 In FIG. 4, in the region where the length Le of the short-circuit electrode is 7 μm or more, the contact area between the short-circuit electrode and the semiconductor operation layer increases, so that the contact resistance Rc decreases and the resistance value of Rp decreases. A conventional semiconductor magnetoresistive element uses this region. The relationship between the resistance values in this region is R 2 > Rs.

一方、短絡電極の長さLeが7μm以下の領域でもRpの抵抗値は小さくなっている。これは短絡電極の長さLeが小さくなることで接触抵抗Rcが増加するが、同時に短絡電極直下の半導体動作層抵抗R2が減少し、R2とRsの大小関係が逆転する。つまり、R2<Rsの関係となっていることを示している。 On the other hand, the resistance value of Rp is small even in the region where the length Le of the short-circuit electrode is 7 μm or less. This is because the contact resistance Rc increases as the length Le of the short-circuit electrode decreases, but at the same time, the semiconductor operating layer resistance R 2 immediately below the short-circuit electrode decreases, and the magnitude relationship between R 2 and Rs is reversed. That is, it is shown that R 2 <Rs.

従来、小さい短絡電極の長さLeではキャリアは短絡電極に作用しなくなり、リセット効果が期待できないと考えられてきたため、この領域(短絡電極の長さLeが7μm以下)は利用されてこなかった。従来は短絡電極にキャリアを作用させることを想定していたためRpの磁気抵抗効果は期待できないと考えられてきた。   Conventionally, it has been considered that the carrier does not act on the short-circuited electrode with a small length of the short-circuited electrode and a reset effect cannot be expected. Therefore, this region (the length Le of the short-circuited electrode is 7 μm or less) has not been used. Conventionally, since it was assumed that carriers act on the short-circuit electrode, it has been considered that the magnetoresistance effect of Rp cannot be expected.

しかしながら、上述した図4の結果から考察すると、キャリアがR2に作用しだすと、R2は磁気抵抗効果を示すのでRpも磁気抵抗効果を発動するようになると考えられる。 However, considering from the result of FIG. 4 mentioned above, the carrier is the starts to act on the R 2, R 2 is Rp would also be to trigger the magnetoresistance effect exhibits a magnetoresistance effect.

以上のことを踏まえて、半導体動作層の幅Wが125μm、60μm、30μmで、短絡電極の長さLeが10μm、5μm、2μmのときの磁気抵抗変化率のL/W依存性を算出した。外部磁場強度は0.2テスラで、電子移動度は42000cm2/Vsとした。図5(a)は、半導体動作層の幅Wが125μmの場合の磁気抵抗変化率のL/W依存性を表す図である。図5(b)は、同様に、半導体動作層の幅Wが60μmの磁気抵抗変化率のL/W依存性を表す図である。図5(c)は同様に、半導体動作層の幅Wが30μmの磁気抵抗変化率のL/W依存性を表す図である。図5(a)における、丸、菱形、三角は、実デバイスの測定値である。図5(a)に示したように、磁場シミュレーションの計算と、実際の測定値とに相関があることが分かる。 Based on the above, the L / W dependency of the magnetoresistance change rate when the width W of the semiconductor operation layer is 125 μm, 60 μm, and 30 μm and the length Le of the short-circuit electrode is 10 μm, 5 μm, and 2 μm was calculated. The external magnetic field strength was 0.2 Tesla, and the electron mobility was 42000 cm 2 / Vs. FIG. 5A is a diagram showing the L / W dependency of the magnetoresistance change rate when the width W of the semiconductor operation layer is 125 μm. FIG. 5B is a diagram similarly showing the L / W dependency of the magnetoresistance change rate when the width W of the semiconductor operation layer is 60 μm. FIG. 5C is also a diagram showing the L / W dependency of the magnetoresistance change rate when the width W of the semiconductor operation layer is 30 μm. In FIG. 5A, circles, diamonds, and triangles are measured values of actual devices. As shown in FIG. 5A, it can be seen that there is a correlation between the calculation of the magnetic field simulation and the actual measurement value.

図5からは、以下のことが理解される。半導体動作層の幅Wがどの場合でも、短絡電極の長さLeが小さくなるほど磁気抵抗変化率の増加幅が大きくなる。特に、半導体動作層の幅Wが小さいときにその増加幅は大きく、L/W=0.2のときに、125μmの場合は短絡電極の長さLeが10μmから2μmになることで、磁気抵抗変化率が57.2%から62.3%の微増にとどまるのに対し、30μmの場合は45.6%から61.8%にまで増加している。   The following is understood from FIG. Regardless of the width W of the semiconductor operation layer, the increase width of the magnetoresistance change rate increases as the length Le of the short-circuit electrode decreases. In particular, when the width W of the semiconductor operation layer is small, the increase width is large. When L / W = 0.2, the length Le of the short-circuit electrode is changed from 10 μm to 2 μm in the case of 125 μm. While the rate of change is only a slight increase from 57.2% to 62.3%, in the case of 30 μm, the increase is from 45.6% to 61.8%.

小さいL/Wで磁気抵抗変化率が低下するのは、印加磁場によるR1の抵抗増加割合ΔR1/R1は大きくなるが、短絡電極間距離Lが小さくなるにしたがってR1が小さくなり、無磁場でのR1とRpの抵抗のバランスが崩れ、全体抵抗に対するRpの占める割合が大きくなる、すなわち、n×Rp/{n×(R1+Rp)}が大きくなるからであると考えられる。ここで、ΔR1は印加磁場によるR1の抵抗増加成分である。 The magnetoresistance ratio decreases with a smaller L / W, the injection resistance increase rate [Delta] R 1 / R 1 of R 1 by the magnetic field is increased, R 1 is reduced in accordance with short-circuit distance L between electrodes is small, It is considered that the resistance balance between R 1 and Rp in the absence of a magnetic field is lost, and the ratio of Rp to the total resistance increases, that is, n × Rp / {n × (R 1 + Rp)} increases. . Here, ΔR 1 is a resistance increasing component of R 1 due to the applied magnetic field.

図6(a)、(b)、(c)は、図5で使用した同じデータを短絡電極の長さLeでまとめ直した図である。この図からは、短絡電極の長さLeが短ければ、半導体動作層の幅Wが小さくなっても磁気抵抗変化率の低下は、短絡電極の長さLeが10μmのときよりも小さいことが分かる。   FIGS. 6A, 6B, and 6C are diagrams in which the same data used in FIG. 5 is rearranged by the length Le of the short-circuit electrode. From this figure, it can be seen that if the length Le of the short-circuit electrode is short, the decrease in magnetoresistance change rate is smaller than that when the length Le of the short-circuit electrode is 10 μm even if the width W of the semiconductor operation layer is small. .

図5(a)、(b)、(c)より、短絡電極の長さLeを従来の10μmから小さくすることで、どのような半導体動作層の幅Wでも磁気抵抗効果は大きくなっており、少なくとも2μm以上5μm以下ではその効果を確認できる。   5A, 5B, and 5C, the magnetoresistive effect is increased regardless of the width W of the semiconductor operation layer by reducing the length Le of the short-circuit electrode from the conventional 10 μm. The effect can be confirmed at least from 2 μm to 5 μm.

また、半導体動作層の幅Wが小さいほどこの磁気抵抗変化率の、短絡電極の長さLeが小さくなることに対する増加幅は大きくなり、少なくとも30μm以上60μm以下でその効果を確認できる。   Further, the smaller the width W of the semiconductor operation layer, the larger the increase in the magnetoresistance change rate with respect to the decrease in the length Le of the short-circuit electrode, and the effect can be confirmed at least from 30 μm to 60 μm.

また、以上から、L/Wが小さい方が磁気抵抗効果は大きいことが理解されるが、素子の量産性と特性の安定性より実デバイスではL/W=0.1〜0.3程度が使用されている。例えば、L/W=0.01の場合、半導体動作層の幅Wが125μmであっても短絡電極間距離Lは125×0.01=1.25μmとなってしまい、短絡電極形成時のマージンが非常に小さくなってしまう。   From the above, it can be understood that the smaller the L / W, the greater the magnetoresistive effect. However, in the actual device, L / W is about 0.1 to 0.3 because of the mass productivity of the element and the stability of characteristics. in use. For example, when L / W = 0.01, even if the width W of the semiconductor operation layer is 125 μm, the distance L between the short-circuit electrodes is 125 × 0.01 = 1.25 μm, and a margin for forming the short-circuit electrodes Becomes very small.

また、量産時には、短絡電極間距離Lと半導体動作層の幅Wのマージン分だけL/Wが変化してしまい、その結果磁気抵抗変化率も変化するので、可能な限り磁気抵抗変化率の変化が小さい領域でL/Wを設定する必要がある。   In mass production, L / W changes by the margin of the distance L between the short-circuit electrodes and the width W of the semiconductor operation layer, and as a result, the magnetoresistance change rate also changes. It is necessary to set L / W in a region where is small.

本発明による磁気抵抗素子においては、短絡電極の長さLeを小さくする効果は、特に半導体動作層の幅Wが小さいときに効果を発揮することが分かる。つまり、本発明を使用して短絡電極の長さLeを小さくすることで、半導体動作層の幅Wを小さく、すなわち、小さいモジュールMに対応した素子においても、従来の大きな半導体動作層の幅Wと同程度の高い磁気抵抗変化率を実現することができる。   In the magnetoresistive element according to the present invention, it can be seen that the effect of reducing the length Le of the short-circuit electrode is particularly effective when the width W of the semiconductor operation layer is small. That is, by using the present invention to reduce the length Le of the short-circuit electrode, the width W of the semiconductor operation layer is reduced, that is, even in the element corresponding to the small module M, the width W of the conventional large semiconductor operation layer is reduced. High magnetoresistance change rate can be realized.

以下、図面を参照して本発明の実施例について説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図7(a)、(b)は、本発明の磁気抵抗素子の一実施例の構造を説明するための図で、図7(a)は素子全体の上面図、図7(b)は図7(a)でのA−Aでの断面図である。図中、符号5が基板、符号6は半導体動作層で、符号7が入出力電極、符号8が短絡電極である。本発明に用いられる半導体動作層6は、高い磁気抵抗変化率を得るためにできるだけ高い電子移動度を有していることが好ましく、Si、GaAsの半導体はもちろんのこと、InSbやInAsおよびそれらの混晶系であるInAsSbなどが特に好ましいものとなる。   7A and 7B are views for explaining the structure of an embodiment of the magnetoresistive element of the present invention. FIG. 7A is a top view of the entire element, and FIG. It is sectional drawing in AA in 7 (a). In the figure, reference numeral 5 is a substrate, reference numeral 6 is a semiconductor operation layer, reference numeral 7 is an input / output electrode, and reference numeral 8 is a short-circuit electrode. The semiconductor operation layer 6 used in the present invention preferably has as high an electron mobility as possible in order to obtain a high magnetoresistance change rate. In addition to Si and GaAs semiconductors, InSb, InAs, and their InAsSb, which is a mixed crystal system, is particularly preferable.

本発明に用いられる基板5は、固体形状を示すものであればどんなものでも良く、例えば半導体でも誘電体でもセラミックでもガラス基板でも用いることができる。また、マイカ等のフレキシブル性を有する基板5上に半導体動作層6を形成し、他の基板上に、転写しても良い。また、半導体基板の中でもGaAs、Si、InP、GaPなどの基板を用いると、特に半導体動作層6をエピタキシャル成長させることで、高い電子移動度が得られるようになり、特に好ましいものとなる。   The substrate 5 used in the present invention may be any substrate as long as it exhibits a solid shape. For example, a semiconductor, a dielectric, a ceramic, or a glass substrate can be used. Alternatively, the semiconductor operation layer 6 may be formed on a flexible substrate 5 such as mica and transferred onto another substrate. Moreover, when a substrate such as GaAs, Si, InP, or GaP is used among the semiconductor substrates, high electron mobility can be obtained particularly by epitaxially growing the semiconductor operation layer 6, which is particularly preferable.

図8は、基板5と半導体動作層6との間に緩衝層9を挿入した場合を示す図である。半導体動作層6の電子移動度をより高くするためには、図8の構成とすることができる。この場合、緩衝層9としては半導体でも誘電体でも良く、誘電体としてはSiO2、Si34などが用いられ、半導体としては半導体動作層6と格子定数がなるべく近いものを選択することが好ましく、GaAs、InAs、GaSb、AlSbのような2元系、InGaAs、GaAsSb、AlAsSb、AlInSbのような3元系、AlGaAsSbのような4元系を用いても良い。さらに上述した材料を交互に積層させて超格子構造とすることはさらに好ましい形態となる。 FIG. 8 is a diagram showing a case where the buffer layer 9 is inserted between the substrate 5 and the semiconductor operation layer 6. In order to further increase the electron mobility of the semiconductor operation layer 6, the configuration shown in FIG. In this case, the buffer layer 9 may be a semiconductor or a dielectric, SiO 2 , Si 3 N 4 or the like is used as the dielectric, and a semiconductor having a lattice constant as close as possible to the semiconductor operation layer 6 may be selected. Preferably, a binary system such as GaAs, InAs, GaSb, and AlSb, a ternary system such as InGaAs, GaAsSb, AlAsSb, and AlInSb, and a quaternary system such as AlGaAsSb may be used. Further, it is a more preferable form that the above-described materials are alternately laminated to form a superlattice structure.

本発明での半導体動作層6中のキャリアを増加させるための不純物を添加する方法としては、半導体動作層6を形成する際に同時に行っても良いが、成膜後にイオン注入法を用いて打ち込んでも良い。用いられる不純物は、例えば、InSbやInAsのようなIII−V族化合物半導体の場合は、Si、SnのようなIV族元素や、Se、Te、Sに代表されるVI族元素を添加すると良い。   As a method of adding impurities for increasing carriers in the semiconductor operation layer 6 in the present invention, it may be performed simultaneously with the formation of the semiconductor operation layer 6, but it is implanted using an ion implantation method after film formation. But it ’s okay. For example, in the case of a III-V group compound semiconductor such as InSb or InAs, the impurities used may be a group IV element such as Si or Sn, or a group VI element typified by Se, Te, or S. .

半導体動作層6中にキャリアを増加させるための不純物を添加することで、作製した磁気抵抗素子の温度特性を改善する効果があるが、あまり多くの不純物を添加してしまうと、磁気抵抗素子の感度を左右するキャリア移動度が低下してしまうという問題があるため、添加するキャリアの数は、1×1016/cm3から1×1018/cm3とすることが好ましく、さらに好ましくは、1×1016/cm3から3×1017/cm3とするのが良い。 Adding impurities for increasing carriers in the semiconductor operation layer 6 has an effect of improving the temperature characteristics of the manufactured magnetoresistive element. However, if too much impurities are added, the magnetoresistive element Since there is a problem that the carrier mobility that affects the sensitivity is lowered, the number of added carriers is preferably 1 × 10 16 / cm 3 to 1 × 10 18 / cm 3, and more preferably, It is good to set it as 1 * 10 < 16 > / cm < 3 > to 3 * 10 < 17 > / cm < 3 >.

本発明での半導体動作層6および緩衝層9を形成する方法としては、真空蒸着法が一般的に用いられるが、分子線エピタキシー(MBE)法は薄膜の膜厚や組成の制御性が高く特に好ましい方法である。   As a method for forming the semiconductor operation layer 6 and the buffer layer 9 in the present invention, a vacuum deposition method is generally used. However, the molecular beam epitaxy (MBE) method has a particularly high controllability of the film thickness and composition of the thin film. This is the preferred method.

本発明での入出力電極7や短絡電極8に用いられる電極材料は、Cu単層やTi/Au、Ti/Pt/Au、Ni/Au、Ni/Pt/Au、Cu/Pt/Au、Cu/Ni/Auのような積層としても良い。この電極材料は、作製した素子の使用される動作条件と環境条件とに耐えられる材質であれば、どのような材料を用いてもかまわない。   The electrode material used for the input / output electrode 7 and the short-circuit electrode 8 in the present invention is a Cu single layer, Ti / Au, Ti / Pt / Au, Ni / Au, Ni / Pt / Au, Cu / Pt / Au, Cu A laminate such as / Ni / Au may be used. This electrode material may be any material as long as it can withstand the operating conditions and environmental conditions in which the manufactured element is used.

また、電極を形成する方法としては、電子ビーム蒸着や抵抗加熱蒸着といった一般的な真空蒸着法や、スパッタ法やメッキ法によって形成しても良い。また、電極形成後に電極と半導体動作層とのオーミック接触性を良好にするために、急昇温熱アニール(RTA)法等を用いて熱処理することも好ましい。   In addition, as a method for forming the electrode, the electrode may be formed by a general vacuum deposition method such as electron beam deposition or resistance heating deposition, a sputtering method, or a plating method. In order to improve the ohmic contact between the electrode and the semiconductor operation layer after the electrode is formed, it is also preferable to perform a heat treatment using a rapid temperature rise annealing (RTA) method or the like.

図9は、素子の耐環境性を高めるための構造例を示す図である。Si34やSiO2等のような保護膜10を形成した後に必要な部分のみ保護膜を開口し、短絡電極と入出力電極を形成することができる。 FIG. 9 is a diagram showing a structural example for improving the environmental resistance of the element. After the protective film 10 such as Si 3 N 4 or SiO 2 is formed, the protective film can be opened only at necessary portions to form short-circuit electrodes and input / output electrodes.

以下に本発明を具体的な磁気抵抗素子の作製方法の例について述べるが、本発明はこれらの例のみに限定されるものではない。   Hereinafter, the present invention will be described with reference to specific examples of a method for manufacturing a magnetoresistive element, but the present invention is not limited to these examples.

(実施例1)
薄膜形成方法の一例として分子線エピタキシー法を用いて、GaAs基板上に半導体動作層としてSnドープInSb薄膜を形成する場合の詳細について述べる。まず、GaAs基板にAsを照射しながら650℃で加熱し表面酸素を脱離させる。次に、580℃に温度を下げてGaAsバッファ層を200nmの厚さで形成する。次に、Asを照射しながら400℃まで温度を下げた後、SnとIn、Sbを同時に基板に照射しながら半導体動作層の膜厚1μmからなるSnドープInSb薄膜を形成した。この際、InSb薄膜の電子移動度は、7×1016/cm3になるようにSnセル温度を調節した。
(Example 1)
The details of forming a Sn-doped InSb thin film as a semiconductor operating layer on a GaAs substrate using molecular beam epitaxy as an example of the thin film forming method will be described. First, the surface oxygen is desorbed by heating at 650 ° C. while irradiating the GaAs substrate with As. Next, the temperature is lowered to 580 ° C. to form a GaAs buffer layer with a thickness of 200 nm. Next, the temperature was lowered to 400 ° C. while irradiating As, and then a Sn-doped InSb thin film having a semiconductor operating layer thickness of 1 μm was formed while simultaneously irradiating the substrate with Sn, In, and Sb. At this time, the Sn cell temperature was adjusted so that the electron mobility of the InSb thin film was 7 × 10 16 / cm 3 .

磁気抵抗素子の作製プロセスは、通常のフォトリソグラフィーの技術を用いることができる。まず、InSb/GaAs基板のInSb表面にフォトレジストを、スピンコーターを用いて均一に塗布する。フォトレジストの塗布条件は、100cpの粘度で3200rpmの回転速度で20秒間回転すると2.5μmの厚さとなる。InSbのメサエッチング用のフォトマスクを用いて、露光・現像した後に塩酸・過酸化水素系のエッチング液で所望の形状にInSb薄膜をメサエッチングする。ウェットエッチングの場合、サイドエッチングの影響があるので、現実的に制御良く作製できる半導体動作層の幅Wは、10μm程度となる。   As a manufacturing process of the magnetoresistive element, a normal photolithography technique can be used. First, a photoresist is uniformly applied to the InSb surface of the InSb / GaAs substrate using a spin coater. The photoresist coating condition is 2.5 μm when rotated for 20 seconds at a rotational speed of 3200 rpm with a viscosity of 100 cp. Using a photomask for InSb mesa etching, after exposure and development, the InSb thin film is mesa-etched into a desired shape with a hydrochloric acid / hydrogen peroxide-based etching solution. In the case of wet etching, since there is an influence of side etching, the width W of the semiconductor operation layer that can be manufactured practically with good control is about 10 μm.

この場合は、ウェットエッチング法を用いて半導体動作層のエッチングを行った例を紹介したが、イオンミリングや反応性イオンエッチング法のドライエッチングによってメサエッチングを行っても良い。ドライエッチングの場合、サイドエッチング量は小さいので、3μm程度まで半導体動作層の幅Wを小さくすることができる。   In this case, the example in which the semiconductor operation layer is etched using the wet etching method has been introduced. However, the mesa etching may be performed by dry milling using ion milling or reactive ion etching. In the case of dry etching, since the amount of side etching is small, the width W of the semiconductor operation layer can be reduced to about 3 μm.

次に再度、フォトレジストを塗布した後に、短絡電極と入出力電極を形成するための露光・現像を行い、真空蒸着法により電極を蒸着し、リフトオフ法で電極を形成する。電極形成工程では、短絡電極と入出力電極を一度に形成しても良いし、2度の工程に分けても良い。   Next, after applying a photoresist again, exposure and development for forming a short-circuit electrode and an input / output electrode are performed, an electrode is deposited by a vacuum deposition method, and an electrode is formed by a lift-off method. In the electrode forming step, the short-circuit electrode and the input / output electrode may be formed at once, or may be divided into two steps.

フォトレジストにより、電極形成用のレジストパターンを形成した後に、電子ビーム蒸着法により電極として50nm厚のTiと400nm厚のAuからなる積層電極を形成し、リフトオフ法を用いて所望の電極形状を作製し、素子形状を完成させた。この際の半導体動作層の幅Wを30μm、短絡電極の長さLeを2μmとし、短絡電極間隔Lが3μm、4.5μm、6μm、7.5μm、9μm、12μmの計6種類の素子を作製した。本実施例で使用した露光装置は等倍露光タイプであるので、短絡電極の長さLeは1μm程度の微細加工が限界であるが、ステッパー等を用いれば0.1μm程度まで形成可能となる。   After forming a resist pattern for forming an electrode with a photoresist, a laminated electrode made of 50 nm thick Ti and 400 nm thick Au is formed as an electrode by an electron beam evaporation method, and a desired electrode shape is formed using a lift-off method Thus, the element shape was completed. At this time, the width W of the semiconductor operation layer is 30 μm, the length Le of the short circuit electrode is 2 μm, and the short circuit electrode interval L is 3 μm, 4.5 μm, 6 μm, 7.5 μm, 9 μm, and 12 μm. did. Since the exposure apparatus used in this embodiment is of the same size exposure type, the length Le of the short-circuit electrode is limited to fine processing of about 1 μm, but if a stepper or the like is used, it can be formed up to about 0.1 μm.

図10は、これらの素子の完成後に、磁気抵抗素子の外部磁場強度−素子端子間抵抗特性の測定を行い、0.2テスラの外部磁場強度における磁気抵抗変化率のL/W依存性を示す図である。   FIG. 10 shows the L / W dependence of the magnetoresistance change rate at an external magnetic field strength of 0.2 Tesla by measuring the external magnetic field strength of the magnetoresistive element-resistance between the element terminals after completion of these elements. FIG.

(比較例1)
図11は、実施例1と同様の方法を用いて、磁気抵抗素子を作製する際に、短絡電極の長さLeを10μm、5μmとした磁気抵抗素子の外部磁場強度−素子端子間抵抗特性の測定を行い、外部磁場強度が0.2テスラのときの磁気抵抗変化率を実施例1の結果に加えた場合の、L/Wに対する磁気抵抗変化率の変化を示す図である。
(Comparative Example 1)
FIG. 11 shows the external magnetic field strength of the magnetoresistive element with the length Le of the short-circuit electrode set to 5 μm when the magnetoresistive element is manufactured using the same method as in Example 1, and the resistance characteristic between the element terminals. It is a figure which shows the change of the magnetoresistive change rate with respect to L / W at the time of measuring and adding the magnetoresistive change rate when an external magnetic field intensity | strength is 0.2 Tesla to the result of Example 1. FIG.

比較例1では、短絡電極の長さLeを10μm、5μmとすることでRpが大きくなったために、磁気抵抗素子の外部磁場に対する磁気抵抗変化率ΔR/{n×(R1+Rp)}が小さくなったと考えられる。また、短絡電極の長さLeを小さくすると、L/Wに依存せず特性は向上する。 In Comparative Example 1, since Rp was increased by setting the length Le of the short-circuit electrode to 10 μm and 5 μm, the magnetoresistance change rate ΔR / {n × (R 1 + Rp)} with respect to the external magnetic field of the magnetoresistive element was small. It is thought that it became. Further, when the length Le of the short-circuit electrode is reduced, the characteristics are improved without depending on L / W.

さらに、短絡電極の長さLeが10μm、5μmの場合、L/Wが0.1の場合に、0.2の場合に較べてで磁気抵抗変化率が低下しているが、短絡電極の長さLeが2μmでは、L/Wが0.4から0.1に近づいても上昇しつづけている。   Further, when the length Le of the short-circuit electrode is 10 μm and 5 μm, the rate of change in magnetoresistance is lower when L / W is 0.1 than when 0.2, but the length of the short-circuit electrode When the length Le is 2 μm, the L / W continues to rise even when it approaches 0.4 to 0.1.

したがって、この条件の場合、この図からは、L/Wが0.1から0.4の範囲では、Leが2μの場合が良い特性を示す、この傾向は、L/Wが0.4から0.1になるにつれて、磁気抵抗変化率が向上することが分かる。   Therefore, under this condition, this figure shows that when L / W is in the range of 0.1 to 0.4, Le is 2 μm, which shows good characteristics. This tendency is from L / W from 0.4. It can be seen that the magnetoresistive change rate improves as the value becomes 0.1.

(比較例2)
図12は、実施例1と同様の方法を用いて、磁気抵抗素子を作製する際に、半導体動作層の幅Wを60μm、125μmとした磁気抵抗素子の外部磁場強度−素子端子間抵抗特性の測定を行い、外部磁場強度が0.2テスラのときの磁気抵抗変化率を実施例1の結果に加えた場合のL/Wに対する磁気抵抗変化率の変化を示す図である。同様に、図13は、実施例1の方法で、短絡電極の長さLeが10μmで、半導体動作層の幅Wが30μm、60μm、125μmとした磁気抵抗素子の外部磁場強度−素子端子間抵抗特性の測定を行い、外部磁場強度が0.2テスラのときのL/Wに対する磁気抵抗変化率の変化を示す図である。
(Comparative Example 2)
FIG. 12 shows the external magnetic field strength of the magnetoresistive element with the width W of the semiconductor operating layer being set to 60 μm and 125 μm when the magnetoresistive element is manufactured using the same method as in Example 1, and the resistance characteristics between the element terminals. It is a figure which shows the change of the magnetoresistive change rate with respect to L / W at the time of measuring and adding the magnetoresistive change rate when the external magnetic field strength is 0.2 Tesla to the result of Example 1. Similarly, FIG. 13 shows the external magnetic field strength of the magnetoresistive element in which the length Le of the short-circuiting electrode is 10 μm and the width W of the semiconductor operation layer is 30 μm, 60 μm, and 125 μm, and the resistance between the element terminals in the method of Example 1. It is a figure which shows the change of the magnetoresistive change rate with respect to L / W when the characteristic is measured and the external magnetic field strength is 0.2 Tesla.

短絡電極の長さLeが10μmの場合、半導体動作層の幅Wが小さくなったときの磁気抵抗変化率は著しく低下している(図13)が、短絡電極の長さLeが2μmの素子は殆ど低下していない(図12)。   When the length Le of the short-circuit electrode is 10 μm, the rate of change in magnetoresistance when the width W of the semiconductor operation layer is reduced is significantly reduced (FIG. 13), but the element with the length Le of the short-circuit electrode is 2 μm Almost no decrease (FIG. 12).

以上の比較例1および2から、短絡電極の長さLeを小さくする効果は、特に半導体動作層の幅Wが小さいときに効果を発揮していることが分かる。つまり、短絡電極の長さLeを小さくすることで、半導体動作層の幅Wを小さく、すなわち、小さいモジュールMに対応した素子においても、従来の大きな半導体動作層の幅Wと同程度の高い磁気抵抗変化率を実現することができる。   From the above Comparative Examples 1 and 2, it can be seen that the effect of reducing the length Le of the short-circuit electrode is particularly effective when the width W of the semiconductor operation layer is small. In other words, by reducing the length Le of the short-circuit electrode, the width W of the semiconductor operation layer is reduced, that is, even in an element corresponding to the small module M, the magnetic field is as high as the width W of the conventional large semiconductor operation layer. A rate of change in resistance can be realized.

(a)は半導体磁気抵抗素子の構造例の上面図を示す図であり、(b)は半導体磁気抵抗素子の構造例の断面図を示す図であり、(c)は半導体磁気抵抗素子の磁気抵抗効果の典型例を示す図である。(A) is a figure which shows the top view of the structural example of a semiconductor magnetoresistive element, (b) is a figure which shows sectional drawing of the structural example of a semiconductor magnetoresistive element, (c) is a figure which shows the magnetism of a semiconductor magnetoresistive element. It is a figure which shows the typical example of a resistance effect. 図1(b)の磁気抵抗素子における一組の半導体動作層と短絡電極の等価回路を示す図である。It is a figure which shows the equivalent circuit of a pair of semiconductor operation | movement layer and short circuit electrode in the magnetoresistive element of FIG.1 (b). 半導体動作層の幅Wが100μmと60μm、30μmの場合の、外部磁場強度と磁気抵抗変化率の関係の一例を示す図である。It is a figure which shows an example of the relationship between an external magnetic field strength and a magnetoresistive change rate in case the width W of a semiconductor operation layer is 100 micrometers, 60 micrometers, and 30 micrometers. 半導体動作層の幅Wが125μmの場合の無磁場におけるRp(磁気抵抗素子としての直列抵抗成分となる短絡電極を含む部分の抵抗)の短絡電極の長さ依存性の計算結果を示す図である。It is a figure which shows the calculation result of the length dependence of Rp (resistance of the part containing the short circuit electrode used as a serial resistance component as a magnetoresistive element) in the non-magnetic field in case the width W of a semiconductor operation layer is 125 micrometers. . (a)は半導体動作層の幅Wが125μmで、短絡電極の長さLeが10μm、5μm、2μmのときの磁気抵抗変化率のL/W依存性を算出した図であり、(b)は半導体動作層の幅Wが60μmで、短絡電極の長さLeが10μm、5μm、2μmのときの磁気抵抗変化率のL/W依存性を算出した図であり、(c)は半導体動作層の幅Wが30μmで、短絡電極の長さLeが10μm、5μm、2μmのときの磁気抵抗変化率のL/W依存性を算出した図である。(A) is the figure which computed the L / W dependence of the magnetoresistive change rate when the width W of a semiconductor operation layer is 125 micrometers and the length Le of a short circuit electrode is 10 micrometers, 5 micrometers, and 2 micrometers, (b) It is the figure which computed the L / W dependence of the magnetoresistive change rate when the width W of a semiconductor operation layer is 60 micrometers and the length Le of a short circuit electrode is 10 micrometers, 5 micrometers, and 2 micrometers, (c) is a figure of (c) It is the figure which computed the L / W dependence of the magnetoresistive change rate when width W is 30 micrometers and length Le of a short circuit electrode is 10 micrometers, 5 micrometers, and 2 micrometers. (a)は図5で使用した同じデータを短絡電極の長さLeが10μmの場合のみとしてまとめ直した図であり、(b)は図5で使用した同じデータを短絡電極の長さLeが5μmの場合のみとしてまとめ直した図であり、(c)は図5で使用した同じデータを短絡電極の長さLeが2μmの場合のみとしてまとめ直した図である。磁気抵抗効果の計算結果(A) is the figure which summarized the same data used in FIG. 5 only when the length Le of the short-circuit electrode is 10 μm, and (b) is the same data used in FIG. FIG. 6C is a diagram in which the same data used in FIG. 5 is rearranged only when the length Le of the short-circuit electrode is 2 μm. Calculation result of magnetoresistance effect (a)は本発明の一実施例の構造の上面図を説明する図であり、(b)は本発明の一実施例の構造の断面図を説明する図である。(A) is a figure explaining the top view of the structure of one Example of this invention, (b) is a figure explaining sectional drawing of the structure of one Example of this invention. 緩衝層を挿入した本発明の一実施例の構造の断面図を説明する図である。It is a figure explaining sectional drawing of the structure of one Example of this invention which inserted the buffer layer. 保護膜の開口部に短絡電極と入出力電極を形成した本発明の一実施例の構造の断面図を説明する図である。It is a figure explaining sectional drawing of the structure of one Example of this invention which formed the short circuit electrode and the input-output electrode in the opening part of the protective film. 本発明を使用して、半導体動作層の幅Wを30μm、短絡電極の長さLeを2μmとした場合の磁気抵抗変化率のL/W依存性を示す図である。It is a figure which shows the L / W dependence of the magnetoresistive change rate when the width W of a semiconductor operation layer is 30 micrometers and the length Le of a short circuit electrode is 2 micrometers using this invention. 図10に、短絡電極の長さLeを10μm、5μmの場合を加えた図である。It is the figure which added the case where length Le of a short circuit electrode is 10 micrometers and 5 micrometers in FIG. 図10に、半導体動作層の幅Wが60μm、125μmの場合を加えた場合の図であるFIG. 10 is a diagram when the case where the width W of the semiconductor operation layer is 60 μm and 125 μm is added to FIG. 10. 従来構造、すなわちLeが10μm、半導体動作層の幅Wが30μm、60μmおよび125μmの場合における磁気抵抗変化率のL/W依存性を示す図である。It is a figure which shows the L / W dependence of the magnetoresistive change rate in the conventional structure, ie, when Le is 10 micrometers and the width W of a semiconductor operation layer is 30 micrometers, 60 micrometers, and 125 micrometers.

符号の説明Explanation of symbols

1 基板
2 半導体動作層
3 入出力電極
4 短絡電極
5 基板
6 半導体動作層
7 入出力電極
8 短絡電極
9 緩衝層
10 保護膜
DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor operation layer 3 Input / output electrode 4 Short-circuit electrode 5 Substrate 6 Semiconductor operation layer 7 Input / output electrode 8 Short-circuit electrode 9 Buffer layer 10 Protective film

Claims (12)

基板上に形成された薄膜状半導体動作層と、
当該半導体動作層上の少なくとも2つの端部に配置された入出力電極と、
当該入出力電極間の前記半導体動作層上で、前記入出力電極間に延在する前記半導体層の延在方向と直角方向に延在する形で、前記半導体層の前記延在方向に一定間隔をおいて、配置された複数の短絡電極と
を有する半導体磁気抵抗素子において、
前記入出力電極間に延在する前記半導体層の延在方向と直角方向の前記半導体動作層の幅が60μm以下であり、
前記短絡電極の、前記半導体層の延在方向の長さが5μm以下であり、
前記半導体動作層の前記幅をW、前記一定間隔の複数の短絡電極間の距離をLとしたとき、LとWの比であるL/Wが0.3以下であることを特徴とする半導体磁気抵抗素子。
A thin film semiconductor operating layer formed on the substrate;
Input / output electrodes disposed at at least two ends on the semiconductor operation layer;
On the semiconductor operation layer between the input / output electrodes, the semiconductor layer extending between the input / output electrodes extends in a direction perpendicular to the extending direction of the semiconductor layer, and is spaced at a constant interval in the extending direction of the semiconductor layer. In a semiconductor magnetoresistive element having a plurality of short-circuit electrodes arranged,
The width of the semiconductor operation layer in the direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes is 60 μm or less;
The length of the short circuit electrode in the extending direction of the semiconductor layer is 5 μm or less,
L / W, which is a ratio of L to W, is 0.3 or less, where W is the width of the semiconductor operation layer, and L is the distance between the plurality of short-circuited electrodes at regular intervals. Magnetoresistive element.
前記L/Wが0.1以上であることを特徴とする請求項1に記載の半導体磁気抵抗素子。   2. The semiconductor magnetoresistive element according to claim 1, wherein the L / W is 0.1 or more. 前記短絡電極の長さが2μm以上であることを特徴とする請求項1または2に記載の半導体磁気抵抗素子。   The length of the said short circuit electrode is 2 micrometers or more, The semiconductor magnetoresistive element of Claim 1 or 2 characterized by the above-mentioned. 前記半導体動作層の組成がInAsySb1-y(0≦y≦1)であることを特徴とする請求項1乃至3のいずれかに記載の半導体磁気抵抗素子。 4. The semiconductor magnetoresistive element according to claim 1, wherein the composition of the semiconductor operation layer is InAs y Sb 1-y (0 ≦ y ≦ 1). 5. 前記半導体動作層にIV族元素、もしくは、VI族元素がドーピングされており、その電子密度が1×1016〜1×1018(cm-3)であることを特徴とする請求項1乃至4のいずれかに記載の半導体磁気抵抗素子。 5. The semiconductor operating layer is doped with a group IV element or a group VI element, and the electron density thereof is 1 × 10 16 to 1 × 10 18 (cm −3 ). The semiconductor magnetoresistive element according to any of the above. 前記半導体動作層が作成される基板は、SiまたはGaAsであることを特徴とする請求項1乃至5のいずれかに記載の半導体磁気抵抗素子。   6. The semiconductor magnetoresistive element according to claim 1, wherein the substrate on which the semiconductor operation layer is formed is Si or GaAs. 基板上に形成された薄膜状半導体動作層と、
当該半導体動作層上の少なくとも2つの端部に配置された入出力電極と、
当該入出力電極間の前記半導体動作層上で、前記入出力電極間に延在する前記半導体層の延在方向と直角方向に延在する形で配置された複数の短絡電極と
を有する半導体磁気抵抗素子の設計方法であって、
前記入出力電極間に延在する前記半導体層の延在方向と直角方向の前記半導体動作層の幅を60μm以下とし、
前記短絡電極の、前記半導体層の延在方向の長さを5μm以下とし、
前記半導体動作層の前記幅をW、前記一定間隔の複数の短絡電極間の距離をLとしたとき、LとWの比であるL/Wが0.3以下とする
ことを特徴とする半導体磁気抵抗素子の設計方法。
A thin film semiconductor operating layer formed on the substrate;
Input / output electrodes disposed at at least two ends on the semiconductor operation layer;
A plurality of short-circuit electrodes arranged on the semiconductor operation layer between the input / output electrodes and extending in a direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes. A resistance element design method comprising:
The width of the semiconductor operation layer in the direction perpendicular to the extending direction of the semiconductor layer extending between the input / output electrodes is 60 μm or less,
The length of the short-circuit electrode in the extending direction of the semiconductor layer is 5 μm or less,
L / W, which is a ratio of L to W, is 0.3 or less, where W is the width of the semiconductor operation layer, and L is the distance between the plurality of short-circuited electrodes at regular intervals. Design method of magnetoresistive element.
前記L/Wが0.1以上であることを特徴とする請求項7に記載の半導体磁気抵抗素子の設計方法。   8. The method of designing a semiconductor magnetoresistive element according to claim 7, wherein the L / W is 0.1 or more. 前記短絡電極の長さが2μm以上であることを特徴とする請求項7または8に記載の半導体磁気抵抗素子の設計方法。   9. The method of designing a semiconductor magnetoresistive element according to claim 7, wherein the length of the short-circuit electrode is 2 [mu] m or more. 前記半導体動作層の組成がInAsySb1-y(0≦y≦1)であることを特徴とする請求項7乃至9のいずれかに記載の半導体磁気抵抗素子の設計方法。 10. The method of designing a semiconductor magnetoresistive element according to claim 7, wherein the composition of the semiconductor operation layer is InAs y Sb 1-y (0 ≦ y ≦ 1). 前記半導体動作層にIV族元素、もしくは、VI族元素がドーピングされており、その電子密度が1×1016〜1×1018(cm-3)であることを特徴とする請求項7乃至10のいずれかに記載の半導体磁気抵抗素子の設計方法。 11. The semiconductor operating layer is doped with a group IV element or a group VI element, and an electron density thereof is 1 × 10 16 to 1 × 10 18 (cm −3 ). A method for designing a semiconductor magnetoresistive element according to any one of the above. 前記半導体動作層が作成される基板は、SiまたはGaAsであることを特徴とする請求項7乃至11のいずれかに記載の半導体磁気抵抗素子の設計方法。   12. The method of designing a semiconductor magnetoresistive element according to claim 7, wherein the substrate on which the semiconductor operation layer is formed is Si or GaAs.
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JP2000269567A (en) * 1999-03-18 2000-09-29 Tdk Corp Semiconductor magnetoresistive element
JP2004022678A (en) * 2002-06-13 2004-01-22 Asahi Kasei Corp Magnetoresistive semiconductor element and its manufacturing method

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JP2000269567A (en) * 1999-03-18 2000-09-29 Tdk Corp Semiconductor magnetoresistive element
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Publication number Priority date Publication date Assignee Title
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