JP2009054246A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device for increasing speed in a verify operation. <P>SOLUTION: The semiconductor storage device comprises a memory cell transistor for retaining n bits (n>2) according to a threshold voltage, a sense amplifier for amplifying readout data, first to n-th latch circuits for retaining a value of a first to n-th bit of program data, and a computing unit for performing logical operations of the value transferred from the first to n-th latch circuits and the readout data. When "i" data is verified, the value is transferred from the latch circuit among the first to n-th latch circuits, in which the value retained when the "i" data is programmed is effective data. Among the first to n-th latch circuits, the combination that retains the effective data when "j" data (j is one of "0" to "2<SP>n</SP>-2") is programmed is different from the combination when data of which threshold voltage is higher than that of the "j" data is programmed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device. For example, it relates to a verify operation of a multi-level NAND flash memory.

  Conventionally, a NAND flash memory is known as a nonvolatile semiconductor memory. In the NAND flash memory, a verify operation for confirming whether the threshold voltage of the memory cell has reached a predetermined level is performed in the data write operation. At this time, a method has been proposed in which each bit of data to be verified is held in a latch circuit, and the verify operation is performed by comparing the data read from the latch circuit with the data read from the memory cell ( For example, see Patent Document 1).

  In this method, data to be verified is described in a Gray code. This is because the data exchange between the NAND flash memory and the outside is performed using the Gray code.

However, with the above method, it is necessary to read all bits of data to be verified from the latch circuit. Therefore, it takes a long time for the verify operation, and there is a problem that the time required for the verify differs for each data to be verified.
US Patent Application Publication No. 2005/0195653

  The present invention provides a semiconductor memory device capable of speeding up a verify operation.

A semiconductor memory device according to one embodiment of the present invention includes a stacked gate including a charge storage layer and a control gate, and n bits of “0” data to “2 ⁿ −1” data (n is 2) depending on a threshold voltage. The above natural number) memory cell transistor capable of holding data, a sense amplifier that amplifies the data read from the memory cell transistor during a verify operation, and the memory cell during a program operation and the verify operation Transfer from at least one of the first to nth latch circuits that respectively hold the values of the 1st to nth bits in the program data to be programmed in the transistors, and the first to nth latch circuits during the verify operation. A logical operation of the obtained value and the data amplified by the memory cell transistor ; And a Cormorant calculator, "i" data when verifying the (i is "1" ~ either "2 n ^-1") are among the first to n latch circuits, said " Since the value held when i ”data is programmed becomes effective data, the value is transferred to the arithmetic unit, and among the first to nth latch circuits,“ j ”data (j is “0” to “2 ⁿ −2”) are all programmed when data having a threshold voltage higher than that of “j” data is programmed. Different from the above combination.

  According to the present invention, it is possible to provide a semiconductor memory device capable of speeding up a verify operation.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an 8-level NAND flash memory according to this embodiment. As shown in the figure, the NAND flash memory 1 includes a memory cell array 2, a row decoder 3, a source line driver 4, a page buffer 5, a verify circuit 6, a control circuit 7, a voltage generation circuit 8, and an input / output buffer 9. .

  The memory cell array 2 includes a plurality of memory cell transistors. Each memory cell transistor has a gate connected to the word line, a drain electrically connected to the bit line, and a source electrically connected to the source line. The row decoder 3 selects the row direction of the memory cell array 2. That is, the word line is selected. The source line driver 4 applies a voltage to the source line. The page buffer 5 senses and amplifies data read from the memory cell transistor when reading data, and holds write data when writing. The verify circuit 6 performs verification at the time of data writing. Details of the memory cell array 2, row decoder 3, page buffer 5, and verify circuit 6 will be described later.

  The input / output buffer 9 receives commands, addresses, and write data from the outside, and outputs read data read from the memory cell array to the outside.

  The control circuit 7 controls the operations of the verify circuit 6 and the voltage generation circuit 8. The control circuit 7 executes a write sequence at the time of writing, instructs the voltage generation circuit 8 to generate a voltage, and controls the operation of the verify circuit 6. The write data received by the input / output buffer 9 is transferred to the verify circuit 6.

  The voltage generation circuit 8 generates a voltage in accordance with an instruction from the control circuit 7. The voltage generated by the voltage generation circuit 8 is supplied to the row decoder 3, the source line driver 4, the page buffer 5, and the like.

  Next, details of the memory cell array 2, the row decoder 3, the page buffer 5, and the verify circuit 6 will be described with reference to FIG. FIG. 2 is a block diagram showing details of the memory cell array 2, row decoder 3, page buffer 5, and verify circuit 6.

  First, the memory cell array 2 will be described. As shown, the memory cell array 2 has a plurality of NAND cells. FIG. 2 shows only one row of NAND cells. Hereinafter, for the sake of simplification of description, a case where the NAND cell is one row will be described as an example. Each of the NAND cells includes 32 memory cell transistors MT0 to MT31 and select transistors ST1 and ST2. Hereinafter, for simplification of description, when the memory cell transistors MT0 to MT31 are not distinguished, they may be simply referred to as memory cell transistors MT. The memory cell transistor MT includes a charge storage layer (for example, a floating gate) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween. A stacked gate structure is provided. The number of memory cell transistors MT is not limited to 32, but may be 8 or 16, and the number is not limited. Adjacent ones of the memory cell transistors MT share a source and a drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain on one end side of the memory cell transistors MT connected in series is connected to the source of the select transistor ST1, and the source on the other end side is connected to the drain of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to one of the word lines WL0 to WL31, and the gates of the selection transistors ST1 and ST2 of the memory cells in the same row are common to the select gate lines SGD and SGS, respectively. It is connected. Further, the drains of the select transistors ST1 in the same column in the memory cell array are commonly connected to any one of bit lines BL0 to BLm (m is a natural number). The sources of the selection transistors ST2 are commonly connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as a NAND cell can be selected.

  In the memory cell array 2 configured as described above, data is collectively written into the plurality of memory cell transistors MT connected to the same word line WL. A unit in which this data is written is called a “page”. In the present embodiment, it is assumed that data is collectively written to (m + 1) memory cell transistors MT connected to the same word line. Also, data reading is performed in the same unit as writing.

  The threshold distribution of the memory cell transistors MT in the memory cell array 2 will be described with reference to FIG. FIG. 3 is a graph in which the horizontal axis represents the threshold voltage Vth and the vertical axis represents the existence probability of the memory cell transistor MT.

  As shown in the figure, each memory cell transistor MT can hold 8 types of data (3-bit data). That is, the memory cell transistor MT can hold eight types of data of “0”, “1”, “2”, “3”,... “7” in order from the lowest threshold voltage Vth.

  The threshold voltage Vth0 of “0” data in the memory cell transistor MT is Vth0 <V01. The threshold voltage Vth1 of “1” data is V01 <Vth1 <V12. The threshold voltage Vth2 of “2” data is V12 <Vth2 <V23. The threshold voltage Vth3 of “3” data is V23 <Vth3 <V34. The threshold voltage Vth4 of the “4” data is V34 <Vth4 <V45. The threshold voltage Vth5 of “5” data is V45 <Vth5 <V56. The threshold voltage Vth6 of “6” data is V56 <Vth6 <V67. The threshold voltage Vth7 of the “7” data is V67 <Vth7. As described above, the memory cell transistor MT can hold 3-bit data of “0” data to “7” data according to the threshold voltage.

  Returning to FIG. 2, the description will be continued. The row decoder 3 selects one of the word lines WL0 to WL31 and the select gate lines SGD and SGS based on the row address signal RA supplied from the input / output buffer 9. Then, a voltage is supplied to the selected word line WL and select gate lines SGD and SGS. Further, the row decoder 3 applies a voltage to the semiconductor substrate on which the memory cells are formed. These voltages are given by the voltage generation circuit 8.

  Next, the page buffer 5 will be described. The page buffer 5 includes sense amplifiers 10-0 to 10-m provided for the bit lines BL0 to BLm. When reading data from the memory cell array 2, the sense amplifiers 10-0 to 10-m sense and amplify the data read to the bit lines BL0 to BL-m, respectively. When data is written, the sense amplifiers 10-0 to 10-m hold write data to the memory cell transistors MT connected to the bit lines BL0 to BLm, respectively. Hereinafter, when the sense amplifiers 10-0 to 10-m are not distinguished, they are simply referred to as the sense amplifiers 10.

  The verify circuit 6 includes arithmetic circuits 20-0 to 20-m provided for the bit lines BL0 to BLm, that is, for the sense amplifiers 10-0 to 10-m. Each of the arithmetic circuits 20-0 to 20-m includes arithmetic units 21-0 to 21-m, first latch circuits 22-0 to 22-m, second latch circuits 23-0 to 23-m, and third latches. Circuits 24-0 to 24-m and MOS transistors 25-0 to 25-m are provided. Hereinafter, the arithmetic circuits 20-0 to 20-m are simply the arithmetic circuit 20, the arithmetic units 21-0 to 21-m are simply the arithmetic unit 21, and the first latch circuits 22-0 to 22-m are simply the first latch circuit 22. The second latch circuits 23-0 to 23-m are simply the second latch circuit 23, the third latch circuits 24-0 to 24-m are simply the third latch circuit 24, and the MOS transistors 25-0 to 25-m are Sometimes simply referred to as MOS transistor 25.

  Each of the first to third latch circuits 22 to 24 holds each bit of 3-bit data to be written to the memory cell transistor MT connected to the corresponding bit line BL when data is written. That is, each bit of 3-bit data to be written to the memory cell transistor MT connected to the bit line BL0 is held in the first to third latch circuits 22-0, 23-0, and 24-0. The first to third latch circuits 22-m, 23-m, and 24-m hold each bit of 3-bit data to be written to the memory cell transistor MT connected to the bit line BLm.

  The arithmetic unit 20 holds “1” data as an initial value, and performs an AND operation on the initial value, the data in the corresponding sense amplifier 10, and the data in the corresponding first to third latch circuits 22 to 24. I do. That is, the arithmetic unit 20-0 performs an AND operation on the initial value, the data in the sense amplifier 10-0, and the data in the first to third latch circuits 22-0, 23-0, and 24-0. . The computing unit 20-m performs an AND operation on the initial value, the data in the sense amplifier 10-m, and the data in the first to third latch circuits 22-m, 23-m, and 24-m.

  In the MOS transistor 25, the signal TD is input to the gate, and the data supplied to the second latch circuit 23 is transferred to the first latch circuit 22 and the third latch circuit 24. Details of the operation of the verify circuit 6 will be described later.

Next, the operation of the NAND flash memory having the above configuration will be described.
[Data write operation]
A data write operation in the NAND flash memory according to the present embodiment will be described with reference to FIG. The data write operation is roughly a repetition of a program operation and a verify operation. The program operation is an operation of setting the threshold voltage of the memory cell transistor MT to a desired value by injecting / non-injecting charge into the memory cell transistor MT according to the write data. The verify operation is performed after the program operation, and is an operation for reading data from the memory cell transistor MT and confirming whether or not the threshold voltage of the memory cell transistor MT is within a desired range. FIG. 4 is a flowchart of the write operation in the NAND flash memory according to the present embodiment.

  As shown in the figure, first, a write command, an address, and write data (3-bit data) are input to the NAND flash memory 1 (step S10). In the NAND flash memory 1, these signals are received by the input / output buffer 9. The input / output buffer 9 transfers the row address RA to the row decoder 3 and transfers a write command and write data to the control circuit 7. Note that write data given from the outside is given as a Gray code.

  Next, the control circuit 7 transfers the write data to the verify circuit 6, and sets each bit of the 3-bit data (gray code) in the first to third latch circuits 22-0 to 24-0 (step S11). The write data may be directly transferred from the input / output buffer 9 to the verify circuit 6. A method for transferring write data will be described below. The lower bits of the write data (gray code) to the memory cell transistors MT connected to the bit lines BL0 to BLm are Blow-0 to Blow-m, respectively, and the middle bits are Bmid-0 to Bmid-m, respectively. The upper bits are Bup-0 to Bup-m, respectively.

  First, the control circuit 7 transfers (m + 1) -bit data composed of, for example, the lower bits Blow-0 to Blow-m to the verify circuit 6, and stores these data in the second latch circuits 23-0 to 23-m, respectively. . At this time, the control circuit 7 sets the signal TD = “H” level to turn on the MOS transistors 25-0 to 25-m. Thereby, Blow-0 to Blow-m in the second latch circuits 23-0 to 23-m are transferred to the first latch circuits 22-0 to 22-m, respectively.

  Next, the control circuit 7 stores the middle bits Bmid-0 to Bmid-m in the second latch circuits 23-0 to 23-m, respectively. Then, Bmid-0 to Bmid-m in the second latch circuits 23-0 to 23-m are transferred to the third latch circuits 24-0 to 24-m, respectively. Finally, the control circuit 7 transfers the upper bits Bup-0 to Bup-m to the second latch circuits 23-0 to 23-m, respectively. Thus, the write data that is a Gray code is set in the verify circuit 6.

  After step S11, the control circuit 7 converts the write data held in each of the arithmetic circuits 20-1 to 20-m of the verify circuit 6 from gray code to binary code (step S12). That is, the 3-bit code obtained by combining the data held in each of the first to third latch circuits is converted so as to be in the ascending or descending order of the write data “0” to “7”. In the present embodiment, the bit held in the first latch circuit 22 is the lower bit, the bit held in the second latch circuit 23 is the middle bit, and the bit held in the third latch circuit is the upper bit. The 3-bit code obtained by these is converted so as to be in descending order of the write data “0” to “7”.

  A binary code obtained by the control circuit 7 is shown in FIG. FIG. 5 is a table showing a relationship between write data and data held in the first to third latch circuits 22 to 24. If the bit held in the first latch circuit 22 is “b1”, the bit held in the second latch circuit 23 is “b2”, and the bit held in the third latch circuit 24 is “b3”, the obtained code Is (b3, b2, b1). When the write data is “0”, b1 = “1”, b2 = “1”, b3 = “1”, and the obtained code is (111). When the write data is “1”, the obtained code is (110). Hereinafter, when the write data is “2” to “7”, the obtained codes are (101) to (000). In this way, the control circuit 7 converts the combination of data held by the latch circuits 22 to 24 from a gray code to a binary code as shown in FIG.

  In addition, the control circuit 7 counts the program count i. Initially, i = 1 is set (step S13). In response to the command from the control circuit 7, the voltage generation circuit 8 generates the program voltage Vpgm-i and supplies it to the row decoder 3 (step S14).

  Then, a program operation is performed (step S15). That is, the row decoder 3 selects the word line WL corresponding to the row address RA, and applies the program voltage Vpgm-i to the selected word line WL. The arithmetic circuits 20-0 to 20-m store program data in the page buffer 5 (sense amplifiers 10-0 to 10-) according to the values set in the first to third latch circuits 22 to 24, respectively. Set to m). The program data is an AND calculation result in the calculator 21. That is, if the data held by at least one of the first to third latch circuits 22 to 23 is “0”, the AND operation result in the calculator 21 is “0”. On the other hand, if all the data held by the first to third latch circuits 22 to 23 is “1”, the AND operation result is “1”. The calculation result is transferred as program data to the sense amplifier 10 of the page buffer 5.

  When the program data is “0”, the sense amplifier 10 applies 0V to the corresponding bit line BL. Then, charges are injected into the charge storage layer of the memory cell transistor MT, and the threshold voltage of the memory cell transistor MT increases. On the other hand, when the program data is “1”, the sense amplifier 10 applies a positive voltage (for example, 3 V) to the corresponding bit line BL. Then, no charge is injected into the charge storage layer of the memory cell transistor MT, and the threshold voltage of the memory cell transistor MT does not change.

  When the program operation is completed, the control circuit 7 instructs the verify circuit 6 to perform the verify operation. In response to this command, the verify circuit 6 performs verify for each of the “1” to “7” data (step S16). Details of the verify operation will be described later.

  When the verify operation is completed, the control circuit 7 confirms whether or not the program operation has been performed a predetermined number of times (or whether or not all data has been verified), and has reached the predetermined number of times (or If (passed) (step S17, YES), the writing operation is terminated. If not reached (or not passed) (step S17, NO), the program count i is set to (i + 1). Then, the program data is set again in the page buffer 5 (step S19), and the process returns to step S14.

  The flow of the above write operation will be described with reference to the timing chart of FIG. FIG. 6 is a timing chart showing the state of the NAND flash memory, the ready / busy signal (R / B signal), and the voltage of the word line selected by the row decoder 3 in the write operation shown in FIG. is there. The R / B signal is a signal output to the outside by the NAND flash memory. The ready state in which the signal from the outside can be received is set to “H” level, and the busy state in which the signal cannot be received. Is set to the “L” level.

  First, by receiving a write command, an address, and write data from the outside (step S10), the NAND flash memory is in a busy state (time t1). In the period from time t1 to time t2, the control circuit 7 converts the write data from gray code to binary code (step S12). When this conversion is completed (time t2), a program voltage (Program pulse) Vpgm1 is applied to the selected word line WL, and programming is performed during the period of time t2 to t3 (steps S14 and S15).

  Next, a verify operation is performed during a period from time t3 to time t4 (step S16). The verify is performed for each of “1” to “7” data. The verify is an operation for confirming whether the threshold voltage of the memory cell transistor MT is a desired value as described above. Therefore, for example, when verifying the memory cell transistor MT in which “1” data is to be written, the voltage V01 (see FIG. 3) is applied as the verify voltage to the word line WL. If the memory cell transistor MT is not turned on, the threshold voltage Vth1 is higher than V01, and therefore verification is passed. On the other hand, when the transistor is turned on, the threshold voltage Vth1 is smaller than V01, so that the verification misses. If a mistake is made, it is necessary to perform programming again to make the threshold voltage Vth1 higher than V01. The same applies to the memory cell transistors MT to which the “2” to “7” data is to be written. When verifying each, the voltages V12 to V67 are applied to the word lines. Hereinafter, verification of the memory cell transistor MT in which “1” to “7” data is to be written may be simply referred to as “1” to “7” verification. Also, write data to be verified may be referred to as verify data.

  When the first verify is completed at time t4, the second program is performed next. The program voltage used in the second and subsequent programs is set higher by ΔVpgm than the previous program voltage. That is, the program voltage Vpgm2 used in the second program is (Vpgm1 + ΔVpgm). The second and subsequent programming is performed only for the memory cell transistor MT that has been missed by the verification performed before that time. When the second program ends (time t5), verification is performed again in the same manner as at times t3 to t4.

  When the predetermined number of times of programming is completed (or when all the memory cell transistors MT reach a desired threshold voltage), the write operation is completed (time t8). Therefore, the NAND flash memory returns to the ready state, and the R / B signal becomes “H” level.

[Verify operation]
Next, details of the verify operation in FIG. 4 will be described with reference to FIG. 7, focusing on the operation of the verify circuit 6 in particular. FIG. 7 is a flowchart of the verify operation according to the present embodiment.

  First, the verify circuit 6 sets the verify data j = “1” (step S20) and starts the verify (step S21). First, data is read from the memory cell transistor MT to be verified to the bit line BL. Data is read in page units. Then, the sense amplifiers 10-0 to 10-m sense and amplify the data read to the bit lines BL0 to BLm, respectively (step S22).

  A state of sensing in the sense amplifier 10 will be described with reference to FIG. FIG. 8 shows a case where the verify data is “4” (j = “4”) as an example. In this case, the voltage V34 (verify voltage) is applied to the word line WL. If the threshold voltage of the memory cell transistor MT is higher than V34, that is, if the programming of “4” data is completed, the memory cell transistor MT is turned off. Accordingly, the potential of the bit line BL remains the precharge potential, and the sense amplifier 10 holds “1” as read data. On the other hand, when V34 or less, the memory cell transistor MT is turned on. Therefore, the potential of the bit line BL falls from the precharge potential, and the sense amplifier 10 holds “0” as read data.

  Next, the sense amplifier 10 transfers the read data held by itself to the arithmetic unit 21 of the corresponding arithmetic circuit 20 (step S23). That is, the read data held by the sense amplifiers 10-0 to 10-m are transferred to the computing units 20-0 to 20-m, respectively.

  In the arithmetic circuit 20, the data in the latch circuit whose value becomes “1” when the verification data is held is transferred to the arithmetic unit 21 (step S 24). That is, for example, when the verify data j = “1”, as described with reference to FIG. 5, b2 = “1” and b3 = “1”. That is, the second latch circuit 23 and the third latch circuit 24 hold “1”. Accordingly, in all the arithmetic circuits 20, the data in the second latch circuits 23-0 to 23-m and the data in the third latch circuits 24-0 to 24-m are converted into arithmetic units 21-0 to 21-. forwarded to m respectively.

  Then, the arithmetic unit 21 performs an AND operation on the initial value and the transferred data. If all of the data transferred in step S25 and the read data transferred in step S23 are “1”, the calculation result is “1” (YES in step S26). In this case, the computing unit 21 transfers the computation result “1” to the one holding the “0” data among the first to third latch circuits 22 to 24 corresponding to the computing unit 21, and the data is transferred. Rewriting is performed (step S27). That is, as a result, the data held by the corresponding first to third latch circuits 22 to 24 are all “1”. If the calculation result is “0” (step S26, NO), the calculation result is not transferred.

  If the verify data j is “7” (YES in step S28), the control circuit 7 ends the verify operation. If not "7", the control circuit 7 sets j = j + 1 and returns to step S21 (step S29).

  The above verify operation is executed by, for example, a sequencer in the control circuit 7. Then, the data transfer process in the computing unit 21 is configured by sequence steps as shown in FIG. FIG. 9 is a table showing sequence processing by the sequencer.

  As shown in the figure, the sequence step has seven steps ST1 to ST7. Step ST1 is data (read data) transfer from the sense amplifier 10 to the computing unit 21. Step ST2 is data transfer from the second latch circuit 23 to the computing unit. Step ST3 is data transfer from the first latch circuit 22 to the computing unit. Step ST4 is data transfer from the third latch circuit 24 to the arithmetic unit. Step ST <b> 5 is data transfer from the arithmetic unit 21 to the first latch circuit 22. Step ST 6 is data transfer from the computing unit 21 to the second latch circuit 23. Step ST 7 is data transfer from the computing unit 21 to the third latch circuit 24.

  Then, the sequence at the time of “1” to “7” verification when verification is passed is as shown in FIG. FIG. 10 is a table showing a sequence executed at the time of “1” to “7” verification.

  First, “1” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “1” verification, in order to transfer data from the second latch circuit 23 and the third latch circuit 24 to the arithmetic unit 21 (because b2 = “1” and b3 = “1”), steps ST2 and ST4 are performed. Executed. Finally, step ST5 is executed to transfer the calculation result of the calculator 21 to the first latch circuit 22.

  Next, “2” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “2” verification, in order to transfer data from the first latch circuit 22 and the third latch circuit 24 to the computing unit 21 (because b1 = “1” and b3 = “1”), steps ST3 and ST4 are performed. Executed. Finally, step ST6 is executed to transfer the calculation result of the calculator 21 to the second latch circuit 23.

  Next, “3” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “3” verification, step ST4 is executed in order to transfer data from the third latch circuit 24 to the computing unit 21 (because b3 = “1”). Finally, steps ST5 and ST6 are executed in order to transfer the calculation result of the calculator 21 to the first latch circuit 22 and the second latch circuit 23.

  Next, “4” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “4” verify, in order to transfer data from the first latch circuit 22 and the second latch circuit 23 to the computing unit 21 (because b1 = “1” and b2 = “1”), steps ST2 and ST3 are performed. Executed. Finally, step ST7 is executed to transfer the calculation result of the calculator 21 to the third latch circuit 24.

  Next, “5” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “5” verification, step ST2 is executed in order to transfer data from the second latch circuit 23 to the computing unit 21 (because b2 = “1”). Finally, steps ST5 and ST7 are executed to transfer the calculation result of the calculator 21 to the first latch circuit 22 and the third latch circuit 24.

  Next, “6” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “6” verification, step ST3 is executed in order to transfer data from the first latch circuit 22 to the computing unit 21 (because b1 = “1”). Finally, steps ST6 and ST7 are executed to transfer the calculation result of the calculator 21 to the second latch circuit 23 and the third latch circuit 24.

  Next, “7” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “7” verification, since b1 = b2 = b3 = “0”, data transfer from the first to third latch circuits 22 to 24 to the calculator 21 is not performed. Then, steps ST5, ST6, and ST7 are executed in order to transfer the calculation result of the calculator 21 to the first to third latch circuits 22 to 24.

  As described above, in any case of “1” to “7” verification, the data transfer process via the arithmetic unit 21 is four steps.

[Specific example of verify operation]
Next, a specific example of the verify operation will be described with reference to FIGS. 11 to 15 are circuit diagrams of the arithmetic circuit 20, the sense amplifier 10, and the memory cell transistor MT. In the following, a case where there are three bit lines BL1 to BL3 will be described as an example for simplification of description. A case will be described in which “1”, “3”, and “7” data are written to the memory cell transistors MT connected to the word line WL1 and the bit lines BL1 to BL3, respectively. For the sake of convenience of description, the memory cell transistors MT connected to the word line WL1 and the bit lines BL1 to BL3 will be referred to as memory cell transistors MT11, MT12, and MT13, respectively, only in the following description of the specific example of the verify operation. To do.

  FIG. 11 shows a state in which “1” verification is performed after “1”, “3”, and “7” programs are performed.

  As shown in the figure, when performing “1” verification, the voltage V01 is applied to the word line WL0. At this time, it is assumed that the threshold voltages of all the memory cell transistors MT11, MT12, and MT13 are higher than V01. Then, the data held by the sense amplifiers 10-1 to 10-3 is “1”.

  At the time of “1” verification, that is, at the time of “1” programming, the data to be held by the first latch circuit 22 is “0”, and the data to be held by the second and third latch circuits 23 and 24 is “1”. ". Therefore, the data in the second latch circuits 23-1 to 23-3 and the data in the third latch circuits 24-1 to 24-4 are transferred to the computing units 21-1 to 21-3 ( Steps ST2 and ST4).

  Then, the AND operation result of the calculator 21-1 is “1”. However, the AND operation result of the arithmetic unit 21-2 becomes “0” because the second latch circuit 23-2 holds “0”. Similarly, the AND operation result of the calculator 21-3 is also “0”.

  Accordingly, the arithmetic unit 21-1 transfers the operation result “1” to the first latch circuit 22-1 (step ST5), and the data held by the first latch circuit 22-1 changes from “0” to “1”. Rewritten. On the other hand, the computing units 21-2 and 21-3 do not transfer the computation results. Therefore, the data held by the first latch circuits 22-2 and 22-3 remains “0”.

  Next, “3” verification is performed. “3” verification will be described with reference to FIG. FIG. 12 shows a state at the time of “3” verification.

  As shown in the figure, when performing “3” verification, the voltage V23 is applied to the word line WL0. At this time, it is assumed that the threshold voltages of the memory cell transistors MT12 and MT13 are higher than V23. On the other hand, since “1” data is programmed in the memory cell transistor MT11, the threshold voltage is lower than V23. Then, only the memory cell transistor MT11 is turned on, and the data held by the sense amplifiers 10-1 to 10-3 are “0”, “1”, and “1”, respectively.

  At the time of “3” verification, that is, at the time of “3” programming, the data to be held by the first and second latch circuits 22 and 23 is “0”, and the data to be held by the third latch circuit 24 is “1”. ". Accordingly, the data in the third latch circuits 24-1 to 24-3 is transferred to the computing units 21-1 to 21-3 (step ST4).

  Then, the AND operation result of the arithmetic unit 21-1 becomes “0” because the data in the sense amplifier 10-1 is “0”. The AND operation result of the arithmetic unit 21-3 is “0” because the data in the third latch circuit 24-3 is “0”. On the other hand, the AND operation result of the arithmetic unit 21-2 is “1” because the data in the sense amplifier 10-2 and the data in the third latch circuit 24-2 are “1”.

  Accordingly, the arithmetic unit 21-2 transfers the operation result “1” to the first and second latch circuits 22-2 and 23-2 (steps ST5 and ST6), and the first and second latch circuits 22-2 and 23 are transferred. The data held in -2 is rewritten from “0” to “1”. On the other hand, the computing units 21-1 and 21-3 do not transfer the computation results.

  Next, “7” verification is performed. The “7” verify will be described with reference to FIG. FIG. 13 shows a state during “7” verification.

  As shown in the figure, first, when performing “7” verification, the voltage V67 is applied to the word line WL0. At this time, it is assumed that the memory cell transistor MT13 is not sufficiently programmed and its threshold voltage is lower than V67. The threshold voltage of the memory cell transistors MT11 and MT12 is naturally lower than V67. Then, all the memory cell transistors MT11 to MT13 are turned on, and the data held by the sense amplifiers 10-1 to 10-3 are all “0”. That is, the verify is a mistake.

  At the time of “7” verification, that is, at the time of “7” programming, all the data to be held by the first to third latch circuits 22 to 24 is “0”. Therefore, data transfer from the first to third latch circuits 22 to 24 to the computing unit 21 is not performed.

  Then, the AND operation results of the computing units 21-1 to 21-3 are all “0”. Accordingly, data transfer from the arithmetic unit 21 to the first to third latch circuits 22 to 24 is not performed.

  Thus, the first verify operation is completed. The above operation corresponds to, for example, the period from time t3 to t4 in FIG. At this point, since the “7” program has not been completed, the program is executed again. This second program corresponds to the period from time t4 to time t5 in FIG.

  FIG. 14 shows a state during the second programming. In this program, the program is performed only for “7” data that has not been completed. Program data is given by an AND operation result of data held by the first to third latch circuits 22 to 24, and the AND operation is performed by the arithmetic unit 21. Then, the calculation result in the calculator 21 is given to the sense amplifier 10. If the program data is “1”, the sense amplifier 10 determines that the program is unnecessary, and applies the write inhibit voltage VDD to the corresponding bit line BL. On the other hand, if the program data is “0”, it is determined that the program is necessary and, for example, 0 V is applied to the corresponding bit line BL.

  In the case of FIG. 14, the AND operation result of the calculators 21-1 and 21-2 is “1”. This is because all the data in the corresponding first to third latch circuits 22 to 24 are “1”. Accordingly, the sense amplifiers 10-1 and 10-2 apply the write inhibit voltage VDD to the corresponding bit lines BL1 and BL2, respectively. On the other hand, the AND operation result of the calculator 21-3 is “0”. Accordingly, the sense amplifier 10-3 applies 0 V to the corresponding bit line BL3. The row decoder 3 applies a program voltage Vpgm2 to the word line WL1. As a result, the memory cell transistors MT11 and MT12 are not programmed, and only the memory cell transistor MT13 is programmed. That is, “7” data is programmed.

  Next, verification for the program performed in FIG. 14 is performed. This verification corresponds to times t5 to t6 in FIG. Regarding “1” verification and “3” verification, the calculation results of the calculators 21-1 to 21-3 are all “0”, and thus description thereof is omitted. Therefore, only “7” verify will be described with reference to FIG. Further, it is assumed that the threshold voltage of the memory cell transistor MT13 is higher than V67 by the program shown in FIG.

  As shown in the figure, when performing “7” verification, the voltage V01 is applied to the word line WL0. Then, the memory cell transistor MT13 is turned off. Therefore, the data held by the sense amplifiers 10-1 to 10-3 are “0”, “0”, and “1”, respectively.

  Then, the AND operation result of the calculator 21-3 is “1”. Therefore, the computing unit 21-3 transfers the computation result “1” to the first to third latch circuits 22-3 to 24-3 (steps ST5 to ST7), and the first to third latch circuits 22-3 to 24-24. The data held in -3 is rewritten from “0” to “1”.

  As a result, the data in the first latch circuits 22-1 to 22-3, the second latch circuits 23-1 to 23-3, and the third latch circuits 24-1 to 24-3 are all “1”. . That is, all of the memory cell transistors MT11 to MT13 have reached a desired threshold voltage, and subsequent programming is unnecessary. Thus, the write operation is completed.

As described above, the semiconductor memory device according to the first embodiment of the present invention has the following effect (1).
(1) The verify operation can be speeded up.
As described above, the write data input from the outside to the NAND flash memory is described in the Gray code. An example of a gray code is shown in FIG. FIG. 16 is a table showing gray codes corresponding to write data “0” to “7”, and shows data held in the first to third latch circuits 22 to 24 for each of the write data.

  As shown in the figure, the gray code differs only by 1 bit at maximum in relation to adjacent data. When verifying using such a gray code, it is necessary to transfer all the data of the first to third latch circuits 22 to 24 to the arithmetic unit 21. This is because it cannot be distinguished from other write data unless all three bits of the Gray code are transferred. For example, assuming that only “1” data in the first latch circuit 22 is read at the time of “4” verification, it can be distinguished from “0” to “3” data, “5” data, and “6” data. This is because at the time of “4” verification, the memory cell transistor MT holding “0” to “3” data should be turned on, and the “5” data and “6” data are supplied to the first latch circuit 22. This is because the retained data is “0”. However, the data held in the first latch circuit 22 in the “7” data is “1”. Therefore, it cannot be distinguished from “7” data.

  Therefore, when using the Gray code, it is necessary to use all three bits of data. In this case, however, there is a problem that it takes a very long time for the verify operation. That is, even if any of the data “0” to “7” is verified, the processing of steps ST2 to ST4 shown in FIG. 9 is necessarily required. For example, when the “5” data is to be verified when the gray code shown in FIG. 16 is used, all the steps ST1 to ST7 are required, which takes a very long time.

  Further, at the time of “1” verification, data transfer from the arithmetic unit 21 need only be performed with respect to the first latch circuit 22, and therefore, the necessary steps are five steps ST1 to ST5. That is, the number of times of data transfer via the arithmetic unit differs for each verify data. As described above, the dependency on the data causes inconvenience in shortening the operation time in the sequence design of the verify operation. In addition, the sequence becomes complicated, which causes difficulties in circuit design and circuit verification.

  However, in the configuration according to the present embodiment, the control circuit 7 converts the gray code into a binary code. Therefore, the data transfer from the first to third latch circuits 22 to 24 to the computing unit 21 may be data “1”, and thus the write data can be discriminated. This point will be described with reference to FIG. FIG. 17 is a table showing data held in the first to third latch circuits 22 to 24 when the write data is “0” to “7”, and also shows the threshold distribution of each write data. ing.

  As shown in the figure, for example, when “5” verification is performed, the memory cell transistor MT holding “0” to “4” data is turned on, so that it can be distinguished from these write data. This is the same as when the Gray code is used. On the other hand, “6” and “7” data can be distinguished by the bit b2 in which the binary code of “5” data is “1”. This is because the latch circuit that holds “1” at the time of “5” verification is the second latch circuit 23, but the data in the second latch circuit 23 that holds “6” and “7” data is “0”. is there. That is, in the “j” data verification (j is “1” to “6”), the “j” data and the data below “j−1” can be distinguished by the data in the sense amplifier 10. Further, “j” data and data of “j + 1” or more can be distinguished by data transferred from any of the first to third latch circuits 22 to 24 holding “1” at the time of “j” data programming. is there.

  Therefore, in the case of an 8-level NAND flash memory, as described with reference to FIG. 10, the data transfer through the arithmetic unit 21 is performed four times for all the verify data, and not only the number of data transfers can be shortened. The number of data transfers can be made uniform between data. In particular, in a multi-level NAND flash memory, the larger the number of bits stored in the memory cell transistor MT, the more the number of data transfers through the arithmetic unit 21 increases.

[Second Embodiment]
Next explained is a semiconductor memory device according to the second embodiment of the invention. In this embodiment, the first embodiment is applied to a 16-level NAND flash memory. Since the basic configuration and operation of the NAND flash memory according to this embodiment are the same as those of the first embodiment, only differences from the first embodiment will be described below.

  The block configuration of the NAND flash memory 1 according to this embodiment is the same as that shown in FIG. FIG. 18 is a graph showing the threshold distribution of the memory cell transistor MT. The horizontal axis indicates the threshold voltage Vth, and the vertical axis indicates the existence probability of the memory cell transistor MT.

  As shown in the figure, each memory cell transistor MT can hold 16 types of data (4-bit data). That is, the memory cell transistor MT has 16 types of “0”, “1”, “2”, “3”,... “9”, “A”, “B”,. Data can be retained. That is, the threshold voltage Vth0 of “0” data in the memory cell transistor MT is Vth0 <V01. The threshold voltage Vth1 of “1” data is V01 <Vth1 <V12. The threshold voltage Vth2 of “2” data is V12 <Vth2 <V23. The threshold voltage Vth3 of “3” data is V23 <Vth3 <V34. The threshold voltage Vth4 of the “4” data is V34 <Vth4 <V45. The threshold voltage Vth5 of “5” data is V45 <Vth5 <V56. The threshold voltage Vth6 of “6” data is V56 <Vth6 <V67. The threshold voltage Vth7 of the “7” data is V67 <Vth7 <V78. The threshold voltage Vth8 of the “8” data is V78 <Vth8 <V89. The threshold voltage Vth9 of the “9” data is V89 <Vth9 <V9A. The threshold voltage VthA of the “A” data is V9A <VthA <VAB. The threshold voltage VthB of “B” data is VAB <VthB <VBC. The threshold voltage VthC of “C” data is VBC <VthC <VCD. The threshold voltage VthD of “D” data is VCD <VthD <VDE. The threshold voltage VthE of “E” data is VDE <VthE <VEF. The threshold voltage VthF of “F” data is VEF <VthF.

  Next, the configuration of the arithmetic circuits 20-0 to 20-m in the verify circuit 6 will be described with reference to FIG. FIG. 19 is a block diagram showing details of the memory cell array 2, row decoder 3, page buffer 5, and verify circuit 6. Note that the configurations and operations of the memory cell array 2, the row decoder 3, and the page buffer 5 are the same as those in the first embodiment, and a description thereof will be omitted.

  As shown in the figure, each of the arithmetic circuits 20-0 to 20-m includes arithmetic units 21-0 to 21-m, first latch circuits 22-0 to 22-m, and second latch circuits 23-0 to 23-m. , Third latch circuits 24-0 to 24-m, fourth latch circuits 26-0 to 26-m, and MOS transistors 25-0 to 25-m, respectively. Hereinafter, the arithmetic circuits 20-0 to 20-m are simply the arithmetic circuit 20, the arithmetic units 21-0 to 21-m are simply the arithmetic unit 21, and the first latch circuits 22-0 to 22-m are simply the first latch circuit 22. The second latch circuits 23-0 to 23-m are simply the second latch circuit 23, the third latch circuits 24-0 to 24-m are simply the third latch circuit 24, and the fourth latch circuits 26-0 to 26-m. Is simply referred to as the fourth latch circuit 26, and the MOS transistors 25-0 to 25-m may be simply referred to as the MOS transistor 25.

  Each of the first to fourth latch circuits 22 to 24 and 26 holds each bit of 4-bit data to be written to the memory cell transistor MT connected to the corresponding bit line BL when data is written. That is, the difference from the first embodiment is that the memory cell transistor MT holds 4-bit data in this embodiment, so that four latch circuits are required per bit line. Therefore, a fourth latch circuit 26 is newly added to the configuration of FIG. 2 described in the first embodiment. The data transferred from the control circuit 7 or the input / output buffer 9 is first held in the fourth latch circuit 26 and transferred from the fourth latch circuit 26 to the first to third latch circuits 22-24.

  Next, the operation of the NAND flash memory having the above configuration will be described. The operation of the flash memory according to the present embodiment is basically the same as that shown in FIGS. 4, 6, and 7 described in the first embodiment, except that the verify is performed from “1” to “F”. “Only the point that is performed for data and the point that there is data transfer between the fourth latch circuit 26 and the arithmetic unit 21.

  In step S12, as in the first embodiment, the control circuit 7 converts the write data held in each of the arithmetic circuits 20-1 to 20-m from gray code to binary code. That is, the 4-bit code obtained by combining the data held in each of the first to fourth latch circuits is converted so as to be in the ascending or descending order of the write data “0” to “F”. In this embodiment, the bit held in the first latch circuit 22 is the first (least significant) bit, the bit held in the second latch circuit 23 is the second bit, and the bit held in the third latch circuit 23 is When the third bit and the bit held in the fourth latch circuit 26 are the fourth (most significant) bit, the 4-bit code obtained by these is in descending order of the write data “0” to “7”. Is converted as follows.

  A binary code obtained by the control circuit 7 is shown in FIG. FIG. 20 is a table showing a relationship between write data and data held in the first to fourth latch circuits 22 to 24 and 26. The bit held in the first latch circuit 22 is “b1”, the bit held in the second latch circuit 23 is “b2”, the bit held in the third latch circuit 24 is “b3”, and the fourth latch circuit 26 If the bit held in “b4” is “b4”, the obtained code is (b4, b3, b2, b1). When the write data is “0”, b1 = “1”, b2 = “1”, b3 = “1”, b4 = “1”, and the obtained code is (1111). When the write data is “1”, the obtained code is (1110). Hereinafter, when the write data is “2” to “F”, the obtained codes are (1101) to (0000). In this way, the control circuit 7 converts the combination of data held by the latch circuits 22 to 24 and 26 from a gray code to a binary code as shown in FIG.

  Next, sequence steps executed by the control circuit 7 during the verify operation will be described with reference to FIG. FIG. 21 is a table showing sequence processing by the sequencer.

  As shown in the figure, the sequence step has nine steps ST1 to ST9. Step ST1 is data (read data) transfer from the sense amplifier 10 to the computing unit 21. Step ST <b> 2 is data transfer from the first latch circuit 22 to the computing unit 21. Step ST3 is data transfer from the second latch circuit 23 to the computing unit 21. Step ST4 is data transfer from the third latch circuit 24 to the computing unit 21. Step ST5 is data transfer from the fourth latch circuit 26 to the computing unit 21. Step ST 6 is data transfer from the computing unit 21 to the first latch circuit 22. Step ST7 is data transfer from the arithmetic unit 21 to the second latch circuit 23. Step ST8 is data transfer from the arithmetic unit 21 to the third latch circuit 24. Step ST9 is data transfer from the arithmetic unit 21 to the fourth latch circuit 26. That is, in FIG. 9 described in the first embodiment, data transfer (steps ST5 and ST9) between the fourth latch circuit 26 and the arithmetic unit 21 is newly added.

  Then, the sequence at the time of “1” to “F” verification when the verification is passed is as shown in FIG. FIG. 22 is a table showing a sequence executed at the time of “1” to “F” verification.

  For example, at the time of “1” verification, step ST1 is executed first, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “1” verification, since “1” is held in the second to fourth latch circuits 23, 24, and 26, steps ST3 to ST5 are executed. Thereafter, if the verification is passed, step ST6 is executed to set the data of the first latch circuit 22 from “0” to “1”. Hereinafter, the same applies to “2” to “F” verification.

  As described above, the first embodiment can be applied to a 16-value NAND flash memory, and the effect (1) described in the first embodiment can be obtained.

[Third Embodiment]
Next explained is a semiconductor memory device according to the third embodiment of the invention. In the present embodiment, the program operation is performed in two stages of the first program and the second program in the first embodiment. Therefore, the verify operation is also performed separately for the first verify and the second verify. Hereinafter, only differences from the first embodiment will be described.

  First, a rough concept of the write operation in the 8-level NAND flash memory according to the present embodiment will be described with reference to FIG. FIG. 23 is a graph showing changes in the threshold voltage of the memory cell transistor MT when the first program and the second program are performed. As an example, a case where “4” data is written will be described.

  First, by repeating the first program, the threshold voltage is raised from the erase level to a certain level. The first program is executed until the first verify level V34 'that is lower than V34, which is the verify level of the "4" data, is exceeded. Further, the threshold voltage fluctuation amount ΔVth1 by one first program is a relatively large value. When performing the first program, as in the first and second embodiments, the write voltage Vpgm is applied to the word line, and the voltage V1 (for example, 0 V) is applied to the bit line BL.

  When the memory cell transistor MT passes the first verify, the second program is performed next. By repeating the second program, the threshold voltage is raised until it exceeds the verify level V34 of the “4” data (hereinafter referred to as the second verify level in the present embodiment). Further, the threshold voltage fluctuation amount ΔVth2 by one second program is set to a value smaller than ΔVth1. In order to reduce the value, a voltage V2 (> V1, for example, about 0.4V) higher than 0V is applied to the bit line BL when the second program is performed.

  That is, in the write operation according to the present embodiment, the program is first roughly performed, and the program is finely programmed when the threshold voltage approaches a predetermined voltage. FIG. 24 is a flowchart showing the flow of the above program. As shown in the drawing, when the first verify is missed (step S30, NO), the first program is executed (step S31). In the first program, the voltage of the bit line BL is set to V1 (step S32).

  If the first verification is passed (step S30, YES) and the second verification is missed (step S33, NO), the second program is executed (step S34). In the second program, the voltage of the bit line BL is set to V2 (> V1) (step S35).

  If the second verification is passed (step S33, YES), the second program is prohibited (step S36). Therefore, the write inhibit voltage (VDD> V2) is applied to the bit line BL (step S37). When all the memory cell transistors MT pass the second verify, the write operation is completed.

  Next, the configuration of the arithmetic circuits 20-0 to 20-m in the verify circuit 6 will be described with reference to FIG. FIG. 25 is a block diagram showing details of the memory cell array 2, row decoder 3, page buffer 5, and verify circuit 6. Note that the configurations and operations of the memory cell array 2, the row decoder 3, and the page buffer 5 are the same as those in the first embodiment, and a description thereof will be omitted.

  As shown in the drawing, each of the arithmetic circuits 20-0 to 20-m is further provided with fifth latch circuits 27-0 to 27-m in the configuration of FIG. 2 described in the first embodiment. Hereinafter, the fifth latch circuits 27-0 to 27-m may be simply referred to as the fifth latch circuit 27. The fifth latch circuit holds “0” data as an initial value, and “1” is written by the arithmetic unit 21 when the first verification is passed. That is, the fifth latch circuit holds information indicating whether or not to execute the second program.

Next, the operation of the NAND flash memory having the above configuration will be described.
[Data write operation]
A data write operation in the NAND flash memory according to the present embodiment will be described with reference to FIG. The data write operation is roughly a repetition of the program operation and the verify operation, as in the first embodiment. However, in the present embodiment, as described above, the first program and the second program are performed as the program operation, and the first verify and the second verify are performed as the verify operation. FIG. 26 is a flowchart of the write operation in the NAND flash memory according to the present embodiment.

  First, similarly to the first embodiment, the operations in steps S10 to S14 are performed. Then, a program is performed (step S40). Whether the first program or the second program is executed in step S40 is determined by the data in the fifth latch circuit 27. That is, the program is executed when the AND operation result of the data and the initial value in the first to third latch circuits 22 to 24 is “0”, and at this time, the fifth latch circuit 27 holds “0”. If so, the first program is executed, and if "1" is held, the second program is executed.

  Next, a first verify is performed for “0” data (step S41), and then a first verify and a second verify are performed for each of “1” to “7” data (step S42). The second verify is the same as the verify operation described in the first embodiment. Details of the first verify will be described later. When the verify operation ends, the process proceeds to step S17.

  The flow of the above write operation will be described with reference to the timing chart of FIG. FIG. 27 is a timing chart showing the voltage of the word line selected by the row decoder 3 at the time of programming and verifying in the write operation shown in FIG. 4, and the times t2 to t6 in FIG. 6 described in the first embodiment. It corresponds to.

  When the conversion from the gray code to the binary code by the control circuit 7 is completed, the program is executed at times t2 to t3. Next, a verify operation is performed during a period from time t3 to t4 (steps S41 and S42). As described above, the verify operation includes the first verify and the second verify. During the second verification for the “1” to “7” data, voltages V01 to V67 are applied to the word lines WL, respectively. On the other hand, during the first verification for the “1” to “7” data, the voltages V01 ′ to V67 ′ lower than the voltages V01 to V67 are applied to the word lines WL, respectively. The first verify is also performed on “0” data.

  As shown in the figure, first verification for “0” data is performed (step S41). Next, the first verify and the second verify are sequentially performed on the “1” data. Next, the first verification and the second verification are sequentially performed on the “2” data. Thereafter, similarly, the first verify and the second verify are sequentially performed for each of the “3” to “7” data (step S42).

[Verify operation]
Next, details of the first verify in FIG. 26 will be described using FIG. 28 while paying attention to the operation of the verify circuit 6 in particular. FIG. 28 is a flowchart of the first verify operation according to the present embodiment. Details of the second verify are the same as those in FIG. 7 described in the first embodiment, and a description thereof will be omitted.

  First, the verify circuit 6 sets the verify data j = “0” (step S50) and starts the first verify (step S51). Then, similarly to the second verification, the processes of steps S22 to S25 are performed.

  If the calculation result in step S25 is “1” (step S26, YES), the calculator 21 transfers the calculation result “1” to the fifth latch circuit 27 corresponding to the calculator 21 and stores the data. Rewriting is performed (step S52). However, data transfer to the first to third latch circuits 22 to 24 is not performed.

  Thereafter, the processes of steps S28 and S29 are performed. That is, the first verify is different from the second verify in that when the calculation result in the calculator 21 is “1”, the calculation result is not sent to the fifth latch circuit 27 but to the first to third latch circuits 22 to 24. The point is to transfer “1”.

  The first verification and the second verification are executed by, for example, a sequencer in the control circuit 7. The second verification sequence step and the sequence for verifying each data are the same as those in FIGS. 9 and 10 described in the first embodiment.

  FIG. 29 is a table showing the sequence processing by the sequencer in the second verification. As shown in the figure, the sequence step has a sequence step ST8 in addition to the sequence steps ST1 to ST7 in the first verification. The sequence step ST8 is data transfer from the arithmetic unit 21 to the fifth latch circuit 27.

  Then, the sequence at the time of “0” to “7” verification when the first verification is passed is as shown in FIG. FIG. 30 is a table showing a sequence executed at the time of the first verification for “0” to “7” data.

  First, “0” verification will be described. First, step ST <b> 1 is executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, at the time of “0” verify, step 1 is to transfer data from the first to third latch circuits 22 to 24 to the arithmetic unit 21 (because b1 = “1”, b2 = “1”, and b3 = “1”). ST2, ST3 and ST4 are executed. Finally, step ST8 is executed to transfer the calculation result of the calculator 21 to the fifth latch circuit 27.

  Next, “1” to “7” verification will be described. The first verify for “1” to “7” data is different from the second verify in that the data transfer to the fifth latch circuit 27 is performed instead of the data transfer to the first to third latch circuits 22 to 24. This is the point to be done. Accordingly, at the time of “1” verification, step ST1 is first performed, then steps ST2 and ST4 are performed, and finally step ST8 is performed. At the time of “2” verification, step ST1 is first performed, then steps ST3 and ST4 are performed, and finally step ST8 is performed. At the time of “3” verification, step ST1 is first performed, then step ST4 is performed, and finally step ST8 is performed. At the time of “4” verification, step ST1 is performed first, then steps ST2 and ST3 are performed, and finally step ST8 is performed. At the time of “5” verification, first, step ST1 is performed, then step ST2 is performed, and finally step ST8 is performed. At the time of “6” verification, step ST1 is first performed, then step ST3 is performed, and finally step ST8 is performed. At the time of “7” verification, step ST1 is first performed, and then step ST8 is performed.

[Specific example of verify operation]
Next, a specific example of the above verify operation will be described with reference to FIGS. FIGS. 31 and 37 are graphs showing the threshold voltage of the memory cell transistor MT. FIGS. 32 to 36 and FIGS. 38 to 41 are circuit diagrams of the arithmetic circuit 20, the sense amplifier 10, and the memory cell transistor MT. . In the following, for simplification of description, a case where there are two bit lines BL1 and BL2 will be described as an example. A case will be described in which “1” and “3” data are respectively written to the memory cell transistors MT connected to the word line WL1 and the bit lines BL1 and BL2. Further, only in the following description of the specific example of the verify operation, the memory cell transistors MT connected to the word line WL1 and the bit lines BL1 and BL2 are referred to as memory cell transistors MT11 and MT12, respectively, for convenience of explanation.

  First, it is assumed that the threshold distribution of the memory cell transistors MT11 and MT12 is as shown in FIG. 31 as a result of the first program being performed first. That is, the threshold voltage of the memory cell transistor MT11 to which “1” is to be written is higher than V01 ′ that is the first verify level and lower than V01 that is the second verify level. Further, the threshold voltage of the memory cell transistor MT12 to which “3” is to be written is lower than V23 ′ that is the first verify level and lower than V23 that is the second verify level. That is, the memory cell transistor MT11 is in a state where it passes the first verify but misses the second verify. The memory cell transistor MT12 is in a state where it misses both the first and second verify operations.

  After the program, first verification is performed on “1” data. FIG. 32 shows this state. As shown in the figure, when performing “1” verification, the voltage V01 ′ is applied to the word line WL0. Then, since the memory cell transistors MT11 and MT12 are both turned off, the data held by the sense amplifiers 10-1 and 10-2 is “1”. At the time of “1” verification, the data in the second latch circuits 23-1 and 23-2 and the third latch circuits 24-1 and 24-2 are transferred to the computing units 21-1 and 21-2, respectively. (Steps ST2 and ST4).

  Then, the AND operation result of the arithmetic unit 21-1 is “1”, and the AND operation result of the arithmetic unit 21-2 is “0”. That is, the memory cell transistor MT11 passes the first verify. Accordingly, the arithmetic unit 21-1 transfers the operation result “1” to the fifth latch circuit 27-1 (step ST8), and the data held in the fifth latch circuit 27-1 changes from “0” to “1”. Rewritten. As described above, since data transfer to the first to third latch circuits 22 to 24 is not performed at the time of the first verify, the first latch circuit 22-1 continues to hold “0”. The computing unit 21-2 does not transfer the computation result because the AND computation result is “0”. Therefore, the data held by the fifth latch circuit 27-2 remains “0”.

  Next, the second verify is performed for “1” data. FIG. 33 shows this state. As shown in the figure, when performing “1” verification, a voltage V01 (> V01 ′) is applied to the word line WL0. Then, since the memory cell transistors MT11 and MT12 are turned on and off, respectively, the data held by the sense amplifiers 10-1 and 10-2 are “0” and “1”, respectively. The data in the second latch circuits 23-1, 23-2 and the third latch circuits 24-1, 24-2 are transferred to the computing units 21-1, 21-2, respectively (steps ST2, ST4). .

  Then, the AND operation result of the arithmetic units 21-1 and 21-2 is “0”. That is, the memory cell transistor MT11 misses the second verify. Then, the computing units 21-1 and 21-2 do not transfer the computation results.

  Next, the first verify is performed for “3” data. This is shown in FIG. As shown in the figure, first, when performing “3” verification, the voltage V23 ′ is applied to the word line WL0. Then, since the memory cell transistors MT11 and MT12 are both turned on, the data held by the sense amplifiers 10-1 and 10-2 is “0”. At the time of “3” verification, the data in the third latch circuits 24-1 and 24-2 are transferred to the computing units 21-1 and 21-2, respectively (step ST4).

  Then, the AND operation results of the calculators 21-1 and 21-2 are both “0”. That is, the memory cell transistor MT12 misses the first verify. Then, the computing units 21-1 and 21-2 do not transfer the computation results.

  Next, the second verification is performed on “3” data. This is shown in FIG. As shown in the figure, when performing “3” verification, a voltage V23 (> V23 ′) is applied to the word line WL0. Then, since the memory cell transistors MT11 and MT12 are both turned on, the data held by the sense amplifiers 10-1 and 10-2 is “0”. At the time of “3” verification, the data in the third latch circuits 24-1 and 24-2 are transferred to the computing units 21-1 and 21-2, respectively (step ST4).

  Then, the AND operation results of the calculators 21-1 and 21-2 are both “0”. That is, the memory cell transistor MT12 misses the second verify. Then, the computing units 21-1 and 21-2 do not transfer the computation results.

  Thus, the first program and the first and second verify operations corresponding thereto are completed. That is, the processing at times t2 to t4 in FIG. 27 is completed. At this point, since the memory cell transistors MT11 and MT12 have not reached the desired threshold voltage, programming is performed again.

  The state of the second program is shown in FIG. As described above, the program data is determined by the AND operation result in the arithmetic unit 21 of the data held by the first to third latch circuits 22 to 24. That is, if the calculation result is “0”, the program is performed, and if “1”, the program is not performed. Further, when performing the program, the arithmetic unit 21 refers to the data in the fifth latch circuit 27. If the fifth latch circuit 27 holds “0”, the first program is executed, and if it holds “1”, the second program is executed.

  In the example of FIG. 36, the calculation results of the calculators 21-1 and 21-2 are both “0”. Therefore, programming is performed on both the memory cell transistors MT11 and MT12. Further, since the fifth latch circuits 27-1 and 27-2 hold “1” and “0”, respectively, the second program is performed on the memory cell transistor MT11, and the first latch is performed on the memory cell transistor MT12. The program is performed. Based on the instructions of the arithmetic units 21-1 and 21-2, the sense amplifiers 10-1 and 10-2 have voltages V2 (for example, 0.4V) and V1 (for example, 0V and <V2) applied to the bit lines BL1 and BL2, respectively. Apply. Then, the row decoder 3 applies the program voltage Vpgm2 to the word line WL1 to perform programming.

  As a result of the second program, it is assumed that the threshold voltages of the memory cell transistors MT11 and MT12 change as shown in FIG. That is, as a result of the first program being performed on the memory cell transistor MT11, the threshold voltage becomes higher than V01 which is the second verify level. That is, the writing of “1” data is completed. On the other hand, as a result of the second program being performed on the memory cell transistor MT12, the threshold voltage is higher than the first verify level V23 'and lower than V23 which is the second verify level. That is, the memory cell transistor MT12 is in a state where it passes the first verification but misses the second verification.

  After the program, first verification is performed on “1” data. Of course, the memory cell transistor MT11 passes the first verify.

  Subsequently, the second verify is performed for “1” data. FIG. 38 shows this state. Since the threshold voltage of the memory cell transistor MT12 exceeds the second verify level V01, the memory cell transistor MT11 is turned off. Therefore, the data held by the sense amplifier 10-1 is “1”. As a result, the AND operation result in the calculator 21-1 is “1”. Accordingly, the arithmetic unit 21-1 transfers the operation result “1” to the first latch circuit 22-1 (step ST5), and the data in the first latch circuit 22-1 is rewritten from “0” to “1”. . As a result, the data in the first to third and fifth latch circuits 22-1 to 24-1 and 27-1 are all "1".

  Next, the first verify is performed for “3” data. This is shown in FIG. Since the threshold voltage of the memory cell transistor MT12 exceeds the first verify level V23 ', the memory cell transistor MT12 is turned off. Therefore, the data held by the sense amplifier 10-2 is “1”. As a result, the AND operation result of the arithmetic unit 21-2 is “1”. Accordingly, the calculation result “1” of the calculator 21-2 is transferred to the fifth latch circuit 27-2 (step ST8), and the data in the fifth latch circuit 27-2 is rewritten from “0” to “1”. .

  Next, the second verification is performed on “3” data. This is shown in FIG. Since the threshold voltage of the memory cell transistor MT12 does not exceed the second verify level V23, the memory cell transistor MT12 is turned on. Therefore, the data held by the sense amplifier 10-12 is “0”, and the calculation result is not transferred from the calculator 21-2 to the first and second latch circuits 22-2 and 23-2.

  Thus, the second program and the first and second verify operations corresponding thereto are completed. At this time, the memory cell transistor MT12 has not reached the desired threshold voltage, and therefore programming is performed again.

  The state of the third program is shown in FIG. In the third program, the calculation result of the calculator 21-1 is “1”. Therefore, “1” is held as program data in the sense amplifier 10-1, and the write inhibit voltage VDD is applied to the bit line BL1. Therefore, no programming is performed on the memory cell transistor MT11 for which the “1” program has already been completed. On the other hand, the calculation result of the calculator 21-1 is “0”. Therefore, “0” is held as program data in the sense amplifier 10-2. Further, since “1” is held in the fifth latch circuit 27-2, the voltage V2 is applied to the bit line BL2. That is, the second program is performed on the memory cell transistor MT12.

  As described above, the program and the verify are repeated until the data in the first latch circuits 22-1 to 22-2 and the second latch circuits 23-1 to 23-3 are all "1".

As described above, the semiconductor memory device according to the third embodiment of the present invention has the following effect (2) in addition to the effect (1) described in the first embodiment.
(2) The writing accuracy can be improved while speeding up the data writing.
In the NAND flash memory according to the present embodiment, as described with reference to FIG. 23, the program operation includes the first program with a threshold voltage fluctuation range of ΔVth1 and the second program with a fluctuation range of ΔVth2 (<ΔVth1). Includes programs.

  The threshold voltage of the memory cell transistor MT is set to a level slightly lower than the desired threshold voltage by the first program. At this time, since the fluctuation range of the threshold voltage by the first program is large, the number of programs can be reduced and the writing speed can be improved.

  The threshold voltage of the memory cell transistor MT is set to a desired threshold voltage by the second program after the first program. At this time, according to the second program, the threshold voltage can be finely set, so that the writing accuracy can be improved.

  Since the method described in the first embodiment can be used for verifying the second program (second verify), the effect (1) described in the first embodiment can be obtained.

[Fourth Embodiment]
Next explained is a semiconductor memory device according to the fourth embodiment of the invention. In the present embodiment, the second embodiment is applied to a 16-value NAND flash memory. That is, this embodiment is a combination of the second embodiment and the third embodiment. Therefore, only differences from the second and third embodiments will be described below.

  FIG. 42 is a block diagram showing details of the memory cell array 2, row decoder 3, page buffer 5, and verify circuit 6. The configurations and operations of the memory cell array 2, the row decoder 3, and the page buffer 5 are the same as those in the first embodiment, and thus description thereof is omitted.

  As shown in the drawing, each of the arithmetic circuits 20-0 to 20-m has the fifth latch circuit 27-0 to 27-m described in the third embodiment in the configuration of FIG. 19 described in the second embodiment. Is further provided. As described above, the fifth latch circuit 27 holds “1” when the first verification is passed, and the second program is executed when the fifth latch circuit 27 holds “1”.

  Next, sequence steps executed by the control circuit 7 during the verify operation will be described with reference to FIG. FIG. 43 is a table showing sequence processing by the sequencer.

  As shown in the drawing, the sequence step further includes a step ST10 for transferring data from the computing unit 21 to the fifth latch circuit 27 in addition to the sequence step of FIG. 21 described in the second embodiment.

  Then, the first verification sequence for “0” to “F” when the first verification is passed is as shown in FIG. FIG. 43 is a table showing a sequence executed at the time of the first verification for “0” to “F” data.

As shown in the figure, similarly to FIG. 30 described in the third embodiment, data transfer from the sense amplifier 10 to the arithmetic unit 21, data transfer from the first to fourth latch circuits to the arithmetic unit 21, Data transfer from the arithmetic unit 21 to the fifth latch circuit 27 is performed. For example, at the time of “0” verification, step ST1 is first executed, and read data is transferred from the sense amplifier 10 to the computing unit 21. Next, since “1” is held in the first to fourth latch circuits 22 to 24 and 26 at the time of “0” verification, steps ST2 to ST5 are executed. Thereafter, when the first verification is passed, the calculation result “1” in the calculator 21 is transferred to the fifth latch circuit 27. Hereinafter, the same applies to “1” to “F” verification.
Note that the sequence executed during the second verification is the same as that in FIG. 22 described in the second embodiment.

  As described above, the third embodiment can be applied to a 16-value NAND flash memory, and the effect (2) described in the third embodiment can be obtained.

[Fifth Embodiment]
Next explained is a semiconductor memory device according to the fifth embodiment of the invention. This embodiment relates to a method for converting a Gray code into a binary code in the first to fourth embodiments. FIG. 45 is a table showing gray code and binary code bits corresponding to write data “0” to “F”. In the figure, 1DL, 2DL, 3DL, and XDL indicate each bit constituting a gray code, and 1DL ', 2DL', 3DL ', and XDL' indicate each bit constituting a binary code. 1DL ', 2DL', 3DL ', and XDL' are held in the first to fourth latch circuits.

As illustrated, 1DL ′, 2DL ′, 3DL ′, and XDL ′ are calculated by, for example, the following equations.
1DL '= ~ xor (1DL, xor (2DL, xor (XDL, 3DL)))
2DL '= ~ xor (2DL, xor (XDL, 3DL))
3DL '= ~ xor (XDL, 3DL)
XDL '= XDL
However, “˜” indicates a logical NOT operation, and “xor” indicates an exclusive OR operation. As the sequencer performs the above calculation, the gray code input from the outside is converted into a binary code. In FIG. 45, the case where the write data is 4 bits has been described, but the same method can be used even when the write data is 3 bits.

[Sixth Embodiment]
Next explained is a semiconductor memory device according to the sixth embodiment of the invention. The present embodiment relates to a case where write data input from the outside is a binary code in the first to fourth embodiments. FIG. 46 is a flowchart showing a write operation in the NAND flash memory according to the present embodiment.

  As shown in the figure, a write command, an address, and write data described in binary code are input from the outside to the NAND flash memory (step S60). Then, the control circuit 7 sets the input write data to the latch circuit in the arithmetic circuits 20-0 to 20-m without performing the conversion process (step S61). Thereafter, the process proceeds to step S13.

  In the present embodiment, the conversion from the gray code to the binary code in the control circuit 7 becomes unnecessary.

[Seventh Embodiment]
Next explained is a semiconductor memory device according to the seventh embodiment of the invention. The present embodiment relates to binary code examples in the first to sixth embodiments. In the following, the case where the write data is 3 bits will be described. 47 to 49 are tables showing the relationship between the write data and the binary code associated with each write data.

  In the first embodiment, as described with reference to FIG. 5, the codes (b3, b2,...) Configured when the bits held in the first to third latch circuits are b1, b2, and b3. The binary code is generated so that b1) is in descending order from “0” data.

  However, as shown in FIG. 47, the binary code may be generated so that the codes (b1, b2, b3) are in descending order from “0” data. Further, as shown in FIG. 48, the codes (b3, b1, b2) may be arranged in descending order from “0” data. Further, as shown in FIG. 49, the codes (b1, b3, b2) may be arranged in descending order from “0” data.

  That is, a three-digit code in which the data held in the three latch circuits is any bit may be in descending order from the write data = “0”. In this case, among the first to third latch circuits, a combination of “j” data (j is any one of “0” to “6”) whose value is “1” is stored. Is different from the combination in programming all data having a threshold voltage higher than that of “j” data.

As an example, consider the case of programming “4” data. Then, in the case of FIG. 47, it is bits b2 and b3 that the binary code becomes “1” in the “4” data program. That is, the combination of latch circuits that hold “1” is the second latch circuit and the third latch circuit. On the other hand, when “5” data is programmed, only bit b2 becomes “1”. That is, the only latch circuit that holds “1” is the second latch circuit. When programming the “6” data, only the bit b3 becomes “1”. That is, the third latch circuit is the only latch circuit that holds “1”. Further, when “7” data is programmed, all bits become “0”. That is, when “5” to “7” data is programmed, neither the second latch circuit nor the third latch circuit holds “1”.
The same applies to the cases of FIGS. 48 to 49.

  In FIGS. 5 and 47 to 49, “1” is valid data among “0” and “1” held by each bit. However, “0” may be valid data. That is, the data transferred from the first to third latch circuits to the computing unit 21 may be “0” instead of “1”. An example of the binary code in this case is shown in FIG.

As shown in FIG. 50, the binary code in FIG. 50 is obtained by replacing “0” and “1” in the binary code shown in FIG. Then, the codes (/ b3, / b2, / b1) configured when the bits held in the first to third latch circuits are b1, b2, and b3 are in descending order from the “0” data. “/” Means data inversion. Of course, “0” and “1” may be inverted in the binary codes of FIGS. In this case, the data “0” may be transferred to the computing unit 21 by inverting the “0” data without transferring the “0” data itself to the computing unit 21.
As described above, in the semiconductor memory device according to the first to seventh embodiments of the present invention, write data is handled as binary code instead of gray code. Accordingly, the number of data transfers during verification can be reduced, and the number of data transfers between write data can be made uniform. Therefore, the writing speed of the semiconductor memory device can be improved.

  Although the case where one memory cell transistor MT can take 8 values or 16 values has been described in the above embodiment, this is only an example, and for example, 4 values (2 bits) or 32 values (5 bits). It may be. When the memory cell transistor holds n-bit data, the following configuration may be used.

That is, the memory cell transistor holds n bits (n is a natural number of 3 or more) of “0” data to “2 ⁿ −1” data according to the threshold voltage. Then, first to nth latch circuits are provided for respectively holding the values of the 1st to nth bits in the program data during the program operation and the verify operation. Further, an arithmetic unit is provided for performing a logical operation between the value transferred from at least one of the first to nth latch circuits and the read data amplified by the sense amplifier during the verify operation. When verifying “i” data (i is any one of “1” to “2 ⁿ −1”), the first to nth latch circuits are held when programming “i” data. The value is transferred to the arithmetic unit from the value that becomes the valid data. Of the first to n-th latch circuits, the combination of those that hold valid data when “j” data (j is any one of “0” to “2 ⁿ -2”) is “j” It may be different from the combination in all cases where data having a higher threshold voltage than data is programmed.

  Further, the arithmetic unit determines that the first value when the transferred values are all valid data and the data amplified by the sense amplifier is a value indicating that the threshold voltage of the memory cell transistor passes verification. Or invalid data held in any of the nth latch circuits is rewritten to valid data.

  In addition, the calculation content performed by the calculator is not limited to the AND calculation. For example, the valid data for the program data is “0” as shown in FIG. 50, and the valid data in the sense amplifier is also “0” (“0” is held when the verification is passed). For this, an OR operation may be performed. That is, the arithmetic unit 21 has all the values read from the latch circuit as valid data, and the data transferred from the sense amplifier is a value indicating that the threshold voltage of the memory cell transistor is higher than the verify level. In this case, any configuration that generates valid data may be used.

  In the above embodiment, the most significant bit of the n-bit data constituting the binary code is preferably stored in a latch circuit that can be separated from the arithmetic unit 21 by the MOS transistor 25. This point will be described by taking the case of an 8-level NAND flash memory as an example.

  FIG. 51 is a table showing each bit b1, b2, b3 of the binary code corresponding to “0” to “7” data. As shown in the figure, it is assumed that the binary code composed of three digits (b3, b2, b1) is associated with “0” to “7” data so that the data is in descending order from “0” data. . In this case, it is preferable that b3 which is the most significant bit in the three-digit binary code is stored in the second latch circuit 23 in the configuration of FIG. The reason for this will be described with reference to FIG.

  FIG. 52 is a table showing each bit of the binary code held in each of the first to third latch circuits 22 to 23 when the verification for the “1” to “3” data is completed. As shown in the figure, when the data verification of “1” to “3” is completed, the value in each of the first to third latch circuits 22 to 23 in the arithmetic circuit 20 holding “0” to “3” data is “ It should be 1 ”. That is, after the verification for the “0” to “3” data is completed, the “4” to “7” data can be distinguished only by (b2, b1). Therefore, the bit b3 is not necessary in terms of data identification.

  However, in order to write “4” data, “0” must be held in any latch circuit. That is, the bit b3 is necessary to write “4” data. However, the bit b3 is not necessary for writing the data “5” to “7”. This is because at the time of writing data “5” to “7”, at least one of the bits b1 and b2 is “0”.

  In view of the above, the second latch circuit 23 holds the bit b3 in the second latch circuit 23 in FIG. 2 and keeps the MOS transistor 25 in the OFF state after the data verification of “0” to “4” is completed. Can be used for other purposes. That is, even when the write sequence shown in FIG. 4 is being executed in the NAND flash memory (during “5” to “7” data writing), the arithmetic circuit 20 can take in data from the outside. Therefore, the processing in the NAND flash memory can be made efficient and the processing speed can be improved.

The same applies to a 16-value NAND flash memory. In this case, when there are each bit b1, b2, b3, b4 of the binary code corresponding to “0” to “F” data, for example, a binary code composed of four digits (b4, b3, b2, b1). Are in descending order from the “0” data. In this case, it is preferable that b4 which is the most significant bit of the 4-digit binary code is stored in the fourth latch circuit 26 in the configuration of FIG. This is because, in the case of a 16-value NAND flash memory, the bit b4 becomes unnecessary for data distinction when “0” to “8” data verification is completed. Of course, when the writing of “0” to “C” data is completed, the latch circuit holding the bit b3 can be opened. Further, when the writing of “D” and “E” data is completed, the latch circuit holding the bit b2 can be released, and when the writing of “F” data is completed, the latch circuit holding the bit b1 is opened. It can be made.
The above also applies to the case where the binary code is as shown in FIGS.

  Furthermore, in the above-described embodiment, the case where data is directly written from the erase level to a desired level is described as an example in FIG. 23, but the writing method is not limited to such a method. For example, in the case of the 16-level NAND flash memory shown in FIG. 18, first, a 4-level level write is performed. That is, if the write data is “0” to “3”, the program is not performed. If the write data is “4” to “7”, the program is performed to the “4” level, and the write data is “8” to “7”. If “B”, the program is performed at the “8” level, and if the write data is “C” to “F”, the program is performed at the “C” level. Next, binary level writing is performed. That is, if the write data is “0” to “1”, the program is not performed, and if the write data is “2” to “3”, the program is performed to the “2” level. If the write data is “4” to “5”, the program is performed at the “4” level, and if the write data is “6” to “7”, the program is performed at the “6” level. The same applies hereinafter. Then, the binary level is written again to finally obtain 16 values.

  In such a case, the program shown in FIG. 23 is not necessarily performed with the erasure level as the start point, but of course, such a case is also applicable.

  In the above embodiment, the NAND flash memory is used as an example. However, for example, a NOR flash memory, a DINOR flash memory, and an AND flash memory may be used. Also, other flash memories such as a 3Tr-NAND flash memory in which the number of memory cell transistors is one in a NAND flash memory and a 2Tr flash memory in which the selection transistor ST1 is eliminated in the 3Tr-NAND flash memory are also included. Applicable.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of a flash memory according to a first embodiment of the present invention. 1 is a circuit diagram of a memory cell array, row decoder, page buffer, and verify circuit included in a flash memory according to a first embodiment of the present invention. 3 is a graph showing a threshold distribution of memory cells included in the flash memory according to the first embodiment of the present invention. 4 is a flowchart of a write operation in the flash memory according to the first embodiment of the present invention. 1 is a diagram showing a binary code generated by a flash memory according to a first embodiment of the present invention. 4 is a timing chart of a write operation in the flash memory according to the first embodiment of the present invention. 4 is a flowchart of a verify operation in the flash memory according to the first embodiment of the present invention. 3 is a graph showing a threshold distribution of memory cell transistors in the flash memory according to the first embodiment of the present invention. 2 is a diagram showing a sequence step of a verify operation in the flash memory according to the first embodiment of the present invention. 2 is a diagram showing a sequence of a verify operation in the flash memory according to the first embodiment of the present invention. 1 is a block diagram of a memory cell array, a sense amplifier, and a verify circuit included in a flash memory according to a first embodiment of the present invention. 1 is a block diagram of a memory cell array, a sense amplifier, and a verify circuit included in a flash memory according to a first embodiment of the present invention. 1 is a block diagram of a memory cell array, a sense amplifier, and a verify circuit included in a flash memory according to a first embodiment of the present invention. 1 is a block diagram of a memory cell array, a sense amplifier, and a verify circuit included in a flash memory according to a first embodiment of the present invention. 1 is a block diagram of a memory cell array, a sense amplifier, and a verify circuit included in a flash memory according to a first embodiment of the present invention. Diagram showing gray code. 2 is a diagram showing a relationship between a binary code generated by the flash memory according to the first embodiment of the present invention and a threshold distribution. 6 is a graph showing a threshold distribution of memory cell transistors included in a flash memory according to a second embodiment of the present invention. FIG. 6 is a circuit diagram of a memory cell array, row decoder, page buffer, and verify circuit included in a flash memory according to a second embodiment of the present invention. The diagram which shows the binary code produced | generated by the flash memory based on 2nd Embodiment of this invention. 10 is a diagram showing a sequence step of a verify operation in the flash memory according to the second embodiment of the present invention. 6 is a diagram showing a verify operation sequence in a flash memory according to a second embodiment of the present invention; It is a graph which shows the threshold value distribution of the memory cell transistor with which the flash memory which concerns on 3rd Embodiment of this invention is provided, and is a figure which shows the write-in method. 9 is a flowchart of a write operation in a flash memory according to a third embodiment of the present invention. FIG. 6 is a circuit diagram of a memory cell array, row decoder, page buffer, and verify circuit included in a flash memory according to a third embodiment of the present invention. 9 is a flowchart of a write operation in a flash memory according to a third embodiment of the present invention. 9 is a timing chart of a write operation in a flash memory according to a third embodiment of the present invention. 9 is a flowchart of a verify operation in a flash memory according to a third embodiment of the present invention. 9 is a diagram showing a sequence step of a verify operation in a flash memory according to a third embodiment of the present invention. 9 is a diagram showing a verify operation sequence in a flash memory according to a third embodiment of the present invention; 10 is a graph showing a threshold distribution of memory cell transistors included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. 10 is a graph showing a threshold distribution of memory cell transistors included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 9 is a block diagram of a memory cell array, sense amplifier, and verify circuit included in a flash memory according to a third embodiment of the present invention. FIG. 10 is a circuit diagram of a memory cell array, row decoder, page buffer, and verify circuit included in a flash memory according to a fourth embodiment of the present invention. The diagram which shows the sequence step of the verify operation | movement in the flash memory which concerns on 4th Embodiment of this invention. The diagram which shows the sequence of the verify operation | movement in the flash memory which concerns on 4th Embodiment of this invention. The diagram which shows the method of converting the Gray code into a binary code in the flash memory which concerns on 5th Embodiment of this invention. 18 is a flowchart of a write operation in a flash memory according to the sixth embodiment of the present invention. The diagram which shows the relationship between the write data and the binary code in the flash memory based on 7th Embodiment of this invention. The diagram which shows the relationship between the write data and the binary code in the flash memory based on 7th Embodiment of this invention. The diagram which shows the relationship between the write data and the binary code in the flash memory based on 7th Embodiment of this invention. The diagram which shows the relationship between the write data and the binary code in the flash memory based on 7th Embodiment of this invention. The diagram which shows the relationship between the write data and the binary code in the flash memory which concerns on the modification of the 1st thru | or 7th embodiment of this invention. The diagram which shows the relationship between the write data and the binary code in the flash memory which concerns on the modification of the 7th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Flash memory, 2 ... Memory cell array, 3 ... Row decoder, 4 ... Source line driver, 5 ... Page buffer, 6 ... Verify circuit, 7 ... Control circuit, 8 ... Voltage generation circuit, 9 ... Input / output buffer, 10- 0-10-m sense amplifier, 20-0-20-m arithmetic circuit, 211-1 to 21-m arithmetic unit, 22-0 to 22-m first latch circuit, 23-0 to 23- m: second latch circuit, 24-0 to 24-m ... third latch circuit, 25-0 to 25-m ... MOS transistor, 26-0 to 26-m ... fourth latch circuit, 27-0 to 27- m ... Fifth latch circuit

Claims (5)

A memory cell transistor having a stacked gate including a charge storage layer and a control gate and capable of holding n bits (n is a natural number of 2 or more) of “0” data to “2 ⁿ −1” data according to a threshold voltage When,
A sense amplifier that amplifies the data read from the memory cell transistor during a verify operation;
First to n-th latch circuits for holding values of 1st to nth bits in program data to be programmed in the memory cell transistors during a program operation and a verify operation,
An arithmetic unit that performs a logical operation of the value transferred from at least one of the first to n-th latch circuits and the data amplified by the sense amplifier during the verify operation; When verifying “i” data (i is any one of “1” to “2 ⁿ −1”), when programming the “i” data in the first to nth latch circuits. Since the value to be held is valid data, the value is transferred to the computing unit,
Among the first to n-th latch circuits, a combination of those holding the valid data when “j” data (j is any one of “0” to “2 ⁿ -2”) is programmed as “ The semiconductor memory device, wherein the combination is different in all cases where data having a threshold voltage higher than j ″ data is programmed. In the arithmetic unit, the transferred values are all valid data, and the data amplified by the sense amplifier is a value indicating that a threshold voltage of the memory cell transistor is higher than a verify level. 2. The semiconductor memory device according to claim 1, wherein invalid data held in any of the first to nth latch circuits is rewritten to the valid data. An n-bit code obtained by combining the values held in each of the first to nth latch circuits is an ascending or descending value in the order of “0” to “2 ⁿ −1”. The semiconductor memory device according to claim 1. A control circuit for transferring each bit of the n-bit program data described in Gray code to each of the first to n-th latch circuits;
The control circuit is configured such that an n-bit code obtained by combining the values in the first to n-th latch circuits with the values held in the first to n-th latch circuits is “0”. 4. The semiconductor memory device according to claim 3, wherein conversion is performed so that values are in ascending order or descending order in order of “2 ⁿ −1”. A (n + 1) th latch circuit;
The verify operation includes a first verify operation for determining whether a threshold voltage of the memory cell transistor is higher than a first verify level, and whether the threshold voltage is higher than a second verify level higher than the first verify level. Including a second verify operation for determining whether
In the first verify operation, the arithmetic unit is configured such that the read values are all valid data, and the data amplified by the sense amplifier is the threshold voltage of the memory cell transistor. If the value is higher than the level, the valid data is set in the (n + 1) th latch circuit, and the transferred value is all valid data in the second verify operation, When the data amplified by the sense amplifier is a value indicating that the threshold voltage of the memory cell transistor is higher than the second verify level, the data is supplied to any one of the first to nth latch circuits. Rewrite the invalid data held by the valid data,
When the data amplified by the sense amplifier in the first verify operation is a value indicating that the threshold voltage of the memory cell transistor is lower than the first verify level, the drain of the memory cell transistor The program operation is performed by applying a first voltage to
The data amplified by the sense amplifier in the first verify operation is a value indicating that the threshold voltage of the memory cell transistor is higher than the first verify level, and the sense amplifier in the second verify operation. When the data amplified in step (b) is a value indicating that the threshold voltage of the memory cell transistor is lower than the second verify level, the drain voltage of the memory cell transistor is lower than the first voltage. The semiconductor memory device according to claim 1, wherein the program operation is performed by applying a high second voltage.

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