JP2009048718A - Semiconductor memory device and bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing power consumption of an address decoder when an invalid address is entered, and a bus system. <P>SOLUTION: A bus slave 20a is provided with an access control circuit 22 for generating an access invalid signal AI when it is determined that an address signal ADD is an invalid address based on upper addresses A16 to A19 of the address signal AD. The bus slave 20a is provided with a selector 23 for supplying a stop address SAD to an address decoder 27 according to the access invalid signal AI from the access invalid signal AI. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a semiconductor memory device and a bus system.
In recent years, the memory capacity of semiconductor memory devices has been increasing year by year due to miniaturization and higher integration due to the progress of manufacturing process technology. However, as the memory capacity increases, the operation speed at the time of reading of the semiconductor memory device decreases. Therefore, the operation speed at the time of reading is improved by dividing a large-capacity semiconductor memory device into a plurality of memory blocks. However, as the number of memory blocks increases, the number of address decoders that uselessly consume power in an invalid address increases, which increases the power consumption of the entire bus system.

  Conventionally, a bus system in which a bus master including a central processing unit (CPU) and a direct access memory controller (DMAC) and a bus slave including a semiconductor storage device and a timer transfer data via a common bus has been widely used. Yes. In such a bus system, a bus signal (address signal, control signal, write data, etc.) corresponding to the processing requested by the bus master is output to the common bus, and the bus slave acquires the bus signal and executes the desired processing. It is supposed to be.

  By the way, in recent years, the memory capacity of a semiconductor memory device serving as a bus slave is increasing year by year due to miniaturization and high integration due to the progress of manufacturing process technology. However, as the memory capacity increases, there arises a problem that the operation speed during reading of the semiconductor memory device decreases. That is, the miniaturization of the manufacturing process shortens the distance between the word lines (bit lines) and increases the wiring capacity, and the higher integration increases the number of memory cells connected to one word line (bit line). This increases the parasitic capacitance of the word line (bit line). Then, due to the increase in the wiring capacitance and the parasitic capacitance, the data read time becomes long.

  Therefore, a method for improving the data reading speed by dividing a large-capacity semiconductor memory device into a plurality of memory blocks (bus slaves) has been proposed. However, as the number of memory blocks increases, the number of drive circuits (sensor amplifiers, etc.) for driving the memory blocks increases. Since this drive circuit operates even when an address signal (invalid address) for selecting a different memory block is input, the power consumption of the entire bus system increases as the number of memory blocks increases. .

  Therefore, as shown in FIG. 5, a bus slave 50a that selectively activates the sense amplifier 52 according to the address An of the most significant bit of the address signal ADD from the bus master 40 has been proposed (for example, Patent Documents). 1). That is, the bus slave 50a deactivates the sense amplifier 52 according to the highest address An of “1” indicating the inactivation of the memory block 51a in the bus slave 50a. The bus slave 50a activates the sense amplifier 52 in accordance with the highest address An of “0” indicating the activity of the memory block 51a. In other words, the bus slave 50a deactivates the sense amplifier 52 when the address signal ADD is an invalid address, and activates the sense amplifier 52 when the address signal ADD is a valid address.

Also, as shown in FIG. 6, a bus slave 60a that selectively controls access to the memory block 61a according to the highest address An of the address signal ADD from the bus master 40 has been proposed (for example, Patent Documents). 2). That is, the bus slave 60a outputs a decoding result (selection signal) from the address decoder 63 to the memory block 61a in accordance with the highest address An of “1” indicating inactivation of the memory block 61a in the bus slave 60a. And the memory block 61a is deactivated.
JP 2000-21187 A Japanese Patent Laid-Open No. 10-125068

  Any of the methods disclosed in Patent Documents 1 and 2 can reduce wasteful power consumption by a sense amplifier or the like when an invalid address is input. However, in either method of Patent Documents 1 and 2, the lower addresses A0 to An-1 other than the highest address An are address decoders 53 regardless of the logical level (valid address / invalid address) of the highest address An. , 63. That is, as shown in FIG. 7, the address decoders 53 and 63 each time the address signal ADD is switched even if the address signal ADD is an invalid address (in FIG. 7, the address signals ADD2 to ADD5 are invalid addresses). A selection signal SS for selecting one word line of the memory blocks 51a and 61a is always generated. Accordingly, in such bus slaves 50a and 60a, when an invalid address is input, useless power is consumed by the switching operation of the address decoder (generation of the selection signal SS). Therefore, as the number of memory blocks increases, the number of address decoders connected to the memory blocks increases, and there is a problem that the power consumption of the entire bus system increases. This problem is not limited to the bus systems shown in FIGS. 5 and 6 and commonly occurs in bus systems having a plurality of semiconductor memory devices.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device and a bus system capable of reducing power consumption in an address decoder when an invalid address is input. .

  To achieve the above object, the invention according to claim 1 is a memory block including a plurality of registers to / from which data is input / output from a bus master via a bus, and a selection signal for selecting a register corresponding to an input address And an address decoder for generating an n-bit address signal input from the bus master via the bus, an effective address for designating an address in the memory block, or an address in the memory block A determination unit that determines whether the address is an invalid address, and a low-order m-bit address of the address signal according to a determination result by the determination unit that indicates that the address signal is the valid address Outputs an address to the address decoder and the address signal Address decoder control for outputting to the address decoder stop addresses composed of m-bit addresses that are not used as the plurality of registers in the memory block in accordance with a determination result by the determination means indicating the invalid address A circuit.

  According to this configuration, when an invalid address is input, stop addresses that are not used as a plurality of registers in the memory block are always input to the address decoder. Therefore, when invalid addresses are continuously input, the same stop address is continuously input to the address decoder. As a result, address switching in the address decoder when invalid addresses are continuously input can be suppressed, and switching operation in the address decoder can be suppressed. As a result, power consumption by the address decoder when an invalid address is input can be reduced. Note that n is an integer of 2 or more, and m is an integer of 1 or more.

  According to a second aspect of the present invention, the address decoder control circuit receives a stop address holding circuit that holds the stop address, the lower address, and the stop address from the stop address holding circuit. The semiconductor memory device includes an address holding circuit that is provided between the selection circuit and the address decoder and latches the lower address or the stop address input from the selection circuit. The circuit outputs the lower address to the address holding circuit according to a determination result by the determination unit indicating that the address signal is the effective address, and indicates that the address signal is the invalid address. According to the determination result by the determination means, the stop address is assigned to the address holding circuit. To output.

  According to this configuration, when the invalid address is continuously input, the stop address is held in the address holding circuit, so that the same stop address is continuously supplied to the address decoder reliably. Therefore, the switching operation in the address decoder when an invalid address is input can be more reliably suppressed.

  According to a third aspect of the present invention, the determination means receives a write signal for instructing a write operation and a read signal for instructing a read operation, and the determination means determines that the address signal is the effective address. And when the write signal is input, a write enable signal for permitting the write operation is generated, and when the address signal is determined to be the effective address and the read signal is input, the reading is performed. A read enable signal for permitting an operation is generated, and an access invalid signal for stopping the write operation and the read operation is generated when the address signal is determined to be the invalid address.

  According to this configuration, the determination unit generates the write enable signal, the read enable signal, and the access invalid signal based on the write signal, the read signal, and the address signal.

  According to a fourth aspect of the present invention, there is provided a memory block including a plurality of registers for inputting / outputting data from / to a bus master via a bus, an address decoder for generating a selection signal for selecting a register corresponding to an input address, In the bus system including a plurality of bus slaves configured to include at least one of the plurality of bus slaves, an n-bit address signal input from the bus master via the bus is transmitted to the bus slave. Determining means for determining whether the address in the memory block provided in the memory block is an effective address, or an invalid address not specifying the address in the memory block provided in the bus slave; and Responding to the determination result by the determination means indicating that the address is valid. And outputs a lower address consisting of lower m bits of the address signal to the address decoder, and in the memory block according to a determination result by the determination means indicating that the address signal is the invalid address. And an address decoder control circuit for outputting to the address decoder a stop address consisting of an m-bit address that is not used as the plurality of registers.

  According to a fifth aspect of the present invention, the address decoder control circuit includes a stop address holding circuit that holds a stop address composed of m-bit addresses that are not used as the plurality of registers in the memory block, and the lower address And a selection circuit to which the stop address from the stop address holding circuit is input, the selection circuit according to a determination result by the determination means indicating that the address signal is the effective address The lower address is output to the address decoder, and the stop address is output to the address decoder in accordance with a determination result by the determination means indicating that the address signal is the invalid address.

  According to these configurations, when an invalid address is input, stop addresses that are not used as a plurality of registers in the memory block are always input to the address decoder. Therefore, when invalid addresses are continuously input, the same stop address is continuously input to the address decoder. As a result, address switching in the address decoder when invalid addresses are continuously input can be suppressed, and switching operation in the address decoder can be suppressed. As a result, power consumption by the address decoder when an invalid address is input can be reduced. Note that n is an integer of 2 or more, and m is an integer of 1 or more.

  As described above, according to the present invention, it is possible to provide a semiconductor memory device and a bus system that can reduce power consumption in an address decoder when an invalid address is input.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
As shown in FIG. 1, the bus system 1 includes a bus master 10 and a plurality (three in FIG. 1) of bus slaves 20 a to 20 c that are memory-accessed by the bus master 10. The bus master 10 and the bus slaves 20a to 20c are connected to each other by a common bus BS. The common bus BS includes an address bus AB, a control bus CB, and a data bus DB.

  The bus master 10 is configured by a CPU, a DMAC, and the like. The bus master 10 accesses each of the bus slaves 20a to 20c by memory by outputting an address signal ADD of n + 1 bits (20 bits in this embodiment) to the address bus AB. For example, when the bus master 10 writes the data D1 to the address 11000H in the memory block 21a of the bus slave 20a, the bus master 10 outputs the address signal ADD1 designating the address 11000H to the address bus AB and the write signal WD instructing the write operation. The data is output to the control bus CB, and the write data D1 is output to the data bus DB. For example, when reading data at address 11000H in the memory block 21a of the bus slave 20a, the bus master 10 outputs the address signal ADD1 to the address bus AB, and sends a read signal RD instructing a read operation to the control bus CB. Output. As is well known, “H” indicates that the value is a hexadecimal number, and “B” indicates that the value is a binary number.

  The bus slaves 20a to 20c are semiconductor memory devices each including memory blocks 21a to 21c each including a plurality of registers R mapped to the address space of the common bus BS. The bus slaves 20a to 20c are configured by, for example, a read only memory (ROM), a static random access memory (SRAM), a dynamic random memory (DRAM), a flash memory (FLASH), and the like. In the present embodiment, as shown in FIG. 2, the memory block 21a of the bus slave 20a is mapped to the address space of addresses 10000H to 1FFFFH. The memory block 21b of the bus slave 20b is mapped to the address space of addresses 40000H to 4FFFFH. The memory block 21c of the bus slave 20c is mapped to the address space of addresses 50000H to 5FFFFH.

  After acquiring the bus signals (address signal ADD, control signals WD and RD, write data D) from the bus master 10, the bus slaves 20a to 20c execute processing indicated by the bus signals. For example, when the bus slave 20a acquires the address signal ADD1 (effective address) designating the address 11000H in the memory block 21a of the bus slave 20a, the write signal WD, and the write data D, the write data is written to the address 11000H. Write D. When the bus slave 20a obtains the address signal ADD1 (effective address) for designating the address 11000H in the memory block 21a of the bus slave 20a and the read signal RD, the bus slave 20a reads the data D at the address 11000H and reads the data D The data D is output to the data bus DB.

  On the other hand, when the bus slave 20a acquires an address signal ADD (invalid address) that does not specify an address in the memory block 21a of the bus slave 20a (specifies an address other than the address in the memory block 21a), The switching operation of the address decoder provided inside is stopped.

  FIG. 3 shows the internal configuration of the bus slave 20a. The bus slaves 20b and 20c are accessed by the bus master 10 in the same manner as the bus slave 20a. Accordingly, here, the bus slave 20a will be described as an example to describe the bus slave of the present embodiment.

  As shown in FIG. 3, the bus slave 20a includes the write signal WD or the read signal RD and the upper p bits (in the present embodiment, the upper 4 bits) of the address signal ADD, that is, the upper addresses A16 to A19 (An-p + 1 to An) is provided. The access control circuit 22 compares the input higher addresses A16 to A19 with a preset comparison address AC, and determines whether the address signal ADD is an effective address designating the address in the memory block 21a of the bus slave 20a. Then, it is determined whether the address is an invalid address designating the other bus slaves 20b and 20c. Specifically, since the memory block 21a is mapped to addresses 10000H to 1FFFFH, if the upper addresses A16 to A19 are “0001B”, the address signal ADD becomes an effective address. Therefore, the access control circuit 22 sets the comparison address AC to “0001B” having the same number of bits as the upper address. The access control circuit 22 determines that the address signal ADD is a valid address when the upper addresses A16 to A19 match the comparison address AC, and the address signal when the upper addresses A16 to A19 do not match the comparison address AC. It is determined that ADD is an invalid address.

  The access control circuit 22 determines that the address signal ADD is a valid address, and generates a write enable signal WDB that is 2-bit data (for example, “10”) when the write signal WD is input. The access control circuit 22 determines that the address signal ADD is a valid address, and generates a read enable signal RDB that is 2-bit data (for example, “01”) when the read signal RD is input. When the access control circuit 22 determines that the address signal ADD is an invalid address, the access control circuit 22 generates an access invalid signal AI that is 2-bit data (for example, “00”). Then, the access control circuit 22 outputs the generated write enable signal WDB, read enable signal RDB, or access invalid signal AI to the selector 23 as a selection signal.

  The selector 23 receives lower m (= n−p) bits (lower 16 bits in the present embodiment) of the address signal ADD, that is, lower addresses A0 to A15 (A0 to Am−1). The selector 23 is supplied with a preset stop address SAD from the stop address holding circuit 24. Here, the stop address SAD is a fixed address having the same number of bits (16 bits in this embodiment) as the lower addresses A0 to A15, and is not used as the register R in the memory block 21a of the bus slave 20a. Used address. Further, the stop address SAD may be an unused address that does not exist in the memory block 21a. Note that the stop address SAD of the bus slave 20a in the present embodiment is a fixed address in which all 16 bits are “1”.

  The selector 23 selects one of the lower addresses A0 to A15 from the bus master 10 and the stop address SAD from the stop address holding circuit 24 based on the enable signals WDB and RDB and the access invalid signal AI from the access control circuit 22. select. Specifically, when the write enable signal WDB or the read enable signal RDB is input from the access control circuit 22, the selector 23 selects the lower addresses A0 to A15 from the bus master 10 and holds the lower addresses A0 to A15 as addresses. Output to the register 26. On the other hand, when the access invalid signal AI is input from the access control circuit 22, the selector 23 selects the stop address SAD from the stop address holding circuit 24 and outputs the stop address SAD to the address holding register 26. The selector 23 and the stop address holding circuit 24 constitute an address decoder control circuit 25.

  The address holding register 26 latches the address (lower address A0 to A15 or stop address SAD) input from the selector 23 and outputs the latched address to the address decoder 27.

  The address decoder 27 decodes the address input from the address holding register 26 and generates a selection signal SS or a pseudo selection signal RSS. Specifically, the address decoder 27 decodes the lower addresses A0 to A15 input from the address holding register 26, and outputs a selection signal SS for selecting one register R among the registers R1 to Rk constituting the memory block 21a. Generate. On the other hand, the address decoder 27 decodes the stop address SAD input from the address holding register 26 and generates a pseudo selection signal RSS that does not select any of the registers R1 to Rk.

  The bus slaves 20b and 20c are provided with an access control circuit 22, an address decoder control circuit 25, and an address holding register 26, like the bus slave 20a. In the access control circuit 22 in the bus slave 20b, the upper addresses A16 to A19 are compared with the comparison address AC (0100B). The access control circuit 22 in the bus slave 20c compares the upper addresses A16 to A19 with the comparison address AC (0101B).

Next, write / read operations in the bus system 1 configured as described above will be described with reference to FIG. Here, the operation of the bus slave 20a will be mainly described.
First, the operation of writing the write data D1 to the register R2 in the memory block 21a of the bus slave 20a will be described. Here, it is assumed that the address of the register R2 in the memory block 21a of the bus slave 20a is “11000H”.

  As shown in FIG. 4, the bus master 10 outputs an address signal ADD1 (A0 to A19: 00010001000000000B) designating the address “11000H” to the address bus AB, outputs a write signal WD to the control bus CB, and writes data D1. Is output to the data bus DB (time t1). Then, the upper addresses A16 to A19 (0001B) of the address signal ADD1 and the write signal WD are input to the access control circuit 22 of the bus slave 20a. The access control circuit 22 determines that the address signal ADD1 input from the bus master 10 is a valid address because the upper addresses A16 to A19 match the comparison address AC (0001B). Further, since the write signal WD is input, the access control circuit 22 generates a write enable signal WDB and outputs the write enable signal WDB to the selector 23.

  In response to the write enable signal WDB, the selector 23 supplies lower addresses A0 to A15 input from the bus master 10 to the address decoder 27 through the address holding register 26 (time t2).

  Next, the address decoder 27 decodes the lower addresses A0 to A15 (000100000000B) and generates a selection signal SS for selecting the register R2 (time t3). The address decoder 27 outputs the generated selection signal SS to the memory block 21a, and activates the register R2.

Next, the operation of the bus slave 20a when writing the write data D2 to the address “41000H” in the memory block 21b of the bus slave 20b will be described.
The bus master 10 outputs the address signal ADD2 (A0 to A19: 00001000000000000000000B) designating the address “41000H” to the address bus AB, outputs the write data D2 to the data bus, and outputs the write signal WD to the control bus (time). t4). Then, the upper address A16 to A19 (0100B) of the address signal ADD2 and the write signal WD are input to the access control circuit 22 of the bus slave 20a. The access control circuit 22 determines that the address signal ADD2 input from the bus master 10 is an invalid address because the upper addresses A16 to A19 do not match the comparison address AC (0001B), and generates an access invalid signal AI. . The access control circuit 22 outputs the generated access invalid signal AI to the selector 23.

  In response to the access invalid signal AI, the selector 23 supplies the stop address SAD from the stop address holding circuit 24 to the address decoder 27 through the address holding register 26 (time t5).

  Next, the address decoder 27 decodes the stop address SAD to generate the pseudo selection signal RSS (time t6). As a result, none of the registers R in the memory block 21a is activated.

  Similarly, in the case of processing for designating an address (for example, address signals ADD3, ADD4, ADD5) other than the address in the memory block 21a of the bus slave 20a, the address input to the address decoder 27 is always the stop address. SAD. Therefore, as shown in FIG. 4, when the address signals ADD3, ADD4, and ADD5 for designating addresses other than the addresses in the memory block 21a of the bus slave 20a are continuously input, the address input to the address decoder 27. (Stop address SAD) is not switched. Accordingly, the switching operation in the address decoder 27 is stopped.

Next, an operation of reading data D1 stored in the register R2 in the memory block 21a of the bus slave 20a will be described.
The bus master 10 outputs the address signal ADD1 designating the address “11000H” of the register R2 to the address bus AB, and outputs the read signal RD to the control bus CB (time t7). Then, the upper address A16 to A19 (0001B) of the address signal ADD1 and the read signal RD are input to the access control circuit 22 of the bus slave 20a. The access control circuit 22 generates the read enable signal RDB because the upper addresses A16 to A19 coincide with the comparison address AC (0001B) and the read signal RD is input, and the read enable signal RDB is selected by the selector 23. Output to.

  In response to the read enable signal RDB, the selector 23 supplies the lower addresses A0 to A15 input from the bus master 10 to the address decoder 27 through the address holding register 26 (time t8).

  Next, the address decoder 27 decodes the lower addresses A0 to A15 (0001000000000000B) and generates a selection signal SS for selecting the register R2 (time t9). The address decoder 27 outputs the generated selection signal SS to the memory block 21a, and activates the register R2.

According to this embodiment described above, the following effects can be obtained.
(1) When the bus slaves 20a to 20c determine that the address signal ADD is an invalid address based on the upper address of the address signal ADD, the access slave circuit 22 generates the access invalid signal AI, and the access invalid signal. And a selector 23 for supplying a stop address SAD to the address decoder 27 in accordance with the AI. Thus, the stop address SAD is always input to the address decoder 27 when the address signal ADD is an invalid address. Accordingly, when invalid addresses are continuously input, the same stop address SAD is continuously input to the address decoder 27. As a result, switching of addresses in the address decoder 27 when invalid addresses are continuously input is prevented, so that the switching operation in the address decoder 27 can be stopped. As a result, wasteful power consumption by the address decoder 27 when an invalid address is input can be reduced. As a result, the power consumption of the entire bus system 1 can be reduced.

  (2) An address holding register 26 that holds an address (lower address or stop address SAD) input from the selector 23 is provided between the selector 23 and the address decoder 27. As a result, when the invalid address is continuously input, the stop address SAD is held in the address holding register 26, so that the stop address SAD is reliably supplied continuously to the address decoder 27. Therefore, the switching operation in the address decoder 27 when an invalid address is input can be more reliably suppressed.

In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
The input of the write signal WD and the read signal RD to the access control circuit 22 in the above embodiment may be omitted. At this time, the access control circuit 22 may output a determination result indicating whether the address signal ADD is a valid address or an invalid address to the selector 23 based on the upper address. This determination result may be 1-bit data.

  In the above embodiment, the write enable signal WDB, the read enable signal RDB, and the access invalid signal AI are 2-bit data, but the number of bits is not particularly limited. Further, the logic level is not particularly limited.

In the above embodiment, the address holding register 26 may be omitted.
In the above embodiment, the stop address SAD is all fixed addresses of “1”, but is not particularly limited to this address. The stop address SAD is not particularly limited as long as it is an address that is not used as the plurality of registers R in the corresponding memory block.

There are no particular restrictions on the number of bits of the address signal ADD, upper address, and lower address in the above embodiment.
The bus slaves 20a to 20c in the above embodiments may be different types of semiconductor memory devices. That is, the bus slave 20a may be configured with SRAM, the bus slave 20b may be configured with DRAM, and the bus slave 20c may be configured with FLASH. Note that it is not necessary for all the bus slaves of the bus slaves 20a to 20c to include the access control circuit 22, the address decoder control circuit 25, and the address holding register 26.

  -There is no restriction | limiting in particular in the number of the bus master 10 and the bus slaves 20a-20c in the said embodiment. As the number of bus slaves (memory blocks) increases, the power consumption can be greatly reduced as compared with the conventional bus system.

  The stop address holding circuit 24 in the above embodiment may be omitted. In this case, when the address signal ADD is an invalid address, for example, the selector 23 that operates according to the access invalid signal AI generated by the access control circuit 22 stops the supply of the lower addresses A0 to A15 to the address decoder 27. You can make it.

The block diagram which shows the bus system of this embodiment. The address map of this embodiment. The block diagram which shows the internal structure of the bus slave of this embodiment. The timing chart which shows operation | movement of the bus system of this embodiment. The block diagram which shows the conventional bus system. The block diagram which shows the conventional bus system. The timing chart which shows operation | movement of the conventional bus system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bus system 10 Bus master 20a-20c Bus slave (semiconductor memory device)
21a to 21c Memory block 22 Access control circuit (determination means)
23 Selector (selection circuit)
24 stop address holding circuit 25 address decoder control circuit 26 address holding register (address holding circuit)
27 Address decoder R1-Rk Register BS Common bus

Claims (5)

In a semiconductor memory device comprising: a memory block including a plurality of registers in which data is input / output from a bus master via a bus; and an address decoder that generates a selection signal for selecting a register according to an input address.
Determination means for determining whether an n-bit address signal input from the bus master via the bus is a valid address that specifies an address in the memory block or an invalid address that does not specify an address in the memory block When,
In response to a determination result by the determination means indicating that the address signal is the effective address, a lower address consisting of lower m bits of the address signal is output to the address decoder, and the address signal is invalid An address decoder control circuit for outputting to the address decoder stop addresses composed of m-bit addresses that are not used as the plurality of registers in the memory block in accordance with a determination result by the determination means indicating an address; A semiconductor memory device comprising: The address decoder control circuit includes:
A stop address holding circuit for holding the stop address;
A selection circuit to which the lower address and the stop address from the stop address holding circuit are input,
The semiconductor memory device includes an address holding circuit that is provided between the selection circuit and the address decoder and latches the lower address or the stop address input from the selection circuit,
The selection circuit outputs the lower address to the address holding circuit according to a determination result by the determination unit indicating that the address signal is the effective address, and the address signal is the invalid address. 2. The semiconductor memory device according to claim 1, wherein the stop address is output to the address holding circuit in accordance with a determination result by the determination unit indicating. The determination means receives a write signal for instructing a write operation and a read signal for instructing a read operation,
The determination means includes
When the address signal is determined to be the effective address and the write signal is input, a write enable signal that permits the write operation is generated,
When the address signal is determined as the effective address and the read signal is input, a read enable signal that permits the read operation is generated,
3. The semiconductor memory device according to claim 1, wherein when the address signal is determined to be the invalid address, an access invalid signal for stopping the write operation and the read operation is generated. A bus slave comprising a memory block including a plurality of registers to / from which data is input / output from a bus master, and an address decoder for generating a selection signal for selecting a register corresponding to the input address In a bus system with multiple units,
At least one bus slave among the plurality of bus slaves is:
An n-bit address signal input from the bus master via the bus is an effective address designating an address in the memory block provided in the bus slave, or in the memory block provided in the bus slave. A determination means for determining whether the address is an invalid address without designating an address;
In response to a determination result by the determination means indicating that the address signal is the effective address, a lower address consisting of lower m bits of the address signal is output to the address decoder, and the address signal is invalid An address decoder control circuit for outputting to the address decoder stop addresses composed of m-bit addresses that are not used as the plurality of registers in the memory block in accordance with a determination result by the determination means indicating an address; A bus system comprising: The address decoder control circuit includes:
A stop address holding circuit for holding a stop address consisting of an m-bit address that is not used as the plurality of registers in the memory block;
A selection circuit to which the lower address and the stop address from the stop address holding circuit are input,
The selection circuit outputs the lower address to the address decoder according to a determination result by the determination unit indicating that the address signal is the effective address, and the address signal is the invalid address. 5. The bus system according to claim 4, wherein the stop address is output to the address decoder in accordance with a determination result by the determination means.

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