JP2009047812A - Shift register circuit system and electrooptic device including shift register circuit system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce electric power consumption in a shift register circuit system. <P>SOLUTION: The shift register circuit system includes a shift register circuit section 40 and an output circuit section 32. The voltage amplitude (VH1-VL) of the input signal of the shift register circuit section 40 is set smaller than the voltage amplitude (VH2-VL) of the output circuit section 32 by appropriately setting: the magnitude of respective capacitances of a capacitance element of the poststage included in a boot-strapping circuit 26 of the shift register circuit section 40, a gate capacitance 27 of a transistor in the output circuit section 32 and a parasitic capacitance hanging down from a signal line connecting the capacitance element of the poststage and the output circuit section 32; and the threshold of the transistor of the output circuit section 32. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a shift register circuit system and an electro-optical device including the shift register circuit system, and more particularly to a shift register circuit system including a plurality of transistors having the same conductivity type and an electro-optical device including the shift register circuit system. .

  In an electro-optical device such as an active matrix liquid crystal display device, desired display is performed on each display region arranged in a matrix using a plurality of scanning signal lines and a plurality of data signal lines. A shift register circuit technique is used to sequentially select a plurality of scanning signal lines and to sequentially supply video signals to the plurality of data signal lines. As a shift register circuit technique, for example, a system in which a plurality of data flip-flops and the like are connected in series, driven by a clock signal, and data is sequentially transferred from the previous stage to the subsequent stage is known. Furthermore, a system using a resistance load type inverter circuit as shown in Non-Patent Document 1 is also known.

  Patent Document 1 points out that the shift register circuit using the resistance load type inverter circuit shown in Non-Patent Document 1 consumes a large amount of current, and discloses a configuration that suppresses a through current. Here, as the display device, a first circuit portion having a plurality of transistors that are turned on in response to the first signal and an on-state period that does not overlap with the on-state period of each transistor of the first circuit portion are obtained. And a shift register circuit portion including a second circuit portion having a plurality of transistors turned on in response to two signals.

Masayoshi Kishino, “Basics of Semiconductor Devices”, Ohm Publishing Company, April 25, 1985, p184-187 JP 2006-146091 A

  According to the shift register circuit portion of Patent Document 1, it is possible to configure a shift register circuit that uses an inverter circuit system and suppresses through current and reduces current consumption. Since the output of the shift register circuit is supplied to, for example, the scanning signal line, it is generally adjusted to the voltage amplitude of the scanning signal line. Therefore, when the voltage amplitude of the scanning signal line is large, the voltage amplitude of the shift register circuit is also large, which limits the reduction of power consumption.

  An object of the present invention is to provide a shift register circuit system and an electro-optical device including the shift register circuit system that can further reduce power consumption.

  The shift register circuit system according to the present invention (vertical direction driver circuit 30 or horizontal direction switch circuit 18 constituted by N channel transistors in the embodiment) includes a scanning signal line (Gate Line 1 in the embodiment) and a data signal line. Used in a display device (liquid crystal display device 10 in the embodiment) that performs a desired display on a display region (display region 14 in the embodiment) arranged in a matrix, and selects the scanning signal line or the data signal line. A shift register circuit system for outputting a selection signal (a scanning line selection signal (GateLine1 signal) or a data line selection signal in the embodiment), which is made up of transistors of the same conductivity type, and an input signal (a clock signal in the embodiment) CKV) is a shift signal (in the embodiment) The shift register circuit includes a shift register circuit (in the embodiment, shift register circuits 40 and 61) that outputs Rout1) and an output circuit (in the embodiment, the output circuit unit 32) that outputs the selection signal according to the shift signal. Has a bootstrap circuit (bootstrap circuit 26 in the embodiment) for bootstrapping the shift signal.

  According to this configuration, the voltage amplitude range of the input signal input to the shift register circuit (in the embodiment, the clock signal is a voltage amplitude range between VH1 and VL) is the voltage of the shift signal input to the output circuit. Since the range (in the embodiment, the shift signal is a voltage amplitude range between VH2 + Vth and VL) can be made smaller, the voltage range of the input signal input to the shift register circuit is input to the output circuit unit It may be smaller than the voltage range of the shift signal. Therefore, the shift register circuit unit can be driven at a lower voltage than the output circuit unit, and the power consumption of the shift register circuit system can be further reduced as compared with the case of driving at the same voltage.

  In the shift register circuit system according to the present invention, a plurality of transistors including at least one transistor having the same conductivity type and responding to an input signal are set in advance as a clock signal line (clock signal line CKV in the embodiment). An inverter circuit is configured by connecting in series with a predetermined potential signal line having the predetermined potential VL (in the embodiment, the potential signal line VL), and has a previous stage output node (the previous stage output node ND101 in the embodiment). A plurality of transistors including a pre-stage circuit (pre-stage circuit 63 in the embodiment) and at least one transistor having the conductivity type and responding to a signal of the pre-stage output node are connected to the clock signal line and the predetermined potential signal line. Are connected in series to form an inverter circuit, and a rear output node (the rear output in the embodiment) A post-stage circuit (in the embodiment, the post-stage circuit 65) having the node ND105), a post-stage response transistor (in the embodiment, the output transistor NT104) having the conductivity type and responding to a signal of the post-stage output node, and the pre-stage A pre-stage response transistor (output transistor NT105 in the embodiment) that responds to the signal of the output node is connected between a bootstrap signal line (bootstrap signal line VBP1 in the embodiment) and the predetermined potential signal line; A bootstrap circuit in which a connection point between the front stage response transistor and the rear stage response transistor is used as a connection terminal to the next stage shift register circuit, and a rear stage capacitive element is connected between the rear stage output node and the connection point. A bootstrap circuit 26) The post-stage output unit is connected to the star circuit unit (shift register circuit unit 40 in the embodiment) and the conductive type, and is connected from the rear-stage output node via the output circuit connection wiring (output connection wiring 53 in the embodiment). A plurality of transistors including at least one input-side transistor (in the embodiment, the input-side transistor 52 and NT142) that responds to a node signal include an enable signal line (an enable signal line VEND in the embodiment) and the predetermined potential signal line An output circuit unit (output circuit unit 32 in the embodiment) that outputs the output signal from the output circuit output node, the shift register circuit system comprising: The other side of the voltage amplitude of the input signal including the signal of the clock signal line with respect to VL VH1, the potential of the other side of the voltage amplitude of the input signal including the signal of the enable signal line in the output circuit section with respect to VL is VH2, the parasitic capacitance of the output circuit connection wiring is Ca, VH1 <VH2 and VH1> {(Ca + Cb + Cc) / (Ca + Cb + 2Cc)} × (Vh1 <VH2 and VH1> {(Ca + Cb + Cc)}. VH2 + Vth) is satisfied.

  According to the above configuration, the voltage amplitude (VH1-VL) of the input signal of the shift register circuit unit may be smaller than the voltage amplitude (VH2-VL) of the input signal of the output circuit unit. Since the output signal from the output circuit unit is supplied to, for example, the scanning signal line of the electro-optical device, the voltage amplitude of the input signal of the output circuit unit is limited by the voltage amplitude of the scanning signal line, etc. The voltage amplitude of the input signal of the unit may be sufficient if the signal level of the subsequent output node is sufficient to operate the input side transistor of the output circuit unit. In the above configuration, a condition for operating the input-side transistor of the output circuit unit is obtained from the size of each capacitor that includes the latter-stage capacitive element and hangs from the latter-stage output node, and VL is determined in advance so as to satisfy the condition. VH1 that defines the voltage amplitude of the input signal of the shift register circuit section is determined. Therefore, the voltage amplitude of the input signal of the shift register circuit portion can be made smaller than the voltage amplitude of the input signal of the output circuit portion, and the power consumption of the shift register circuit system can be further reduced as compared with the case where the voltage amplitude is the same.

  In the shift register circuit system according to the present invention, the pre-stage circuit is connected to the clock signal line and connected between the second transistor responding to a second signal and the second transistor and the pre-stage output node. A third transistor in which a gate terminal and a drain terminal are connected to each other, a tenth transistor connected to the predetermined potential signal line and responding to the clock signal, the tenth transistor, and the previous output node A first transistor that responds to a first signal that is the input signal, and a front-stage capacitive element that is connected between the front-stage output node and the predetermined potential signal line, and the rear-stage circuit Is connected to the clock signal line, and responds to the first signal between the seventh transistor, the seventh transistor, and the subsequent output node. An eighth transistor having a gate terminal and a drain terminal connected to each other, and a sixth transistor connected between the predetermined potential signal line and the subsequent output node and responding to a signal from the previous output node Connected to the predetermined potential signal line and connected between the fifth transistor, which is the preceding stage response transistor that responds to the signal of the preceding stage output node, the fifth transistor, and the bootstrap signal line, A fourth transistor that is the latter-stage response transistor responding to a signal at the latter-stage output node, a connection point between the fifth transistor and the fourth transistor, and the latter-stage capacitance element connected between the latter-stage output node; It is preferable to have. Specifically, according to this configuration, the shift register circuit operation can be performed by making the voltage amplitude of the shift register circuit unit smaller than the voltage amplitude of the output circuit unit.

  The electro-optical device according to the present invention is characterized in that the shift register circuit system having the above-described configuration is mounted on an insulating substrate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a shift register circuit system used for sequential scanning of scanning signal lines of a liquid crystal display device will be described as a shift register circuit system, but a shift register circuit used for sequentially supplying video signals to data signal lines of a liquid crystal display device It may be a system. Further, it may be a shift register circuit system used in an electro-optical device other than the liquid crystal display device. For example, an electroluminescence device, a plasma display device, an electrophoretic display device, or a shift register circuit system used in the device using an electron-emitting device may be used. Further, a shift register circuit system used in a circuit device other than the electro-optical device may be used.

  In the following description, a liquid crystal display device is described as a shift register circuit system formed on a glass substrate using low-temperature polysilicon technology, but the shift register circuit system is mounted on an insulating substrate by other methods. Anything to do. For example, a shift register circuit system may be formed on an insulating substrate using high-temperature polysilicon technology. A shift register circuit system may be formed using amorphous silicon technology instead of polysilicon technology. A part, not all of the shift register circuit system, may be formed on an insulating substrate by polysilicon technology or amorphous silicon technology. Alternatively, all or part of the shift register circuit system may be formed on a separate chip and mounted on an insulating substrate of the liquid crystal display device.

  FIG. 1 is a schematic plan view of a liquid crystal display device 10 for active matrix type full color display. The liquid crystal display device 10 uses a glass substrate 12 in which a semiconductor element such as a TFT (Thin Film Transistor) is formed by low-temperature polysilicon technology, and is connected to another glass substrate on which a color filter or the like is formed. Liquid crystal molecules are sandwiched between them.

  In FIG. 1, a liquid crystal display device 10 includes a driver IC 16 including a level shift circuit and a DC / DC converter, a horizontal switch circuit 18 for supplying video signals to a plurality of data signal lines, The charge switch circuit 20 includes a vertical driver circuit 30 that sequentially scans a plurality of scanning signal lines. Here, the driver IC 16 is formed as a separate chip and is mounted on the glass substrate 12 by a so-called COG (Chip On Glass) technique. The horizontal switch circuit 18, the precharge switch circuit 20, and the vertical driver circuit 30 are formed on the glass substrate 12 by the low-temperature polysilicon technique described above. FIG. 1 shows an external signal 22 such as a video signal and its flow. That is, as shown in FIG. 1, the external signal 22 is transmitted to each component according to the purpose via the driver IC 16.

  The active matrix type liquid crystal display device 10 has a matrix of a plurality of scanning signal lines extending in the horizontal direction which is the horizontal direction on the paper surface of FIG. 1 and a plurality of data signal lines extending in the vertical direction which is the vertical direction on the paper surface. The display area 14 is configured by a plurality of pixel areas or the like corresponding to the product of the number of scanning signal lines and the number of data signal lines, with each area partitioned into a pixel area as a pixel area. Then, in order to sequentially supply a video signal to each pixel area constituting the display area 14 to perform a desired display, a plurality of scanning signal lines are sequentially selected in the vertical direction, and a plurality of data signal lines are horizontally selected. A video signal is sequentially supplied. A shift register circuit system is used for each of the vertical scanning and the horizontal scanning.

  Hereinafter, a shift register circuit system used for vertical scanning, that is, a shift register circuit system related to the vertical driver circuit 30 formed on the glass substrate 12 which is an insulating substrate will be described.

  2 to 8 are explanatory diagrams regarding the configuration of the vertical driver circuit 30 and its shift register circuit system. FIG. 2 is a diagram in which repeating units of the vertical direction driver circuit 30 are extracted, FIG. 3 is a diagram showing the voltage level of each input signal, and FIGS. 4 and 5 are diagrams for explaining the operation of the shift register circuit unit. FIGS. 7A and 7B are diagrams for explaining a state in a connection portion between the shift register circuit portion and the output circuit portion. FIG. 8 is a diagram showing the vertical direction driver circuit 30, FIG. 9 is a time chart regarding its operation, and FIG. 10 is a vertical direction driver circuit 30 composed of N channel transistors, whereas FIG. It is a figure which shows the comprised vertical direction driver circuit 31. FIG.

  The vertical driver circuit includes, for example, a shift register circuit having the number of stages corresponding to the number of scanning signal lines and its output circuit, and the basic configuration of the shift register circuit and its output circuit in each stage is the same. FIG. 2 is a diagram showing a repeating unit of the vertical direction driver circuit 30. Here, it is shown that the vertical direction driver circuit 30 uses two stages of the shift register circuit unit 40 and two stages of the output circuit unit 32 as repeating units.

  Here, CSV, XCSV, STV, VBP2, VBP1, CKV, and XCKV are shown as input signals of the shift register circuit section 40, and VENB, XVENB, and SRout (see FIG. 4 and the like) are input signals of the output circuit section 32. It is shown. Detailed contents of each signal will be described later. Here, as shown in FIG. 3, the voltage level of each input signal of the shift register circuit section 40 is VH1 at a high potential and VL at a low potential, whereas the voltage level of each input signal of the output circuit section 32. Is VH2 at a high potential and VL at a low potential. As specific voltage values, in the example of FIG. 3, VH1 is set to + 5.0V, VH2 is set to + 8.0V, and VL is set to -4.5V.

  The voltage level of the output circuit section 32 is the same as the voltage level of the scanning signal line. Here, assuming that the voltage level of the scanning signal line is + 8.0V and −4.5V, VH2 = + 8.0V, VL = It is set to -4.5V. Of course, when the voltage level of the scanning signal line is different from this, the settings of VH2 and VL are also adjusted to that, so these numerical values are an example.

  On the other hand, the voltage level of the shift register circuit unit 40 does not necessarily have to be constrained by the voltage level of the scanning signal line, and therefore may not be the same as the voltage level of the output circuit unit 32.

  However, as shown in FIG. 2, the input to the output circuit unit 32 is performed via the bootstrap circuit 26 of the shift register circuit unit 40. Therefore, the voltage level of the signal supplied to the output circuit unit 32 by the operation of the bootstrap circuit 26 needs to be high enough to operate the output circuit unit 32. The voltage level of the signal supplied to the output circuit unit 32 by the operation of the bootstrap circuit 26 includes, as will be described later, a post-stage capacitance element included in the bootstrap circuit 26, a gate capacitance 27 of the transistor of the output circuit unit 32, It is determined by a parasitic capacitance 28 or the like hanging from a signal line connecting the subsequent-stage capacitive element and the output circuit unit 32.

  Therefore, even if the voltage level of the shift register circuit unit 40 is set lower than the voltage level of the output circuit unit 32 by appropriately setting the size of these capacitors and the threshold value of the transistor of the output circuit unit 32, The output circuit unit 32 can be sufficiently operated. Before describing the details of the contents, the operation of the shift register circuit unit 40, particularly the operation of the bootstrap circuit 26, will be described with reference to FIGS.

  FIG. 4 is a circuit diagram of the shift register circuit section 40. Here, two stages of shift register circuits 61 and 62 are shown.

  In the following description, the N-channel first transistor is indicated as NT1, the second transistor is indicated as NT2, and for example, NT8 is abbreviated as indicating the eighth transistor. In the shift register circuit portion 40 of FIG. 4, the transistors are all the same conductivity type and are N-channel MIS transistors. The MIS transistor is a field effect transistor using an insulating film as a gate film, and an oxide film, a nitride film, a composite insulating film of an oxide film and a nitride film, or the like can be used as the insulating film. In FIG. 4, standard transistors having the same dimensions are represented by one symbol. For example, NT1 indicates that two standard transistors are connected in series. The same applies to NT2, NT6, and NT7. On the other hand, NT4 and NT5 are configured using one standard transistor. NT3 and NT8 are two-terminal elements in which the drain terminal and the gate terminal of the MIS transistor are connected, and are used as resistance elements having diode characteristics. NT8 is used as a resistance element having a diode characteristic in which two standard transistors are connected in series and both gate terminals are connected to one drain terminal.

  In FIG. 4, VL is a potential signal line having a predetermined potential, CKV is a clock signal line for vertical scanning, and VBP1 raises the gate bias of NT4 which is an output transistor to the next stage. RESET is a reset signal line for forcibly resetting the potential of ND1, which is the output node of the preceding circuit, to a predetermined potential. The output node of the pre-stage circuit 63 is ND1, the first input signal to the pre-stage circuit 63 is IN, the second input signal is SRin2, and the shift signal that is the output of the shift register circuit 61 in the post-stage circuit 65 is SRout1, and the post-stage circuit 65 And the output signal to the next-stage shift register circuit 62 is shown as SR1.

  As shown in FIG. 4, the shift register circuit 61 and the shift register circuit 62 constituting the shift register circuit unit 40 use the same transistors and capacitive elements. In the shift register circuit 61, NT2 and NT7 are The difference is that NT12 and NT17 are connected to XCKV and NT14 is connected to VBP2 in the shift register circuit 62, whereas NT4 and VBP1 are connected to CKV. The shift register circuit unit 40 is configured as a whole by sequentially connecting these two types of shift register circuits 61 and 62 in series in the required number of stages.

  The first type shift register circuit 61 in FIG. 4 includes a front-stage circuit 63 and a rear-stage circuit 65. The pre-stage circuit 63 and the post-stage circuit 65 are configured by connecting a plurality of N-channel transistors and capacitive elements as follows.

  To explain using the above-described symbols, symbols, etc., the pre-stage circuit 63 is connected to CKV and connected between NT2 responding to SRin2, NT2 and ND1, and the gate terminal and the drain terminal are mutually connected. NT1 connected to VL, NT10 connected to VL and responding to CKV, connected between NT10 and ND1, NT1 responding to IN, and C1 which is a pre-stage capacitive element connected between NT1 and VL It is comprised.

  Further, the post-stage circuit 65 is connected to CKV, is connected to NT7 responding to IN, is connected between NT7 and SRout1, and is connected between NT8 and VL and SRout1 whose gate terminal and drain terminal are mutually connected. And NT6 responding to the signal of ND1, and further connected to VL, NT5 responding to the signal of ND1, connected between NT5 and VBP1, and NT4 responding to the signal of SRout1. , C2 which is a subsequent capacitive element connected between the connection point of NT5 and NT4 and SRout1, and SR1 is output to the shift register circuit 62 of the next stage from the connection point of NT5 and NT4. Is done.

  As described above, the pre-stage circuit has a plurality of transistors including at least one transistor having the same conductivity type and responding to an input signal, a clock signal line to which the clock signal CKV is supplied, and a predetermined potential VL set in advance. An inverter circuit is configured by connecting in series with a predetermined potential signal line having a pre-stage output node. Further, the post-stage circuit has the same conductivity type as the pre-stage circuit, and includes a plurality of transistors including at least one transistor responding to the signal of the pre-stage output node, a clock signal line to which the clock signal CKV is supplied, and a predetermined signal This circuit is connected in series with a predetermined potential signal line having a potential VL to form an inverter circuit, and has a subsequent output node.

  The next-stage shift register circuit 62 is also configured to include a front-stage circuit 64 and a rear-stage circuit 66. Here, the sign of the N-channel transistor is shown as being +10 to that in the shift register circuit 61. That is, the first transistor is indicated as NT11 and the second transistor is indicated as NT12. For example, NT18 is an eighth transistor. As compared with the shift register circuit 61, the first signal becomes SR1, and as described above, NT12 and NT17 are connected to XCKV, and NT14 is connected to VBP2. Here, XCKV is an inverted signal of CKV, and VBP2 is an inverted signal of VBP1, and is a signal whose phase is shifted by a half cycle of CKV and XCKV from VP1.

  The operation of the shift register circuit unit 40 will be described with reference to the time chart of FIG. In the state before timing a in FIG. 5, CKV is VH1 (H level potential, ie, high potential), XCKV is VL (L level potential, ie, low potential), IN is VL, and SRin2 is VL. Further, ND1 is VH1, assuming that VH1 when last driven by C1 is held. Alternatively, at the time of the first drive, it may be considered that RESET shown in FIG. 4 is set to VH1, ND1 is forcibly set to VH1, and the state is held by C1, in any case ND1 is set to VH1. It is. Note that SR2 that is an output signal of the next stage shift register circuit 62 and an output signal to the next stage is used for SRin2.

  First, the shift register circuit 61 operates as follows. That is, at the timing a, an input signal is input from IN when CKV is in the VL period. When IN is input, NT1 is turned on and NT7 is turned on. Since ND1 is VH1, NT5 and NT6 are on. Here, since CKV is VL and SRin2 is VL, NT2 and NT3 are off in the pre-stage circuit 63, and NT8 is off and NT4 is off in the post-stage circuit 65. Therefore, in both the front-stage circuit 63 and the rear-stage circuit 65, the ON states of the plurality of transistors connected in series do not overlap, and no through current flows.

  Further, NT1 is turned on when IN changes to VH1, but NT10 is turned off, and NT2 and NT3 are also turned off. Therefore, the state of ND1 does not change when IN changes to VH1, and VH1 Maintain state. That is, even if IN changes to VH1, ND1 remains at VH1, so that NT6 connected to VL remains on and SRout1 does not become high impedance. In other words, the off states of the plurality of transistors in the post-stage circuit 65 do not overlap at the same time, and SRout1 does not become high impedance.

  At the timing b, the control signal CKV changes to VH1. This turns on NT10. Since NT1 remains on, ND1 now changes to VL. Therefore, NT5 and NT6 are turned off. However, since CKV becomes VH1, since NT8 is turned on via NT7 that is kept on, SRout1 becomes VH1. Therefore, NT4 is turned on and SR1 is fixed to VL (L level potential) of VBP1. As a result, VH1 (H level potential) and VL (L level potential) are applied to both ends of C2.

  In the state of b, in the front circuit 63, NT1 and NT10 are on, but NT2 and NT3 are off, and in the rear circuit, NT7 and NT8 are on, but NT6 is off, and NT4. Is on but NT5 is off. Therefore, in both the front-stage circuit 63 and the rear-stage circuit 65, the ON states of the plurality of transistors connected in series do not overlap, and no through current flows.

  At timing c, the control signal VBP1 changes to VH1 (H level potential). Therefore, the potential of SRout1, which is the other side of C2, rises to the potential of VH1 + (VH1-VL) through C2. That is, the potential of SRout1 rises because the potential of the bootstrap signal line changes from VL to VH1 at the timings b and c, and thereby a potential higher than the source terminal potential is applied to the gate terminal of NT4. As a result, NT4 can be reliably turned on. As a result, SR1 changes to VH1.

  Thereafter, IN changes to VL before CKV changes to VL next time. Since IN is the first signal and this signal is sequentially shifted, input of the signal to be shifted is completed at this point.

  In c, when SR1 changes to VH1, SR1 as the first signal in the next-stage shift register circuit 62 changes from VL to VH1. Also in the shift register circuit 62, the same operation as described in the timings a to c is performed. Similarly to the rise of SR1 which is the output signal to the next stage of the shift register circuit 61 at the timing c, the output signal to the next stage of the shift register circuit 62 is delayed by a half cycle of XCKV. SR2 rises and is used as SRin2, which is the second signal of the shift register circuit 61. That is, SRin2 rises from VL to VH1.

  Thereafter, at timing d, the control signal VBP1 changes from VH1 to VL. This changes SR1 to VL through NT4. At this time, SRout1 drops through C2 by the amount of the potential increased at the timing c.

  At the timing e, the control signal CKV changes to VH1. Here, since NT2 and NT3 are on, ND1 changes to VH1. As a result, NT5 and NT6 are turned on, so SRout1 changes to VL.

  In this way, SRout1 is output from the shift register circuit 61 as a shift signal in which the IN signal input at the timing a is shifted by a half cycle of CKV. Similarly, SRout2 is output from the shift register circuit 62 as the next shift signal after another half cycle of CKV. In the shift register circuit section 40, the required number of stages of shift register circuits 61 and 62 are connected, and the operation timing of each transistor is controlled as described above. By repeating this, a signal obtained by sequentially shifting the IN signal is obtained. Can be output.

  In FIG. 5, since IN and SRin2 do not overlap with each other in the ON state, and IN and ND1 do not overlap with each other in the ON state, either of the pre-stage circuit 63 and the post-stage circuit 65 of the shift register circuit 61 In FIG. 2, the ON states of the plurality of transistors connected in series do not overlap, and no through current flows. The same applies to the shift register circuit 62.

  Having described the basic configuration and operation of the shift register circuit, the connection relationship between the shift register circuit portion and the output circuit portion will be described next. Below, it demonstrates using the code | symbol and symbol of FIGS. 1-5.

  As described with reference to FIG. 2, the input to the output circuit unit 32 is performed via the bootstrap circuit 26 of the shift register circuit unit 40. FIG. 6 shows the state of the post-stage capacitance element 51 of the bootstrap circuit 26, the input side transistor 52 of the output circuit section 32, and the output connection wiring 53 that connects both of them. In FIG. 6, the parasitic capacitance 28 of the output connection wiring 53 and the gate capacitance 27 of the input side transistor 52 are shown. Here, the output connection wiring 53 is the SRout1 described in relation to FIG. Three capacitors are hung from this SRout1, and for these three capacitors, the capacitance value of the parasitic capacitor 28 is Ca, the capacitance value of the gate capacitor 27 is Cb, and the capacitance value of the subsequent capacitor 51 is Cc. It shall be expressed as

  FIG. 7 shows the potential of the bootstrap signal line (VBP1), the potential of the clock signal line (CKV), and the potential of the output connection wiring 53 (SRout1) corresponding to FIG. The timings b, c, d, e are the timing at which CKV changes from VL to VH1, the timing at which VBP1 changes from VL to VH1, the timing at which VBP1 changes from VH1 to VL, and the CKV, as described in FIG. This is the timing when VH1 changes to VL. Thus, since VBP1 and CKV are input signals of the shift register circuit unit 40, their high potential is VH1, but since the input side transistor 52 belongs to the output circuit unit 32, its high potential is VH2. .

  As already described in detail with reference to FIG. 5, when CKV changes from VL to VH1 at timing c, the potential of SRout1 rises from VL to VH1. Next, when VBP1 changes from VL to VH1 at timing d, SRout1 rises above VH1 due to the action of the post-stage capacitive element 51. The potential of SRout1 is supplied to the gate of the input side transistor 52 of the output circuit section.

  Therefore, if the potential of SRout1 at the timing c is a voltage level sufficient to operate the input side transistor 52, the shift register circuit system operates normally. That is, although the potential level of VH2 is shown by SRout1 in FIG. 7, it is a condition for the shift register circuit system to operate normally that the potential of SRout1 sufficiently exceeds VH2 at timing c. If present, VH1 may be a lower voltage than VH2.

  Returning to FIG. 6 again, looking at the potential relationship of SRout1, three capacitors are associated with SRout1. Then, as described with reference to FIG. 7, at the stage of timing c, the potential of SRout1 is increased to VH1 which is a high potential of CKV, and the potential of the increase due to VH1 which is the high potential of VBP1 by the action of the post-stage capacitive element 51. Is added. Since the potential of the latter is divided by the parasitic capacitor 28 of SRout1 and the gate capacitor 27 of the input side transistor 52, the magnitude thereof is {Cc / (Ca + Cb + Cc)}. When the threshold value of the input side transistor 52 is Vth, the SRout1 potential needs to be (VH2 + Vth) in order to reliably operate the input side transistor 52 with the SRout1 potential.

  From this, it is possible to satisfy VH1 <VH2 in a range of conditions satisfying VH1 × [1+ {Cc / (Ca + Cb + Cc)}]> VH2 + Vth. Alternatively, VH1 can be set to satisfy VH2> VH1> {(Ca + Cb + Cc) / (Ca + Cb + 2Cc)} × (VH2 + Vth) by rewriting this equation.

  As described above, the voltage range (VH1−VL) of the shift register circuit portion can be made smaller than the voltage range (VH2−VL) of the output circuit portion in accordance with the magnitudes of Vth and Cc. One example is VL = −4.5V, VH2 = + 8.0V, and VH1 = + 5.0V as described with reference to FIG.

  The configuration in which the operating voltage range of the shift register circuit portion is smaller than the operating voltage range of the output circuit portion in the shift register circuit has been described above. Next, the overall configuration and operation of the vertical driver circuit will be described.

  FIG. 8 is a circuit diagram showing a vertical direction driver circuit 30 including a shift register circuit unit 40 composed of N-channel transistors. Here, a four-stage shift register circuit portion is shown, but of course, the vertical driver circuit 30 can include the shift register circuit section 40 having a required number of stages.

  The vertical driver circuit 30 includes a shift register circuit unit 40 having the contents described in FIGS. 4 and 5, an input unit 34 to the shift register circuit unit 40, and an output circuit unit 32 from the shift register circuit unit 40. Composed.

  Here, the output circuit section 32 from the shift register circuit section 40 is connected to each scanning signal line in the display area 14 described with reference to FIG. In FIG. 8, a scanning signal line is shown as GateLine. The input unit 34 to the shift register circuit unit 40 is connected to a control circuit unit (not shown). The control circuit unit has a function of controlling the operation timing of the shift register circuit unit 40. For example, the control circuit unit is provided in the external control device of the liquid crystal display device 10, or may be provided in the liquid crystal display device 10 in some cases. it can. Therefore, the control circuit unit and the shift register circuit unit 40 constitute a shift register circuit system.

  In FIG. 8, the reference numerals of the transistors constituting the shift register circuit unit 40 are used from 100. That is, NT101 in FIG. 8 corresponds to NT1 in FIG. 4, and NT102 in FIG. 8 corresponds to NT2 in FIG. The same applies to the following. For example, NT110 in FIG. 8 corresponds to NT10 in FIG.

  In addition, VENB in FIG. 8 is an enable signal that enables the scanning line selection in the vertical direction, and XVENB is an inverted signal of VENB. STV has the same contents as RESET in FIG. CSV is a scanning direction switching signal having a function of setting the scanning direction, which is the shift direction, to the forward direction when VH1 (H level), and the reverse direction to the scanning direction, which is the shift direction, when VL (L level). .

  For example, in FIG. 1, assuming that the direction in which the scanning line selection signal is scanned from the top to the bottom of the paper is the forward direction, the direction of scanning the scanning line selection signal from the bottom to the top of the paper is the reverse direction. is there. Therefore, when the CSV is set to VH1, the shift register circuit unit 40 sequentially shifts and outputs the IN signal in the forward direction, and can sequentially select and scan the scanning lines in the direction from the upper direction to the lower direction on the paper surface of FIG. Further, when it is desired to reverse the sequential selection direction of the scanning lines, the CSV may be set to VL. Note that XCSV in FIG. 6 is an inverted signal of CSV.

  The operation of the vertical driver circuit 30 configured as described above will be described with reference to the time chart of FIG. In FIG. 9, symbols indicating the respective signals are those shown in FIG. 8, and CKV, XCKV, VBP1, VBP2, VENB, and XVENB arranged at the top of FIG. 9 are control signals. As described above, the voltage range of CKV, XCKV, VBP1, and VBP2 is high potential VH1 and low potential is VL, and the voltage range of VENB and XVENB is high potential VH2 and low potential is VL. However, the difference between VH1 and VH2 is omitted on the time chart.

  In FIG. 9, NDxxx (xxx is a three-digit number) arranged below CKV or the like is a state signal of each node of the shift register circuit in each stage. For example, ND1xx is a status signal of each node of the first-stage shift register circuit. For example, ND101 is a status signal of the node ND101 in FIG. 8, and corresponds to the status signal of the previous output node ND1 described in FIG. . ND102 is a state signal of the node ND102 in FIG. 8, and corresponds to the first signal IN in FIG. The ND 103 corresponds to the second signal SRin2. Further, ND 105 corresponds to SRout1 in FIG. 4, and based on this, a signal of GateLine1 is generated. The ND 104 corresponds to SR1 in FIG.

  Therefore, as described in FIG. 4 that SR1 becomes the input of the shift register circuit of the next stage, in FIG. 8, NDn04 (n is a number indicating the number of stages) of each stage is the input signal NDm02 (here, M = n + 1: that is, the next stage) is indicated by a broken line frame and an arrow. In FIG. 4, SRin2 that is the second signal is output signal SR2 of the next stage, and in FIG. 8, NDm04 corresponds to NDn03 by a broken line frame and an arrow. Yes. The same applies hereinafter.

  Hereinafter, the scanning direction that is the shift direction will be described as being representative of the forward direction. That is, a case where the CSV is set to VH1 will be described. Thus, during forward scanning, NT131, NT231, NT331, NT431, etc., and NT121, NT221, NT321, NT421, etc., to which the scanning direction switching signal CSV is input to the gate, are held in the ON state. Also, NT132, NT232, NT332, NT432, etc., and NT122, NT222, NT322, NT422, etc., in which XCSV is input to the gate, are held in the OFF state.

  In the initial state, the potentials of the pre-stage output nodes ND101, ND201, ND301, ND401, etc. of the remarkable shift register circuit are unstable potentials between VH1 and VL. In this state, the start signal STV is input and input to the gates of the reset transistors NT109, NT209, NT309, NT409, and the like. As a result, the reset transistor is turned on, and VH1 is supplied to the node NDn01 (n is the number of stages) via the reset transistor, so that the unstable potential state is eliminated. Then, VL is supplied to the nodes NDn05 and NDn06 via the transistors NTn05 and NTn06. For example, in the first stage, VH1 is forcibly supplied to the ND 105 to cancel the high impedance state, the NT 105 and NT 106 are turned on, and VL is supplied to the nodes ND 105 and ND 106 via the NT 105 and NT 106. This state is a reset initial state and a state before the operation starts.

  Next, the signal VH1 is supplied to the input node ND102 as the rising edge of the input pulse to be shifted. Thereby, NT101 and NT107 are turned on. At this time, the clock signal CKV, which is a control signal, is VL, so that NT110 and NT108 are off. Therefore, the previous-stage output node ND101 holds the initial state VH1 by the action of C101, and the output nodes ND104 and ND105 hold the initial state VL by the action of C102.

  Next, when CKV which is a control signal changes to VH1, since VH1 is input to the gates of NT110 and NT108, NT110 and NT108 are turned on. When NT101 and NT110 are turned on, the previous output node ND101 changes to VL via NT101 and NT110. As a result, NT105 and NT106 are turned off. At the same time, VH1 of CKV which is a control signal is supplied to the subsequent output node ND105 via NT108. Further, when NT 104 is turned on, VL of the bootstrap signal VBP 1 that is a control signal is supplied to the ND 104 that is an output node to the next stage. At this time, VH1 of ND105 and VL of ND104 are applied to both ends of C102.

  Next, when the control signal VBP1 changes to VH1, the ND 104 starts changing to VH1 via the NT104. Along with this change, C102 tries to keep the potential difference between both ends as “VH1−VL”, so that ND105 which is the other terminal of C102 changes to “VH1 + VH1−VL” (bootstrap). effect). In this way, the potential of ND 105 connected to the gate of NT 104 changes to a potential sufficiently higher than VH2. As a result, the NT 104 continues to be in the ON state, and the ND 104 completes the change to VH1 in a sufficiently fast time.

  Thereafter, the ND 104 that is an output node to the next stage transfers a shift pulse to the ND 202 that is an input unit of the next-stage shift register circuit via the NT 232. In FIG. 7, this state is indicated by a broken line frame and an arrow. Note that the shift register circuit of the next stage is of a type that is different from the connection of the first stage shift register circuit, and XCKV and VBP2 are connected as control signals.

  The next-stage shift register circuit operates in the same manner as the previous-stage shift register circuit, and a shift pulse is output from the ND 205 that is the subsequent-stage output node. The ND 204, which is an output node to the next stage, outputs an input signal for the next stage, that is, the third stage shift register circuit, and the output signal is output from the first stage shift register circuit. Two signals are returned to the ND 103 of the first-stage shift register circuit and output. In FIG. 9, this state is indicated by a broken line frame and an arrow.

  When VH1 is supplied to the ND 103 as the second signal, the NT 102 is turned on. At this time, since the control signal CKV is VL, the NT 103 is off.

  Then, when the control signal VBP1 changes to VL, the ND 104 changes to the VL potential via the NT104. At this time, due to the action of C102, the potential of the ND 105 drops by the amount of the rise in potential due to the bootstrap effect.

  Next, when the control signal CKV becomes VH1, NT103 is turned on via NT102, whereby the previous output node ND101 changes to VH1. When ND101 changes to VH1, NT105 and NT106 are turned on.

  Finally, ND103 changes to VL, and NT102 and NT103 are turned off. The pre-stage output node ND101 holds VH1 by the action of C101, whereby the first-stage shift register circuit returns to the initial state before the operation.

  By repeating these operations for the first stage shift register circuit, the second stage shift register circuit, the third stage shift register circuit, the fourth stage shift register circuit, and the target number of stages, the clock signal as the control signal is obtained. The signal can be shifted synchronously. As shown in FIG. 8, the odd-numbered shift register circuits have the same configuration, the even-numbered shift register circuits have the same configuration, and CKV becomes XCKV in the odd-numbered and even-numbered stages as described above. The only difference is that VBP1 becomes VBP2.

  Then, NDn05, which is a subsequent output node of each shift register circuit, is input to the gates of NTn41 and NTn42 in the output circuit section 32 of FIG. 8, and the logical sum of the control signal VENB and the nodes 105 and ND105 is obtained. Is output to GateLine (n).

  The above is the description of the vertical direction driver circuit 30 composed of N-channel transistors, but it can also be composed of P-channel transistors. FIG. 10 is a circuit diagram of the vertical driver circuit 31 composed of P-channel transistors. 8, the vertical driver circuit 31 includes a shift register circuit unit 41 having the contents described in FIGS. 4 and 5, an input unit 35 to the shift register circuit unit 41, and an output from the shift register circuit unit 41. The circuit unit 33 is included. The vertical driver circuit 31 has a configuration in which the potential relationship is changed so as to be suitable for the operation of the P-channel transistor in the configuration in FIG. 8, and the operation is the same as that described in relation to FIG. Detailed description will be omitted.

  Further, the shift register circuit system of the present invention may be employed for the sequential scanning of the data signal lines in the horizontal direction. In this case, the shift register circuit system configured as the horizontal switch circuit 18 is composed of transistors of the same conductivity type and outputs a shift signal according to an input signal, and an output circuit that outputs a selection signal according to the shift signal. The shift register circuit may include a bootstrap circuit that bootstraps a gate bias of a transistor to which the input signal is supplied.

1 is a schematic plan view of a liquid crystal display device according to an embodiment of the present invention. It is a figure which shows the repeating unit of the vertical direction driver circuit system in embodiment which concerns on this invention. In an embodiment concerning the present invention, it is a figure explaining a potential state of each signal. It is a figure which shows the basic composition of the shift register circuit part of embodiment which concerns on this invention. It is a time chart of the shift register circuit part of embodiment which concerns on this invention. FIG. 7 is a diagram for explaining a state of a potential relationship between a connection portion of a shift register circuit portion and an output circuit portion in an embodiment according to the present invention. In an embodiment concerning the present invention, it is a figure explaining a situation of each signal about a connection part of a shift register circuit part and an output circuit part. In an embodiment concerning the present invention, it is a figure showing composition of a vertical direction driver circuit. 4 is a time chart of a vertical driver circuit in the embodiment according to the present invention. In an embodiment concerning the present invention, it is a circuit diagram at the time of comprising a vertical direction driver circuit with a P channel transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Liquid crystal display device, 12 Glass substrate, 14 Display area, 16 Driver IC, 18 Horizontal switch circuit, 20 Precharge switch circuit, 22 External signal, 26 Bootstrap circuit, 27 Gate capacity, 28 Parasitic capacity, 30, 31 Vertical direction driver circuit, 32, 33 Output circuit section, 34, 35 Input section, 40, 41 Shift register circuit section, 51 Subsequent capacitance element, 52 Input side transistor, 53 Output connection wiring, 61, 62 Shift register circuit, 63 , 64 Pre-stage circuit, 65, 66 Sub-stage circuit.

Claims (4)

A shift register circuit system that is used in a display device that performs desired display in a display area arranged in a matrix by scanning signal lines and data signal lines, and that outputs a selection signal for selecting the scanning signal lines or data signal lines. And
A shift register circuit that is composed of transistors of the same conductivity type and outputs a shift signal according to an input signal, and an output circuit that outputs the selection signal according to the shift signal,
The shift register circuit system, wherein the shift register circuit includes a bootstrap circuit that bootstraps the shift signal. A plurality of transistors having the same conductivity type and including at least one transistor responding to an input signal are connected in series between a clock signal line and a predetermined potential signal line having a predetermined predetermined potential VL. A pre-stage circuit that constitutes a circuit and has a pre-stage output node;
A plurality of transistors having the conductivity type and including at least one transistor responding to a signal at the preceding output node are connected in series between the clock signal line and the predetermined potential signal line to constitute an inverter circuit. A post-stage circuit having a post-stage output node;
A post-stage response transistor having the conductivity type and responding to the signal of the post-stage output node and a pre-stage response transistor responding to the signal of the pre-stage output node are interposed between the bootstrap signal line and the predetermined potential signal line. A bootstrap circuit in which a connection point between the preceding stage response transistor and the subsequent stage response transistor is used as a connection terminal to a next stage shift register circuit, and a subsequent stage capacitive element is connected between the subsequent stage output node and the connection point. When,
A shift register circuit unit including
A plurality of transistors including at least one input side transistor having the conductivity type and connected from the subsequent-stage output node via an output circuit connection wiring and responding to a signal of the subsequent-stage output node include an enable signal line and the predetermined potential signal An output circuit unit that is connected in series with the line and outputs an output signal from the output circuit output node;
A shift register circuit system comprising:
The voltage amplitude of the input signal including the signal of the enable signal line in the output circuit unit is set to VH1 on the other side of the voltage amplitude of the input signal including the signal of the clock signal line in the shift register circuit unit with respect to VL. VH2 is a potential on the other side of the VL, Ca is a parasitic capacitance of the output circuit connection wiring, Cb is a gate capacitance of the input-side transistor, Cc is a capacitance value of the subsequent capacitive element, and A shift register circuit system satisfying a relationship of VH1 <VH2 and VH1> {(Ca + Cb + Cc) / (Ca + Cb + 2Cc)} × (VH2 + Vth) where a threshold voltage of the transistor is Vth. The shift register circuit system according to claim 2,
The preceding circuit is
A second transistor connected to the clock signal line and responsive to a second signal;
A third transistor connected between the second transistor and the previous output node and having a gate terminal and a drain terminal connected to each other;
A tenth transistor connected to the predetermined potential signal line and responsive to the clock signal;
A first transistor connected between the tenth transistor and the previous output node and responsive to a first signal as the input signal;
A pre-stage capacitive element connected between the pre-stage output node and the predetermined potential signal line;
Have
The latter circuit is
A seventh transistor connected to the clock signal line and responsive to the first signal;
An eighth transistor connected between the seventh transistor and the subsequent output node and having a gate terminal and a drain terminal connected to each other;
A sixth transistor connected between the predetermined potential signal line and the subsequent output node and responding to a signal of the previous output node;
A fifth transistor that is connected to the predetermined potential signal line and that responds to a signal at the preceding output node and is the preceding response transistor;
A fourth transistor that is connected between the fifth transistor and the bootstrap signal line and that is the post-stage response transistor that responds to a signal of the post-stage output node;
The latter-stage capacitive element connected between a connection point between the fifth transistor and the fourth transistor and the latter-stage output node;
A shift register circuit system comprising:   4. An electro-optical device, wherein the shift register circuit system according to claim 1 is mounted on an insulating substrate.

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