JP2009047486A - Semiconductor package inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package inspection method which can perform a test on the wiring between semiconductor chips by a simple method. <P>SOLUTION: An SW and an FF are arranged between an internal circuit and an external terminal of a first semiconductor chip, while an SW and an FF are arranged between an internal circuit and an external terminal of a second semiconductor chip. After writing data on the FF arranged on the first semiconductor chip and the FF arranged on the second semiconductor chip, the first semiconductor chip and the second semiconductor chip are driven. After shifting data between the FF arranged on the first semiconductor chip and the FF arranged on the second semiconductor chip, the shifted data are read and are compared to an expected value. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor package inspection method. Specifically, the present invention relates to a method for inspecting a semiconductor package configured by integrally sealing two or more semiconductor chips.

  In recent years, large-scale integrated circuits (LSIs) have shifted not only to digital systems but also to systems on chip (SOC) in which all systems including analog systems are mounted on a single semiconductor chip. This is a factor in promoting downsizing and high performance of various electronic devices.

  Furthermore, with the miniaturization of the CMOS process, high-density mounting and low voltage are required. Under such circumstances, in a semiconductor chip in which a digital system and an analog system are mixed, the digital portion is high. Although it is possible to meet demands such as density mounting and lower voltage, the analog part has to be limited in its functions by lowering the voltage.

  SIP (system on package) technology has been proposed to cope with such analog performance degradation problems. Specifically, the analog part (analog chip) is developed using a stable process that is not subject to low voltage restrictions, and the large-scale logic part (digital chip) is developed using a miniaturization process with high density. By embedding a chip in one semiconductor package, a high-performance digital / analog semiconductor package is realized.

  By the way, a boundary scan test method called a JTAG test has been developed as a test method for a substrate on which a plurality of semiconductor chips are mounted. In recent years, most microprocessors are compatible with this boundary scan test. Some have come to support it. The boundary scan test is a method for checking whether or not the external terminals of the semiconductor chip and LSI package device mounted on the substrate are definitely connected by sending a signal from a tester such as a host computer outside the substrate.

  Here, the device corresponding to the boundary scan test is configured as shown in FIG. 6, for example. In addition to the core logic 101 that realizes the original function of the device, a boundary scan register (BSR) 102, an instruction register 103, a bypass register 104, an option register 105, a test access port (TAP) 106 for controlling them, a controller (TAPC) 107 for controlling TAP, and the like.

  The TAP 106 described above is a serial interface for inputting / outputting instructions, data, and test results to / from the core logic 101, and is composed of five signal lines TDI, TDO, TCK, TMS, and TRST in accordance with the boundary scan test standard. ing.

  The BSR 102 described above is formed by connecting a series of shift registers 102 s called cells that are interposed between the input / output terminals of the core logic 101 and the corresponding external terminals 108. The lines TDI, TDO and the input / output terminals of the core logic 101 are connected. Further, a bypass register 104, an instruction register 103, and an option register 105 are interposed in parallel between the signal lines TDI and TDO.

  The TDI described above is a signal line for serially inputting commands and data to the core logic 101, TDO is a signal line for serially outputting data from the core logic 101, and TCK is specific to the core logic 101. A signal line for supplying a test clock independent of the system clock, TMS is a signal line for controlling a test operation, and TRST is a signal line for asynchronously initializing TAPC. A boundary scan test can be performed by controlling these five signal lines with an external host computer.

  The contents of the boundary scan test are disclosed in Non-Patent Document 1 and Patent Document 1.

  FIG. 7 is a schematic diagram for explaining the method of the boundary scan test. A plurality of devices IC1, IC2,..., ICn (hereinafter collectively referred to as “IC”) are formed on the printed circuit board 111 to be tested. The connector 112 is mounted on the edge of the printed circuit board 111, and the host computer 113 is connected to the connector 112.

  In each device IC, the external terminals corresponding to the signal lines TCK, TMS, and TRST described above are connected to the external terminals corresponding to the connector 112 in parallel with each other through a pattern formed on the printed circuit board 111. On the other hand, the external terminals corresponding to the signal lines TDI, TDO are connected in cascade to the external terminals corresponding to the signal line TDI of the device on the subsequent stage, and the external terminals corresponding to the signal line TDI of the device on the subsequent stage are sequentially connected. The external terminal corresponding to the signal line TDI of the first stage device and the external terminal corresponding to the signal line TDO of the final stage device are connected to the corresponding external terminal of the connector 112.

  In the printed circuit board 111 configured as described above, the host computer 113 controls each device IC, whereby the boundary scan test is performed on all the device ICs simultaneously. The function test unique to each device IC is sequentially performed individually for each device IC using an external terminal different from the above-described external terminal.

  Now, in conducting a wiring test between semiconductor chips in a semiconductor package having a plurality of semiconductor chips, conventionally, the semiconductor package is inspected by mounting the above-described boundary scan.

JTAG Test Basics and Applications, December 1, 1998, CQ Publisher JP-A-5-322988

However, when the boundary scan is implemented to enable the boundary scan test, five signal lines are required for each chip, the number of external terminals is increased, and only the wiring test between the semiconductor chips is involved. First, since it is necessary to interpose the BSR between the external terminal irrelevant to the wiring test between the semiconductor chips and the core logic, the result is an increase in the area of the semiconductor chip.
It should be noted that the increase in the number of external terminals and unnecessary BSR arrangement are very serious problems for analog chips that are inherently small in chip size, even if they are minor problems for large-scale chips (logic chips). It can be said that there is.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor package inspection method capable of performing a wiring test between semiconductor chips by a simple method.

  In order to achieve the above object, according to a semiconductor package inspection method of the present invention, a first semiconductor chip provided with a first external terminal and a second external terminal connected to the first external terminal , A first memory element disposed between the internal circuit of the first semiconductor chip and the first external terminal, and the internal circuit of the second semiconductor chip And a second memory element disposed between the first external memory terminal and the second external terminal, wherein predetermined data is written to the first memory element and the second memory element Driving the first semiconductor chip and the second semiconductor chip in a state where the first memory element and the second memory element corresponding to the first memory element are connected to each other; And the first storage element. A step of transferring data between the corresponding storage element and the corresponding second storage element; and after driving the first semiconductor chip and the second semiconductor chip, the first storage element and the second storage element And a step of reading data written in the second memory element.

  Here, predetermined data is written to the first memory element and the second memory element, and the first memory element and the second memory element corresponding to the first memory element are connected to each other. By driving one semiconductor chip and the second semiconductor chip, data is transferred between the first memory element and the second memory element corresponding to the first memory element, and then, After driving the first semiconductor chip and the second semiconductor chip, the data written in the first memory element and the second memory element are read out, whereby the first semiconductor chip, the second semiconductor chip, The data is transferred from the first storage element or the second storage element that is the data transmission source to the first storage element or the second storage element that is the data transmission destination via the interchip wiring. To be done The data written in the first storage element or the second storage element that is the data transmission source is compared with the data read from the first storage element or the second storage element that is the data transmission destination. As a result, the inter-chip wiring test between the first semiconductor chip and the second semiconductor chip can be performed.

Here, by writing predetermined data to the first memory element and the second memory element in a state where all the first memory elements and all the second memory elements are connected in series, the data writing operation is performed. It can be done efficiently.
Similarly, data is read by reading data written in the first memory element and the second memory element in a state where all the first memory elements and all the second memory elements are connected in series. Work can be performed efficiently.

  In the semiconductor package inspection method to which the present invention is applied, it is not necessary to make a difficult setting unlike the boundary scan test, and a wiring test between semiconductor chips can be realized by an extremely simple method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
In the following embodiments, a signal is sent from the first wiring L1 to the first wiring M1, a signal is sent from the second wiring L2 to the second wiring M2, and the third wiring L3 A signal is sent to the third wiring M3, a signal is sent from the fourth wiring M4 to the fourth wiring L4, a signal is sent from the fifth wiring M5 to the fifth wiring L5, and the sixth wiring M4 is sent. A semiconductor package in which a signal is sent from the wiring M6 to the sixth wiring L6 will be described as an example.

  FIG. 1 is a schematic view for explaining a semiconductor package inspection method to which the present invention is applied. In the semiconductor package shown here, a first semiconductor chip 1 and a second semiconductor chip 2 are integrally sealed. The first semiconductor chip includes a first wiring L1, a second wiring L2, a third wiring L3, a fourth wiring L4, a fifth wiring L5, and a sixth wiring connected to the internal circuit 3. A wiring L6 is formed, the first wiring L1 is configured to be connected to the outside via the Tristate terminal 4, and the second wiring L2 is connected to the outside via the second external terminal 5. The third wiring L3 is configured to be connected to the outside via the third external terminal 6, and the fourth wiring L4 is connected to the outside via the fourth external terminal 7. The fifth wiring L5 is externally connected via the fifth external terminal 8. Is constructed as to be connected to the, the sixth wiring L6 are configured as to be connected to the outside via the external terminal 9 of the sixth.

  Similarly, the second semiconductor chip includes a first wiring M1, a second wiring M2, a third wiring M3, a fourth wiring M4, a fifth wiring M5, and a sixth wiring connected to the internal circuit 10. A wiring M6 is formed, the first wiring M1 is configured to be connected to the outside via the first external terminal 11, and the second wiring M2 is connected to the outside via the second external terminal 12. The third wiring M3 is configured to be connected to the outside via the third external terminal 13, and the fourth wiring M4 is connected to the outside via the fourth external terminal 14. The fifth wiring M5 is configured to be connected to the outside via the fifth external terminal 15, and the sixth wiring M6 is connected to the outside via the sixth external terminal 16. It is configured to be connected.

  Then, the Tristate terminal 4 and the first external terminal 11 are connected by wiring, whereby the first wiring L1 and the first wiring M1 are connected, and the second external terminal 5 and the second external terminal are connected. The second wiring L2 and the second wiring M2 are connected by connecting the terminal 12 to the wiring, and the third external terminal 6 and the third external terminal 13 are connected by wiring. The third wiring L3 and the third wiring M3 are connected, and the fourth external terminal 7 and the fourth external terminal 14 are connected by wiring, whereby the fourth wiring L4 and the fourth wiring M4 are connected. Are connected, and the fifth external terminal 8 and the fifth external terminal 15 are connected to each other, whereby the fifth wiring L5 and the fifth wiring M5 are connected, and the sixth external terminal 9 and the sixth external terminal 16 are connected to each other by wiring. Wiring L6 and the wiring M6 of the sixth is connected.

  In the first semiconductor chip, a switch circuit (hereinafter referred to as “switch circuit” will be referred to as SW) 17 and a flip-flop circuit (hereinafter referred to as “flip-flop”) in this order from the internal circuit side between the internal circuit 3 and the Tristate terminal 4. ”Is shown as FF.) 18 is arranged, and SW 19 and FF 20 are arranged in this order from the internal circuit side between the internal circuit 3 and the second external terminal 5, and the internal circuit 3 and the third external terminal 6. SW21 and FF22 are arranged in this order from the internal circuit side, and FF23 and SW24 are arranged in order from the internal circuit side between the internal circuit 3 and the fourth external terminal 7, and the internal circuit 3 and the fifth external terminal are arranged. FFs 25 and SW 26 are sequentially arranged between the terminal 8 and the internal circuit side, and an FF 27 is disposed between the internal circuit 3 and the sixth external terminal 9.

  Further, in the second semiconductor chip, the FF 28 is disposed between the internal circuit 10 and the first external terminal 11, and the FF 29 is sequentially disposed between the internal circuit 10 and the second external terminal 12 from the internal circuit side. , SW 30 are arranged, FF 31 and SW 32 are arranged in order from the internal circuit side between the internal circuit 10 and the third external terminal 13, and the internal circuit is arranged between the internal circuit 10 and the fourth external terminal 14. SW33 and FF34 are arranged in this order from the side, and SW35 and FF36 are arranged in order from the internal circuit side between the internal circuit 10 and the fifth external terminal 15, and between the internal circuit 10 and the sixth external terminal 16. SW37 and FF38 are arranged in this order from the internal circuit side.

  Here, the SW 17 is configured to output the output signal from the internal circuit 3 and the output signal from the FF 20 as an input signal and output either one of the input signals as an output signal. An output signal from the FF 22 is used as an input signal, and either one of the input signals is output as an output signal. The SW 21 uses the output signal from the internal circuit 3 and the output signal from the FF 23 as input signals, and the input signal Either one is configured to output as an output signal, and the SW 24 receives an input signal from the fourth external terminal 7 and an output signal from the FF 25 as an input signal, and outputs either one of the input signals as an output signal. The SW 26 uses the input signal from the fifth external terminal 8 and the output signal from the FF 27 as an input signal, and either one of the input signals as an output signal. And it is configured so as to output.

  The SW 30 is configured to output the input signal from the second external terminal 12 and the output signal from the FF 28 as an input signal, and output one of the input signals as an output signal. The SW 32 is configured to output the third external terminal 13. The input signal from FF29 and the output signal from FF29 are input signals, and either one of the input signals is output as an output signal. SW33 is configured to output the output signal from internal circuit 10 and the output signal from FF31 as input signals. The SW 35 is configured to output one of the input signals as an output signal, and the SW 35 outputs the output signal from the internal circuit 10 and the output signal from the FF 34 as an input signal, and outputs either one of the input signals as an output signal. The SW 37 receives the output signal from the internal circuit 10 and the output signal from the FF 36 as input signals, and outputs either one of the input signals. And it is configured so as to output as the issue.

  The Tristate terminal 4 is configured to be switched between a normal state and a high impedance state (high resistance state) by a switching signal input from the Tristate switching terminal 39, and each SW is a switching input from the SW switching terminal 40. Depending on the signal, which of the two input signals is selected as the output signal can be switched. Further, the inter-chip wiring N1 that connects the first wiring L1 and the first wiring M1 is connected to the data input and data observation terminal 41, and supplies data to the wiring N1 from the data input and data observation terminal. In addition, the data passing through the wiring N1 can be observed at the data input and data observation terminal.

Hereinafter, a method for inspecting the semiconductor package configured as described above will be described. That is, a semiconductor package inspection method to which the present invention is applied will be described.
In the semiconductor package inspection method to which the present invention is applied, first, by inputting a switching signal from the SW switching means 40, the SW 17 uses the output signal from the FF 20 as an output signal, and the SW 19 uses the output signal from the FF 22 as an output signal. , SW21 is the output signal from FF23, SW24 is the output signal from FF25, SW26 is the output signal from FF27, SW30 is the output signal from FF28, and SW32 Is set so that the output signal from FF29 is the output signal, SW33 is the output signal from FF31, SW35 is the output signal from FF34, and SW37 is the output signal from FF36. To do. Further, the Tristate terminal 4 is set to a high impedance state (high resistance state) by inputting a switching signal from the Tristate switching means 39.

In this state, data is written from the data input / data observation terminal 41 to each FF.
Specifically, for example, data such as “111000111000” is input from the data input and data observation terminal 41, and the input data is FF28, FF29, FF31, FF34, FF36, FF38, FF27, FF25, FF23, FF22, FF20. , FF18 are sent in this order, and as shown in FIG. 2, FF18 is data 1, FF20 is data 1, FF22 is data 1, FF23 is data 0, FF25 is data 0, FF27 is data 0, data 1 is written in FF38, data 1 is written in FF36, data 1 is written in FF34, data 0 is written in FF31, data 0 is written in FF29, and data 0 is written in FF28.

  Next, by inputting a switching signal from the SW switching means 40, SW17 uses the output signal from the internal circuit 3 as an output signal, SW19 uses the output signal from the internal circuit 3 as an output signal, and SW21 from the internal circuit 3 Are output signals, SW24 is an input signal from the fourth external terminal 7, SW26 is an input signal from the fifth external terminal 8, and SW30 is the second external terminal 12. Is an output signal, SW32 is an input signal from the third external terminal 13, SW33 is an output signal from the internal circuit 10, and SW35 is an output signal from the internal circuit 10. The output signal is set so that the SW 37 uses the output signal from the internal circuit 10 as the output signal. Further, by inputting a switching signal from the Tristate switching means 39, the Tristate terminal 4 is set to the normal state (see FIG. 3).

  Subsequently, the first semiconductor chip and the second semiconductor chip are driven to shift the data written to each FF, that is, the data written to the FF 18 is shifted to the FF 28, and the data written to the FF 20 is shifted. Is shifted to FF29, the data written to FF22 is shifted to FF31, the data written to FF34 is shifted to FF23, the data written to FF36 is shifted to FF25, and the data written to FF38 is shifted to FF27. Shift to. At this time, data from the internal circuit 3 is shifted to FF18, FF20, and FF22, and data from the internal circuit 10 is shifted to FF34, FF36, and FF38.

Specifically, data 1 is shifted from FF18 to FF28, data 1 is shifted from FF20 to FF29, data 1 is shifted from FF22 to FF31, data 1 is shifted from FF34 to FF23, and data is transferred from FF36 to FF25. 1 is shifted, and data 1 is shifted from FF38 to FF27 (see FIG. 4). Here, in FIG. 4, since the data shifted from the internal circuit is indefinite, the data shifted to FF18, FF20, FF22, FF34, FF36, and FF38 is indicated as “X”.
FIG. 4 shows data when the wiring between semiconductor chips is normal. That is, data 1 is normally shifted from FF18 to FF28, data1 is normally shifted from FF20 to FF29, data1 is normally shifted from FF22 to FF31, and data1 is normally shifted from FF34 to FF23, In this example, data 1 is normally shifted from FF 36 to FF 25 and data 1 is normally shifted from FF 38 to FF 27.

  Subsequently, by inputting a switching signal from the SW switching means 40, SW17 uses the output signal from FF20 as an output signal, SW19 uses the output signal from FF22 as an output signal, and SW21 outputs the output signal from FF23 as an output signal. SW24 is the output signal from FF25, SW26 is the output signal from FF27, SW30 is the output signal from FF28, SW32 is the output signal from FF29, SW33 is set so that the output signal from FF31 is an output signal, SW35 is an output signal from FF34, and SW37 is an output signal from FF36.

  In this state, data is shifted, and data written in each FF is read by the data input and data observation terminal 41. Specifically, FF18 data, FF20 data, FF22 data, FF23 data, FF25 data, FF27 data, FF38 data, FF36 data, FF34 data, FF31 data, FF29 data, FF28 Data is read in the order of the data (see FIG. 5).

  Thereafter, a wiring test between semiconductor chips can be performed by comparing the read data with an expected value. Specifically, when the read data is “XXX111XXX111”, the data is normally shifted from FF18 to FF28, the data is normally shifted from FF20 to FF29, and the data is normally shifted from FF22 to FF31. Thus, data is normally shifted from FF34 to FF23, data is normally shifted from FF36 to FF25, and data is normally shifted from FF38 to FF27.

In the above method, only data 1 is confirmed to be normally shifted, and it is not clear whether data 0 can be normally shifted.
Therefore, when testing whether data 0 is also shifted or not, by inputting data such as “000111000111” from the data input and data observation terminal 41, a flow similar to the flow described above is executed. It can be confirmed whether or not data 0 can be shifted normally.

In the semiconductor package inspection method to which the present invention is applied, a wiring test between semiconductor chips can be realized only by mounting a very simple test circuit without mounting a boundary scan.
Specifically, when performing a boundary scan test, it is necessary to form five terminals (TDI, TDO, TCK, TMS, TRST), whereas in the semiconductor package inspection method to which the present invention is applied, Since three terminals (Tristate switching terminal, SW switching terminal, data input and data observation terminal) need only be formed, the number of terminals can be reduced, and all of the semiconductor chips can be used for the boundary scan test. However, in the semiconductor package inspection method to which the present invention is applied, if FFs and SWs are formed only on the wiring for transferring data between the semiconductor chips, the BSR needs to be arranged corresponding to the external terminals of the semiconductor chip. It is possible to realize a test between semiconductor chips simply by mounting a very simple test circuit. That.

Further, since the wiring test can be realized with a very simple test circuit, the semiconductor package can be downsized.
Although the reduction in the number of terminals and the need to form a large number of BSRs are minor improvements for large-scale chips (logic chips), the effect is large for analog chips originally having a small chip size. For a semiconductor package including an analog chip, the degree of influence of miniaturization is particularly large.

Furthermore, in the semiconductor package inspection method to which the present invention is applied, since the test method is extremely easy, the semiconductor package can be inspected even by a semiconductor chip designer.
Specifically, when the boundary scan test is performed, the logic chip designer needs to refer to the circuit, so only the logic chip designer can perform the wiring test between the semiconductor chips. On the other hand, in the semiconductor package inspection method to which the present invention is applied, it is not necessary to activate the logic chip circuit as long as the wiring for transferring data between the semiconductor chips is known. Even if it is not a person, the wiring test between semiconductor chips can be performed.

It is a schematic diagram (1) for demonstrating the inspection method of the semiconductor package to which this invention is applied. It is a schematic diagram (2) for demonstrating the inspection method of the semiconductor package to which this invention is applied. It is a schematic diagram (3) for demonstrating the inspection method of the semiconductor package to which this invention is applied. It is a schematic diagram (4) for demonstrating the inspection method of the semiconductor package to which this invention is applied. It is a schematic diagram (5) for demonstrating the inspection method of the semiconductor package to which this invention is applied. It is a schematic diagram for demonstrating the device corresponding to a boundary scan test. It is a schematic diagram for demonstrating the method of a boundary scan test.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor chip 2 2nd semiconductor chip 3 Internal circuit 4 Tristate terminal 5 2nd external terminal 6 3rd external terminal 7 4th external terminal 8 5th external terminal 9 6th external terminal 10 Inside Circuit 11 1st external terminal 12 2nd external terminal 13 3rd external terminal 14 4th external terminal 15 5th external terminal 16 6th external terminal 17, 19, 21, 24, 26, 30, 32 , 35, 37 Switch circuit 18, 20, 22, 24, 25, 27, 28, 29, 31, 34, 36, 38 Flip-flop circuit 39 Tristate switching terminal 40 SW switching terminal 41 Data input and data observation terminal

Claims (3)

A first semiconductor chip provided with a first external terminal;
A second semiconductor chip provided with a second external terminal connected to the first external terminal;
A first memory element disposed between an internal circuit of the first semiconductor chip and the first external terminal;
A method for inspecting a semiconductor package comprising a second memory element disposed between an internal circuit of the second semiconductor chip and the second external terminal,
Writing predetermined data in the first memory element and the second memory element;
By driving the first semiconductor chip and the second semiconductor chip in a state where the first memory element and the second memory element corresponding to the first memory element are connected, Passing data between the first memory element and the second memory element corresponding to the first memory element;
And a step of reading data written in the first memory element and the second memory element after driving the first semiconductor chip and the second semiconductor chip. The step of writing predetermined data in the first memory element and the second memory element is performed in a state where all the first memory elements and all the second memory elements are connected in series. The inspection method of the semiconductor package of description. The step of reading data written in the first storage element and the second storage element is performed in a state where all the first storage elements and all the second storage elements are connected in series. The inspection method of the semiconductor package of 1.

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