JP2009043742A - Planar imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a planar imaging element of a photoconduction type, with deterioration in after images or in resolution, or voids reduced. <P>SOLUTION: The planar image element of a photoconduction type is provided with a photoelectric conversion part, having a structure with a transparent electrode and a photoelectric conversion film laminated on a translucent substrate; electron emission sources arranged into a matrix form, in correspondence with each pixel of a scanning region of the photoelectric conversion part; belt-like cathode electrodes electrically connected to the electron emission sources; and an electron source with belt-like gate electrodes, arrayed to cross the cathode electrodes via an insulating layer. The electron emission sources simultaneously emit electrons and sweep out the residual charges, as the capacitative load of the corresponding pixel is read-out as a time-series signal, during pixel selection period contained in a line read-out period; and at the same time, as voltage is impressed on the cathode electrodes and the gate electrodes of all the electron emission sources, corresponding to the pixels reading out the time-series signal of the line read-out period during the given period in a horizontal blanking period, immediately after the line read-out period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a photoconductive planar imaging device, and more particularly to a planar imaging device that captures a moving image by converting two-dimensional image information into a time-series electrical signal.

  In recent years, semiconductor microfabrication technology has progressed, and it has become possible to manufacture minute devices, which has greatly contributed to the development of vacuum microelectronics technology.

  One type of device in which such microfabrication technology is utilized is a field emission electron source (hereinafter simply referred to as an electron source).

The electron source is a phenomenon in which when the electric field applied to the surface of a conductor or semiconductor is increased to about 10 ⁸ to 10 ⁹ (V / m), electrons are emitted into the vacuum through the barrier by the tunnel effect. It is used. This electron source is attracting attention for its application to flat image sensors as well as to flat display elements.

  In order to increase the definition of an image obtained when an electron source is applied to a planar imaging device, miniaturization of the opening of the anode (gate electrode) and the cathode (cathode electrode) of the electron source has been studied. In addition, in order to widen the image dynamic range, the sharpening of the cathode tip and the production of a cathode using a high-efficiency cathode material are being studied.

  For example, in the photoconductive type planar imaging device including the conventional electron source 1 and the photoelectric conversion unit 2 shown in FIG. 1, the electron source 1 is a so-called Spindt type, and a cathode electrode 1b is provided on a substrate 1a. An insulating layer 1c is provided on the electrode 1b. A pore 1d is formed in the insulating layer 1c, and a minute electron emission source (emitter) 1e protruding from the cathode electrode 1b is provided in the pore 1d. A gate electrode 1f is provided on the insulating layer 1c. The cathode electrode 1b and the gate electrode 1f are arranged in directions orthogonal to each other to form an XY matrix. Then, by driving the cathode electrode 1b and the gate electrode 1f in a matrix, the electron emission source 1e at the intersection can be selected and electrons can be emitted.

  A photoelectric conversion unit 2 is provided facing the electron source 1. The photoelectric conversion unit 2 includes a translucent substrate 2a, a translucent conductive film (transparent electrode) 2b and a photoelectric conversion film 2c laminated on the translucent substrate 2a. Light from the outside enters the photoelectric conversion film 2c through the translucent substrate 2a and the translucent conductor film 2b.

  In the above planar imaging device, the photoelectric conversion film 2c generates and accumulates charges according to the amount of incident light, and reads the charges to the external circuit in time series by the electron beam emitted from the electron emission source 1e. At this time, a video signal corresponding to the spatial distribution of the incident light quantity in the photoelectric conversion film 2c is read out.

  However, in the above conventional planar imaging device, the electron beam may reach the photoelectric conversion film 2c with a spread, and in this case, there is a problem that a false signal is generated between adjacent pixels.

  In order to solve this problem, as shown in FIG. 1, a method of suppressing the spread of the electron beam by further providing a shield-grid electrode 4 between the electron source 1 and the photoelectric conversion unit 2 has been proposed. (See Patent Document 1).

  When such a planar imaging device is used for an imaging tube, for example, it is not necessary to deflect a scanning electron beam using a coil or an electrode as in a conventional imaging tube, so that it is similar to a solid-state imaging device such as a CCD. Therefore, it is possible to reduce the thickness of the imaging tube and to reduce power consumption.

  However, in the above planar imaging device, charges may be accumulated outside the scanning region of the photoelectric conversion film 2c, that is, in the peripheral portion of the photoelectric conversion film 2c, which is a non-scanning region, due to dark current, incident light leakage, or the like. is there. If the potential at the peripheral edge of the photoelectric conversion film 2c rises due to this charge accumulation, the trajectory of the electron beam that reads the video signal is disturbed, which causes shading, resolution reduction, image distortion, and the like.

  In order to alleviate the above problems, for example, a planar imaging device shown in FIG. 2 has been proposed.

  The planar image sensor of FIG. 2 omits the illustration of the electron source and displays only the photoelectric conversion unit 3.

The photoelectric conversion unit 3 includes a substrate 3a, a transparent electrode 3b, and a photoelectric conversion film 3c, and an insensitive portion (indicated by an arrow b) is provided in a non-scanning region around the scanning region (indicated by an arrow a). ing. The insensitive part b has a hole capturing layer 3d and a hole injection blocking layer 3e, and has a structure capable of capturing holes generated by incident light. The insensitive portion b further includes a photoelectric conversion film 3g having an opening 3f, and an electron beam injection blocking layer 3h is provided on the surface of the photoelectric conversion film 3c exposed in the opening 3f, and the second photoelectric conversion film 3g. The electron beam injection blocking enhancement layer 3i is provided on the surface of each. The electron beam injection blocking layer 3h and the electron beam injection blocking enhancement layer 3i prevent the electron beam from entering the photoelectric conversion film 3g located in the insensitive portion b. Further, the second photoelectric conversion film 3g prevents an increase or fluctuation in the surface potential of the non-scanning region (see Patent Document 2).
JP 2000-48743 A JP-A-7-29507

  However, in the planar imaging device shown in FIG. 2, it is necessary to align the shape of the scanning region surrounded by the insensitive portion b of the photoelectric conversion unit 3 and the corresponding part of the electron source, and to precisely align the two. Therefore, it is not always easy to manufacture a planar imaging device that satisfies this condition with high accuracy.

  For example, even if the scanning region of the photoelectric conversion unit 3 and the shape of the corresponding part of the electron source can be formed completely the same, if high-precision alignment is not performed, there is no effect on the electron beam irradiation region. There is a possibility that a part of the video signal is lost due to the overlapping of the sensitivity portions. The same applies when the scanning region of the photoelectric conversion unit is formed smaller than the shape of the corresponding part of the electron source.

  On the other hand, when the scanning region of the photoelectric conversion unit 3 is formed larger than the shape of the corresponding part of the electron source, conventional problems such as shading and a decrease in resolution occur.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a photoconductive type planar imaging device in which afterimages, resolution reduction, and white-out are reduced.

  A planar imaging device according to one aspect of the present invention includes a photoelectric conversion unit having a structure in which a transparent electrode and a photoelectric conversion film are stacked on a light-transmitting substrate, and a matrix shape corresponding to each pixel in a scanning region of the photoelectric conversion unit. An electron source having an electron emission source arranged in a strip, a belt-like cathode electrode to which the electron emission source is electrically connected, and a belt-like gate electrode arranged perpendicular to the cathode electrode through an insulating layer, The electron emission source includes a charge-conducting planar imaging device, in which the accumulated charge of the corresponding pixel is read out as a time-series signal in a pixel selection period included in the line readout period, and immediately after the line readout period. Within a predetermined period within the horizontal blanking period, voltage is applied to the cathode electrode and the gate electrode of all the electron emission sources corresponding to the pixels that read out the time-series signal during the line readout period. It is wise, characterized in that sweep out simultaneously emit electrons residual charge.

  A planar imaging device according to another aspect of the present invention includes a photoelectric conversion unit having a structure in which a transparent electrode and a photoelectric conversion film are stacked on a light-transmitting substrate, and a matrix corresponding to each pixel in a scanning region of the photoelectric conversion unit. An electron emission source, an electron source having a belt-like cathode electrode to which the electron emission source is electrically connected, and a belt-like gate electrode arranged orthogonal to the cathode electrode via an insulating layer; The electron emission source is provided within a predetermined period in a horizontal blanking period immediately before a line readout period including a pixel selection period in which accumulated charge of a corresponding pixel is read out. In addition, the accumulated charges that can be read out in the pixel selection period in advance are discharged to the cathode electrodes and the gate electrodes of all electron emission sources corresponding to the pixels from which the time-series signal is read out in the line readout period. With voltage to emit electrons simultaneously applied for, the stored charge in the corresponding pixel, characterized in that the read out as a time-series video signal to the pixel selection period.

  With the above-described configuration of the present invention, it is possible to realize a photoconductive planar imaging device in which afterimages, resolution reduction, and whitening are reduced. Driving the electron emission source means that a voltage is applied to the electron emission source to emit electrons.

  According to the present invention, it is possible to realize a photoconductive type planar imaging device in which afterimages, reduction in resolution, and whitening are reduced.

  A preferred embodiment (hereinafter referred to as this embodiment) of an electron source, a manufacturing method thereof, and a planar imaging device according to the present invention will be described below with reference to the drawings.

  First, an electron source according to this embodiment will be described with reference to FIGS. FIG. 3 is a plan view of the electron source according to the present embodiment, and FIG. 4 is a broken partial view showing the upper right corner portion of the electron source of FIG. 3 cut out along the line IV-IV.

  The electron source 10 according to the present embodiment is a field emission type.

  Similar to a conventional field emission electron source, the electron source 10 has, as a basic configuration, an insulating layer, a plurality of strip-like cathode electrodes and gate electrodes arranged orthogonally across the insulating layer, and an electric current connected to the cathode electrode. Connected to an electron emission source.

  The electron source 10 includes a rectangular region A1 located in the center of the electron source 10, a frame-like region A2 located around the rectangular region A1, and a peripheral region located on the outermost periphery. It is divided into A3. In FIG. 3, a surrounding broken line indicated by an arrow C is a boundary line between the rectangular region A1 and the frame-like region A2. The rectangular area A1 corresponds to a scanning area of the photoelectric conversion unit described later, and the frame-shaped area A2 corresponds to a non-scanning area of the photoelectric conversion unit.

  The cathode electrode, the gate electrode, and the electron emission source are separately provided in the rectangular region A1 and the frame-like region A2.

  That is, on the upper surface of the substrate 12, four first cathode electrodes 14 a to 14 d corresponding to the pixels of the image formed in a 4 × 4 matrix in this case have a predetermined interval corresponding to the pixel pitch. Thus, in the up-down direction in FIG. 3, it extends from the rectangular area A1 and the rectangular area A1 to the frame-like area A2 and the peripheral area A3 that continue to the lower side in FIG. A portion (indicated by an arrow B) formed in the peripheral region A3 of the first cathode electrodes 14a to 14d serves as an extraction electrode.

  Further, on the left and right ends in FIG. 3 on the same plane as the first cathode electrodes 14a to 14d on the substrate 12, from the end of the rectangular area A1 to the outermost edge of the peripheral area A3 through the frame-like area A2. The eight first gate lead electrodes 16a to 16h are formed in a short strip shape extending symmetrically in the left-right direction in FIG. 3 at a predetermined interval corresponding to the pixel pitch.

  Furthermore, rectangular second cathode electrodes 18a to 18d are formed at the four corners that occupy the same plane as the first cathode electrodes 14a to 14d on the substrate 12 and extend from the peripheral region A3 to the frame-like region A2. ing.

  Furthermore, between the second cathode electrodes 18a to 18d and the eight gate lead electrodes 16a to 16h, the second second electrode electrodes 20a to 20d are adjacent to the second cathode electrodes 18a to 18d. Extends in the left-right direction in FIG. 3 and is formed in the same shape as the first gate lead electrodes 16a to 16h.

A rectangular region A1 and a frame-like region, except for the peripheral region A3, which is a connection portion (not shown) of the electrodes 14a to 14d, 16a to 16h, 18a to 18d, and 20a to 20d with external circuits. An insulating layer 22 made of an aluminum anodic oxide film (anodized Al ₂ O ₃ film) is formed over the entire surfaces of the electrodes 14a to 14d, 16a to 16h, 18a to 18d, 20a to 20d, and the exposed portion of the substrate 12 located at A2. Is formed. The insulating layer 22 has a large number of fine holes 24 formed over the entire surface. The fine hole 24 is closed at the end on the side in contact with each electrode and at the end on the side in contact with the substrate. That is, each fine hole 24 is opened only on the upper surface side of the insulating layer 22. The portion where the insulating layer 22 at the bottom of the fine hole 24 remains is used as a barrier layer. The insulating layer 22 may be an anodic oxide film of another material instead of the aluminum anodic oxide film.

  On the upper surface of the insulating layer 22, four first gate electrodes 26 a to 26 d are orthogonally crossed with the first cathode electrodes 14 a to 14 d in a rectangular region A 1 at a predetermined interval corresponding to the pixel pitch. 3 is formed in a strip shape extending in the left-right direction. In the first gate electrodes 26 a to 26 d, a through hole 28 is formed in a portion corresponding to the fine hole 24 of the insulating layer 22, whereby the fine hole 24 and the through hole 28 are communicated with each other.

  In addition, a second gate electrode 30 is formed on the upper surface of the insulating layer 22 so as to surround the first gate electrodes 26a to 26d and over the substantially entire surface of the frame-like region A2. Similar to the first gate electrodes 26a to 26d, the second gate electrode 30 has through-holes in portions corresponding to the micro holes 24 of the insulating layer 22 except for portions that overlap the second gate lead electrodes 20a to 20d. 28 is formed, whereby the fine holes 24 and the through holes 28 communicate with each other. In the description of this embodiment, the term “overlap” refers to a state in which the two are vertically spaced apart from each other unless otherwise specified. In addition, the second gate electrode 30 has a through hole 28 formed in a portion corresponding to the fine hole 24 of the insulating layer 22 in a portion overlapping with the second cathode electrodes 18a to 18d. And the through-hole 28 is connected.

  A portion (indicated by an arrow D) where the first gate electrodes 26a to 26d and the first cathode electrodes 14a to 14d are orthogonal to each other corresponds to a pixel. In the description of the present embodiment, the term “perpendicular” refers to a state of spatially intersecting unless otherwise specified. A minute columnar electron emission source 32 exposed from the through hole 28 is provided in the microhole 24 at the orthogonal portion. The electron emission source 32 is electrically connected to the first cathode electrodes 14 a to 14 d via a portion (barrier layer) of the insulating layer 22 at the bottom of the fine hole 24. On the other hand, the electron emission source 32 is separated from the fine hole 24 and the through hole 28 by a gap. By forming the gap, current leakage can be prevented and the electric capacity between the electrodes can be reduced.

  A columnar first gate connection electrode 34 is filled in the fine hole 24 of the insulating layer 22 where the first gate electrodes 26a to 26d overlap the first gate lead electrodes 16a to 16h. Thereby, the first gate electrodes 26a to 26d and the first gate lead electrodes 16a to 16h are electrically connected.

  In the frame-shaped region A2, the second gate electrode 30 of the insulating layer 22 in a portion overlapping the first cathode electrodes 14a to 14d, the second cathode electrodes 18a to 18d, and the first gate lead electrodes 16a to 16h A minute columnar electron emission source 36 is formed inside the microhole 24 so as to be exposed to the through hole 38. Each electron emission source 36 includes a first cathode electrode 14 a to 14 d and a second cathode. The electrodes 18a to 18d or the first gate lead electrodes 16a to 16h are electrically connected.

  The second gate electrode 30 is filled with the second gate connection electrode 39 in the minute hole 24 of the insulating layer 22 where the second gate electrode 30 overlaps the second gate lead electrodes 20a to 20d in the frame-like region A2. Thus, the second gate electrode 30 and the second gate lead electrodes 20a to 20d are electrically connected.

  The electron source 10 according to the present embodiment configured as described above includes the first cathode electrodes 14a to 14d, the second cathode electrodes 18a to 18d, and the first cathode on the same plane of the upper surface of the substrate 12. Gate lead electrodes 16a to 16h and second gate lead electrodes 20a to 20d are formed. Then, the electron emission source 32 is formed on the portion of the rectangular region A1 of the first cathode electrodes 14a to 14d, and further, the portion of the frame-like region A2 of the first cathode electrodes 14a to 14d, the second An electron emission source 36 is also formed on the cathode electrodes 18a to 18d and the first gate lead electrodes 16a to 16h. In addition, the first gate electrodes 26a to 26d and the first gate lead electrodes 16a to 16h are formed by the first gate connection electrode 34, and the second gate electrode 30 and the second gate lead electrodes 20a to 20d are formed. Are electrically connected to each other by the second gate connection electrode 39.

  The frame-like region including the part of the frame-like region A2 of the first cathode electrodes 14a to 14d and the electron-emitting source 32 through the portion of the rectangular-shaped region A1 of the first cathode electrodes 14a to 14d. Since a voltage can be separately applied to the electron emission source 36 through each electrode A2, the electron emission source 32 and the electron emission source 36 can be separately selected and driven.

  The electron source 10 according to the present embodiment drives the electron emission source 36 formed in the frame-like region A2, thereby causing a dark current, incident light leakage, or the like outside the scanning region of the photoelectric conversion film, that is, The electric charge accumulated in the peripheral portion of the photoelectric conversion film, which is a non-scanning region, can be discharged, thereby reducing shading, resolution reduction, image distortion, and the like. This point will be described in detail later.

  Further, the electron source 10 according to the present embodiment can obtain the above effect with the structure of only the electron source as described above, and it is not necessary to precisely position the photoelectric conversion film with respect to the scanning region. For example, the electron source 10 can be easily and inexpensively formed by a manufacturing method described later.

  In addition, the electron source 10 according to the present embodiment includes the first and second gates in which the first and second gate electrodes 26a to 26d and 30 are formed in the fine hole 24 of the insulating layer 22 as described above. The first and second gate lead electrodes 16a to 16h and 20a to 20d, which are connection terminals to the outside, are electrically connected via the connection electrodes 34 and 39, and are not bonded. There is no risk of deformation or breakage of the insulating layer 22 occurring during the process. Further, in the conventional method in which the first and second gate electrodes 26a to 26d and 30 are directly extended to the substrate 12 and used as connection terminals to the outside, connection failure may occur at the step portion of the thick insulating layer. However, this is not a concern in the present invention.

  A method for manufacturing the electron source 10 will be described with reference to FIGS. 5 to 10 show one corner of the electron source 10 corresponding to FIG. 4 showing one corner of the electron source 10, in which (a) shows a side section and (b). Indicates a plane.

  For example, a glass material is used for the substrate 12. However, instead of the glass material, an insulator material such as ceramics or synthetic resin, or a semiconductor material such as silicon may be used.

  Using a photomask (not shown), for example, a copper material is deposited on the substrate 12 in a band shape having a width of about 20 μm and a thickness of about 0.4 to 1 μm, for example, by sputtering or vacuum deposition, and the first cathode electrode 14 (14a˜ 14d), the first gate lead electrode 16 (16a to 16h) and the second gate lead electrode 20 (20a to 20d) are patterned. At the same time, the second cathode electrodes 18 (18 a to 18 d) having a width of about 200 μm and a thickness of about 0.4 to 1 μm are pattern-formed at the four corners of the substrate 12. Note that instead of the copper material, a material such as silver or platinum having good conductivity similar to that of the copper material may be used. Thereafter, for example, a copper material is formed on each electrode 14, 16, 18, 20 and on each electrode 14, 16, 18, 20, except for a peripheral portion (portion corresponding to the peripheral region A3) by sputtering or vacuum deposition. A high-purity aluminum layer 22a is formed to a thickness of about 1 to 5 μm on the portion of the substrate 12 exposed between 20 (FIGS. 5A and 5B).

  Next, the aluminum layer 22a is anodized. Specifically, for example, after the surface of the aluminum layer 22a is cleaned by the procedures of alkaline degreasing treatment, water washing, acid neutralization and water washing, a 2-5% oxalic acid aqueous solution is used as an electrolytic solution, and the aluminum layer 22a is formed. As the anode, for example, constant voltage electrolysis of 40 V is performed at a liquid temperature of 17 ° C. As a result, the aluminum layer 22a is anodized, and the insulating layer 22 made of an aluminum oxide layer in which a number of fine holes 24 having a diameter of about 0.03 μm, for example, are formed innumerable at a pitch of about 0.1 μm can be easily obtained ( FIG. 6A and FIG. 6B).

  A portion of the insulating layer (indicated by an arrow E) that has not been removed by the anodic oxidation treatment remains at the bottom portion of the fine hole 24 and functions as a barrier layer. The insulating layer 22 is further subjected to constant current electrolysis in the above-described electrolytic solution or acid bath until the voltage becomes a sufficiently low value, and each barrier layer is uniformly thinned. Furthermore, only the barrier layer of the micropores 24 in which an electron source or a metal electrode is provided inside is masked with a photomask, and in an electrolytic solution such as ammonium borate or ammonium tartrate, 10 V or more, more preferably 40 V or more. The thickness of the barrier layer of the micropores 24 other than the micropores 24 provided with the electron source or the metal electrode is increased by re-electrolysis at a voltage of (a difference in the thickness of the barrier layer is clearly shown in FIG. 6A). (See Fig. 7 (a)). By these treatments, the thickness of the barrier layer at the bottom of the fine hole 24 of the insulating layer 22 is easily and selectively adjusted. As a method for increasing the thickness of the barrier layer, in addition to the above method, the Japan Printing Society, Vol. 16, No. 3 (1976), pp. It can also process easily in a short time also by the well-known electrolytic printing method described in 137-142.

  Next, the insulating layer 22 is mixed in a mixed solution obtained by adding an appropriate amount of boric acid and ammonium to a sulfate solution of a magnetic metal such as nickel, iron or cobalt or a non-magnetic metal such as tin or copper. The substrate 12 containing is subjected to deformation AC electrolysis. Thereby, a magnetic or non-magnetic metal is selectively electrodeposited on the barrier layer of the fine hole 24 with a thin barrier layer, and the cylindrical metal filled up to the upper end of the fine hole 24, that is, the surface of the insulating layer 22. 40 is formed in the fine hole 24 (FIGS. 7A and 7B). Further, the surface of the insulating layer 22 is adjusted with phosphoric acid and trioxide in order to adjust the position in the height direction between the tip of a columnar metal 40 serving as an electron emission source described later and the first and second gate electrodes described later. Etching may be removed by about 0.02 to 1 μm in a mixed aqueous solution of chromium.

  Next, a metal layer having a good conductivity such as nickel, cobalt, copper, tungsten or the like is formed using a sputtering method, a vacuum evaporation method, or the like, and then etched using a photomask (not shown). Alternatively, a band-shaped metal layer 42 that forms a first gate electrode having a width of about 20 μm and a thickness of about 0.4 to 1 μm, for example, by forming a film by controlling the shape by a sputtering method or a vacuum evaporation method using a mask, and For example, a frame band-shaped metal layer 44 serving as a second gate electrode having a width of 200 μm and a thickness of 0.4 to 1 μm is formed (FIGS. 8A and 8B). Although the metal layer 44 is formed in a frame shape in FIG. 8, the shape of the metal layer 44 is not limited to the frame as long as it surrounds the metal layer 42.

  Next, after a photoresist film is applied to the portion of the metal layer 44 that overlaps the second gate lead electrode 20 via the insulating layer 22, the first cathode electrode 14, the second cathode electrode 18, and the first gate are applied. Using the extraction electrode 16 and the second gate extraction electrode 20 as electrodes, electrolytic polishing treatment (anodic dissolution) is performed in a known electrolytic polishing liquid. At this time, the electric field concentrates and selectively dissolves in the portions of the metal layers 42 and 44 that are in contact with the cylindrical metal 40, and the through hole 28 is formed in the portions of the metal layers 42 and 44 that are in contact with the cylindrical metal 40. The The through hole 28 electrically insulates the columnar metal 40 and the metal layers 42 and 44 from the first gate electrode 26 (26a to 26d) and the second gate electrode 44, respectively. 30 (FIGS. 9A and 9B). Here, when the diameter of the through hole 28 is increased by electrolytic polishing again using the first gate electrode 26 and the second gate electrode 30 as electrodes, the first gate electrode 26 and the second gate electrode 30 and the columnar metal 40 are used. Insulating properties can be further improved.

  Next, constant current electrolysis is performed in a phosphoric acid bath using the first gate electrode 26, the second gate electrode 30, the first gate lead electrode 16 and the second gate lead electrode 20 as electrodes, and the insulating layer 22. The side surfaces of the fine holes 24 are dissolved. Thereby, the space | gap 46 is formed between the side surface of the micropore 24, and the side surface of the columnar metal 40, and the microhole 24 and the columnar metal 40 are electrically insulated. Finally, the photoresist film is removed by a known method. Thereby, the electron source 10 is completed (FIG. 10).

  According to the electron source manufacturing method described above, the electron source of the present invention can be obtained by a simple method.

  Next, a method for manufacturing the electron source 10 by a manufacturing method different from the above-described method will be described with reference to FIGS. In addition, the part of the electron source 10a of FIGS. 11-16 has extracted and shown the same part as the part of the electron source 10 of FIGS. In the following description, a detailed description of the same parts as those described above may be omitted. In each figure, the elements (a) and (b) do not strictly correspond in positional relationship.

  First, in the same procedure as described above, a strip-shaped first cathode electrode 14 having a width of about 50 μm and a thickness of about 0.1 μm, a first gate extraction electrode 16, and a second gate extraction electrode 20 are formed on the substrate 12. Form. At the same time, for example, second cathode electrodes 18 having a width of about 300 μm and a thickness of about 0.1 μm are pattern-formed at the four corners of the substrate 12. Thereafter, the substrate 12 exposed on the electrodes 14, 16, 18, 20 and between the electrodes 14, 16, 18, 20 except for the peripheral portion (peripheral region) by, for example, chemical vapor deposition or sputtering. A silicon oxide layer having a thickness of about 0.8 μm is formed on this portion. The silicon oxide layer becomes the insulating layer 22 (FIGS. 11A and 11B).

  Next, after a metal layer is formed on the insulating layer 22 by using a sputtering method, a vacuum evaporation method, or the like, a metal material having good conductivity is formed, and then the diameter is etched by using a photomask (not shown). A metal layer 46 having a plurality of through holes 28 of about 1 μm and including a portion to be the first gate electrode and a portion to be the second gate electrode is formed (FIGS. 12A and 12B).

  Next, by using an anisotropic dry etching method such as reactive ion etching and an isotropic wet etching method together, the fine holes 24 communicating with the through holes 28 are formed inside the insulating layer 22 using the metal layer 46 as a mask. To do. Thereafter, a lift-off aluminum layer 48 is formed to a thickness of about 0.3 to 0.7 μm only on the metal layer 46 by an oblique deposition method with an inclination angle of 20 ° (FIGS. 13A and 13B). ).

  Next, a metal such as molybdenum having a high melting point and good conductivity is formed on the lift-off aluminum layer 48 by using a sputtering method, a vacuum deposition method, or the like to form a metal layer 50 having a thickness of about 1 μm. As a result, a conical minute electron emission source 52 made of a metal such as molybdenum is formed inside the minute hole 24 of the insulating layer 22 (FIGS. 14A and 14B).

  Next, the metal layer 50 is removed by lifting off the lift-off aluminum layer 48 by a wet etching method (FIGS. 15A and 15B).

  Next, the metal layer 46 is covered with a high-viscosity photoresist film (not shown) except for the portion other than the through hole 28 located in the portion overlapping the first gate lead electrode 16 and the second gate lead electrode 20 and then again. The first and second gate connection electrodes 34 and 39 are formed by sputtering a metal such as molybdenum. Finally, after removing the photoresist film, the metal layer 46 is photo-etched to form the first gate electrode 26 (26a to 26d) having a width of 50 μm and the second gate electrode 30 having a width of 300 μm. By forming, the electron source 10 is obtained.

  In the method of manufacturing the electron source 10 described above, the portion other than the through hole 28 where the metal layer 46 is located at the portion where the metal gate 46 overlaps with the first gate extraction electrode 16 and the second gate extraction electrode 20 is not shown in the drawing. After covering with a high photoresist film and then forming an aluminum layer 48 for lift-off, the photoresist film is removed, and a metal is deposited by sputtering or vacuum deposition, the electron emission source 52 and the first and second The gate connection electrodes 34 and 39 can be formed simultaneously.

  Next, an operation method of the planar imaging device according to the present embodiment will be described with reference to FIGS.

  For example, in the planar imaging device of FIG. 1, the planar imaging device can use the electron source 10 according to the present embodiment as an electron source. In FIG. P. Indicates an output terminal to be described later. As the photoelectric conversion film 2c, for example, a 1-inch HARP (High-gain Avalanche Rushing amorphous Photoconductor) film having a thickness of 8 μm is used. In this case, when the reference signal amount for obtaining 100% white of the standard TV standard is, for example, 200 nA, the scanning surface potential (reference scanning surface potential) of the photoelectric conversion film 2c is about 3.2V. The electron source 10 uses the first gate electrode 26 (26a to 26d) for pixel selection in the vertical (Y) direction, and the first cathode electrode 14 (14a to 14d) for pixel selection in the horizontal (X) direction. Is used.

  For example, an arbitrary one line (horizontal direction) selection period T3 shown in FIG. 17 is set to 63.5 μsec, and in this line selection period T3, the line reading period T5 is set to 52.6 μsec, and the horizontal blanking period T6 is set to 10.9 μsec. . On the other hand, the pixel selection period T4 is set to 160 nsec, for example. At this time, one line is about 250 pixels.

  In order to read out the accumulated charges in the scanning region, a voltage of, for example, 40 V is applied to the first gate electrode (i) during the line selection period T3, and any first cathode electrode during the pixel selection period T4. For example, (j) is set to 0V.

  At this time, an electron beam is emitted from the selected electron emission source 32 located in a region (corresponding to a pixel) where the first gate electrode (i) and the first cathode electrode (j) intersect with each other. Until the scanning surface potential of the conversion film 2c is in equilibrium with the cathode potential, the output terminal O.D. P. A current flows through and is read out as an output signal of one pixel.

  However, when the incident light is very strong, the scanning surface potential of the photoelectric conversion film 2c does not reach equilibrium with the cathode potential within the pixel selection period T4, and an afterimage is generated by reading again in the next field. Alternatively, the resolution of the image may be deteriorated by reading the residual charge by spreading the electron beam of the adjacent pixel.

Therefore, after the pixel signal on one line is read, the voltage is continuously applied to the first gate electrode (i) during the residual charge sweeping period T7, and all the first cathode electrodes (j) are applied. , (J + 1) potential is set to 0V, residual charges that have not been read can be swept out.

  Thereafter, a voltage is applied to the first gate electrode (i + 1) of the next line from the overaccumulated charge sweeping period T8, and the potentials of all the first cathode electrodes (j) and (j + 1) are set to the reference scanning plane potential. By setting the voltage to about 16V, which is five times as large as that of the electron beam, it is possible to preliminarily sweep out the accumulated charges that can be read out by the electron beam during the pixel selection period T4.

  As a result, even when a high-luminance subject is imaged, the same effect as the electronic shutter of the solid-state imaging device can be obtained, and whiteout, smear / afterimage, and resolution degradation can be eliminated.

  On the other hand, during the same horizontal blanking period T6, the first gate lead electrodes other than the first gate lead electrode to which the selected first gate electrodes (i) and (i + 1) are connected and the first The potential of the second cathode electrode is set to 0 V, and the voltage of 40 V, for example, the same as the first gate electrode is applied to the second gate electrode, so that the other first gate lead electrode and second cathode electrode An electron beam is emitted from the electron emission source in the non-scanning region where the second gate electrode and the second gate electrode intersect, and the potential on the scanning surface side due to leakage light or dark current in the non-scanning region of the photoelectric conversion film can be reset. It is possible to eliminate shading and resolution degradation at the periphery of the region. In this case, the potential of only the second cathode electrode may be set to 0V.

  Furthermore, after reading out the accumulated charges on all the scan lines as an output signal during one field readout period T1, among the charges newly accumulated on the photoelectric conversion film 2c, the planar imaging device of the present embodiment example. By sweeping out charges exceeding the dynamic range and charges accumulated in the non-scanning region during the vertical blanking period T2, the above-described defect phenomenon can be solved more easily.

  That is, as shown in FIG. 18, during the vertical blanking period T2, the potential of the second gate electrode is increased, and the potentials of all the first cathode electrodes (j), (j + 1) and the second cathode electrode are increased. Is set to 0 V, all accumulated charges in the periphery of the scanning region can be swept out, and shading and resolution degradation can be prevented.

  Further, during the vertical blanking period T2, the potentials of all the first gate electrodes (i) and (i + 1) are increased, and the potentials of all the first cathode electrodes (j) and (j + 1) are set to, for example, By setting the voltage to about 16 V, it is possible to eliminate white-out, smear / afterimage, and resolution degradation.

  According to the operation method of the planar imaging device according to the present embodiment described above, it is possible to easily realize a planar imaging device that has uniform characteristics over the entire scanning region and does not generate false signals such as afterimages and smears. it can.

  Note that various modifications and changes can be made within the scope of the present invention regardless of the embodiment described above.

It is a figure which shows schematic structure of an example of the conventional plane image sensor. It is a figure which shows schematic structure of the photoelectric conversion part of the other example of the conventional plane image sensor. It is a top view of the electron source which concerns on the example of this Embodiment. It is a fragmentary perspective view which shows the state which fractured | ruptured and took out some electron sources which concern on the example of this Embodiment. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view (a) and a partial plan view (b) for explaining a method for manufacturing an electron source according to an embodiment and showing steps until an insulating layer is stacked on a substrate. . FIG. 2 is a partial side cross-sectional view (a) and a partial plan view (b) for explaining a manufacturing method of an electron source according to the present embodiment and showing steps until a fine hole is formed in an insulating layer. is there. FIG. 2 is a partial side cross-sectional view (a) and a partial plan view (b) for explaining a method for manufacturing an electron source according to the present embodiment and showing steps until an electron emission source is formed in a microhole. ). FIG. 9 is a partial side cross-sectional view (a) and a partial plan view (b) for explaining a method for manufacturing an electron source according to the present embodiment and showing steps until a gate electrode is formed on an insulating layer. It is. FIG. 2 is a partial side cross-sectional view (a) and a partial plan view (b) for explaining a method for manufacturing an electron source according to the present embodiment and showing steps until a through hole is formed in a gate electrode. is there. It is for demonstrating the manufacturing method of the electron source which concerns on this Example, and is a partial sectional side view of the completed electron source. Partial side sectional view (a) and partial plan view (b) for explaining another method of manufacturing the electron source according to the present embodiment and showing steps until an insulating layer is stacked on the substrate. It is. FIG. 8 is a partial side cross-sectional view (a) and a partial plan view (steps) for explaining another method for manufacturing the electron source according to the present embodiment and showing steps until a metal layer is formed on the insulating layer. b). It is for demonstrating the other manufacturing method of the electron source which concerns on this Embodiment, and after forming the aluminum layer for lift-off, the process until it opens the aluminum layer for lift-off, and forms a fine hole and penetration They are a partial sectional side view (a) and a partial top view (b) which show. Partial side sectional view (a) and part for explaining another method of manufacturing the electron source according to the present embodiment and showing steps until a metal layer is further formed on the lift-off aluminum layer It is a top view (b). Partial side sectional view (a) and partial plan view (b) for explaining another manufacturing method of the electron source according to the present embodiment and showing steps until the lift-off aluminum layer is lifted off It is. It is for demonstrating the manufacturing method of the electron source which concerns on this Example, and is a partial sectional side view of the completed electron source. It is a figure for demonstrating the operation | movement method of the plane image sensor which concerns on the example of this Embodiment, and is a figure which shows the drive pattern of line reading. It is a figure for demonstrating the operation | movement method of the plane image sensor which concerns on the example of this Embodiment, and is a figure which shows the drive pattern of field reading.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Electron source 12 Substrate 14, 14a-14d 1st cathode electrode 16, 16a-16h 1st gate extraction electrode 18a-18d 2nd cathode electrode 20, 20a-20d 2nd gate extraction electrode 22 Insulating layer 22a Aluminum Layer 26, 26a to 26d First gate electrode 30 Second gate electrode 32, 36, 52 Electron emission source 34 First gate connection electrode 39 Second gate connection electrode 40 Columnar metal 42, 44, 46, 50 Metal Layer 48 Aluminum layer for lift-off

Claims (2)

A photoelectric conversion part having a structure in which a transparent electrode and a photoelectric conversion film are laminated on a light-transmitting substrate;
Electron emission sources arranged in a matrix corresponding to each pixel in the scanning region of the photoelectric conversion unit, a strip-shaped cathode electrode to which the electron emission source is electrically connected, and orthogonal to the cathode electrode through an insulating layer An electron source having a strip-shaped gate electrode arranged in a row,
A photoconductive type planar imaging device comprising:
The electron emission source reads the accumulated charge of the corresponding pixel as a time series signal in a pixel selection period included in a line readout period, and within a predetermined period in a horizontal blanking period immediately after the line readout period, A planar imaging device, wherein a voltage is applied to the cathode electrode and the gate electrode of all electron emission sources corresponding to pixels that read out a time-series signal in a line readout period to simultaneously emit electrons and sweep out residual charges. A photoelectric conversion part having a structure in which a transparent electrode and a photoelectric conversion film are laminated on a light-transmitting substrate;
Electron emission sources arranged in a matrix corresponding to each pixel in the scanning region of the photoelectric conversion unit, a strip-shaped cathode electrode to which the electron emission source is electrically connected, and orthogonal to the cathode electrode through an insulating layer An electron source having a strip-shaped gate electrode arranged in a row,
A photoconductive type planar imaging device comprising:
The electron emission source is a pixel that reads a time-series signal in the line readout period within a predetermined period in the horizontal blanking period immediately before the line readout period including a pixel selection period in which the accumulated charge of the corresponding pixel is read out. A voltage is applied to the cathode electrode and the gate electrode of all corresponding electron emission sources in advance so that the accumulated charge more than can be read during the pixel selection period is emitted, and electrons are simultaneously emitted, and the accumulated charge of the corresponding pixel is A planar imaging device, which is read out as a time-series video signal during the pixel selection period.