JP2009042068A - Pulse radar device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse radar device capable of detecting an object existing on the periphery highly accurately regardless of a peripheral temperature change. <P>SOLUTION: This pulse radar device 1 includes a trigger signal generation part 4 for generating and outputting a transmission trigger signal Gt and a reception trigger signal Gr. The trigger signal generation part 4 has variable period pulse generation circuits 41, 42, a reception trigger signal generation circuit 43 and a transmission trigger signal generation circuit 43. The variable period pulse generation circuit 41 generates an output signal D1 having a different period corresponding to a frequency setting signal Df based on a clock signal C, and the variable period pulse generation circuit 42 delays the output signal D1 as long as a fixed delay time Td by using a digital fixed delay circuit 70 operated based on the clock signal C, and then generates an output signal P2 based on the delayed output signal D2. The reception trigger signal generation circuit 43 and the transmission trigger signal generation circuit 44 generate respectively the reception trigger signal Gr and the transmission trigger signal Gt based on the output signals P1, P2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pulse radar device that detects an object existing in the vicinity by outputting a pulse signal and receiving at least a part of a reflected wave thereof.

  In recent years, as a vehicle-mounted pulse radar device for the purpose of detecting people in blind spots around a vehicle, parking assistance, following traveling, etc., it is generally called 22 to 29 GHz called UWB (Ultra Wide Band). Those using the quasi-millimeter wave band are known. In the pulse radar apparatus using UWB, a very short pulse signal having a width of about 1 ns generated using a very wide frequency band can be used, so that a high distance resolution of about 15 cm can be realized.

  FIG. 10 is a block diagram showing a configuration of a pulse radar device 100 according to a conventional example. In FIG. 10, when the transmission trigger signal Gt generated at a predetermined repetition period is input by the controller 101, the wireless transmission circuit 5 generates a transmission signal Pt having a predetermined width and a predetermined carrier frequency, and passes through the transmission antenna 5a. Radiate into space. The transmission signal Pt is reflected by the object 2, and a part of the transmission signal Pt is received and detected by the wireless reception circuit 102 via the reception antenna 102a as the reception signal Pr. The signal processing unit 7 performs predetermined signal processing based on the detection result Dr of the wireless reception circuit 102 and detects the distance R to the object 2. For example, as disclosed in Non-Patent Document 1, the distance R to the object 2 is expressed by the following equation (1) using the time Δt from when the transmission signal Pt is radiated until the reception signal Pr is received and the speed of light c. Can be calculated.

[Equation 1]
R = c × (Δt / 2) (1)

  FIG. 11 is a waveform diagram showing the transmission signal Pt and the reception signal Pr in the pulse radar device 100 of FIG. In FIG. 11, the reception signal Pr is detected after a round-trip time corresponding to the distance between the transmission antenna 5 a and the obstacle 2 from the transmission timing at which the transmission signal Pt is radiated. The wireless reception circuit 102 detects the reception signal Pr at a detection timing delayed by a delay time that is sequentially changed according to a desired distance within the search range from the transmission timing of the transmission signal Pt.

International Publication No. WO2006 / 041042 Pamphlet. Supervised by Takashi Yoshida, "Revised Radar Technology 3rd Edition", pages 1-3, published by the Institute of Electronics, Information and Communication Engineers, October 1996.

  When using the above-described UWB in the pulse radar device according to the conventional example, the width of the reception signal Pr is as short as about 1 ns. Therefore, in order to reliably detect this, the delay time from the transmission timing to the detection timing is: It is necessary to control accurately at intervals smaller than the pulse width. Conventionally, a method has been proposed in which a plurality of analog delay lines having different delay amounts are configured in multiple stages and the connection time is changed by a switch to change the delay time. However, since each analog delay line generally has an error, the error increases by using a plurality of analog delay lines, and an accurate delay time cannot be obtained, thereby deteriorating the accuracy of detection timing. There was a point. Furthermore, since a severe temperature condition (for example, −40 to 85 degrees Celsius) is imposed on the on-vehicle pulse radar device, the delay amount of the analog delay line changes with the temperature change, and the detection timing is further increased. The accuracy may deteriorate.

  An object of the present invention is to solve the above-described problems and provide a pulse radar device capable of detecting an object present in the surroundings with high accuracy regardless of a change in ambient temperature.

  A pulse radar apparatus according to a first aspect of the present invention is a pulse radar apparatus that detects a surrounding object by outputting a pulse signal and receiving at least part of a reflected wave of the pulse signal, and radiates the pulse signal. A trigger signal generator for generating and outputting a transmission trigger signal for providing a transmission timing for receiving and a reception trigger signal for providing a detection timing for receiving at least a part of the reflected wave, wherein the trigger signal generator is input A digital waveform generation circuit that generates and outputs a first digital output signal having a different period according to an input frequency setting signal, and based on the first digital output signal, A first signal generator for generating and outputting a first variable period pulse output signal; and operating based on the clock signal And delaying the first digital output signal by a predetermined fixed delay time and then generating a second variable period pulse output signal based on the delayed first digital output signal. A second signal generator that outputs the received trigger signal based on the first variable period pulse output signal, a reception trigger signal generator that generates and outputs the reception trigger signal, the first variable period pulse output signal, And a transmission trigger signal generator for generating and outputting the transmission trigger signal based on a second variable period pulse output signal.

  In the pulse radar apparatus, the digital fixed delay circuit is a plurality of delay flip-flops cascaded to each other.

  In the pulse radar device, the first signal generation unit generates a digital signal of a sine wave or a cosine wave having a different period according to the frequency setting signal, and the first signal generator generates the first signal based on the digital signal. An output signal is generated and output.

  Furthermore, in the above pulse radar device, the fixed delay time is a natural number multiple of the period of the clock signal.

  According to the pulse radar device of the present invention, the first signal generator that generates and outputs the first output signal having a different period according to the input frequency setting signal based on the input clock signal. And delaying the first output signal by a predetermined fixed delay time using a digital fixed delay circuit that operates based on the clock signal, and then generating a second output signal based on the delayed first output signal A second signal generator for outputting, a reception trigger signal generator for generating and outputting a reception trigger signal based on the first output signal, and on the basis of the first output signal and the second output signal Since the trigger signal generation unit including the transmission trigger signal generation unit that generates and outputs the transmission trigger signal is provided, it is possible to detect an object existing in the vicinity with high accuracy regardless of the ambient temperature change.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, the same reference numerals are assigned to the same components.

  FIG. 1 is a block diagram showing a configuration of a pulse radar device 1 according to an embodiment of the present invention. In FIG. 1, a pulse radar device 1 includes a controller 3, a trigger signal generation circuit 4, a wireless transmission circuit 5, a transmission antenna 5a, a wireless reception circuit 6, a reception antenna 6a, and a signal processing circuit 7. Configured.

  The controller 3 generates a search command signal Cd for every 10 us repetition period P and outputs it to the trigger signal generation circuit 4. Each time the search command signal Cd from the controller 3 is input, the trigger signal generation circuit 4 generates a transmission trigger signal Gt and a reception trigger signal Gr delayed with respect to the transmission trigger signal Gt. 5 and the radio reception circuit 6.

  The wireless transmission circuit 5 generates a transmission signal Pt having a 1 ns width modulated at a carrier frequency of 26 GHz, for example, with the rising edge of the transmission trigger signal Gt as a transmission timing, and radiates it to the space via the transmission antenna 5a. The transmission signal Pt is reflected by the object 2 existing in the space, and at least a part of the reflected signal is received by the wireless reception circuit 6 via the reception antenna 6a as the reception signal Pr. The radio reception circuit 6 detects, for example, the voltage level of the reception signal Pr using the rising edge of the reception trigger signal Gr as the detection timing, and outputs a detection result Dr including the detected voltage level to the signal processing circuit 7.

  The signal processing circuit 7 acquires the detection result Dr output from the wireless reception circuit 6, and detects the presence / absence of the object 2 and the distance to the object 2 by performing predetermined signal processing such as averaging processing and distance detection processing. The detection result Ds is output to the controller 3. The controller 3 generates and outputs the next search command signal Cd based on the detection result Ds from the signal processing unit 7.

  FIG. 2 is a waveform diagram showing signals at various parts of the pulse radar device 1 of FIG. In FIG. 2, the wireless transmission circuit 5 outputs a transmission signal Pt with the rising edge of the transmission trigger signal Gt as a transmission timing. Further, the wireless reception circuit 6 detects the reception signal Pr using the rising edge of the reception trigger signal Gr as the detection timing. At this time, the search command signal Cd from the controller 3 includes information related to the setting of the delay time from the transmission timing to the detection timing in addition to the information related to the repetition period P, and the detection timing from the transmission timing in the first repetition period P. Is set by the controller 3 so that the delay time Tr1 from the transmission timing in the second repetition period P to the detection timing Tr2 is different (details will be described later).

  FIG. 3 is a block diagram showing a detailed configuration of the trigger signal generation circuit 4 of FIG. In FIG. 3, the trigger signal generation circuit 4 includes variable period pulse generation circuits 41 and 42, a reception trigger signal generation circuit 43, and a transmission trigger signal generation circuit 44. The variable period pulse generation circuit 41 includes a digital waveform generation circuit 60, a D / A converter 61, a low-pass filter (hereinafter referred to as LPF) 62, and a waveform shaper 63. The variable period pulse generation circuit 42 includes a digital fixed delay circuit 70, a D / A converter 71, an LPF 72, and a waveform shaper 73. In the variable period pulse generating circuit 41, the digital waveform generating circuit 60 and the D / A converter 61 constitute a DDS (Direct Digital Synthesizer) 50.

  The search command signal Cd input from the controller 3 to the trigger signal generation circuit 4 includes a start signal Tg that rises at the start of the repetition period P, a frequency setting signal Df for setting a delay time from the transmission timing to the detection timing, Clock signal C. The digital waveform generation circuit 60 receives the frequency setting signal Df and the clock signal C, and outputs an output signal D1 that is a digital signal having a cycle Tsi (i = 1, 2, 3,...) Corresponding to the frequency setting signal Df. Generated and output to the D / A converter 61 and the digital fixed delay circuit 70. The frequency setting signal Df is controlled so that the period Tsi (i = 1, 2, 3,...) Is gradually increased every time the repetition period P is repeated. The digital fixed delay circuit 70 delays the output signal D1 from the digital waveform generation circuit 60 by a predetermined fixed delay time Td, and outputs it as an output signal D2 to the D / A converter 71.

  The D / A converter 61 converts the digital output signal D1 into the analog output signal S1 on the staircase by performing a sample hold process on the digital output signal D1 input from the digital waveform generation circuit 60 based on the clock signal C. And output to the LPF 62. The LPF 62 converts the output signal S1 into a smooth output signal S2 by removing the harmonic component of the output signal S1, and outputs it to the waveform shaper 63. The waveform shaper 63 is a comparator, for example, which converts the output signal S2 into a pulse waveform and outputs an output signal P1 that is a pulse signal to the reception trigger signal generation circuit 43.

  The D / A converter 72 performs a sample hold process on the digital output signal D2 input from the digital fixed delay circuit 70 based on the clock signal C, thereby converting the digital output signal D2 into an analog output signal S3 on the staircase. And output to the LPF 72. The LPF 72 converts the output signal S3 into a smooth output signal S4 by removing the harmonic component of the output signal S3, and outputs it to the waveform shaper 73. The waveform shaper 73 is a comparator, for example, which converts the output signal S4 into a pulse waveform and outputs an output signal P2 that is a pulse signal to the transmission trigger generation circuit 44. Since the digital fixed delay circuit 70 is provided, the output signal P2 is delayed by a predetermined fixed delay time Td with respect to the output signal P1.

  The reception trigger signal generation circuit 43 generates and outputs a reception trigger signal Gr based on the activation signal Tg and the output signal P1. The transmission trigger signal generation circuit 44 generates and outputs a transmission trigger signal Gt based on the activation signal Tg and the output signals P1 and P2 (described later with reference to FIG. 4).

  FIG. 4 is a waveform diagram showing signals at various parts in the reception trigger signal generation circuit 43 and the transmission trigger signal generation circuit 44 of FIG. In each repetition period P, the reception trigger signal generation circuit 43 and the transmission trigger signal generation circuit 44 receive the high level activation signal Tg from the controller 3 and then become an internal signal that becomes high level when the rising edge of the output signal P1 is detected. Si is generated. Next, the transmission trigger signal generation circuit 44 outputs the transmission trigger signal Gt which becomes high level at the timing when the rising edge of the output signal P2 is detected after the internal signal Si becomes high level. The reception trigger signal generation circuit 43 outputs the reception trigger signal Gr that becomes high level at the timing when the rising edge of the output signal P1 is detected after the internal signal Si becomes high level. Similar processing is repeated every repetition period P. Therefore, as shown in FIG. 4, the delay time Tri (i = 1, 2, 3,...) From the transmission trigger signal Gt to the reception trigger signal Gr is a cycle of the output signal P1 that changes according to the frequency setting signal Df. Control is performed so that Tsi (i = 1, 2, 3,...) Becomes longer as Tsi becomes longer. The delay time Tri (i = 1, 2, 3,...) Can be expressed by the following equation (2) using the period Tsi (i = 1, 2, 3,...) Of the output signal P1 and the fixed delay time Td. it can.

[Equation 2]
Tri = Tsi−Td (i = 1, 2, 3,...) (2)

  In the above equation (2), the cycle Tsi (i = 1, 2, 3,...) Of the output signal P1 changes from Td to a predetermined value according to the distance to be detected. When the period Tsi (i = 1, 2, 3,...) Is equal to the fixed delay time Td, the delay time Tri (i = 1, 2, 3,...) Becomes zero, and an object existing at a very close distance is detected. . Further, in order to detect an object existing at a desired distance, the cycle Tsi (i = 1, 2, 3,...) Is set to the sum of a fixed delay time Td and a round trip time to the desired distance (that is, a delay time Tri). Set as follows. Therefore, as shown in the following equation (3), the period Tsi (i = 1, 2, 3,...) Is a value equal to or longer than the fixed delay time Td. By changing the frequency setting signal Df from the controller 3, the delay time Tri (i = 1, 2, 3,...) Can be controlled so as to detect an object existing at a desired distance.

[Equation 3]
Tsi ≧ Td (i = 1, 2, 3,...) (3)

  FIG. 5 is a block diagram showing a detailed configuration of the digital waveform generation circuit 60 of FIG. In FIG. 5, the digital waveform generating circuit 60 includes a sampling incremental phase memory 80, an adder 82, a data holding circuit 83, and a waveform memory 84. The adder 82 and the data holding circuit 83 constitute an address calculator 81.

  The sampling increment phase memory 80 is constituted by a ROM, for example, and outputs the sampling increment phase Ad based on the frequency setting signal Df including the address data of the phase increment memory 80 input from the controller 3. The adder 82 outputs addition data Aa obtained by adding the sampling increment phase Ad and the address data As that is the output signal of the data holding circuit 83 input to the previous waveform memory 84. The data holding circuit 83 holds the input addition data Aa and outputs it as address data As at the rising timing of the clock signal C. The address data As corresponds to the phase of the waveform data. The waveform memory 84 is composed of, for example, a ROM and stores discrete sine wave waveform data for one cycle. The waveform memory 84 outputs an output signal D1 which is a digital signal corresponding to the address data As input from the address calculator 81 at the rising timing of the clock signal C.

  6 (a), 6 (b), 6 (c), and 6 (d) respectively show the trigger signal generation circuit 4 when the frequency setting signal Df is changed in the digital waveform generation circuit 60 of FIG. It is a wave form diagram which shows the output signals D1, S1, S2, and P1. As shown in FIG. 6A, when the sampling increment phase Ad is doubled, the frequency of the output signal D1 is doubled. In this way, the frequency Fs of the output signal D1 can be changed by changing the sampling increment phase Ad by changing the frequency setting signal Df input to the sampling increment phase memory 80.

  The frequency Fs of the output signal D1 is expressed by the following equation (3) using the sampling increment phase Ad, where Fc is the frequency of the clock signal C and M is the number of data in the waveform memory 84.

[Equation 4]
Fs = (Ad / M) × Fc (4)

  As shown in the above equation (3), the output frequency Fs can be set more finely as the number of data M in the waveform memory 84 is larger. For example, when the frequency Fc of the clock signal C is 50 MHz and the number of data M in the waveform memory 84 is 65536, the frequency Fs of the output signal D1 can be finely set at intervals of about 0.0007629 MHz. If the fineness of the setting of the output frequency Fs is converted into a period, the period Tsi (i = 1, 2, 3,...) Can be set at a minute interval of about several ps although it varies depending on the output frequency Fs. With this configuration, the delay time from the transmission trigger signal Gt to the reception trigger signal Gr can be finely changed, and high distance resolution can be realized.

  6B, the D / A conversion circuit 61 in FIG. 3 converts the discrete output signal D1 into analog data having a stepped waveform, thereby generating an output signal S1. In FIG. 6, the LPF 62 generates the output signal S3 which is a smooth sine wave having a single frequency component by removing the high frequency component in the output signal S1, and the waveform shaping circuit 63 in FIG. The output signal P1, which is a pulse signal, is generated by comparing the amplitude of the sine wave, which is the signal S2, and the center value of the amplitude. As described above, the first variable period pulse generation circuit 41 generates the output signal P1 having a period corresponding to the frequency setting signal Df input from the controller 3. Further, by finely changing the frequency setting signal Df, the cycle of the output pulse signal P1 can be finely changed.

  7 (a), 7 (b), 7 (c) and 7 (d) show output signals D1 and D2, S1 and S2, S3 and S4, and P1 and P2 in the trigger signal generation circuit 4, respectively. It is a waveform diagram. In FIG. 7A, the digital fixed delay circuit 70 generates and outputs an output signal D2 by delaying the output signal D1 input from the digital waveform generating circuit 60 by a predetermined fixed delay time Td. In FIG. 7B, the D / A conversion circuit 71 of the variable period pulse generation circuit 42 outputs the output signal D2 output from the digital fixed delay circuit 70, similarly to the D / A conversion circuit 61 of the variable period pulse generation circuit 41. Is converted to analog data. In FIG. 7C, like the LPF 72 of the variable period pulse generation circuit 41, the LPF 72 of the variable period pulse generation circuit 42 removes noise in the output signal S3 of the D / A conversion circuit 71, thereby obtaining a smooth sine. Convert to wave S4. In FIG. 7D, similarly to the waveform shaping circuit 63 of the variable period pulse generation circuit 41, the waveform shaping circuit 73 of the variable period pulse generation circuit 42 includes the amplitude of the sine wave that is the output signal S4 of the LPF 72 and the center of the amplitude. The output signal P2 which is a pulse signal is generated and output by comparing the magnitude with the value.

  FIG. 8 is a circuit diagram showing a detailed configuration of the digital fixed delay circuit 70 of FIG. In FIG. 8, the digital fixed delay circuit 70 includes N delay flip-flops (hereinafter referred to as D-type flip-flops) 90-1 to 90-N connected in multiple stages. Each of the D-type flip-flops 90-1 to 90-N outputs the signal input to the input terminal D from the output terminal Q at the rising timing of the clock signal C. Therefore, as shown in the following equation (5), the fixed delay time Td is N times the cycle Fc of the clock signal C.

[Equation 5]
Td = n × Tc (5)

  In the digital fixed delay circuit 70, the output signal D2 is generated using the rising timing of the clock signal C. Therefore, the fixed delay time with respect to the output signal D1 can be accurately detected regardless of the delay time and the temperature change. An output signal D2 delayed by Td can be generated.

  FIG. 9 is a characteristic diagram showing the relationship between the frequency indicating the output spectrum and the relative power in the digital waveform generating circuit 60 of FIG. In FIG. 9, the frequency of the clock signal C is Fc, and the frequency of the output signal D1 is Fs. As shown in FIG. 9, since the output signals D1 and D2 input to the D / A conversion circuits 61 and 71 are discretized digital data, in addition to the component of the frequency Fs, the frequency spectrum includes A folding signal having a frequency Fi given by the following equation (6) is included.

[Equation 6]
Fi = Fc × a ± Fs (a: natural number) (6)

  In the above equation (4), according to the Nyquist sampling theorem, when the frequency Fs of the output signals D1 and D2 is set to a frequency larger than ½ of the frequency Fc, the folded signal having the frequency component Fc−Fs is obtained from the frequency Fs. Since it occurs in a low frequency band, it becomes difficult to design the LPFs 62 and 72 for extracting only the frequency component of the frequency Fs. Therefore, by setting the frequency Fs to a frequency band lower than 1/2 of the frequency Fc and causing the frequency component of the aliasing signal to appear in a frequency band that is higher than the output frequency Fs and away, the general LPFs 62 and 72 can be easily used. The folding signal can be removed. Therefore, the relationship between the frequency Fs and the frequency Fc of the clock signal C is expressed by the following equation (5).

[Equation 7]
Fs <(1/2) × Fc (7)

  By removing the aliasing signal which is an unnecessary harmonic component, the output signals S2 and S4 which are smooth cosine waves can be obtained in the LPFs 62 and 72, respectively, and are generated by the waveform shapers 63 and 73 in the subsequent stage. The rising jitter components of the output signals P1 and P2 can be reduced, and the error of the period Tsi (i = 1, 2, 3,...) In the above equation (2) can be reduced. As a result, the accuracy of the delay time Tri (i = 1, 2, 3,...) Between the transmission timing and the detection timing can be improved. As the LPFs 62 and 72, for example, a seventh-order elliptic low-pass filter known to have a steep frequency cutoff characteristic may be used in order to effectively remove an unnecessary aliasing signal.

  Also, from the above equations (3) and (5), the relationship between the cycle Tsi (i = 1, 2, 3,...) Of the output signal P1 and the cycle Tc of the clock signal C is expressed by the following equation (8), and the frequency The relationship between Fs and frequency Fc is expressed by the following equation (9).

[Equation 8]
Tsi ≧ n × Tc (i = 1, 2, 3,...) (8)

[Equation 9]
Fs ≦ (1 / n) × Fc (9)

  Therefore, in order to satisfy the expressions (7) and (9) at the same time, the number N of the D-type flip-flops 90-1 to 90-N in the digital fixed delay circuit 70 may be set to at least 3 or more. Finally, the relationship between the frequency Fs and the frequency Fc is expressed by the following equation (10).

[Equation 10]
Fc ≧ 3 × Fs (10)

  When the number N of the D-type flip-flops 90-1 to 90-N in the digital fixed delay circuit 70 is increased, the fixed delay time Td is increased from the above equation (5), and the period Tsi (i) is calculated from the above equation (3). = 1, 2, 3, ...) increases. Therefore, the frequency Fs is lowered, and the frequency Fc of the clock signal C is lowered from the above equation (10). That is, by increasing the number N of the D-type flip-flops 90-1 to 90-N in the fixed delay circuit 90, the frequency Fc of the clock signal C is reduced. As a result, the cost and power consumption of the pulse radar device 1 are reduced. Can be reduced.

  In the pulse radar device 1 described above, for example, the frequency Fc of the clock signal C is set to 50 MHz, that is, the period Tc is set to 20 ns, the number N of the D-type flip-flops 90-1 to 90-N in the digital fixed delay circuit 70 is set to 5, That is, the fixed delay time Td is set to 100 ns, the frequency Fs is changed in the band from 7.1285 to 10 MHz, and the delay time Tri (i = 1, 2, 3,...) Is changed in the range from 100 ns to 140 ns. In this case, a fixed delay time Td from 0 ns to 40 ns corresponding to the search range 0 to 6 m can be generated. According to the above equation (10), the frequency Fc of the clock signal C may be 30 MHz, but by setting this to 50 MHz, the output frequency Fs and the frequency Fi of the folded signal appear in frequency bands that are further away from each other. A higher filter effect is obtained.

  As described above, according to the pulse radar device 1 of the present embodiment, the variable period pulse generation circuit that generates and outputs the output signal D1 having a different period according to the frequency setting signal Df based on the clock signal C. 41 and the digital fixed delay circuit 70 operating based on the clock signal C, the output signal D1 is delayed by a predetermined fixed delay time Td, and then the output signal P2 is generated based on the delayed output signal D2. A variable period pulse generating circuit 42 for outputting, a reception trigger signal generating circuit 43 for generating and outputting a reception trigger signal Gr based on the output signal P1, and a transmission trigger signal Gt for generating the transmission trigger signal Gt based on the output signals P1 and P2. Since the trigger signal generation circuit 4 including the transmission trigger signal generation circuit 44 for output is provided, it exists in the surroundings with high accuracy regardless of the ambient temperature change. Object can be detected that.

  In this embodiment, the waveform memory 84 stores sine wave waveform data for one cycle. However, the present invention is not limited to this, and a cosine wave for one cycle may be stored instead of the sine wave. . By using a sine wave or cosine wave, after converting it to an analog signal, it is possible to easily remove only the required single frequency component by removing unnecessary harmonics with a low-pass filter, so that the accuracy can be improved. effective. Further, the waveform memory 84 may store waveform data of a sine wave for a half cycle and generate a sine wave for one cycle by using the symmetry of the sine wave. There is an effect that the data capacity can be reduced.

  Further, the controller 3 is controlled so that the frequency Tsi is gradually increased every time the frequency setting signal Df repeats the repetition period P. However, the present invention is not limited to this, and the period 3 is repeated every time the repetition period P is repeated. It may be controlled so that Tsi is gradually shortened.

  According to the pulse radar device of the present invention, the first signal generator that generates and outputs the first output signal having a different period according to the input frequency setting signal based on the input clock signal. And delaying the first output signal by a predetermined fixed delay time using a digital fixed delay circuit that operates based on the clock signal, and then generating a second output signal based on the delayed first output signal A second signal generator for outputting, a reception trigger signal generator for generating and outputting a reception trigger signal based on the first output signal, and on the basis of the first output signal and the second output signal Since the trigger signal generation unit including the transmission trigger signal generation unit that generates and outputs the transmission trigger signal is provided, it is possible to detect an object existing in the vicinity with high accuracy regardless of the ambient temperature change.

  The pulse radar apparatus according to the present invention can be used as an in-vehicle pulse radar apparatus using UWB, for example.

1 is a block diagram illustrating a configuration of a pulse radar device 1 according to an embodiment of the present invention. It is a wave form diagram which shows the signal of each part of the pulse radar apparatus 1 of FIG. FIG. 2 is a block diagram illustrating a detailed configuration of a trigger signal generation circuit 4 in FIG. 1. FIG. 4 is a waveform diagram showing signals at various parts in the reception trigger signal generation circuit 43 and the transmission trigger signal generation circuit 44 of FIG. 3. FIG. 4 is a block diagram showing a detailed configuration of a digital waveform generation circuit 60 in FIG. 3. (A), (b), (c), and (d) are output signals D1, S1, S2, and D2 in the trigger signal generation circuit 4 when the frequency setting signal Df is changed in the digital waveform generation circuit 60 of FIG. It is a wave form diagram which shows P1. (A), (b), (c) and (d) are waveform diagrams showing output signals D1 and D2, S1 and S2, S3 and S4, and P1 and P2 in the trigger signal generating circuit 4, respectively. FIG. 4 is a circuit diagram showing a detailed configuration of a digital fixed delay circuit 70 in FIG. 3. It is a characteristic view which shows the relationship between the frequency which shows the output spectrum in the digital waveform generation circuit 60 of FIG. 3, and relative electric power. It is a block diagram which shows the structure of the pulse radar apparatus 100 which concerns on a prior art example. It is a wave form diagram which shows the transmission signal Pt and the reception signal Pr in the pulse radar apparatus 100 of FIG.

Explanation of symbols

1 ... Pulse radar device,
2 ... object,
3 ... Controller,
4 ... trigger signal generation circuit,
5 ... Wireless transmission circuit,
5a: Transmitting antenna,
6 ... wireless receiver circuit,
6a: receiving antenna,
7: Signal processing circuit,
41, 42 ... variable period pulse generation circuit,
43. Reception trigger signal generation circuit,
44. Transmission trigger signal generation circuit,
50 ... DDS,
60: Digital waveform generation circuit,
61, 71 ... D / A converter,
62, 72 ... Low-pass filter (LPF)
63, 73 ... waveform shaper,
70: Digital fixed delay circuit,
80 ... Sampling incremental phase memory,
81: Address calculator,
82 ... adder,
83. Data holding circuit,
84: Waveform memory,
90-1 to 90-N D-type flip-flops.

Claims (4)

In a pulse radar apparatus that detects a surrounding object by outputting a pulse signal and receiving at least part of a reflected wave of the pulse signal,
A trigger signal generator for generating and outputting a transmission trigger signal for providing a transmission timing for radiating the pulse signal and a reception trigger signal for providing a detection timing for receiving at least a part of the reflected wave;
The trigger signal generator is
A digital waveform generation circuit for generating and outputting a first digital output signal having a different period according to the input frequency setting signal based on the input clock signal; and based on the first digital output signal A first signal generator for generating and outputting a first variable period pulse output signal;
The digital fixed delay circuit that operates based on the clock signal is used to delay the first digital output signal by a predetermined fixed delay time, and then a second variable based on the delayed first digital output signal. A second signal generator for generating and outputting a periodic pulse output signal;
A reception trigger signal generator for generating and outputting the reception trigger signal based on the first variable period pulse output signal;
A pulse radar apparatus comprising: a transmission trigger signal generation unit configured to generate and output the transmission trigger signal based on the first variable period pulse output signal and the second variable period pulse output signal.   2. The pulse radar apparatus according to claim 1, wherein the digital fixed delay circuit is a plurality of stages of delay flip-flops connected in cascade.   The first signal generator generates a sine wave or cosine wave digital signal having a different period according to the frequency setting signal, and generates and outputs the first output signal based on the digital signal. The pulse radar device according to claim 1 or 2, wherein   4. The pulse radar device according to claim 1, wherein the fixed delay time is a natural number multiple of a period of the clock signal. 5.

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