JP2009038208A - Semiconductor device and its production process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is equipped with a protective diode to protect a semiconductor element such as MOSFET from insulation breakdown, suppress a leakage current which may be caused on the protective diode at the time of low voltage, and can supply a greater amount of current when high voltage is applied, such as in the case of coming of surge. <P>SOLUTION: A grain size of polycrystalline semiconductor is made larger than that of the conventional semiconductors by forming a protective diode with a polycrystalline semiconductor which is obtained by crystallizing an amorphous semiconductor by thermal processing. This improves characteristics of the protective diode, makes it easier to have a thinner gate insulating film in an insulating gate type semiconductor and attain miniaturization (reduction in input capacity) of chip size. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a protection diode that protects a MOSFET, an insulated gate bipolar transistor (IGBT), and the like from dielectric breakdown, and a manufacturing method thereof.

For example, Patent Document 1 describes a semiconductor device having a MOSFET and a protective diode connected between its gate and source on the same chip. When the gate insulating film is thinned to reduce the gate threshold voltage in the FET or the input capacitance is reduced by downsizing the chip, dielectric breakdown is likely to occur even with small energy such as static electricity. For this reason, a Zener diode is formed as the above-described protective diode in polycrystalline silicon provided on the semiconductor substrate via an insulating film, and the gate insulating film of the FET is protected from electrostatic breakdown.
JP-A-1-202867

  FIG. 7 shows a cross-sectional TEM image of polycrystalline silicon used in a conventional protection diode. The protection diode as described above is required to have a characteristic that a current that flows when a low voltage is applied is low and a current that flows when a high voltage is applied such that a surge such as static electricity enters. However, as shown in FIG. 7, the grain size of polycrystalline silicon is as small as about 50 to 100 nm. If the grain size is small, the leakage current increases. For this reason, if the impurity concentration introduced into the polycrystalline silicon is increased in order to flow a large current when a high voltage is applied, the junction leakage increases and the current flowing when the low voltage is applied cannot be sufficiently suppressed. Conversely, if the impurity concentration is reduced to suppress the leakage current, a sufficient current cannot be supplied when a high voltage is applied. If the Zener diode, which is a protective diode, cannot sufficiently release electric charge, it will eventually cause breakdown of the transistor.

  The present invention solves the above-mentioned problems of the prior art, and does not increase the leakage current when a protective diode is applied with a low voltage, and more current is applied when a high voltage is applied such as a surge such as static electricity. An object of the present invention is to provide a semiconductor device that realizes a protection diode that can flow a current and a method for manufacturing the same.

  In order to achieve the above-mentioned object, the present invention suppresses a leakage current when a low voltage is applied and allows a large current to flow when a high voltage is applied, by forming the protective diode from a polycrystalline semiconductor having a large grain size. A structure that can be made.

  A semiconductor device provided by the present invention includes a protective diode that protects a semiconductor element formed on a substrate on the same substrate from dielectric breakdown, and the protective diode is a polycrystal obtained by crystallizing an amorphous semiconductor film by heat treatment. It is formed in a semiconductor film. The average grain size of the crystal grains in this polycrystalline semiconductor film can be larger than 200 nm.

  In another aspect, the present invention provides a method for manufacturing a semiconductor device including a protection diode that protects a semiconductor element formed on the same substrate from dielectric breakdown. This method for manufacturing a semiconductor device includes a step of forming an amorphous semiconductor and a step of crystallizing the amorphous semiconductor by heat treatment to form a polycrystalline semiconductor used for the protection diode. The average grain size of the polycrystalline semiconductor can also be made larger than 200 nm.

  In the present invention, the material of the protection diode is made of an amorphous semiconductor, so that the grain size after crystallization can be increased, and the leakage current when a low voltage is applied to the protection diode can be reduced. For this reason, it is possible to flow more current when applying a high voltage without increasing the leakage current when a low voltage is applied to the protection diode. In the device, it is easy to reduce the thickness of the gate insulating film and reduce the chip size (lower input capacitance).

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention. In this semiconductor device, a transistor cell portion (FET portion 101) of a vertical MOSFET and a protection diode portion 102 that protects the gate insulating film of the FET portion 101 from electrostatic breakdown are formed on the same semiconductor substrate 103. .

  For example, an n− type semiconductor layer (hereinafter referred to as an epitaxial growth layer) 104 is formed on the n + type semiconductor substrate 103 by epitaxial growth. In the FET portion 101, a p-type body region 105 of reverse conductivity type and an n + type source region 106 of the same conductivity type are formed on the surface side of the epitaxial growth layer 104. Further, in the FET portion 101, a trench groove 107 is formed that reaches from the source region 106 through the body region 105 to the epitaxial growth layer 104. A gate insulating film 108 made of an insulating layer such as silicon dioxide is provided on the inner wall of the trench groove 107. A gate electrode 109 made of a semiconductor (for example, n-type polycrystalline silicon) buried in the trench groove 107 is insulated from the source region 106, the body region 105, and the epitaxial growth layer 104 by the gate insulating film 108. The source electrode 110 is connected to the source region 106 and the body region 105 from a body contact region (not shown), and is insulated from the gate electrode 109 by the insulating layer 111. A drain electrode (not shown) is formed on the back surface of the semiconductor substrate 103.

  In the protection diode portion 102, a Zener diode connected to the gate electrode 109 and the source electrode 110 is formed. In the protection diode portion 102, a polycrystalline semiconductor 112 such as polycrystalline silicon is formed on the epitaxial growth layer 104 via an insulating layer 113. In this polycrystalline semiconductor, an n-type semiconductor region 114 and a p-type semiconductor region 115 constituting a pn junction of a Zener diode are formed. The n-type region adjacent to the FET portion 101 is connected to the source electrode 110, and the n-type region in the center of the protection diode portion 102 is connected to the gate electrode 109 via the electrode 116.

  FIG. 2A shows a plan view of the protection diode portion, and FIG. 2B shows an equivalent circuit. As shown in the plan view, in the protection diode portion, the n-type regions 114 and the p-type regions 115 are alternately arranged concentrically and have an npnpn connection structure. In this structure, the outermost n-type region 114a is connected to the source electrode 110, and the central n-type region 114b is connected to the gate electrode 109 via the electrode 116 made of Al or the like. For this reason, as shown in the equivalent circuit, a bidirectional Zener diode is connected as a protection diode between the gate and the source of the FET.

  FIG. 3 shows an example of a cross-sectional TEM image of polycrystalline silicon used in the protection diode portion in this embodiment. In this example, the polycrystalline silicon used for the protection diode has an average grain size of 200 nm. This polycrystalline silicon is obtained by changing the crystalline state of amorphous silicon by heat treatment. More specifically, it is exposed to an atmosphere at 750 ° C. while being carried into a batch-type heat treatment furnace whose temperature in the furnace is controlled at 750 ° C. at about 50 mm / min for about 30 minutes. Silicon is obtained. As a result, the grain size of the conventional polycrystalline silicon is about 50 nm to 100 nm (FIG. 7), but the grain size in this example is larger than that overall. Thus, the characteristics as a protective diode are improved by making the grain size of polycrystalline silicon 200 nm or more and 10 μm or less using amorphous silicon.

  FIG. 4 shows an example of voltage-current characteristics of the protection diode in this embodiment. The horizontal axis is the applied voltage (V), and the vertical axis is the current (A) flowing through the diode. The white rhombus indicates the characteristics of the protection diode in this embodiment, and the black rhombus indicates the characteristics of the conventional protection diode. The protection diode in this example is a protection diode for a transistor having an actual use voltage of 4 V and a maximum rated voltage of 10 V, and the current flowing between the gate and source below the actual use voltage and the maximum rated voltage must be kept as low as possible. . Specifically, the maximum rated voltage is set to 3 μA or less, and a gate leakage current is generated when a voltage is applied to the gate. Also, in order to protect the gate oxide film when a high voltage surge is applied to the gate, a large amount of current needs to flow through the protection diode when a high voltage is applied.

  This protective diode uses the polycrystalline silicon shown in FIG. 3 and has an average grain size of 200 nm, which is larger than the conventional one, so that the leakage current when applying a low voltage is suppressed as compared with the conventional one. . As shown in FIG. 4, the current at the maximum rated voltage is set to an allowable value, and the gate leakage current at the actual use voltage is also smaller than that of the conventional protection diode, so that excessive power consumption can be suppressed.

  On the other hand, as shown in the voltage-current characteristics of FIG. 4, when a high voltage is applied, the slope is significantly larger than in the conventional case, and a large current can flow. For example, when 15 V is applied, a current about 500 times that of the conventional protection diode flows. As a result, when a high voltage such as a surge is applied from the outside of the element, the charge that has entered through the diode in a shorter time can be released. For this reason, even when surges such as static electricity enter from the outside when the thickness of the gate insulating film is reduced and the breakdown voltage is further reduced, it is possible to release charges more than conventional protection diodes, and the breakdown against static electricity Durability is significantly improved. In addition, it is effective to remarkably improve the breakdown tolerance even with a smaller chip (low input capacitance).

  FIG. 5 shows an example of the electrostatic breakdown voltage of the MOSFET provided with the protection diode in this embodiment. The horizontal axis indicates between terminals, and the vertical axis indicates MM (machine model) -ESD. Each plot shows data of a protection diode (white triangle, white circle) and a conventional diode (black triangle, black circle) in this embodiment having an input capacitance (Ciss) of 100 pF and 300 pF. In addition, since the electrostatic breakdown voltage is more than 1000 V between the drain and the source, only “1000 V or more” is described.

  As shown in this figure, in a MOSFET with a conventional protection diode, charge cannot be sufficiently released by the protection diode. Therefore, when the input capacitance is reduced, electrostatic breakdown is likely to occur at a lower voltage. Yes. On the other hand, in the MOSFET provided with the protection diode in the present embodiment, the charge is released satisfactorily, and the withstand voltage between the terminals is 200 V or more regardless of whether the input capacitance of the MOSFET is 300 pF or 100 pF. That is, compared to the case where a conventional protection diode is provided, the electrostatic breakdown resistance of the MOSFET provided with the protection diode in this embodiment is significantly improved, and a smaller chip (lower input capacitance) is designed and produced. It becomes possible.

(Second Embodiment)
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.

  6A to 6D are cross-sectional explanatory views for explaining the steps of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 6A, an n − type semiconductor having a specific resistance of about 0.1 to several tens of Ω · cm and a thickness of about several μ to several tens of μm by epitaxial growth on the surface of an n + type semiconductor substrate 601. Layer 602 is formed. An oxide film 603 is formed on the surface of the semiconductor layer 602 using a thermal oxidation method or a CVD method, a resist mask is formed, p-type impurities are introduced, and a body region 604 of a transistor cell is formed. Subsequently, a resist mask is formed to form the trench groove 605, and a trench groove 605 that reaches the semiconductor layer 602 through the oxide film 603 and the body region 604 is formed by anisotropic etching.

Next, as shown in FIG. 6B, a gate insulating film 606 made of a silicon oxide film (or a laminated film of a silicon oxide film, a silicon nitride film, a silicon oxide film, etc.) is formed by thermal oxidation or CVD, Amorphous silicon 607 having a thickness of about 100 nm to 1000 nm used for a gate electrode or a protective diode is formed by a CVD method. For example, phosphorus is selectively implanted into the amorphous silicon 607a of the gate electrode by a resist mask in an amount of about 1e16 to 1e17 / cm ² , and in the protective diode portion, boron is used for 2e13 to 5e14 in order to form the p-type region 607b. About n / cm ^{2 is} implanted, and about 1e15 to 2e16 / cm ² of phosphorus or arsenic is selectively implanted into the n-type region 607c using a resist mask. Then, it is uniformly diffused in the amorphous silicon by heat treatment at 900 ° C. to 1000 ° C. By this heat treatment, the crystalline state of amorphous silicon changes to polycrystalline silicon, and at the same time, the grain size becomes larger than that of conventional polycrystalline silicon.

  Although described as 900-1000 degreeC here, in order to enlarge a grain size, you may heat-process previously at the low temperature of 560 degreeC-900 degreeC. For example, even when diffusion and activation are performed on the ion-implanted impurities by heat treatment at 950 ° C., as described in the first embodiment, the batch-type heat treatment furnace in which the furnace temperature is controlled to 750 ° C. is set to 50 mm / If it takes about 30 minutes, the grain size is basically determined at that stage. During the loading, the amorphous silicon is exposed to an atmosphere of 750 ° C. for a sufficient time, and the grain growth ends. For this reason, the grain size of polycrystalline silicon is basically determined at that stage, and it is assumed that diffusion and activation of impurities are carried out by raising the furnace temperature to 950 ° C. continuously (8 ° C./min) after loading. However, the grain size does not vary greatly. The grain size change due to the heat treatment is dominated by the influence on the first temperature zone where the amorphous state changes to the polycrystalline state. Even if heat treatment is subsequently applied, the grain size does not vary greatly unless the temperature is increased to 1200 ° C. or higher. Moreover, when it is slowly crystallized at a relatively low temperature, the grains grow greatly. In the case of heat treatment at 560 ° C., a very large particle size of about 10 μm can be obtained by taking time. Further, the order of injection is not important, and the same effect can be obtained no matter which is first.

  Subsequently, as shown in FIG. 6C, the protection diode portion 608 and the gate electrode lead portion (not shown) are patterned with a resist mask, and the polycrystalline silicon is etched using an etching method, so that the transistor portion 609 and the protection diode portion 608 are formed. Is patterned. At this time, the gate electrode 610 is formed from polycrystalline silicon embedded in the trench groove 605.

  Further, as shown in FIG. 6D, for example, an n-type source region 611 and a p-type contact region (not shown) of the body region 604 are formed by implantation using a resist mask. Further, an insulating film 612 is formed by a CVD method, patterned using a resist mask, and then electrode contacts of the transistor portion 609 and the protective diode portion 608 are formed by etching. Thereafter, an Al film 613 is formed by a PVD method or the like, and a desired Al electrode is patterned by a resist mask and etching. Finally, a protective film to be a passivation 614 is formed with a plasma silicon nitride film or a polyimide and patterned.

  According to the above-described manufacturing method, since the protective diode is formed using amorphous silicon as a material, the grain size of polycrystalline silicon obtained by modifying the amorphous silicon after the heat treatment becomes larger than that of the conventional technique (FIG. 3: cross-sectional TEM). As a result, the diode characteristics are remarkably improved (FIG. 4: diode characteristics). As a result, even if the gate oxide film thickness is reduced and the breakdown voltage drops, if a surge such as static electricity enters from the outside, charges can be released more than conventional protection diodes, and the breakdown resistance against static electricity is significantly improved. It becomes possible to make it. In addition, it is effective to remarkably improve the breakdown tolerance even with a smaller chip (low input capacitance).

  In each of the above-described embodiments, the first conductivity type of the MOSFET is described as n-type and the second conductivity type is described as p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. A similar effect can be obtained with a MOSFET. In addition, although a trench type MOSFET has been described as a vertical transistor, a Zener diode is used as a protective element, such as a MOSFET with a channel portion on the surface or another insulated gate semiconductor element such as an insulated gate bipolar transistor (IGBT). It is also effective for other semiconductor devices.

  As described above, the present invention is useful for a semiconductor device including a protection diode such as a MOSFET or an insulated gate bipolar transistor (IGBT), a manufacturing method thereof, and the like.

The figure which shows the cross-section of the semiconductor device which concerns on the 1st Embodiment of this invention. Diagram for explaining protection diode The figure which shows an example of the cross-sectional TEM image of the polycrystalline silicon used for the protection diode part in 1st Embodiment The figure which shows an example of the voltage-current characteristic of the protection diode in 1st Embodiment The figure which compares the electrostatic breakdown voltage of MOSFET provided with the protection diode in 1st Embodiment with the electrostatic breakdown voltage of MOSFET provided with the conventional protection diode The figure for demonstrating the process of the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. The figure which shows an example of the cross-sectional TEM image of the protection diode part in the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 FET part 102 Protection diode part 103 Semiconductor substrate 104 Epitaxial growth layer 105 Body area | region 106 Source area | region 107 Trench groove | channel 108 Gate insulating film 109 Gate electrode 110 Source electrode 112 Polycrystalline silicon 114 N-type semiconductor area 115 P-type semiconductor area 601 Semiconductor substrate 602 n-type semiconductor layer 604 body region 605 trench groove 606 gate insulating film 607 amorphous silicon 608 protective diode portion 609 transistor portion 610 gate electrode 611 source region

Claims (4)

A protection diode for protecting a semiconductor element formed on the same substrate from dielectric breakdown,
A semiconductor device in which the protection diode is formed in a polycrystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by heat treatment.   The semiconductor device according to claim 1, wherein an average grain size of crystal grains in the polycrystalline semiconductor film is larger than 200 nm and smaller than 10 μm. A method for manufacturing a semiconductor device comprising a protective diode for protecting a semiconductor element formed on the same substrate from dielectric breakdown,
Forming an amorphous semiconductor film;
And crystallizing the amorphous semiconductor by heat treatment to form a polycrystalline semiconductor used for the protection diode.   The method for manufacturing a semiconductor device according to claim 3, wherein an average grain size of crystal grains in the polycrystalline semiconductor is larger than 200 nm and smaller than 10 μm.