JP2009037720A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a nonvolatile memory system which have a means for reducing writing errors in a nonvolatile semiconductor memory device of a multi-value storage method. <P>SOLUTION: In a nonvolatile semiconductor memory device of a multi-value storage method, when writing is completed earlier and verification is performed to a memory cell whose threshold level can be easily shifted, a plurality of verify voltages lower than a normal verify level are set and the plurality of verify voltages are switched step by step according to the number of times of applying a writing voltage pulse. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a nonvolatile semiconductor memory device configured using electrically rewritable nonvolatile memory cells.

A NAND flash memory using an EEPROM (Electronically Erasable and Programmable Read Only Memory) has been proposed as an electrically rewritable nonvolatile semiconductor memory device. In recent years, in order to realize a larger-capacity flash memory, various multi-value storage systems in which a single nonvolatile memory cell (hereinafter sometimes simply referred to as “memory cell”) stores multi-bit data have been proposed. (For example, refer to Patent Document 1).

In the multi-value storage system, a wide voltage region is divided into a plurality of voltage ranges from a low voltage region to a high voltage region and used as a memory cell threshold. When a threshold value is set in a higher voltage region, writing needs to be performed with a higher writing voltage.

When a high voltage region is set as a threshold for a memory cell to be written, and a memory cell adjacent on the same word line of the memory cell has already been written, and the memory cell that has already been written When the threshold voltage of the memory cell (that is, the adjacent memory cell) is in the low voltage region, the following phenomenon occurs when a high voltage is applied to the word line of the memory cell to be written. That is, since the same high voltage is applied to the word line of the adjacent memory cell that has already been written for a long time, the threshold value in the low voltage region of the adjacent memory cell is affected and transitions to the high potential side. Also, due to the recent reduction in design rules, capacitive coupling between a floating gate of a memory cell to be written and a floating gate of an adjacent memory cell cannot be ignored. For this reason, the threshold value of the memory cell for which writing has been completed may transition to the high potential side. If the threshold value of the adjacent memory cell is shifted to the high potential side and exceeds the range of the threshold value corresponding to the initially written data value, there is a problem that erroneous writing occurs.
JP 2003-196988 A

The present invention provides a nonvolatile semiconductor memory device that is a nonvolatile semiconductor memory device of a multi-value storage system and includes means for reducing erroneous writing.

A nonvolatile semiconductor memory device according to an embodiment of the present invention includes a memory in which a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set are arranged A cell array; a voltage generator for generating a plurality of voltages including a write voltage and a verify voltage applied to the nonvolatile memory cell; and the write voltage applied to the nonvolatile memory cell as a pulse voltage. A counter unit that counts the number of applied write voltage pulses, a plurality of verify voltage data set for each threshold level, and a reference voltage for switching the plurality of verify voltages. A storage unit that stores the number of applications, and the writing that the counter unit counts for each threshold level A comparison unit that compares the number of applied pressure pulses with the number of application of the write voltage pulse stored in the storage unit, and a voltage applied to the nonvolatile memory cell based on a comparison result of the comparison unit. And a control unit that performs verification control by switching a plurality of verification voltages in stages.

In addition, a nonvolatile semiconductor memory device according to another embodiment of the present invention includes a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set. An arrayed memory cell array; and a voltage generator for generating a plurality of voltages including a write voltage applied to the nonvolatile memory cell, a first write method verify voltage, and a second write method verify voltage; When the write voltage is applied as a pulse voltage to the nonvolatile memory cell, a counter unit that counts the number of write voltage pulses applied, and a plurality of first write methods set for each threshold level The verify voltage data and the write that is a reference for switching the verify voltages of the plurality of first write methods A storage unit that stores the number of applied voltage pulses, a number of application of the write voltage pulse counted by the counter unit for each threshold level, and a verification of the first write method stored in the storage unit. A comparison unit that outputs a comparison result comparing the number of voltage pulses applied as a reference for switching the voltage, and the plurality of applications applied to the nonvolatile memory cell based on the comparison result of the comparison unit And a controller that switches the verify voltage of the first write method stepwise and controls the bit line potential of the memory cell array based on the verify result of the first write method. .

In addition, a nonvolatile semiconductor memory device according to another embodiment of the present invention includes a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set. An arrayed memory cell array; and a voltage generator for generating a plurality of voltages including a write voltage applied to the nonvolatile memory cell, a first write method verify voltage, and a second write method verify voltage; When the write voltage is applied as a pulse voltage to the nonvolatile memory cell, a counter unit that counts the number of write voltage pulses applied, and a plurality of second write methods set for each threshold level The verify voltage data and the write that serves as a reference for switching the verify voltages of the plurality of second write methods A storage unit that stores the number of applied voltage pulses, a number of application of the write voltage pulse counted by the counter unit for each threshold level, and a verification of the second write method stored in the storage unit. A comparison unit that outputs a comparison result comparing the number of voltage pulses applied as a reference for switching the voltage, and the plurality of applications applied to the nonvolatile memory cell based on the comparison result of the comparison unit And a control unit that switches the verify voltage of the second write method stepwise and controls the bit line potential of the memory cell array based on the verify result of the first write method.

According to an embodiment of the present invention, it is possible to provide a nonvolatile semiconductor memory device including means for reducing erroneous writing.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different modes and should not be construed as being limited to the description of the embodiments described below.

FIG. 1 shows a functional block configuration of a memory chip of a NAND flash memory according to the first embodiment of the present invention. FIG. 2 is a diagram showing an array of memory cells in the memory cell array 12. As shown in FIG. 2, the memory cell array 12 is configured by arranging a plurality of NAND cell units. Each NAND cell unit includes a plurality of electrically rewritable nonvolatile memory cells (for example, MC00-MC0n) and select gate transistors (for example, for connecting both ends to the source line CELSRC and the bit line BL, respectively). , S01, S02).

Control gates of memory cells MC00-MC0n are connected to different word lines WL0-WLn, respectively. The gates of the selection gate transistors S01 and S02 are connected to selection gate lines SGS and SGD parallel to the word line.

A set of NAND cell units sharing a word line constitutes a block serving as a data erasing unit. As shown in FIG. 2, a plurality of blocks BLK0, BLK1,... Are arranged in the normal bit line direction.

The row decoder 10 includes a word line driving circuit that selects a word line of the memory cell array 12 and drives the word line.

The column decoder 14 selects a bit line. The sense amplifier circuit 13 is connected to a bit line of the memory cell array 12 and holds data to be written and read through a sense amplifier circuit that temporarily holds input / output data, and holds write data and read data. Has a data latch function.

At the time of data reading, the data read to the sense amplifier circuit 13 is output to the external input / output terminals I / O1 to I / O8 via the I / O control circuit 2.

At the time of data writing, write data supplied from the external controller to the input / output terminals I / O 1 to I / O 8 is loaded into the sense amplifier circuit 13 via the I / O control circuit 2.

A command supplied from the input / output terminals I / O 1 to I / O 8 via the I / O control circuit 2 is decoded by the control signal generation circuit (internal controller) 8 via the command register 7. External control signals such as a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, an address latch enable signal ALE, and a command latch enable signal CLE are supplied from the outside via a logic control circuit 3 as a control signal generation circuit. 8 is supplied. The control signal generation circuit 8 performs data write / erase sequence control and data read control based on an external control signal and command supplied according to the operation mode.

The status register 5 is for notifying the outside of various states inside the chip. The status register 5 includes, for example, a ready / busy register that holds data indicating whether the chip is in a ready / busy state, a write status register that holds data indicating a write pass / fail, and the presence / absence of an erroneous write state ( An erroneous write status register for holding data indicating erroneous write verify pass / fail), an overwrite status register for holding data indicating presence / absence of overwrite state (overwrite verify pass / fail), and the like.

The ROM fuse 122 is formed by a memory cell having the same structure as the memory cell in the memory cell array 12, for example. The ROM fuse 122 may be formed in a region different from the memory cell array 12. Alternatively, it may be set in a part of the memory cell array 12. In FIG. 1, the memory cell array 12 is divided into a first storage area 121 and a second storage area. The first storage area 121 stores normal data, and the second storage area stores data different from the normal data as the ROM fuse 122. Furthermore, the ROM fuse 122 can also be constituted by a metal fuse.

The memory cell array 12 and the row decoder 10 require various high voltages Vpp (write voltage Vpgm, verify voltage Vr, write pass voltage Vpass, read voltage Vread, etc.) depending on the operation mode. The voltage generation circuit 9 is provided for generating these high voltages Vpp. The voltage generation circuit 9 is controlled by a control signal generation circuit 8.

Next, the write operation of the NAND flash memory will be described. FIG. 3 is a cross-sectional view showing an example of the configuration of the memory cell portion of the NAND flash memory. As shown in FIG. 3, for example, the basic unit of the memory cell portion of the NAND flash memory is composed of a plurality of memory cells MC00 to MC0n connected in series and two select gate transistors S01 and S02. The selection gate transistor S02 is connected to the bit line BL, and the selection gate transistor S01 is connected to a common source line CELSRC in the memory cell array. One memory cell uses an N-type diffusion layer 33 formed on a p-type well (p-well) 31 as a source / drain, and includes a control gate 35 and a floating gate (FG) 34 connected to the word line WL. Have. The amount of electrons injected into the floating gate (FG) 34 is controlled by changing the write voltage Vpgm applied to the word line and its application time. The threshold value (Vt) of the memory cell changes depending on the amount of electrons injected into the floating gate (FG) 34. Therefore, the threshold value (Vt) of the memory cell is controlled by the write voltage Vpgm.

FIG. 4 is a diagram showing an example of voltage application conditions to the NAND cell unit during the write operation. The write voltage Vpgm is applied to a word line to be written, for example, WL0. A large number of memory cells are arranged on one word line WL0. Writing to the memory cell is performed in units of one word line. In this specification, for convenience, the word line to be written may be referred to as a “selected word line”.

The write pass voltage Vpass is applied to the other non-selected word lines WL1 to WLn that are not write targets except WL0.

The write voltage Vpgm is applied to the selected word line WL0 while stepping up in a pulse manner at a voltage of, for example, about 14V to 20V so as to fall within the threshold range corresponding to the data to be written.

The selection gate transistor S02 arranged on the bit line BL0 side has a normal transistor structure having no floating gate (FG). A voltage slightly lower than the power supply voltage Vdd is applied to the gate. The selection gate transistor S01 on the source line side has the same structure as the selection gate transistor S02 on the bit line BL0 side. The potential of the gate is controlled to 0V.

As shown in FIG. 4, the potential of the bit line BL0 to be written is controlled to 0V through the sense amplifier circuit. When the memory cell on the selected word line to be written is set within the target threshold range and the writing is completed, the bit line potential is set to the power supply voltage Vdd through the sense amplifier circuit as in the bit line BL1 shown in FIG. It is controlled to become.

In the case of writing, 0V applied to the bit line BL0 is transferred to the memory cell before the select gate transistor S01. For this reason, when the write voltage Vpgm is applied to the selected word line WL0, the channel potential of the memory cell MC00 to be written becomes 0 V, and a potential difference of Vpgm is generated between the selected word line WL0 and the channel. Due to this potential difference, a Fowler-Nordheim (FN) tunnel current is generated, and electrons are injected into the floating gate (FG0). Due to the injected electrons, the distribution of the threshold value (Vt) of the memory cell MC00 is shifted to the positive side. On the other hand, other non-selected word lines WL1 to WLn that are not to be written except WL0 are applied with a write pass voltage Vpass that does not allow a Fowler-Nordheim (FN) tunnel current to flow. For this reason, the threshold value (Vt) distribution of the memory cells connected to the unselected word lines is hardly changed.

On the other hand, when writing into the memory cell is completed or when writing into the memory cell is not performed, the bit line potential is set to the power supply voltage Vdd through the sense amplifier circuit as in the bit line BL1 in FIG. Be controlled. A voltage slightly lower than Vdd is applied to the gate of the selection gate transistor S12. For this reason, the select gate transistor S12 is cut off. As a result, the channels of the memory cells MC10 to MC1n are in a floating state. In this state, when Vpass or Vpgm is applied to the word lines WL0 to WL, the channel potential of the memory cells MC10 to MC1n is boosted and raised to, for example, about 8V. For this reason, the potential difference between the selected word line WL0 and the channel does not increase. That is, the FN tunnel current does not flow, and the threshold (Vt) distribution of the memory cell hardly shifts.

In the following, a data writing method for controlling the storage operation of multi-value data by finely dividing the threshold value of one memory cell of the memory chip of the NAND flash memory will be described.

The amount of electrons injected into the floating gate (FG) 34 shown in FIG. 3 can be changed by controlling the write voltage value applied to the word line and the application time thereof. The threshold voltage of the memory cell (hereinafter sometimes simply referred to as “threshold”) varies depending on the amount of electrons injected into the floating gate (FG) 34 shown in FIG. Multi-value data can be stored by changing the threshold value (Vt) of the memory cell in accordance with the data to be stored. When data is written to the memory cell, the threshold value of the memory cell needs to be accurately controlled according to the data to be written. For this reason, for example, a writing method in which the voltage applied to the control gate of the memory cell gradually increases is executed. Such a writing method is called a “step-up writing method”.

FIG. 5 is a diagram illustrating an example of a step-up writing method. FIG. 5 shows that the write voltage (Vpgm) applied to one word line is applied step-up to a pulse shape. The vertical axis represents the write voltage (Vpgm), and the horizontal axis represents the number of times the program voltage (Vpgm) pulse is applied to the word line (number of program voltage applications). The width 51 of each step-up of Vpgm is, for example, 0.2V. The value of the initial write voltage pulse is, for example, 14V. Thereafter, the write voltage pulse is stepped up by 0.2V. Verification is performed at the bottom 52 between the peaks of the pulse, and a verify voltage is applied to the selected word line at the bottom 52, although not shown in FIG.

The verify voltage applied at the time of verify is set as a voltage corresponding to the lower limit value of the threshold distribution. In the case of the multi-value storage method, a range in which thresholds should be distributed is set according to write data, and the verify voltage is set as a voltage corresponding to the lower limit value of each threshold distribution. In the write operation, when the threshold level of the write target memory cell exceeds the verify voltage, the write to the memory cell is completed. For this reason, the potential of the bit line to which the NAND cell unit including the memory cell is connected is controlled from 0 V to Vdd.

Hereinafter, a case where multivalued data to be written in a memory cell is four values will be described as an example. FIGS. 6A to 6C are diagrams showing threshold value distributions of memory cells in the case of four values. In this specification, for convenience, a group of memory cells formed by the distribution of four threshold values is referred to as Level E, Level A, Level B, and Level C from the lowest threshold level. Further, a group name is substituted for a threshold value to be set in order to make a memory cell belong to each group. For example, a threshold value set for causing a memory cell to belong to the group Level A is referred to as Level A. The verify voltage corresponding to Level A is referred to as verify Level A, the verify voltage corresponding to Level B is referred to as Verify Level B, and the verify voltage corresponding to Level C is referred to as Verify Level C.

FIG. 7A is a distribution diagram showing variations in the number of times the write voltage is applied when a pulsed write voltage is applied to a plurality of memory cells before the verify Level A corresponding to Level A is exceeded. Similarly, FIG. 7B is a distribution diagram showing the variation in the number of times the write voltage is applied when the pulsed write voltage is applied to a plurality of memory cells before the verify Level B corresponding to Level B is exceeded. It is. FIG. 7C is a distribution diagram showing the variation in the number of write voltage application times when a pulsed write voltage is applied to a plurality of memory cells before the verify level C corresponding to the level C is exceeded.

Prior to the data write operation, all memory cells in the selected block are set to an erased state. For this reason, all the memory cells are in the state of the lowest threshold level E. When the threshold value of the memory cell is left at Level E, writing is not performed and the state at the time of erasing is maintained. In the step-up writing method, for example, the writing is finished first from the low threshold data. For example, when the threshold value of one memory cell is divided into four and stored, the writing of Level B and Level C ends in order from Level A having the lower threshold value.

However, since the thickness of the gate oxide film, the coupling ratio, and the like vary among the memory cells, the memory cells cannot be set within the same threshold range depending on the number of applied write voltages. For example, in the case where the threshold value is set to 1.0 V or more, a certain memory cell is set to a threshold value of 1.0 V by three pulse applications, but in another memory cell, it is finally 1.0 V by six pulse applications. There is a variation such as being set to the threshold value. The left side 71 of each distribution of FIGS. 7A to 7C shows a memory cell in which writing is completed (writing is completed early) with a small number of pulse applications. The right side 72 of the distribution shown in FIGS. 7A to 7C shows a memory cell in which writing is finished (writing is finished late) with a larger number of pulse applications.

Writing is performed in units of one word line in which a large number of memory cells are arranged. The write voltage Vpgm is applied to the selected word line to be written as a pulse voltage while stepping up. Therefore, among the memory cells arranged on the same selected word line, when writing is completed early as shown on the left side of the distribution in FIG. The write voltage Vpgm is continuously applied to the selection gate. For this reason, the threshold value of such a memory cell is easily shifted to the high potential side. In particular, when such a memory cell is adjacent to the selection gate transistor, a phenomenon in which the threshold value is shifted to the high potential side easily occurs.

Hereinafter, an example of a phenomenon in which the threshold value shifts to the high potential side will be described. FIG. 4 is a circuit diagram showing an example of voltage application conditions when writing is performed by selecting the word line WL0. FIG. 8 is a circuit diagram showing an example of voltage application conditions when writing is performed by selecting the word line WLn. The memory cell MC10 illustrated in FIG. 4 and the memory cell MC1n illustrated in FIG. 8 are memory cells in which a phenomenon in which the threshold value shifts to the high potential side is likely to occur.

First, a phenomenon in which the threshold value of the memory cell MC10 shifts to the high potential side will be described with reference to FIGS. 4 and 9A. FIG. 9A is a schematic cross-sectional view of the source line CELSRC, the selection gate transistor S11, and the memory cell MC10 when writing is performed by selecting the word line WL0.

Since the memory cell MC10 shown in FIG. 4 is set to a desired threshold level and writing is completed, Vdd is applied to the bit line BL1. This is because Vdd is applied to the bit line BL1 of the memory cell for which writing has been completed. The gate line SGS of the selection gate transistor S11 connected to the source line CELSRC is 0V. Thereby, the selection gate transistor S11 is cut off. Therefore, among the N-type diffusion layers of the selection gate transistor S11, the one connected to the source line CELSRC (CELSRC side diffusion layer) becomes 0 V that is the potential of the source line CELSRC. Note that 0V is an example. The potential of CELSRC may be Vdd (power supply voltage) higher than 0V. Even if the CELSRC potential is set to a potential higher than 0V, the same phenomenon occurs as described later.

In FIG. 9A, the drain of the select gate transistor S11 and the source of the memory cell MC10 share the N-type diffusion layer 33. Since the channel layer CH1 of the memory cell MC10 is in a floating state, the channel potential of the memory cell MC10 is boosted and raised to, for example, about 8V due to the influence of Vpgm applied to WL0. On the other hand, the potential of the CELSRC side diffusion layer is 0V. Therefore, a potential difference is generated between the CELSRC side diffusion layer of the select gate transistor S11 and the channel layer CH1 of the memory cell MC10, and electrons are accelerated from CELSRC toward the N-type diffusion layer 33. A pair of electrons and holes is formed at the end portion on the side of the select gate transistor S11, and the hole flows to the cell p-Well31. This phenomenon is called GIDL (Gate Induced Drain Leakage). There is also a phenomenon in which the generated pair of electrons and holes are pulled by the write voltage Vpgm applied to the control gate WL0 of the memory cell MC10 and injected into the floating gate FG of the memory cell MC10 with a certain probability. Arise. As a result, in the memory cell MC10 that has already been written, electrons are further injected into the floating gate FG, so that the threshold value changes in a higher direction. In the worst case, there is a possibility that the data value to be written and the threshold value cannot be matched and the erroneous writing is performed beyond the initially set threshold value range.

Similarly, a phenomenon in which the threshold value of the memory cell MC1n is shifted to the high potential side will be described with reference to FIGS. 8 and 9B. FIG. 9B is a schematic cross-sectional view of the bit line BL1, the select gate transistor S12, and the memory cell MC1n when writing is performed by selecting the word line WLn.

Since the memory cell MC1n shown in FIG. 8 is set to a desired threshold level and writing is finished, Vdd is applied to the bit line BL1. Since a voltage slightly lower than Vdd is applied to the selection gate line SGD of the selection gate transistor S12, the selection gate transistor S12 is cut off. Therefore, the potential on the bit line BL1 side of the select gate transistor S12 is Vdd because it is connected to the bit line BL1.

In FIG. 9B, the drain of the select gate transistor S12 and the source of the memory cell MC1n share an N-type diffusion layer. The channel layer CHn of the memory cell MC1n is affected by Vpgm in a floating state, and the channel potential of the memory cell MC1n is boosted and raised to about 8V, for example. On the other hand, the drain side N-type diffusion layer BL1 is Vdd. Therefore, a potential difference is generated between the drain-side N-type diffusion layer BL1 of the select gate transistor S12 and the channel layer CHn of the memory cell MC1n, and electrons are transferred from the drain-side N-type diffusion layer BL1 to the N-type diffusion layer 33. Accelerated, a pair of electrons and holes is formed at the end of the N-type diffusion layer 33 on the side of the selection gate transistor S12, and the same phenomenon as the above GIDL in which the holes flow to the cell p-Well 31 occurs. In addition, a phenomenon occurs in which the generated electron-hole pair electrons are pulled by the write voltage Vpgm applied to the control gate WLn of the memory cell MC1n and injected into the floating gate FG of the memory cell MC10 with a certain probability. As a result, in the memory cell MC1n in which writing has already been completed, electrons are further injected into the floating gate FG, so that the threshold value changes in a higher direction. In the worst case, there is a possibility that the data value to be written and the threshold value cannot be matched and the erroneous writing is performed beyond the initially set threshold value range.

FIG. 6A is a diagram showing an example of threshold value distribution of all memory cells in the memory cell array 121. FIG. 6B shows memory cells that are not adjacent to SGS and SGD (memory cells connected to the word lines WL1 to WLn-1 shown in FIGS. 4 and 8). Such memory cells are not adjacent to the select gate transistor. FIG. 3 is a diagram showing a distribution of threshold values. 6C shows a memory cell adjacent to SGS and SGD (a memory cell connected to the word lines WL0 and WLn shown in FIGS. 4 and 8). Such a memory cell is located at a position adjacent to the selection gate transistor. It is a figure showing the distribution of threshold values.

The threshold distribution of the memory cells adjacent to SGS and SGD shown in FIG. 6C is compared with the threshold distribution of the memory cells not adjacent to SGS and SGD shown in FIG. It is shown that the right side of the distribution is shifted to the higher potential side. As a result, the right side of the threshold distribution of all the memory cells shown in FIG. 6A is distributed on the high potential side.

Further, regardless of whether or not the memory cell is adjacent to SGS and SGD, the threshold distribution of the memory cell may transition to a higher potential side depending on the capacitance between the opposing side surfaces of the floating gate with the adjacent memory cell.

FIG. 10 is a diagram for explaining the capacitance between the opposing side surfaces of the floating gate with the adjacent memory cell. In FIG. 10A, a floating gate (FG) 1001 is surrounded by floating gates 1002, 1003, 1004, and 1005 positioned on the left, right, and top and bottom. When the design rule is reduced for the purpose of increasing the memory capacity, the distance between the floating gate 1001 and the floating gates 1002, 1003, 1004, 1005 adjacent thereto is reduced. For this reason, capacitive coupling occurs between the floating gates. This capacity is referred to as “capacity between opposing side surfaces”. Therefore, when the design rule is reduced, the capacitance between the opposing side surfaces between the floating gate 1001 and the floating gates 1002, 1003, 1004, and 1005 cannot be ignored. In addition, it is difficult to reduce the thickness of the insulating film formed between the floating gate and the control gate, which is why the capacitance between the opposing side surfaces cannot be ignored.

In FIG. 10A, the symbol of the capacitor between the floating gate 1001 and the floating gates 1002, 1003, 1004, and 1005 schematically indicates the existence of the capacitance between the opposing side surfaces that cannot be ignored. For example, when data is written to a memory cell having the floating gate 1001 and electrons are injected into the floating gate 1001, the potential of the floating gate 1001 is lowered. This change in potential of the floating gate 1001 also affects the adjacent floating gates 1002, 1003, 1004, and 1005 via the capacitance between the opposing side surfaces, and the potential of each floating gate is lowered. Therefore, apparently, the floating gates 1002, 1003, 1004, and 1005 adjacent to the floating gate 1001 are the same as the amount of electrons increased, and the threshold value of the memory cell having the floating gates 1002, 1003, 1004, and 1005 is increased. Will transition to a higher value. The greater the amount of electrons injected into the floating gate of the memory cell adjacent to the memory cell, the more prominent this effect is, and the threshold value of the memory cell transitions to a higher value. Further, the higher the ratio of the capacitance between the opposing side surfaces between the floating gates with respect to the total capacitance of the floating gate, the higher the threshold value of the memory cell. Such a phenomenon that the threshold value is increased by surrounding memory cells may be referred to as “inter-memory cell interference”.

Further, as the miniaturization progresses, as shown in FIG. 10B, the influence of the capacitance between the opposing side surfaces between the floating gates in the diagonal direction increases. That is, in addition to the memory cell interference by the floating gates 1002, 1003, 1004, and 1005 on the upper, lower, left, and right sides of the floating gate 1001, between the memory cells by the floating gates 1006, 1007, 1008, and 1009 arranged in the oblique direction of the floating gate 1001. An increase in threshold value due to interference also tends to occur.

FIG. 11 shows a cross section of the memory array in a direction parallel to the word line of the NAND flash memory. As shown in FIG. 11A with reference numerals, the cross section shows a floating gate cell structure. That is, there is a region 1101 that serves as a word line and a control gate, and an active region 1102 is provided on the lower surface thereof. Between the region 1101 and the active region 1102, there is a floating gate in a portion surrounded by the ONO film 1103, the insulating film 1104, and element isolation regions (Shallow Trench Isolation) 1105, 1106, 1107, 1108, and the like. ing.

Attention is now paid to the three floating gates FG1, FG2, and FG3 shown in FIGS. 11A to 11D as floating gates. FIG. 11A shows a state where all memory cells have been erased. In order to indicate this state, “E” is assigned to the floating gates FG1, FG2, and FG3, respectively. “E” can be interpreted to indicate that the threshold of the memory cell is at the lowest level.

Next, it is assumed that data is written in the memory cell having the floating gate FG2. Then, as shown in FIG. 11B, it is assumed that the threshold value of the memory cell having the floating gate FG2 is set to P2.

Next, it is assumed that data is written so that the threshold value of the memory cell having the floating gate FG1 is higher than the threshold value of the memory cell having the floating gate FG2. As shown in FIG. 11C, the threshold value of the memory cell having the floating gate FG1 is set to P1. Then, since the capacitance between the opposing side surfaces exists between the floating gates FG1 and FG2, the threshold value of the memory cell having the floating gate FG2 rises and changes to P2 '.

Further, it is assumed that data is written so that the threshold value of the memory cell having the floating gate FG3 is higher than the threshold value of the memory cell having the floating gate FG2. As shown in FIG. 11D, the threshold value of the memory cell having the floating gate FG3 is set to P3. Then, the floating gate FG2 is affected by the capacitance between the opposing side surfaces between the floating gates FG1 and FG3. As a result, the threshold value of the memory cell having the floating gate FG2 further increases and becomes P2 ″.

In FIG. 11, the memory cell interference of the memory cells arranged in the word line direction has been described. The memory cell interference of the memory cells arranged in the bit line direction can be similarly described.

FIG. 12 is a diagram for explaining the variation of the threshold value of the memory cell due to the influence of the capacitance between the opposing side surfaces described above. FIG. 12A shows the variation in the threshold value of the memory cell immediately after writing is performed using a certain verify level. In FIG. 12B, when writing is also performed on the memory cells around the memory cell, the threshold value variation of the memory cell is increased as a whole due to the influence of the capacitance between the opposite side surfaces. To do. If another read level exists in the section 1201, erroneous writing of data held in the memory cell occurs.

The occurrence of the threshold fluctuation due to the capacitance between the opposing side surfaces does not occur only in the memory cell array having the floating gate structure. For example, even in a charge trap type memory cell having a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure or the like, this phenomenon may occur as design rules are reduced.

One aspect of the present invention is that the verify voltage is stepped according to the number of times of application of the write voltage at the time of writing so as not to be erroneously written even if a threshold value transition as shown in FIGS. 6C and 12B occurs. This is a method using a writing method that steps up.

(First embodiment)
In the first embodiment of the present invention, the verification voltage is not set as a voltage corresponding to one lower limit value of the threshold distribution, but a plurality of multi-level verification voltages are set to voltages lower than the lower limit value of the threshold distribution. Thus, the verify voltage is switched depending on the number of application times of the write voltage. In the following, a four-value batch writing method will be described as an example. Note that the first embodiment of the present invention is not limited to the 4-value batch writing method, and can be implemented for multi-values such as 8-value and 16-value. In the first embodiment of the present invention, not only a method of writing memory cells connected to all bit lines on the same word line at a time, but also writing to memory cells on the same word line such as a bit line shield method. The writing method performed in several steps can also be implemented. Furthermore, not only a method of writing all threshold level data other than the erased state to memory cells on the same word line in a batch, but also a method of writing data of a specific threshold level first and data of another threshold level later. Can also be implemented.

FIG. 13A is a diagram showing that the write voltage (Vpgm) applied to the selected word line is stepped up by a pulse operation. FIG. 13B shows the verify voltage applied to the selected word line in the verify read operation performed after each pulse of the write voltage (Vpgm) falls and before the next write voltage pulse rises. FIG. As the verify voltage, a voltage corresponding to each of the threshold levels Level A, Level B, and Level C is applied.

In the example shown in FIG. 13B, the verify voltage corresponding to each threshold level is set as exemplified below. That is, for Level A, the verify voltage is set to, for example, four stages of the first verify voltage to the fourth verify voltage. The first verify voltage (A-1) after the first to third pulse application of each write voltage Vpgm, and the second verify voltage (A−) after the fourth to sixth pulse application of each write voltage Vpgm. 2) The third verify voltage (A-3) after the seventh to tenth pulse application of each write voltage Vpgm, and the fourth verify voltage (A−) after the eleventh pulse application of each write voltage Vpgm. 4) is used.

For Level B, the verify voltage is divided into three stages of the first verify voltage to the third verify voltage, and the first verify voltage (B-1) is applied after the first to sixth pulse application of each write voltage Vpgm. The second verify voltage (B-2) after the seventh to ninth pulse application of each write voltage Vpgm, and the third verify voltage (B-3) after the tenth and subsequent pulse application of each write voltage Vpgm. used.

For Level C, the verify voltage is divided into two stages of a first verify voltage and a second verify voltage, and the first verify voltage (C-1) is applied after the first to tenth pulse application of each write voltage Vpgm. The second verify voltage (C-2) is used after the 11th and subsequent pulses of each write voltage Vpgm.

The first embodiment of the present invention is not limited to that shown in FIGS. 13A and 13B, and various variations are conceivable. For example, Level B and Level C may be set as one verify voltage without being divided into a plurality of stages, or only Level C may be set as one verify voltage without being divided into a plurality of stages. Furthermore, more stages may be set.

Next, the configuration of means for realizing the method shown in FIGS. 13A and 13B will be described with reference to the block diagram of FIG. For example, initial setting data relating to a write operation is stored in the ROM fuse 122 shown in FIG. The initial setting data to be stored includes the number of threshold levels, data related to the verify voltage corresponding to each threshold level, settings for switching the verify voltage according to each threshold level, and the write voltage Vpgm for switching the verify voltage according to the threshold level. Step-up number, verify voltage, etc. In this specification, for the sake of convenience, the step-up number of the write voltage Vpgm that triggers switching of the verify voltage according to the threshold level is referred to as “verify voltage switching step-up number”.

Initial setting data relating to these write operations stored in the ROM fuse 122 or the like may be programmed before the memory is shipped, or input / output terminals I / O1 to I / O8 from an external controller (not shown). The data register / sense amplifier circuit 13 may be loaded through the I / O control circuit 2 and written into the ROM fuse 122 or the like.

When the power is turned on, the power-on reset circuit operates, and the control signal generation circuit 8 automatically reads the initial setting data including the data of the verify voltage switching step-up number to the data register / sense amplifier 13. The data of the control and verify voltage switching step-up number is transferred and held in the parameter register 4 and further transferred to the control signal generation circuit 8. The parameter register 4 may be included in the control signal generation circuit 8.

In the examples of FIGS. 13A and 13B, the verify voltage switching step-up data transferred from the ROM fuse 122 to the parameter register 4 is as follows. With respect to the threshold Level A, the verify voltage is switched when the number of step-ups is 3, 6, and 10, so that data indicating values of 3, 6, and 10 is transferred to the parameter register 4. With respect to the threshold Level B, the verify voltage is switched when the number of step-ups is 6 and 9, so that data indicating the values of 6 and 9 is transferred to the parameter register 4. As for the threshold Level C, the verify voltage is switched when the step-up number is 10, so that data indicating a value of 10 is transferred to the parameter register 4. The verify voltage switching step-up number data is transferred to the comparison circuit 16. Further, it may be held in the comparison circuit 16. The comparison circuit 16 may be included in the control signal generation circuit 8.

On the other hand, data corresponding to the verify voltages of the threshold levels A, B, and C stored in the ROM fuse 122 is transferred and held in the control signal generation circuit 8 through the parameter register 4. The data corresponding to the verify voltages of the threshold levels A, B, and C will be described with reference to the example shown in FIG. 13B. For the threshold level A, the four verify voltages are switched, and the first verify voltage is A-1. (For example, 0.1 V), the second verify voltage is A-2 (for example, 0.3 V), the third verify voltage is A-3 (for example, 0.5 V), and the fourth verify voltage is A-4 (for example, 0.7V). As for the threshold level B, the three verify voltages are switched, the first verify voltage is B-1 (for example, 1.5 V), the second verify voltage is B-2 (for example, 1.6 V), and the third verify voltage is Is data indicating B-3 (for example, 1.7 V). For the threshold Level C, switching between two verify voltages, the first verify voltage is C-1 (for example 2.6V), and the second verify voltage is C-2 (for example 2.7V).

The control signal generation circuit 8 is provided with a counter circuit (not shown), and is a value obtained by counting pulses (either rising or falling) when stepping up the write voltage generated by the voltage generation circuit 9 Hold. This count value is transferred to the comparison circuit 16. It may also be held.

The comparison circuit 16 compares the count value and the data of the verify voltage switching step-up number for each of the threshold levels Level A, Level B, and Level C, and transfers the result to the control signal generation circuit 8. The control signal generation circuit 8 generates a signal for controlling the verify voltage for each of the threshold levels Level A, Level B, and Level C based on the comparison result. The voltage generation circuit 9 generates a verify voltage for each of the threshold levels Level A, Level B, and Level C based on the control signal transferred from the control signal generation circuit 8.

It is considered that the shift amount of the threshold level due to GIDL is larger as the memory cell has a lower threshold level and smaller as the memory cell has a higher threshold level. Therefore, in the above example, it is desirable to increase the step width of the verify voltage for the threshold Level A and to decrease the step width of the verify voltage as the threshold Level B and the threshold Level C are reached.

Table 1 shows the relationship between the verify voltages of the threshold levels A, B, and C and the number of pulse application times of the write voltage Vpgm shown above. The numerical values listed in Table 1 are merely examples, and the present invention is not limited to this. There are many variations in the number of verify voltage switches, the respective verify voltage values, and the number of verify voltage switching steps.

Based on the result of comparing the counter value and the step-up number by the comparison circuit 16, the control signal generation circuit 8 controls the voltage generation circuit 9 as follows according to the threshold level. While the number of step-ups is 2 or less, the control signal generation circuit 8 generates voltages so that the threshold levels A, B, and C generate the first verify voltages (A-1, B-1, and C-1), respectively. The circuit 9 is controlled.

While the step-up number is 3 to 5, the control signal generation circuit 8 sets the second verify voltage (A-2) for the threshold Level A, and the first verify voltage (B-1) for the threshold Levels B and C. , C-1) is controlled.

While the step-up number is 6 to 8, the control signal generation circuit 8 applies the third verify voltage (A-3) for the threshold Level A and the second verify voltage (B-2) for the threshold Level B. For the threshold Level C, the voltage generation circuit 9 is controlled so as to generate the first verify voltage (C-1).

When the step-up number is 9, the control signal generation circuit 8 sets the third verify voltage (A-3) for the threshold Level A and the third verify voltage (B-3) for the threshold Level B. The voltage generation circuit 9 is controlled so as to generate the first verify voltage (C-1) for Level C.

After the step-up number is 10, the control signal generation circuit 8 sets the fourth verify voltage (A-4) for the threshold Level A, the third verify voltage (B-3) for the threshold Level B, and the threshold Level C. For the above, the voltage generation circuit 9 is controlled so as to generate the second verify voltage (C-2).

FIG. 20 is a flowchart for explaining the flow of processing when the nonvolatile semiconductor memory device according to the first embodiment of the present invention writes data to the memory cell. In step S2001, the count value of the counter circuit is initialized. For example, it is initialized to 1. In step S2002, the write voltage (Vpgm) value is determined. Since the write voltage is stepped up as described above, the value of the write voltage is mainly determined by the count value of the counter circuit. In step S2003, the write voltage (Vpgm) determined in step S2002 is applied to the selected word line to perform data write.

Next, as the processing in step S2004, the value of the verify voltage corresponding to the threshold value is determined. That is, depending on whether the threshold value of the memory cell into which data is written is Level E, Level A, Level B, or Level C, and the comparison result by the comparison circuit 16 using the count value of the counter circuit, The voltage is determined. Further, as described below, the verify voltage may be determined in consideration of the position of the selected word line.

In step S2005, the verify voltage determined in step S2004 is applied to the selected word line to verify the threshold value. At this time, if there are a plurality of memory cells set to a plurality of thresholds on the selected word line, a plurality of verify voltages corresponding to the respective thresholds may be sequentially applied to perform the verification.

In step S2006, the verification result is referred to, and it is determined whether or not the threshold values of all the memory cells connected to the selected word line are values corresponding to the data to be written. If the determination is affirmative, the process proceeds to step S2007, the writing success is notified to an external device connected to the nonvolatile semiconductor memory device, and the process is terminated.

If the result of the determination in step S2006 is negative, the process proceeds to step S2008, and MAX, which is a parameter indicating the upper limit of the number of loops stored in the ROM fuse 122, and the count value of the counter circuit are set. Compare. If the count value exceeds MAX, the process proceeds to step S2009, a write failure is notified, and the process ends. If the count value does not exceed MAX, in step S2010, the count value is incremented, and the process returns to step S2002.

The first embodiment of the present invention described above includes a memory cell that indicates whether a memory cell is adjacent to a selection gate transistor and how many other memory cells exist between the memory cell and the selection gate transistor. The presence or absence of application may be determined as follows according to the positional relationship of the select gate transistors. The positional relationship between the memory cell and the select gate transistor can be described by the positional relationship between the word line connecting the memory cell and SGS and SGD. Therefore, the verify voltage may be changed in consideration of the positional relationship between the word line and SGS and SGD.

That is, the first embodiment of the present invention described above is applied only to the writing of the word line WL0 close to SGS shown in FIG. 4 that is easily affected by GIDL, and the remaining word lines WL1 to WL1 are applied. For WLn, writing may be performed using a normal verify voltage.

Further, the first embodiment of the present invention is applied only to the word lines WL0 and WLn close to SGS and SGD shown in FIGS. 4 and 8 that are easily affected by GIDL, and the remaining word lines WL1. With respect to ˜WLn−1, writing may be performed using one normal verify voltage.

FIG. 14B shows the memory cell on the word line WL0 adjacent to the SGS according to the first embodiment of the present invention, from the first verify voltage (A-1) of Level A to the second verify voltage (A FIG. 14 is a diagram showing threshold distributions of memory cells to which data of threshold level A should be written immediately before switching to (-2) (immediately after writing of step-up number 3 in FIG. 13B).

FIG. 14C shows the first verify voltage (B-1) of the Level B to the second verify voltage (B-1) in the memory cell on the word line WL0 adjacent to the SGS according to the first embodiment of the invention. -2) is a diagram showing a threshold distribution of memory cells to which data of threshold level B should be written immediately before switching to (just after writing of step-up number 6 in FIG. 13B).

FIG. 14D shows the second verify voltage from the first verify voltage (C-1) of Level C in the memory cell on the word line WL0 adjacent to SGS according to the first embodiment of the present invention. It is the figure which showed the threshold value distribution of the memory cell in which the data of threshold LevelC should be written just before switching to (C-2) (immediately after writing of the step-up number of 10 in FIG. 13B). Note that, for memory cells to which data of threshold level E is to be written, the threshold distribution in an erased state where writing is not performed is shown.

FIG. 14A is a diagram showing the threshold distribution of the memory cells after all the memory cells on the word line WL0 adjacent to the SGS have been written. The same applies to the threshold distribution of the memory cells on the word line WLn adjacent to the SGD.

According to the first embodiment of the present invention described so far, as shown in FIG. 14B, the threshold level of the memory cell that has finished writing earlier is distributed at a potential lower than the original threshold distribution. However, when the threshold level of the memory cell is changed to a high potential due to GIDL, the threshold value distribution is almost within the original threshold distribution as shown in FIG. In addition, when writing is performed sequentially from the memory cell close to SGS toward the memory cell close to SGD, the memory cell on WL0 completes writing earlier than the memory cell on WLn, and the threshold shift is performed. Since the amount increases, for each verify level corresponding to Level A, Level B, and Level C, the verify voltage value for the memory cell on word line WL0 adjacent to SGS is equal to the memory cell on word line WLn adjacent to SGD. It is desirable to set it lower than the verify voltage value.

In addition, the first embodiment of the present invention is not only applicable to a memory close to SGS or a memory cell close to SGD that is easily affected by GIDL, but also to a memory cell at an arbitrary position. can do.

That is, after writing into a memory cell (for example, MC0n-2 in FIG. 8), writing into a surrounding memory cell (for example, MC1n-2, MC0n-1 in FIG. 8) is performed. In some cases, the threshold value of the memory cell MC0n-2 in FIG. Therefore, as described in the first embodiment of the present invention, threshold value transitions caused by writing to surrounding memory cells can be canceled by writing using a plurality of verify voltages.

FIG. 15 shows a case where writing is performed to a memory cell at an arbitrary position using the above-described (A-1), (A-2), (A-3), and (A-4) as a plurality of verify voltages. It is a figure explaining the transition of the distribution of the threshold value of a memory cell.

FIG. 15A shows a threshold distribution immediately after writing using the lowest verify voltage (A-1). If a sufficient threshold is obtained, the writing process is completed. If a sufficient threshold is not obtained in (A-1), the next lowest verify voltage (A-2) is used. As a result, the threshold distribution shown in FIG. 15B is obtained. Note that one of the reasons that the distribution shown in FIG. 15B is asymmetrical and has a lower threshold is that a sufficient threshold is obtained using (A-1) as the verify voltage. This is because the determined memory cell exists.

Similarly, if a sufficient threshold is not obtained even when (A-2) is used, (A-3) is used as the verify voltage, and the threshold distribution shown in FIG. 15 (d) is obtained. If a sufficient threshold is not obtained even when (A-3) is used, (A-4) is used as the verify voltage, and the voltage distribution shown in FIG.

Although the case where (A-1), (A-2), (A-3), and (A-4) are used as the verify voltages has been described, other verify voltages (B-1), (B-2), The same applies to writing using (B-3), (C-1), and (C-2). The number of verify voltages is not limited to the number shown here, and an appropriate number can be adopted.

Another reason why the threshold distribution is asymmetrical and has a trailing edge is that depending on the situation of writing to surrounding memory cells, memory cells that are not subject to interference between memory cells may also occur, and such memory cells Therefore, the threshold value for writing at a low verify voltage is kept. However, in general, it is considered that the number of memory cells that continue to maintain the threshold for writing at such a low verify voltage decreases exponentially by writing to the surrounding memory cells. .

Further, even if a threshold value is set low due to the presence of a memory cell that continues to hold a threshold value for writing at a low verify voltage, and erroneous reading occurs due to this, the problem can be solved as follows. That is, the data input to the I / O control circuit 2 is not written in the memory cell array 121 as it is, but is written with redundancy by adding an error correction code or the like by the data register / sense amplifier circuit 13 or the like. At the time of reading, error correction at the time of reading can be reduced if error correction is performed by an ECC (Error Correction Circuit) (not shown) provided outside the chip.

Alternatively, the verify voltage used for writing data to the memory cell that has been written first may be set lower than the verify voltage used to write data to the memory cell that has been written later. In other words, the verify voltage used to write data to the memory cell where writing is completed later may be set higher than the verify voltage used to write data to the memory cell where writing is completed first. . As a result, the threshold value of the memory cell in which writing is completed later is set higher than the threshold value of the memory cell in which writing is completed first.

These verify voltages are stored, for example, in the ROM fuse region 122 and read by the control signal generation circuit 8 to be controlled.

As described above, this embodiment can be applied not only to a memory cell connected to a word line adjacent to a selection gate transistor but also to a memory cell not adjacent to a selection gate transistor. In this case, for a memory cell not adjacent to the selection gate, it is preferable to set the stepwise change amount of the verify voltage smaller than that of the memory cell adjacent to the selection gate transistor. In other words, for the memory cell adjacent to the select gate transistor, it is preferable to set the stepwise change amount of the verify voltage larger than that of the memory cell not adjacent to the select gate transistor. This is because for the memory cell adjacent to the select gate transistor, in addition to an increase in the memory cell threshold value caused by inter-memory cell interference, an increase in the memory cell threshold value caused by electron injection caused by GIDL occurs. As for the memory cell adjacent to the selection gate transistor, when writing is performed in order from the cell connected to the word line close to the source line side, the memory cell adjacent to the selection gate transistor on the source line side includes: It is desirable to set the stepwise change amount of the verify voltage larger than that of the memory cell adjacent to the select gate transistor on the bit line side.

According to the first embodiment of the present invention described above, in the multi-value storage type nonvolatile semiconductor memory device, by setting the verify voltage lower than the normal verify voltage stepwise, relatively low write For a memory cell in which writing is completed with the voltage Vpgm, the writing is ended earlier at a threshold level lower than the threshold level to be normally set.

As a result, even if the threshold level of the memory cell that has finished writing earlier transitions to a higher potential due to GIDL or inter-memory cell interference, the amount of the transition is canceled out. As a result, the threshold range corresponding to the write data Can fit in.

(Second Embodiment)
The second embodiment of the present invention not only sets the verify voltage lower than the normal verify voltage stepwise according to the number of steps up of the write voltage Vpgm as in the first embodiment, but also performs the following write Use together. In the writing method used in the second embodiment of the present invention, in order to narrow the threshold distribution, when writing is completed to a threshold level slightly lower than the target of each threshold level to be written, In this method, the bit line potential at the time of application is controlled to a potential between 0 V and the power supply voltage Vdd. In the present invention, for convenience, this writing method is referred to as a second writing method, and the normal writing method used in the first embodiment is referred to as a first writing method.

FIG. 16 is a diagram for explaining a voltage application pattern when the second writing method is used. The second write method can be applied to a memory cell at an arbitrary position as in the first write method. Here, it is assumed that writing is performed on the memory cell MC00 shown in FIG. In the second write method, the verify operation is roughly divided into two stages, that is, a normal verify voltage (Vr) and a low verify voltage (VL) lower than the normal verify voltage. In the first write method, the bit line of the memory cell to be written is controlled to be 0V. Electrons are injected into the floating gate of the memory cell to be written by the potential difference between the write voltage of about 14V to 20V applied to the selected word line and the channel potential of 0V.

On the other hand, in the second write method, when the threshold value of the memory cell to be written exceeds the row verify voltage (VL), the voltage of the bit line BL0 is 0 V as shown in FIG. To the write control voltage (Vreg). The write control voltage (Vreg) is set to an intermediate potential between 0V and Vdd. Then, by reducing the potential difference between the write voltage 14V to 20V applied to the selected word line and the channel potential Vreg, the amount of increase in electrons injected into the floating gate of the memory cell to be written is reduced to the first write. Make it smaller than the method. Thus, the application of the write voltage pulse and the verification are repeatedly executed until the verify voltage is reached, and the threshold value of the memory cell to be written is set within the target threshold range. As a result, the threshold distribution of the memory cell can be concentrated in a certain range, in other words, the controllability of the threshold of the memory cell is increased, and the threshold distribution is finally narrowed.

FIG. 17A is a diagram showing transition of the threshold level according to the second writing method. FIG. 17B shows an intermediate potential between 0 V to 0 V and Vdd when the threshold level of the memory cell to be written exceeds the low verify voltage (VL) in the second programming method. It is the figure which showed being controlled by Vreg. As shown in FIG. 17A, the threshold distribution spreads like a mountain on the left side until the low verify voltage (VL) is reached. When the threshold level exceeds the low verify voltage (VL), the bit line is controlled to a write control voltage (Vreg) that is an intermediate potential between 0 V and Vdd, as shown in FIG. When a write voltage pulse is applied in this state, the amount of increase in electron injection from the channel to the floating gate is moderated, and the write voltage pulse is applied and verified repeatedly until the verify voltage (Vr) is slowly reached. Thereby, the displacement of the threshold value of the memory cell to be written becomes moderate. Eventually, the threshold distribution is set to a narrower distribution range such as the right mountain shown in FIG.

In the second embodiment of the present invention, not only the verify voltage (Vr) but also the row verify voltage (VL) of the second write method can be divided in multiple stages according to the number of steps up of the write voltage Vpgm. Is possible.

To explain using the example shown in FIG. 18B, for Level A, the verify voltage (Vr) is divided into a first verify voltage to a fourth verify voltage and each of the first to third write operations is performed. The first verify voltage (A-1) after applying the pulse of the voltage Vpgm, the second verify voltage (A-2) after applying the pulses of the fourth to sixth write voltages Vpgm, and the seventh to tenth times of each. The third verify voltage (A-3) is used after the pulse application of the write voltage Vpgm, and the fourth verify voltage (A-4) is used after the pulse application of each write voltage Vpgm for the eleventh and subsequent times. Similarly, the row verify voltage (VL) is divided into a first row verify voltage to a fourth row verify voltage, and the first row verify voltage is applied after the first to third write voltage Vpgm is applied. Voltage (AL-1), the second row verify voltage (AL-2) after the fourth to sixth pulse application of each write voltage Vpgm, and the third after the seventh to tenth write voltage Vpgm pulse application. The fourth row verify voltage (AL-4) is used after the pulse application of the write verify voltage Vpgm for the eleventh and subsequent times.

For Level B, the verify voltage (Vr) is divided into a first verify voltage to a third verify voltage, and the first verify voltage (B−) is applied after the first to sixth write voltages Vpgm are applied. 1) The second verify voltage (B-2) after the 7th to 9th pulse application of each write voltage Vpgm, and the third verify voltage (B-3) after the 10th and subsequent pulse application of each write voltage Vpgm. ) Is used. In addition, the row verify voltage (VL) is divided into a first row verify voltage to a third row verify voltage, and the first row verify voltage (VL) is applied after the first to sixth write voltage Vpgm is applied. BL-1), the second row verify voltage (BL-2) after the 7th to 9th pulse application of each write voltage Vpgm, and the 3rd row verify voltage after the 10th pulse application of each write voltage Vpgm. (BL-3) is used.

For Level C, the verify voltage (Vr) is divided into a first verify voltage and a second verify voltage, and the first verify voltage (Cr) is applied after the first to tenth write voltage Vpgm is applied. -1) The second verify voltage (C-2) is used after pulse application of each write voltage Vpgm after the 11th time. The row verify voltage (VL) is divided into a first row verify voltage and a second row verify voltage, and the first row verify voltage is applied after the first to tenth write voltage Vpgm is applied. (CL-1), the second row verify voltage (CL-2) is used after the 11th and subsequent pulses of each write voltage Vpgm.

Note that the second embodiment of the present invention is not limited to that shown in FIGS. 18A and 18B, and various variations are conceivable. For example, Level B and Level C may be one row verify voltage and one verify voltage without being divided into stages, or only Level C may be one row verify voltage and one verify voltage without being divided into stages. Furthermore, more stages may be set.

The difference between the low verify voltage and the verify voltage may be different among Level A, Level B, and Level C, or may be the same. In the same level, the difference between the row verify voltage and the verify voltage in each division may be different or the same. Further, the division of the low verify voltage may be different from the division of the verify voltage. For example, for Level A, the row verify voltage is divided into the first to third, fourth to sixth, seventh to tenth, and eleventh and subsequent times depending on the number of pulse application of Vpgm. May be divided by the first to fourth, fifth to tenth, eleventh and subsequent times.

Further, the voltage Vreg when the threshold value of the memory cell exceeds the row verify voltage by pulse application may be set according to the row verify voltage. For example, the voltage Vreg applied to the bit line when the row verify voltage is (AL-1) may be set higher than when the row verify voltage is (BL-1). By setting in this way, when the verify voltage is low and a small number of electrons are injected into the floating gate, it is possible to control the injection amount finely by reducing the injection amount of electrons after exceeding the low verify voltage. It becomes possible.

Next, regarding the configuration of the means for realizing the second embodiment of the present invention shown in FIGS. 18A and 18B, the initial setting data of the low verify voltage (VL) increases, and the voltage generation circuit 9 is the same as the first embodiment of the present invention except that 9 generates a low verify voltage (VL). This will be described with reference to the block diagram of FIG. Initial setting data relating to the write operation is stored in the ROM fuse 122 shown in FIG. The initial data to be stored are threshold level data, row verify voltage (VL) data corresponding to each threshold level, verify voltage (Vr) data corresponding to the threshold level, and row verify voltage (VL) corresponding to the threshold level. The step-up number of the write voltage Vpgm for switching, the step-up number of the write voltage Vpgm for switching the verify voltage (Vr) according to the threshold level, the value of the row verify voltage (VL), the value of the verify voltage (Vr), etc. . In this specification, for the sake of convenience, the step-up number of the write voltage Vpgm for switching the row verification voltage in accordance with the threshold level is referred to as “row verification voltage switching step-up number (VL switching step-up number)”. Further, the step-up number of the write voltage Vpgm for switching the verify voltage in accordance with the threshold level is referred to as “verify voltage switching step-up number (Vr switching step-up number)”.

In the examples of FIGS. 18A and 18B, the row verification voltage switching step-up data transferred from the ROM fuse 122 to the parameter register 4 is as follows. With respect to the threshold Level A, the row verify voltage is switched when the number of step-ups is 3, 6, and 10, so that data indicating the values of 3, 6, and 10 is transferred to the parameter register 4. For the threshold Level B, the row verify voltage is switched when the number of step-ups is 6 and 9, so that data indicating the values of 6 and 9 is transferred to the parameter register 4. As for the threshold Level C, the row verify voltage is switched when the step-up number is 10, so that data indicating a value of 10 is transferred to the parameter register 4. The data of the number of step-ups for the low verify voltage switching is transferred and held in the comparison circuit 16. The comparison circuit 16 may be included in the control signal generation circuit 8.

The data of the verify voltage switching step-up number is the same as the example described in the first embodiment.

On the other hand, data corresponding to each of the low verify voltages (VL) of the threshold levels A, B, and C stored in the ROM fuse 122 is transferred and held in the control signal generation circuit 8 through the parameter register 4. The data corresponding to the row verify voltages (VL) of the threshold levels A, Level B, and Level C will be described with reference to the example shown in FIG. 18B. For the threshold level A, the four row verify voltages are switched, and the first row verify voltage (VL) is switched. The verify voltage is AL-1 (eg, 0V), the second row verify voltage is AL-2 (eg, 0.2V), the third row verify voltage is AL-3 (eg, 0.4V), and the fourth verify voltage. Is data indicating A-4 (for example, 0.6 V). As for the threshold level B, the three verify voltages are switched, the first verify voltage is BL-1 (for example, 1.4V), the second verify voltage is BL-2 (for example, 1.5V), and the third verify voltage. Is data indicating BL-3 (for example, 1.6 V). Regarding the threshold Level C, switching between two verify voltages is performed, the first verify voltage is CL-1 (for example, 2.5 V), and the second verify voltage is CL-2 (for example, 2.6 V).

The data corresponding to the verify voltages (Vr) of the threshold levels A, B, and C stored in the ROM fuse 122 is the same as the example shown in the first embodiment of the present invention.

A counter circuit included in the control signal generation circuit 8 and a value obtained by counting pulses (which may be rising or falling) when stepping up the write voltage generated by the voltage generation circuit 9 are held. This count value is transferred to and held in the comparison circuit 16. The comparison circuit 16 may be included in the control signal generation circuit 8.

The comparison circuit 16 compares the count value with the data of the row verification voltage switching step-up number and the data of the verification voltage switching step-up number for each of the threshold levels Level A, Level B, and Level C, and the result is sent to the control signal generation circuit 8. Forward. The control signal generation circuit 8 generates a signal for controlling the row verify voltage (VL) and the verify voltage (Vr) for each of the threshold levels Level A, Level B, and Level C based on the comparison result. The voltage generation circuit 9 generates a low verify voltage and a verify voltage for each of the threshold levels Level A, Level B, and Level C based on the control signal transferred from the control signal generation circuit 8.

The shift amount of the threshold level due to GIDL or inter-memory cell interference is larger as the memory cell has a lower threshold level and smaller as the memory cell has a higher threshold level. Therefore, in the above example, it is desirable to increase the step width of the low verify voltage and the verify voltage for the threshold Level A, and to decrease the step width of the low verify voltage and the verify voltage as the threshold Level B and threshold Level C are reached.

The relationship between the low verify voltage (VL) of each of the threshold levels A, B, and C and the number of pulses applied to the write voltage Vpgm, and the verify voltage (Vr) of each of the threshold levels A, B, and C and the pulse of the write voltage Vpgm. Table 2 shows the relationship with the number of times of application. The numerical values listed in Table 2 are merely examples, and the present invention is not limited to them. There are many variations in the number of verify voltage switches, the respective verify voltage values, and the number of verify voltage switching steps. As long as the low verify voltage of each level is set lower than the verify level of each level, the number of step-ups to be switched is arbitrarily set in accordance with the characteristics of the memory cell with respect to the number of verify level switching step-ups. However, the same effect can be obtained.

The above-described second embodiment of the present invention can be applied to a memory cell at an arbitrary position. In particular, writing to the word line WL0 close to SGS shown in FIG. 4 that is easily affected by GIDL. The remaining word lines WL1 to WLn may be written using a normal row verify voltage and a verify voltage.

The second embodiment of the present invention is applied only to the word lines WL0 and WLn close to SGS and SGD shown in FIGS. 4 and 8 that are easily affected by GIDL, and the remaining word lines WL1. With respect to .about.WLn-1, writing may be performed using a normal row verify voltage and a verify voltage.

FIG. 19B shows a first verify voltage (A-1) of Level A to a second verify voltage (A-1) in a memory cell on the word line WL0 adjacent to SGS according to the second embodiment of the present invention. FIG. 14 is a diagram showing threshold distributions of memory cells that perform writing to Level A immediately after the row verification is completed immediately before switching to (−2) (immediately after writing with a step-up number of 3 in FIG. 13B).

FIG. 19C shows a second verify voltage (B-1) from the first verify voltage (B-1) of Level B in the memory cell on the word line WL0 adjacent to the SGS according to the second embodiment of the present invention. FIG. 14 is a diagram showing threshold distributions of memory cells that perform writing to Level B immediately after the row verification is completed immediately before switching to (−2) (immediately after writing with a step-up number of 6 in FIG. 13B).

FIG. 19D shows the second verify voltage from the first verify voltage (C-1) of Level C in the memory cell on the word line WL0 adjacent to the SGS according to the second embodiment of the present invention. It is the figure which showed the threshold value distribution of the memory cell which writes in LevelC immediately after finishing row verification just before switching to (C-2) (immediately after writing of the step-up number 10 of FIG.13 (b)).

Note that the threshold LevelE indicates a threshold distribution in an erased state where no write operation is performed.

FIG. 19A is a diagram showing a memory cell threshold distribution after all the memory cells on the word line WL0 adjacent to the SGS have been written. The same applies to the threshold distribution of the memory cells on the word line WLn adjacent to the SGD.

According to the second embodiment of the present invention, as shown in FIG. 19B, the threshold level of the memory cell immediately after the end of the row verification is distributed at a potential lower than the original threshold distribution. However, after the threshold level of the memory cell to be written exceeds the low verify voltage, the potential of the bit line to be written is controlled to an intermediate potential between 0V and Vdd. As a result, the threshold distribution becomes narrower, and even if the threshold level of the memory cell is shifted to a high potential due to GIDL or inter-memory cell interference, the threshold distribution is almost within the original threshold distribution as shown in FIG. The threshold distribution will be narrowed.

In addition, when writing is performed sequentially from a memory cell close to SGS to a memory cell close to SGD, the memory cell on WL0 completes writing before the memory cell on WLn, and the threshold shift amount Therefore, the verify levels of Level A, Level B, and Level C are set so that the voltage value for the memory cell on the word line WL0 adjacent to SGS is lower than the voltage value for the memory cell on the word line WLn adjacent to SGD. It is desirable to do.

According to the second embodiment of the present invention described above, in the non-volatile semiconductor memory device of the multi-value storage system, the verify voltage lower than the normal verify voltage is set stepwise and the normal row verify voltage is set. By setting a lower row verify voltage in a stepwise manner, a memory cell that has been written with a relatively low write voltage Vpgm is subjected to a row verify at a threshold level lower than the threshold level that should normally be set. This completes the writing process sooner.

As a result, even if the threshold level of the memory cell that has finished writing earlier transitions to a higher potential due to GIDL or inter-memory cell interference, the amount of the transition is canceled out. As a result, the threshold range corresponding to the write data And the threshold distribution can be further narrowed. In this specification, four values are used as an example. However, since each threshold distribution is narrow, the second embodiment of the present invention can be used as a more effective form for eight values, sixteen values, and the like.

Further, as described above, the present invention can be applied not only to memory cells connected to the word line adjacent to the selection gate transistor but also to memory cells not adjacent to the selection gate transistor. In this case, it is preferable to set the row verify voltage and the stepwise change amount of the verify voltage to be smaller for the memory cell not adjacent to the select gate transistor than in the memory cell adjacent to the select gate transistor. In other words, for the memory cell adjacent to the select gate transistor, it is preferable to set the row verify voltage and the stepwise change amount of the verify voltage larger than those of the memory cell not adjacent to the select gate transistor. This is because for the memory cell adjacent to the select gate transistor, in addition to the memory cell threshold value increase caused by the inter-memory cell interference, the memory cell threshold value increase caused by the electron injection caused by GIDL occurs. As for the memory cell adjacent to the selection gate transistor, when writing is performed in order from the cell connected to the word line close to the source line side, the memory cell adjacent to the selection gate transistor on the source line side includes: It is desirable to set the row verify voltage and the stepwise change amount of the verify voltage larger than those of the memory cells adjacent to the select gate transistor on the bit line side.

(Third embodiment)
In the second embodiment of the present invention, the VL switching step-up number and the Vr switching step-up number are determined for the low verify voltage (VL) and the verify voltage (Vr), respectively. That is, as shown in FIG. 18B, when the number of application times of the write voltage Vpgm reaches the VL switching step-up number or the Vr switching step-up, the row verify voltage (VL) or the verify voltage (Vr) is stepped up. To do. On the other hand, as a third embodiment of the present invention described below, a mode in which the low verify voltage (VL) is stepped up but the verify voltage (Vr) is not stepped up will be described.

FIG. 21 shows an example of transition between the low verify voltage (VL) and the verify voltage (Vr) in the third embodiment of the present invention. In other words, the row verify voltage for the threshold Level A is divided into four parts from the first row verify voltage to the fourth row verify voltage. The first row verify voltage (AL-1) after the first to third pulse application of each write voltage Vpgm, and the second row verify voltage (AL-1) after the fourth to sixth pulse application of each write voltage Vpgm. -2), the third row verify voltage (AL-3) after the seventh to tenth pulse application of each write voltage Vpgm, and the fourth row verify voltage after the eleventh pulse application of each write voltage Vpgm. (AL-4) is used.

The row verify voltage for the threshold Level B is obtained by applying the first row verify voltage (BL-1) after the first to sixth pulse application of the write voltage Vpgm, and the seventh to ninth pulse application of the write voltage Vpgm. Later, the second row verify voltage (BL-2) is used after the pulse application of each write voltage Vpgm after the 10th time.

The row verify voltage for the threshold level C is the first row verify voltage (CL-1) after the first to tenth pulse application of each write voltage Vpgm, and the first and subsequent write voltage Vpgm after the eleventh pulse application. A low verify voltage of 2 (CL-2) is used.

While the low verify voltage is divided as described above, the verify voltages for the thresholds Level A, Level B, and Level C are not divided. After any number of pulse application of the write voltage Vpgm, voltage values of A, B, and C are used, respectively.

When the relationship between the row verify voltage (VL) of each of the threshold levels A, Level B and Level C shown in FIG. 21 and the number of pulse application times of the write voltage Vpgm and the verify voltage (Vr) of each of the threshold levels A, Level B and Level C are tabulated Table 3 shows. 21 and Table 3 are only examples, and there can be many variations in the number of VL switching steps, the respective row verify voltage values, and verify voltage values. Further, as long as the low verify voltage of each threshold is set lower than the verify voltage of each level, the number of VL switching steps can be arbitrarily set in accordance with the characteristics of the memory cell.

Data equivalent to Table 3 is stored in the ROM fuse 122 or the like. These data are read out by the operation of the power-on reset circuit, transferred to the parameter register 4, held, and referred to during verification at the time of writing.

Hereinafter, it will be described with reference to FIGS. 22 and 23 that the controllability of the threshold value of the memory cell can be improved by stepping up the row verify voltage and making the verify voltage constant.

FIG. 22A shows that the threshold value of the memory cell is changed by applying a write voltage to the selected word line. In FIG. 22A, it is assumed that the threshold distribution of the memory cell before applying the write voltage to the selected word line is a distribution 2201 in the range from V1 to V2. When a write voltage is applied to the selected word line, the distribution 2201 moves toward the higher threshold voltage, and a distribution 2202 in the range from V3 to V4 is obtained.

FIG. 22B is a diagram expressing the threshold distribution of the memory cells using a technique called σ plot. In FIG. 22A, the number of memory cells having the threshold value is plotted against the threshold value. On the other hand, in FIG. 22B using the σ plot, the number (or cumulative number) of memory cells having a threshold equal to or lower than the threshold is plotted against the threshold. Therefore, for the distribution 2201 in FIG. 22A, a curve 2203 that monotonously increases in a broad range from V1 to V2 is obtained, and a curve 2204 is obtained for the distribution 2202. The shift of the distribution 2201 to the distribution 2202 is expressed by the shift of the curve 2203 to the curve 2204.

FIG. 23 is an example of expression by a σ plot for a certain threshold distribution. In this case, it is assumed that the curve expressed by the σ plot is defined within a range including a certain threshold verify voltage (Vr). Then, the curve can be divided into a memory cell portion 2301 having a threshold lower than the verify voltage (Vr) and a memory cell portion 2302 having a threshold not lower than the verify voltage (Vr).

When a write voltage is applied to the selected word line, the voltage of the bit line to which the NAND cell unit having the memory cells constituting the portion 2301 is connected becomes 0 V, and the NAND cell unit having the memory cells constituting the portion 2302 The voltage of the bit line connected to is a voltage Vreg intermediate between 0V and Vdd. Accordingly, the change in the threshold value of the memory cell constituting the portion 2302 is smaller than the change in the threshold value of the memory cell constituting the portion 2301. Therefore, the threshold curve after the write voltage is applied to the selected word line is defined in a narrower range than before the application. For this reason, the controllability of the threshold value of the memory cell can be improved.

Hereinafter, an operation when the nonvolatile semiconductor memory device according to the embodiment of the present invention writes data to a memory cell will be described with reference to FIGS. 24 and 25. FIG.

FIG. 24 is a diagram for explaining the control of the voltage applied to the bit line. The nonvolatile semiconductor memory device according to one embodiment of the present invention applies at least three kinds of voltages 0, Vreg, and Vdd to the bit line when applying the write voltage to the selected word line. Therefore, a table equivalent to the table shown in FIG. 24A is managed in the control signal generation circuit 8, the data register, the sense amplifier circuit 13, and the like. That is, the voltage to be applied to the bit line is controlled for each bit line.

The management of the table shown in FIG. 24A is performed according to the state transition diagram shown in FIG. In the initial stage of data writing, the voltage of the bit line is 0V as indicated by the node 2401. As long as the verification with the row verification voltage VL fails, the voltage of the bit line is set to 0V. If the verification with the low verification voltage VL is successful, a transition is made to the node 2402, and the voltage of the bit line becomes Vreg. A verify voltage Vr is used at the time of verify. As long as the verification at the verify voltage Vr fails, the voltage of the bit line becomes Vreg. If the verification with the verify voltage Vr is successful, a transition is made to the node 2403 and the voltage of the bit line becomes Vdd. Then, the voltage of the bit line is Vdd until the writing is completed.

FIG. 25 is a flowchart for explaining the flow of processing when the nonvolatile semiconductor memory device according to one embodiment of the present invention writes data to the memory cell. Steps in which the same processing as in FIG. 20 of the flowchart for explaining the flow of processing when the nonvolatile semiconductor memory device according to the first embodiment of the present invention writes data to the memory cell are performed are denoted by the same reference numerals. It is.

In step S2001, the count value of the counter circuit is initialized. As processing in step S2501, a setting is made to set the voltages of all the bit lines of the memory cells that do not maintain the erased state when data is written to 0V. Specifically, in the table shown in FIG. 24A, the values in all the columns of all the bit line potential columns of the memory cells that do not maintain the erased state are set to 0V. Next, the value of the write voltage (Vpgm) is determined as the process of step S2002. In step S2003, the write voltage (Vpgm) determined in step S2002 is applied to the selected word line, and data is written to the memory cell.

In step S2502, the value of the verify voltage corresponding to the threshold value is determined. Whether the threshold value that is the target of the memory cell to which data is written is Level E, Level A, Level B, or Level C, and the comparison result by the comparison circuit 16 using the count value of the counter circuit. The verify voltage is determined depending on whether or not the row verify is successful. Further, as described above, the verify voltage may be determined in consideration of the position of the selected word line.

In step S2503, the verify voltage determined in step S2004 is applied to the selected word line to verify the threshold value. At this time, if there are a plurality of memory cells set to a plurality of thresholds on the selected word line, a plurality of verify voltages corresponding to the respective thresholds may be sequentially applied to perform verification.

As the processing in step S2504, the voltage to be applied to the bit line at the time of the next data write (in the next processing of step S2003) is determined according to the state transition of FIG.

Hereinafter, since it is the same as that of FIG. 20, description is abbreviate | omitted.

Thus, according to an embodiment of the present invention, the controllability of the threshold value of the memory cell can be improved by stepping up the row verify voltage and keeping the verify voltage constant.

In addition, as described in the description of the second embodiment of the present invention, various application examples and modifications can be given. For example, the third embodiment of the present invention may be performed for a memory cell adjacent to a select gate transistor, and other embodiments may be used for other memory cells.

(Fourth embodiment)
In the second embodiment of the present invention, as shown in FIG. 18B, when the number of application times of the write voltage Vpgm reaches the VL switching step-up number or the Vr switching step-up, the row verification voltage (VL) Alternatively, the verify voltage (Vr) is stepped up. On the other hand, as a fourth embodiment of the present invention to be described below, a mode in which the verify voltage (Vr) is stepped up without stepping up the low verify voltage (VL) will be described.

FIG. 26 shows an example of transition between the low verify voltage (VL) and the verify voltage (Vr) in the fourth embodiment of the present invention. That is, the verify voltage for the threshold Level A is divided into four parts from the first verify voltage to the fourth verify voltage. The first verify voltage (A-1) after the first to third pulse application of each write voltage Vpgm, and the second verify voltage (A-2) after the fourth to sixth pulse application of each write voltage Vpgm. ), The third verify voltage (A-3) after the seventh to tenth pulse application of each write voltage Vpgm, and the fourth verify voltage (A-4) after the eleventh pulse application of each write voltage Vpgm. ) Is used.

The verify voltage for the threshold level B is the first verify voltage (B-1) after the first to sixth pulse application of the write voltage Vpgm, and the seventh to ninth ninth write voltage Vpgm after the pulse application. 2 verify voltage (B-2), the third verify voltage (B-3) is used after the tenth and subsequent pulses of each write voltage Vpgm.

The verify voltage for the threshold level C is the first verify voltage (C-1) after the first to tenth pulse application of each write voltage Vpgm, and the second after the 11th and subsequent pulse application of each write voltage Vpgm. A verify voltage (C-2) is used.

As described above, the verify voltage is divided, whereas the row verify voltages of the threshold levels A, B, and C are not divided. After every pulse application of the write voltage Vpgm, the values of the row verify voltages AL, BL, and CL are used, respectively.

The relationship between the verify voltage (Vr) of each of the threshold levels A, Level B and Level C and the number of pulse application times of the write voltage Vpgm shown in FIG. 26 and the low verify voltage (VL) of each of the threshold levels A, Level B and Level C are tabulated. Table 4 shows. FIG. 26 and Table 4 show an example, and there can be many variations in the number of Vr switching steps, the respective verify voltage values, and the low verify voltage values. Further, as long as the low verify voltage of each threshold is set lower than the verify voltage of each level, the number of Vr switching steps can be arbitrarily set according to the characteristics of the memory cell.

The ROM fuse 122 and the like store data equivalent to that in Table 4. These data are read out by the operation of the power-on reset circuit, transferred to the parameter register 4, held, and referred to during verification at the time of writing.

FIG. 27 is a diagram for explaining that the controllability of the threshold value of the memory cell can be improved by stepping up the verify voltage as described above, using the expression of the σ plot. Assume that there are a low verify voltage VL and verify voltages Vr-1 and Vr-2 that step up. Then, the curve indicating the cumulative number of cells is divided into a portion 2701 lower than VL, a portion 2702 that is greater than or equal to VL and less than Vr-1, a portion 2703 that is greater than or equal to Vr-1 and less than Vr-2, and the like.

Since the voltage of the bit line to which the NAND cell unit having the memory cells constituting the portion 2701 is connected is 0V, the threshold voltage is higher than that of the memory cells constituting the portions 2702 and 2703 when the write voltage Vpgm is applied to the selected word line. It will rise greatly.

Further, as a certain level of writing progresses, the number of NAND cell units that allow current to flow from the bit line to the common source line increases. That is, the current flowing into the common source line increases, and the potential of the common source line rises due to the electric resistance existing in the common source line. For this reason, a phenomenon occurs in which the threshold value of the memory cell is apparently increased during the verification. This phenomenon becomes more prominent as the threshold value of the memory cell is distributed in a low voltage range.

This phenomenon occurs remarkably when the bit line and the bit line control circuit are connected one-to-one. In FIG. 28, as an example of one-to-one connection, a bit line control circuit is connected to the same one end of each bit line. In contrast, in FIG. 29, the bit line control circuits are alternately arranged at one end and the other end of the bit line.

Assume that the bit lines and the bit line control circuits are connected one-on-one as shown in FIGS. At the time of verification, first, SGS is set to “L” and SGD is set to “H” to charge the NAND cell unit via the bit line. Then, after setting SGD to “L”, a verify voltage is applied to the selected word line, and a pass voltage is applied to the non-selected word line. In this state, SGD and SGS are set to “H”, and the potential change of all the bit lines is detected by the sense amplifier of the bit line control circuit. For example, a case where the detection of the change in the potential of the bit line is performed in two steps as follows will be described. First, in detecting the bit line potential change at the first stage, a memory cell whose threshold is clearly lower than the verify voltage is detected, and the bit line to which the memory cell is connected is set to the potential of the common source line (for example, ground potential). Discharge. Since the potential change of the bit line to which the memory cell clearly lower than the verify voltage is connected becomes large, it is excluded from the verification target in the first stage. Next, in the detection of the potential change of the bit line in the second stage, only the potential change of the bit line of the memory cell whose threshold is approximately the verify voltage or higher is detected. Thereby, in the detection of the potential change of the bit line at the second stage, the current flowing from the bit line to the common source line is reduced when SGD and SGS are set to “H”, compared with the case of the first stage. It is possible to suppress an increase in the potential of the common source line due to the electrical resistance present in the. However, in this case, as a certain level of writing is performed, the current flowing from the bit line to the common source line increases when SGD and SGS are set to “H” in the detection of the potential change of the bit line at the second stage. . This is because the threshold value of the memory cell to be written increases as a certain level of writing is performed, and the memory cell excluded from the verification target when the potential change of the bit line in the first stage is detected is not excluded. It is to go. As a result, as a certain level of programming progresses, the threshold value of the memory cell that has already been programmed increases gradually.

However, by stepping up the verify voltage (Vr), as a certain level of writing progresses, the current flowing from the bit line to the common source line increases in the potential change of the bit line at the second stage. By setting the verify voltage (Vr) high in each step, the number of memory cells that are turned ON can be made constant or decreased, and verification can be performed in response to an increase in the potential of the common source line. . As a result, it is possible to cancel the increase in the threshold value of the memory cell that has already been written.

Therefore, the controllability of the threshold value of the memory cell can be improved by keeping the row verify voltage constant and stepping up the verify voltage.

In addition, as described in the description of the second embodiment of the present invention, various application examples and modifications can be given. For example, the fourth embodiment of the present invention may be performed for a memory cell adjacent to a select gate transistor, and other embodiments may be used for other memory cells.

(Change in voltage of selected word line)
Hereinafter, the time change of the selected word line of the nonvolatile semiconductor memory device according to each embodiment of the present invention will be described.

FIG. 30 shows an example of a change in voltage according to the time of the selected word line when the row verify voltage is not used, the verify voltage is not stepped up, and Vpgm applied to the word line is stepped up. It is assumed that 4-level data is written in the memory cell. The thresholds corresponding to the respective levels are denoted as Level E, Level A, Level B, and Level C, and the verification voltage values of the threshold Level A, Level B, and Level C are denoted as AV, BV, and CV. In this case, a voltage of Vpgm is applied to the word line, and data is written to the memory cell. Thereafter, AV, BV, and CV are sequentially applied as verify voltages. If the verification fails, the stepped-up Vpgm is applied to the selected word line, and AV, BV, and CV are sequentially applied as verification voltages.

FIG. 31 shows an example of a change in voltage according to the time of the selected word line when the verify voltage is stepped up and Vpgm applied to the word line is stepped up without using the row verify voltage. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In this case, a voltage of Vpgm is applied to the word line, and data is written into the memory cell. Thereafter, AV, BV, and CV are sequentially applied as verify voltages. If the verification fails, the stepped-up Vpgm is applied next, and AV, BV, and CV are sequentially applied as the verification voltages. At this time, the AV is stepped up after the second Vpgm application, the AV and BV are stepped up after the third Vpgm application, and the CV is stepped up after the fourth and fifth Vpgm applications. Therefore, FIG. 31 shows an example of the voltage change of the selected word line in the first embodiment of the present invention.

FIG. 32 is a modification of the change of FIG. As in FIG. 31, it is assumed that 4-level data is written in the memory cell. In this example, in accordance with the value of the write voltage Vpgm, the application of the verify voltage corresponding to some of the threshold values is omitted. That is, while the write voltage Vpgm is low, data corresponding to a low threshold can be written to the memory cell, but data corresponding to a high threshold is not written. Therefore, application of the verify voltage corresponding to the high threshold is omitted while the write voltage Vpgm is low. Further, when there is no memory cell in which data corresponding to a high threshold value is written, it is not necessary to apply a verify voltage corresponding to the high threshold value and can be omitted.

In FIG. 32, only AV is applied after the first Vpgm application, AV and BV are applied after the second and third Vpgm applications, and AV and VVm are applied after the fourth and subsequent Vpgm applications. BV and CB are applied.

FIG. 33 shows an example of a change in voltage according to the time of the selected word line when the row verify voltage is used, the verify voltage is not stepped up, and Vpgm applied to the word line is stepped up. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In FIG. 33, a voltage of Vpgm is applied to the word line, and data is written to the memory cell. Thereafter, the low verify voltage AVL, the verify voltage AV, the low verify voltage BVL, the verify voltage BV, the low verify voltage CVL, and the verify voltage CV are applied as the verify voltages.

FIG. 34 shows an example of a change according to the time of the selected word line when the row verify voltage is stepped up, the verify voltage is not stepped up, and Vpgm applied to the word line is stepped up. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In this case, as in FIG. 33, the low verify voltage AVL, the verify voltage AV, the low verify voltage BVL, the verify voltage BV, the low verify voltage CVL, and the verify voltage CV are applied as the verify voltages. However, in FIG. 34, AVL is stepped up after the second Vpgm application, AVL and BVL are stepped up after the third Vpgm application, and BVL is stepped up after the fourth Vpgm application, and the fifth Vpgm is applied. After application, the CVL is stepped up. Therefore, FIG. 34 shows an example of the voltage change of the selected word line in the fourth embodiment of the present invention.

FIG. 35 is a modification of the change of FIG. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In this example, in accordance with the value of the write voltage Vpgm, the application of the verify voltage corresponding to some of the threshold values is omitted. That is, while the write voltage Vpgm is low, data corresponding to a low threshold can be written to the memory cell, but data corresponding to a high threshold is not written. Therefore, the application of the verify voltage corresponding to the high threshold is omitted. Further, when there is no memory cell in which data corresponding to a high threshold value is written, it is not necessary to apply a verify voltage corresponding to the high threshold value and can be omitted.

In FIG. 35, AVL and AV are applied in the first Vpgm, AVL, AV, BVL, and BV are applied after the second and third Vpgm applications, and after the fourth and subsequent Vpgm applications. , AV, BV and CB are applied. The step-up of AVL, BVL, and CVL is the same as in FIG.

FIG. 36 shows an example of a change in voltage according to the time of the selected word line when the row verify voltage is not stepped up, the verify voltage is also stepped up, and Vpgm applied to the word line is stepped up. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In FIG. 36, the verify voltages AV, BV, and CV are stepped up as in FIG. 32, but the row verify voltages AVL, BVL, and CVL are not stepped up. Therefore, it can be said that FIG. 36 corresponds to the third embodiment of the present invention.

FIG. 37 is a modification of FIG. Similarly to FIG. 30, it is assumed that 4-level data is written in the memory cell. In this example, depending on the value of the write voltage Vpgm, the application of the row verify voltage and the verify voltage corresponding to some of the threshold values is omitted. That is, while the write voltage Vpgm is low, data corresponding to a low threshold can be written to the memory cell, but data corresponding to a high threshold is not written. Therefore, the application of the verify voltage corresponding to the high threshold is omitted. Further, when there is no memory cell in which data corresponding to a high threshold value is written, it is not necessary to apply a verify voltage corresponding to the high threshold value and can be omitted.

In an actual nonvolatile semiconductor memory device, for example, the row verify voltage or verify voltage of the threshold Level A may be 0 V, and when the time change of the voltage of the selected word line as shown in FIGS. 30 to 37 is measured, The application of 0V verify voltage or 0V low verify voltage may not appear. FIGS. 30 to 37 show the case where the row verify voltage and the verify voltage are applied in the order of the threshold value, but in an actual nonvolatile semiconductor memory device, they may be applied in a different order. .

(Other embodiments)
As the first embodiment of the present invention, the mode in which the verify voltage is stepped up and data is written in the memory cell has been mainly described. As the second embodiment of the present invention, the mode in which the row verify voltage and the verify voltage are stepped up to write data to the memory cell has been mainly described. As the third embodiment of the present invention, the description has mainly been given of the mode in which the data is written to the memory cell by stepping up the verify voltage without stepping up the row verify voltage. As the fourth embodiment of the present invention, the description is mainly given of the mode in which the row verify voltage is stepped up, but the data is written to the memory cell without stepping up the verify voltage.

As stated initially, the present invention should not be construed as limited to these embodiments. For example, for Level A, the verify voltage is not stepped up as in the third embodiment of the present invention, but the verify voltage is stepped up. For Level B, the row verify voltage is not increased as in the second embodiment of the present invention. The voltage and the verify voltage may be stepped up, and for Level C, the verify voltage may be stepped up without using the row verify voltage as in the first embodiment of the present invention. That is, the manner of applying the verify voltage may be different depending on the threshold value.

Further, in the case where the row verify voltage is used, in the above description, the case where one value of Vreg is used has been described, but a plurality of Vregs may be set. Then, one of the plurality of Vregs may be selected and applied to the bit line according to the number of times of application of the write voltage Vpgm to the selected word line.

Further, in the verification at the time of applying the initial write voltage Vpgm from the first time to the third time for one word line, the second embodiment of the present invention is used, for example, the middle period from the fourth time to the tenth time. The third embodiment of the present invention is used for verifying when the write voltage Vpgm is applied, and the first embodiment is used for verifying when the write voltage Vpgm is applied in the latter period after the 11th time. Also good. That is, the manner of applying the verify voltage may be different depending on the number of times of writing.

In addition, for one block, the manner of applying the verify voltage may be different depending on the position of the word line.

In addition, the manner in which the verify voltage is applied may be different depending on the total operation time of the nonvolatile semiconductor memory device.

Further, according to the second embodiment of the present invention, for example, a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set are arranged. A memory cell array; a voltage generator for generating a plurality of voltages including a write voltage applied to the nonvolatile memory cell; a verify voltage of a first write method; and a verify voltage of a second write method; and the write voltage Is applied as a pulse voltage to the non-volatile memory cell, and a counter unit that counts the number of write voltage pulses applied, and a plurality of first write method verify voltages set for each threshold level Data, a plurality of second write method verification voltage data, and a plurality of first write method verifications. A storage unit for storing the number of application of the write voltage pulse serving as a reference for switching the write voltage and the number of application of the write voltage pulse serving as a reference for switching the verify voltages of the plurality of second write methods; The number of application of the write voltage pulse counted by the counter unit for each threshold level, and the number of application of the voltage pulse serving as a reference for switching the verify voltage of the first write method stored in the storage unit, And a reference for switching the number of applied write voltage pulses counted by the counter unit and the verify voltage of the second write method stored in the storage unit. A comparator that outputs a second comparison result comparing the number of applied voltage pulses; and the first comparison of the comparator Based on the results, the verify voltages of the plurality of first write schemes applied to the nonvolatile memory cells are switched in stages, and the non-volatile properties are determined based on the second comparison results of the comparison unit. The verify voltage of the plurality of second write methods applied to the memory cell is switched in stages, and the bit line potential of the memory cell array is controlled based on the verify result of the first write method. It is possible to provide a non-volatile semiconductor memory device including a control unit.

In the second embodiment, the verify voltage value of the second write method may be singular while the verify voltage value of the first write method is plural. Alternatively, in this second embodiment, the value of the verify voltage of the first write method is singular, but the value of the verify voltage of the second write method may be plural.

According to an embodiment of the present invention, in the nonvolatile semiconductor memory device described above, switching of the verify voltages of the plurality of first write methods or / and switching of the verify voltages of the plurality of second write methods. The non-volatile memory cell to be subjected to the process can be a non-volatile memory cell adjacent to the select gate transistor.

According to an embodiment of the present invention, in the nonvolatile semiconductor memory device, the control unit includes a plurality of verify voltages of the first write method and / or a plurality of verify of the second write method. Of the amount of change in voltage at the time of voltage switching, control is performed so that the amount of change in a non-volatile memory cell not adjacent to the select gate transistor is smaller than the amount of change in the non-volatile memory cell adjacent to the select gate transistor. It can also be characterized by doing.

In addition, according to an embodiment of the present invention, in the nonvolatile semiconductor memory device described above, in the nonvolatile memory cells commonly connected to the word line, the verify voltage switching of the plurality of first write methods or / and A higher threshold level is set for a nonvolatile memory cell adjacent to the nonvolatile memory cell to be subjected to switching of the verify voltages of the plurality of second write methods when writing has not yet been completed. It can also be characterized.

According to an embodiment of the present invention, in the nonvolatile semiconductor memory device described above, switching of the verify voltages of the plurality of first write methods or / and switching of the verify voltages of the plurality of second write methods. The non-volatile memory cell to be subjected to the operation is a non-volatile memory cell in which the order of setting the threshold level of the non-volatile memory cell is earlier than all or part of the other non-volatile memory cells It can also be characterized.

According to one embodiment of the present invention, in the above-described nonvolatile semiconductor memory device, 0 V is applied to the bit line to which the nonvolatile memory cell whose threshold level is set by the first write method is connected. In addition, a voltage between 0 V and a write inhibit voltage is applied to a bit line connected to a nonvolatile memory cell whose threshold level is set in the second write method. it can.

1 is a diagram showing a functional block configuration of a memory chip of a NAND flash memory according to an embodiment of the present invention. It is the figure which showed the arrangement | sequence of the memory cell of a memory cell array. It is sectional drawing which shows an example of a structure of the memory cell part of NAND type flash memory. FIG. 5 is a circuit diagram showing an example of voltage application conditions when writing is performed by selecting a word line WL0. It is a figure which shows an example of the step-up writing method. (A) is the figure which showed the threshold value distribution of the whole memory cell, (b) is the figure which showed the threshold value distribution of the memory cell which is not adjacent to SGS and SGD, (c) is SGS and SGD It is the figure which showed the threshold value distribution of an adjacent memory cell. (A) is a distribution diagram showing variations in the number of write voltage application times when a write voltage corresponding to Level A is applied, and (b) is a write voltage when a write voltage corresponding to Level B is applied. FIG. 6C is a distribution diagram showing variation in the number of application times, and FIG. 6C is a distribution diagram showing variation in the number of application times of the write voltage when a write voltage corresponding to Level C is applied. It is a circuit diagram showing an example of a voltage application condition when writing is performed by selecting a word line WLn. (A) is a cross-sectional schematic diagram of the memory cell adjacent to SGS, (b) is a cross-sectional schematic diagram of the memory cell adjacent to SGD. (A) is a figure explaining the capacity | capacitance between the opposing side surfaces of the floating gate with an adjacent memory cell, (b) demonstrates the capacity | capacitance between the opposing side surfaces of the floating gate with the memory cell which adjoins also diagonally. FIG. 2 is a cross-sectional view of a memory array in a word line direction in a NAND flash memory. FIG. It is a figure explaining the fluctuation | variation of the threshold value by the influence of the capacity | capacitance between opposing side surfaces. (A) is the figure which showed the step-up write system which concerns on the 1st Embodiment of this invention, (b) is the figure which showed the verify voltage which concerns on the 1st Embodiment of this invention. (A) is a figure which showed the threshold value distribution of all the memory cells adjacent to SGS and SGD after completion | finish of all the writing by the 1st Embodiment of this invention, (b) is 1st of this invention It is the figure which showed the threshold value distribution of the memory cell adjacent to SGS immediately after finishing writing by embodiment of this. It is a figure which shows an example of threshold value distribution of the memory cell at the time of writing data using four verification voltages. It is the circuit diagram which showed an example of the voltage application conditions at the time of using the write system which concerns on one Embodiment of this invention. (A) is a diagram showing a transition of a threshold level by a write method according to an embodiment of the present invention, and (b) is a diagram illustrating a bit line potential from 0 V in the write method according to an embodiment of the present invention. It is the figure which showed being controlled to the intermediate potential Vreg between 0V and Vdd. (A) is a diagram showing a step-up write method according to an embodiment of the present invention, and (b) is a diagram showing a row verify voltage and a verify voltage according to an embodiment of the present invention. (A) is a diagram showing threshold distributions of all memory cells adjacent to the SGS after all writing is completed according to an embodiment of the present invention, and (b) is a diagram illustrating a row distribution according to an embodiment of the present invention. It is the figure which showed the threshold value distribution of the memory cell immediately after finishing verification. 3 is a flowchart for explaining the operation of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 4 is a diagram showing a row verify voltage and a verify voltage in the nonvolatile semiconductor memory device according to the embodiment of the present invention. (A) is an example figure which shows the change of the threshold value of a memory cell, (b) is an example figure which shows the change of the threshold value of a memory cell by (sigma) plot. It is a figure for demonstrating that the controllability of the threshold value of a memory cell can be improved in the 3rd Embodiment of this invention. (A) is an example figure of the table used in order for the non-volatile semiconductor memory device concerning one Embodiment of this invention to manage the voltage applied to a bit line, (b) is a voltage change applied to a bit line. It is an example figure of transition. 4 is a flowchart of processing of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 4 is a diagram showing a row verify voltage and a verify voltage of the nonvolatile semiconductor memory device according to the embodiment of the present invention. FIG. 5 is a diagram for explaining that the controllability of the threshold value of the memory cell can be improved in the embodiment of the present invention. FIG. 3 is an equivalent circuit diagram in which bit lines and bit line control circuits of a memory cell array are connected one-to-one in an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram in which bit lines and bit line control circuits of a memory cell array are connected one-to-one in an embodiment of the present invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention. It is an example figure of the change of the voltage applied to the word line in one Embodiment of this invention.

Explanation of symbols

FG, 34 Floating gate VL Low verify voltage Vpass Write pass voltage Vpgm Write voltage Vr Verify voltage Vreg Write control voltage Vt Threshold 1 NAND flash memory
2 I / O control circuit 3 Logic control circuit 4 Parameter register 7 Command register 8 Control signal generation circuit (internal controller)
DESCRIPTION OF SYMBOLS 9 Voltage generation circuit 10 Row decoder 12 Memory cell array 13 Data register / sense amplifier circuit 14 Column decoder 16 Comparison circuit 121 1st memory area 122 2nd memory area, ROM fuse (pulse application number memory | storage part)

Claims (10)

A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set are arranged;
A voltage generator for generating a plurality of voltages including a write voltage and a verify voltage applied to the nonvolatile memory cell;
A counter unit that counts the number of write voltage pulses applied when the write voltage is applied as a pulse voltage to the nonvolatile memory cell;
A storage unit that stores data of a plurality of verify voltages set for each threshold level and the number of application of the write voltage pulse serving as a reference for switching the plurality of verify voltages;
A comparison unit that compares the number of application of the write voltage pulse counted by the counter unit with the number of application of the write voltage pulse stored in the storage unit for each threshold level;
Based on the comparison result of the comparison unit, a control unit that performs verification control by switching a plurality of verification voltages applied to the nonvolatile memory cell in stages;
A non-volatile semiconductor memory device comprising: 2. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit controls an amount of change in voltage when the plurality of verify voltages are switched so as to change in accordance with the threshold level. 3. The control unit uses the change amount of the non-volatile memory cell not adjacent to the select gate transistor among the change amount of the voltage at the time of switching the plurality of verify voltages to the non-volatile memory cell adjacent to the select gate transistor. The nonvolatile semiconductor memory device according to claim 2, wherein control is performed to make the change amount smaller than the change amount of the non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile memory cell to which the plurality of verify voltages are switched is a nonvolatile memory cell adjacent to a selection gate transistor. 2. The nonvolatile memory according to claim 1, wherein the control unit changes a voltage change amount when the plurality of verify voltages are switched according to a positional relationship between the nonvolatile memory cell and the select gate transistor. 3. Semiconductor memory device. In a non-volatile memory cell commonly connected to a word line, a higher threshold level is applied to a non-volatile memory cell adjacent to the non-volatile memory cell to which the plurality of verify voltages are to be switched is not completed. The nonvolatile semiconductor memory device according to claim 1, wherein The nonvolatile memory cell that is a target for switching the plurality of verify voltages is:
The nonvolatile memory cell according to claim 1, wherein the nonvolatile memory cell is a nonvolatile memory cell in which the order of setting the threshold level of the nonvolatile memory cell is earlier than all or a part of the other nonvolatile memory cells. Semiconductor memory device. A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set are arranged;
A voltage generator for generating a plurality of voltages including a write voltage applied to the nonvolatile memory cell, a first write method verify voltage, and a second write method verify voltage;
A counter unit that counts the number of write voltage pulses applied when the write voltage is applied as a pulse voltage to the nonvolatile memory cell;
For each of the threshold levels, a plurality of first write method verify voltage data, a plurality of second write method verify voltage data, and a plurality of first write method verify voltages are provided. A storage unit that stores the number of application of the write voltage pulse that is a reference to be switched and the number of application of the write voltage pulse that is a reference for switching the verify voltage of the plurality of second write methods;
For each threshold level, the number of application of the write voltage pulse counted by the counter unit and the number of application of the voltage pulse serving as a reference for switching the verify voltage of the first write method stored in the storage unit. The first comparison result is output, and the reference voltage for switching the number of application of the write voltage pulse counted by the counter unit and the verify voltage of the second write method stored in the storage unit A comparison unit that outputs a second comparison result comparing the number of applied pulses;
Based on the first comparison result of the comparison unit, the verification voltages of the plurality of first write methods applied to the nonvolatile memory cell are switched in stages, and the second voltage of the comparison unit is changed. Based on the comparison result, the verify voltages of the plurality of second write schemes applied to the nonvolatile memory cells are switched in stages, and the memory based on the verify results of the first write scheme. A control unit for controlling the bit line potential of the cell array;
A non-volatile semiconductor memory device comprising: A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells in which a plurality of threshold levels corresponding to a plurality of write data are selectively set are arranged;
A write voltage applied to the non-volatile memory cell; a first write method verify voltage; and a second write method verify voltage that is higher than the first write method verify voltage. A voltage generator for generating a plurality of voltages;
A counter unit that counts the number of write voltage pulses applied when the write voltage is applied as a pulse voltage to the nonvolatile memory cell;
For each threshold level, the reference voltage data of the first write method, the verify voltage data of the second write method, and the verify voltage of the first or second write method are switched. A storage unit for storing the number of application of the write voltage pulse;
The write voltage serving as a reference for switching the number of application of the write voltage pulse counted by the counter unit and the verify voltage of the first or second write method stored in the storage unit for each threshold level A comparison unit that outputs a comparison result comparing the number of applied pulses;
Based on the comparison result of the comparison unit, the verify voltage of the first or second write method applied to the nonvolatile memory cell is switched stepwise to obtain the verify result of the first write method. A control unit for controlling the bit line potential of the memory cell array,
A non-volatile semiconductor memory device comprising: The voltage generator generates a plurality of voltages as either the verify voltage of the first write method or the verify voltage of the second write method,
The storage unit stores data of a plurality of verify voltages as either the verify voltage data of the first write method or the verify voltage data of the second write method, and the verify of the first write method 10. The nonvolatile semiconductor memory device according to claim 9, wherein the number of applied write voltage pulses serving as a reference for switching a plurality of verify voltages among the voltages or the verify voltages of the second write method is stored.

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