JP2009033336A - Amplifying circuit and control method of the amplifying circuit, amplifying device, and reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of pop-up noise, for example, when a class-D amplifying circuit with single-power-source and half-bridge constitution is powered on, without inserting a mute circuit into an output line. <P>SOLUTION: A VG generating circuit 10 outputs a voltage VG which gradually increases similar to an exponential function, when rising and becomes stable at a gate drive voltage of transistors Q10 and Q11. The voltage VG is supplied to gate drive circuits 12 and 13, and the Q10 and Q11 of an output stage are driven by the outputs of the circuits 12 and 13, respectively. An output signal, extracted from a middle point between the Q10 and Q11, has its harmonic component removed by an LC filter and also has its DC voltage component removed by a coupling capacitor C2 to be output to a speaker, and the like. When the power source is turned on, inputs to the Q10 and Q11 are gradually increased from 0V to the gate drive voltage similar to exponential function, as the voltage VG rises gradually, so that no sudden application of a voltage to the coupling capacitor C2 is performed and pop-up noise is suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an amplifier circuit that amplifies an audio signal in a class D operation, a method for controlling the amplifier circuit, an amplifier device, and a playback device, and more particularly to a configuration that can suppress pop noise that occurs when the power is turned on.

In recent years, as an amplification method for amplifying an audio signal, a binary 1-bit digital signal having time information by PWM (Pulse Width Modulation) or PDM (Pulse Density Modulation) is used. A so-called class D amplification system in which a 1-bit digital signal is converted into a signal and amplified is popular. The amplified 1-bit digital signal is integrated by a low-pass filter and output to a speaker or the like. An amplifier circuit using a class D amplification system (hereinafter referred to as a class D amplifier circuit) has higher power conversion efficiency than a linear amplifier, and is theoretically distortion-free and noise-free. From large-scale amplifiers to large-scale amplifiers, it has become widely used. Patent Document 1 describes a configuration example of a class D amplifier circuit with higher power efficiency.
JP-A-2005-130061

  FIG. 15 schematically shows a configuration of an example of a conventional class D amplifier circuit. In this example, a 1-bit digital signal is obtained by PWM. The audio signal input from the terminal 200 is modulated by the PWM circuit 201 and converted into a PWM signal having a duty corresponding to the amplitude information. This PWM signal is supplied to a drive circuit 202 composed of a dead time generation circuit, a level shifter, a gate drive circuit, etc., and is inverted and amplified in amplitude suitable for driving a transistor as a switching element in the output stage. The driving signal of the book.

In this example, the output stage is a half-bridge type in which two transistors Q110 and Q111 are combined to supply power from a single power source. For example, each of the transistors Q110 and Q111 uses an N-channel power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and is driven as a switching element. The Hi-side transistor Q110 and the Lo-side transistor Q111 are connected in cascade with respect to the power supply voltage _VDD , and the other end is connected to the ground voltage. The drive signals output from the drive circuit 202 and inverted with each other are input to the gate electrodes of the transistors Q110 and Q111, respectively.

The amplitude of the PWM signal input to the output stage is raised to the power supply voltage V _DD in the transistors Q110 and Q111. The PWM signal whose amplitude is increased to V _DD is taken out as an output from the coupling point of the transistors Q110 and Q111, supplied to an LC filter circuit composed of an inductor L and a capacitor C1, and integrated to generate a harmonic component. Removed.

Furthermore, in the single power supply and half-bridge configuration, the output is taken from the midpoint of the output stage. For this reason, a signal in which a DC voltage having a voltage value that is ½ of the power supply voltage V _DD for the output stage is added to the output of the LC filter circuit is output. Therefore, a large-capacity electrolytic capacitor is inserted into the output as a coupling capacitor C2, and a signal from which a DC component has been removed by this coupling capacitor C2 is supplied to, for example, a load that is a speaker SP.

  By the way, as already explained, the PWM signal is generated by modulating the input audio signal so that the duty changes according to the time change of the level. When there is no input, that is, when the level of the audio signal is 0, the duty of the modulated PWM signal is 50%.

  Here, conventionally, in a class D amplifier circuit of a single power source and a half bridge, pop noise has occurred when the power is turned on. The pop noise generated when the power is turned on will be considered with reference to FIG. Immediately before the power is turned on, as a matter of course, the operations of the PWM circuit 201, the drive circuit 202 and the output stage are stopped, and the potential at the midpoint of the transistors Q110 and Q111 is also 0V. This can be considered as a PWM signal with a duty of 0% (or 100%). Further, the coupling capacitor C2 is considered to be in a state in which no electric charge is accumulated at the first use of the device or when a sufficient time has passed since the previous use.

  When the power is turned on in this state, the PWM circuit 201 outputs a PWM signal with a duty of 50% because it is in a no-input state. This PWM signal is supplied to transistors Q110 and Q111 via drive circuit 202, and an output is taken out from the middle point of transistors Q110 and Q111. This output is a PWM signal with a duty ratio of 50%. This PWM signal is supplied to the LC filter circuit. In other words, it can be considered that a PWM signal whose duty is suddenly changed from 0% (or 100%) to 50% is supplied to the LC filter circuit as the power is turned on.

Since the LC filter circuit has a time constant, the peak value of the power supply voltage V _DD transiently passes through the LC filter circuit with a sudden change in duty. Therefore, a signal that suddenly changes from 0 V to the peak value of the power supply voltage V _DD is suddenly applied to the coupling capacitor C2. In a state where no charge is accumulated in the coupling capacitor C2, this signal appears as it is in the output, resulting in pop noise.

  Conventionally, as a countermeasure against this pop noise, as illustrated in FIG. 17, a mute circuit using, for example, the transistor Q200 as a switching element is provided between the coupling capacitor C2 and the load, and a predetermined time has elapsed since the power was turned on. The generation of pop noise was suppressed by controlling the transistor Q200 to be turned on later to cancel the mute operation.

  However, since the transistor Q200 constituting the mute circuit is inserted into the output line of the audio signal, there is a problem that the influence on the characteristics of the output audio signal is unavoidable.

  Further, in practice, as exemplified in FIG. 18, a mute circuit is inserted in each of the L channel and the R channel as well as a configuration for controlling these mute circuits. In the example of FIG. 18, the transistors Q210 and Q211 are inserted into the L channel and the R channel, respectively, and the mute control signal supplied to the transistor Q221 is pulled up to the ON voltage of the transistors Q210 and Q211 by the transistor Q220. This is supplied to the gate electrode to drive the transistors Q210 and Q211 of the mute circuit.

  Thus, conventionally, at least four transistors, that is, the transistors Q210 and Q211 constituting the mute circuit and the transistors Q220 and Q221 for controlling the mute circuit, are necessary for countermeasures against pop noise. Furthermore, a configuration for generating a mute control signal for controlling the mute operation is also required. For this reason, there is a problem that the circuit scale is increased and the cost is disadvantageous.

  Accordingly, an object of the present invention is to provide an amplifier circuit capable of suppressing the occurrence of pop noise at the time of power-on in a single power supply, class D amplifier circuit having a half bridge configuration without using a mute circuit inserted into an output line of an audio signal. An object of the present invention is to provide an amplifier circuit control method, an amplification device, and a reproduction device.

  In order to solve the above-described problems, the present invention provides an amplifier circuit that amplifies an audio signal that has undergone 1-bit digital signal processing in a class D operation, and includes first and second cascade-connected between a power supply voltage and a ground voltage. 2 switching elements, and a driving voltage output unit that outputs a driving voltage for driving the first and second switching elements. The driving voltage output unit gradually increases the driving voltage at the time of rising, and The amplifier circuit is characterized by being stabilized at a voltage value of.

  The present invention also relates to an amplifier circuit control method for amplifying a 1-bit digital signal processed audio signal by a class D operation, wherein the first and second switching elements are connected in cascade between a power supply voltage and a ground voltage. This is a method for controlling an amplifying circuit, characterized in that the driving voltage for driving is stabilized at a predetermined voltage value by gradually increasing the driving voltage at the time of rising.

  The present invention also provides a 1-bit digital signal processing unit that modulates an audio signal into a 1-bit digital signal, first and second switching elements connected in cascade between a power supply voltage and a ground voltage, A drive voltage output unit for gradually increasing the drive voltage for driving the second switching element at the time of rising and stabilizing the drive voltage at a predetermined voltage value, modulated by a 1-bit digital signal processing unit An amplifying unit that amplifies the audio signal by class D operation using the first and second switching elements; and a filter unit that removes harmonic components from the output signal extracted from the midpoint of the first and second switching elements; And a coupling capacitor for removing a DC voltage component from the output of the filter unit.

  Also, the present invention provides a reproducing unit for reproducing audio data from a recording medium, a 1-bit digital signal processing unit for modulating audio data reproduced by the reproducing unit into a 1-bit digital signal, and a power supply voltage and a ground voltage. The first and second switching elements connected in cascade to each other and the drive voltage for driving the first and second switching elements are gradually increased at the time of rising and output so as to be stabilized at a predetermined voltage value. An amplifying unit including a driving voltage output unit, and amplifying the audio signal modulated by the 1-bit digital signal processing unit by a class D operation using the first and second switching elements; and first and second switching elements A filter unit that removes harmonic components from the output signal extracted from the middle point, and a cup that removes DC voltage components from the output of the filter unit A reproducing apparatus, characterized in that it comprises a ring capacitor.

  As described above, the present invention includes the first and second switching elements connected in cascade between the power supply voltage and the ground voltage when the audio signal subjected to the 1-bit digital signal processing is amplified by the class D operation. Since the drive voltage for driving is gradually increased at the time of rising and stabilized at a predetermined voltage value, a signal having the same potential as the power supply voltage suddenly appears on the output when the power is turned on. Appears to be suppressed.

  As described above, the present invention includes the first and second switching elements connected in cascade between the power supply voltage and the ground voltage when a 1-bit digital signal processed audio signal is amplified by class D operation. Since the drive voltage for driving is gradually increased at the time of rising and stabilized at a predetermined voltage value, a signal having the same potential as the power supply voltage suddenly appears at the output when the power is turned on. This has the effect of suppressing the appearance.

  A first embodiment of the present invention will be described below with reference to the drawings. In the present invention, when the duty of a 1-bit digital signal suddenly changes when the power is turned on in a class D amplifier circuit with a single power supply and a half bridge configuration, as illustrated in FIG. The charging voltage for the coupling capacitor inserted for removal is controlled so as to gradually increase from 0V. As an example, it can be considered that the voltage applied to the coupling capacitor is controlled to gradually increase exponentially. By controlling the voltage in this way, the rise of the voltage on the output side of the coupling capacitor does not become steep, and pop noise is suppressed.

  It is also conceivable that the voltage applied to the coupling capacitor is controlled by a curve such as a simple CR (Capacitor / Resistance) time constant as shown in FIG. 1B. However, in this case, since the amount of change in voltage per hour is large at the start of applying a voltage to the coupling capacitor, noise is generated at a low frequency when charging of the coupling capacitor is started. It is not preferable.

  FIG. 2 shows an example of the configuration of the output stage of the class D amplifier circuit according to the first embodiment of the present invention. As illustrated in FIG. 3A, the ramp generation circuit (ramp) generation circuit 20 generates a signal whose voltage changes linearly when the circuit rises and falls. The signal that is generated by the ramp generation circuit 20 and whose voltage varies linearly is referred to as a ramp signal. For example, when the ramp signal rises, the voltage is linearly increased from 0 V to a predetermined voltage in a predetermined time, and is kept at a constant value. The time when the voltage is increased from 0 V to a predetermined voltage corresponds to, for example, a charging time of a coupling capacitor C2 described later, and is several tens of msec.

  Note that a waveform that changes linearly with respect to time as shown in FIG. 3A can be generated, for example, by discharging a capacitor with a constant current. For example, it may be generated by a microprocessor that controls a device in which this circuit is incorporated.

  The output of the ramp generation circuit 20 is supplied to the VG generation circuit 10. The VG generation circuit 10 shapes a waveform that linearly changes, for example, when the ramp generation circuit 20 rises or falls, and gradually increases from 0 V, for example, exponentially as illustrated in FIG. Convert the waveform to a change waveform. The circuit that converts the linearly changing waveform signal illustrated in FIG. 3A into an exponential changing signal illustrated in FIG. 3B is hereinafter referred to as a gate voltage waveform shaping circuit.

  Although a specific example will be described later, the gate voltage waveform shaping circuit can be realized using, for example, a large-capacity capacitor and a diode. However, the present invention is not limited to this, and the waveform as shown in FIG. 3B may be generated by, for example, a microprocessor that controls a device in which this circuit is incorporated.

  The output of the VG generation circuit 10 is supplied as a gate drive voltage VG to the gate drive circuit 12 that drives the Hi-side transistor Q10 and the gate drive circuit 13 that drives the Lo-side transistor Q11. The gate drive circuits 12 and 13 are respectively supplied with 1-bit digital signals that are inverted from each other from a preceding circuit (not shown).

  The 1-bit digital signal is obtained by modulating an audio signal by 1-bit digital signal processing such as PWM (Pulse Width Modulation) or PDM (Pulse Density Modulation).

In the output stage of the class D amplifier circuit, the Hi-side transistor Q10 and the Lo-side transistor Q11 function as switching elements that perform switching operations that are inverted with respect to each other. The power supply voltage V _DD is supplied to the drain electrode of the high-side transistor Q10. The source electrode of the Hi-side transistor Q10 and the drain electrode of the Lo-side transistor Q11 are connected, and the output is taken out from the connection point. The source electrode of the Lo-side transistor Q11 is connected to the ground voltage GND.

  In the output stage, the Hi-side transistor Q10 is driven by the output of the gate drive circuit 12 based on the gate drive voltage VG supplied from the VG generation circuit 10. Similarly, the Lo-side transistor Q11 is driven by the output of the gate drive circuit 13 based on the gate drive voltage VG. The output of the output stage is taken out from the middle point of the transistors Q10 and Q11, integrated by a filter circuit including the inductor L and the capacitor C1, the harmonic component is removed, and applied to the coupling capacitor C2.

  According to the configuration of the first embodiment, the ramp generation circuit 20 generates a ramp signal in which the voltage rises linearly from 0 V, for example, when the circuit rises, and the gate voltage waveform shaping circuit in the VG generation circuit 10 This ramp signal is converted from 0 V to a signal whose voltage gradually increases exponentially. This signal is supplied to the gate drive circuits 12 and 13 as the gate drive voltage VG. As a result, the change in the peak value of the 1-bit digital signal input to the transistors Q10 and Q11 is controlled, and accordingly, the peak value of the output PWM signal extracted from the midpoint of the transistors Q10 and Q11 also changes gradually. As a result, the occurrence of pop noise accompanying a sudden change in the duty of the 1-bit digital signal is suppressed.

  FIG. 4 shows the configuration of FIG. 2 described above using a more specific example. In FIG. 4, the same reference numerals are given to the same parts as those in FIG. 2 described above, and detailed description thereof is omitted.

  The output of the ramp generation circuit 20 is input to the VG generation circuit 10 via the resistor R10. In the example of FIG. 4, the VG generation circuit 10 includes an operational amplifier OP3, resistors R11, R12, and R13 connected to the operational amplifier OP3, a capacitor C10 made of, for example, an electrolytic capacitor, and a diode D1. The capacitor C10 and the diode D1 constitute the gate voltage waveform shaping circuit described above.

  The signal supplied from the ramp generation circuit 20 via the resistor R10 is supplied to the positive electrode of the electrolytic capacitor C10 and the anode of the diode D1, and is also input to the inverting input terminal of the operational amplifier OP3 via the resistor R11. The negative electrode of electrolytic capacitor C10 and the cathode of diode D1 are each connected to ground potential GND. In the operational amplifier OP3, the non-inverting input terminal is connected to the ground potential GND through the resistor R12, and is connected to the output of the operational amplifier OP3 through the resistor R13.

The gate voltage waveform shaping circuit uses the charging characteristic of the capacitor C10 and the voltage-current characteristic of the diode D1, and the characteristic in which the voltage changes linearly with respect to time, as illustrated in FIG. 3A described above, The characteristic can be converted into a characteristic in which the voltage rises exponentially at the time of rising, as exemplified in FIG. 3B. That is, the following threshold voltage V _F of the diode D1, current flows to the capacitor C10 to charge the capacitor C10, the voltage value of the positive electrode side of the capacitor C10 is gradually increased exponentially. Then, the voltage drop due to the threshold voltage V _F over the diode D1 of the diode D1 is constant, also complete charging of the capacitor C10, the voltage value across the capacitor C10 is saturated at a predetermined value.

  The operational amplifier OP3 amplifies the signal obtained by the gate voltage waveform shaping circuit to a required voltage as the gate drive voltage VG. The output of the operational amplifier OP3 is supplied as the gate drive voltage VG to the gate drive circuit 12 that drives the Hi-side transistor Q10 and the gate drive circuit 13 that drives the Lo-side transistor Q11.

  In the example of FIG. 4, the gate drive circuit 12 for driving the Hi-side transistor Q10 is configured as a push-pull circuit in which a P-channel transistor Q20 and an N-channel transistor Q21 are combined. The source electrode of transistor Q20 and the drain electrode of transistor Q21 are connected, and the connection point is connected to the gate electrode of transistor Q10 via resistor R20. The output of the operational amplifier OP3 is connected to the drain electrode of the transistor Q20, and the gate drive voltage VG is supplied. The source electrode of transistor Q21 is connected to the source electrode of transistor Q10.

  Similarly, the gate drive circuit 13 for driving the Lo-side transistor Q11 is configured as a push-pull circuit in which a P-channel transistor Q22 and an N-channel transistor Q23 are combined. The source electrode of transistor Q22 and the drain electrode of transistor Q23 are connected, and the connection point is connected to the gate electrode of transistor Q11 via resistor R21. The output of the operational amplifier OP3 is connected to the drain electrode of the transistor Q22, and the gate drive voltage VG is supplied. Further, the source electrode of the transistor Q23 is connected to the source electrode of the transistor Q11, and is set to the ground potential GND.

In the output stage, the source electrode of the Hi-side transistor Q10 and the drain electrode of the Lo-side transistor Q11 are connected, and the power supply voltage V _DD is supplied to the drain electrode of the Hi-side transistor Q10. The source electrode of Q11 is connected to the ground potential GND. A 1-bit digital signal is taken out as an output from a connection point between the source electrode of the transistor Q10 and the drain electrode of the transistor Q11, supplied to a filter circuit including an inductor L and a capacitor C1, and integrated to remove harmonic components. It is supplied to the load via the coupling capacitor C2.

  FIG. 5 shows an example of simulating changes in the gate drive voltage VG output from the VG generation circuit 10 and changes in the 1-bit digital signal of the gate drive circuit driven by the gate drive voltage VG in the configuration of FIG. The results are shown. The gate drive voltage VG gradually increases exponentially as time elapses from 0 V, and is saturated and stabilized at a predetermined voltage after a predetermined time. It can be seen that the peak value of the 1-bit digital signal output from the gate drive circuit changes following the change of the gate drive voltage VG. That is, the peak values of the 1-bit digital signals of the gate drive circuits 12 and 13 gradually increase exponentially with the passage of time from 0 V, and are stabilized at a predetermined value after the passage of a predetermined time.

  Therefore, the outputs of the transistors Q10 and Q11 in the output stage also gradually increase from 0V, and when the power is turned on, a current gradually flows into the coupling capacitor C2, thereby suppressing pop noise. Further, since no switching element is inserted between the coupling capacitor C2 and the load, there is no influence on sound quality. Furthermore, since pop noise is suppressed without using a mute circuit, the number of parts can be reduced.

  Next, a second embodiment of the present invention will be described. This second embodiment suppresses the deterioration of distortion that occurs when the volume adjustment is performed by varying the power supply voltage supplied to the output stage with respect to the configuration of the first embodiment described above. It is the example which added the structure for.

First, the relationship between the change in the power supply voltage supplied to the output stage and the distortion rate of the output signal will be schematically described with reference to FIGS. In order to adjust the sound volume in the class D amplifier circuit, there are a method of changing the level of the input digital audio signal and a method of changing the power supply voltage V _DD supplied to the output stage. Among these methods, the method of making the power supply voltage V _DD variable is advantageous over the method of making the level of the input digital audio signal variable because the data resolution does not deteriorate.

Consider the case where the power supply voltage V _DD is variable for volume adjustment in the configuration illustrated in FIG. Hereinafter, the variable power supply voltage V _{DD is referred} to as V _DV . The power supply voltage V _DV is assumed to be variable in the range of 0V to 2V. Transistors Q10 and Q11 have an ON voltage of 2V.

  The gate drive voltage of the transistors Q10 and Q11 to be driven needs to be a voltage that can completely turn on the Hi-side transistor Q10. In the first embodiment described above, the same constant gate drive voltage VG is always applied to the gate drive circuits 12 and 13 of the transistors Q10 and Q11, as exemplified in FIG. In the case of this method, since the source electrode of the Lo-side transistor Q11 is at the ground voltage, an ON voltage of 2 V may be applied to the gate electrode as the gate drive voltage.

On the other hand, since the output of the Hi-side transistor Q10 appears at the source electrode, the voltage of the source electrode changes between 0 V and the voltage V _DV . Since the maximum value V _DVMAX of V _DV is 2V, voltage V _Gb = V _DVMAX (2V) + ON voltage (2V) = 4V is applied to the gate electrode.

Under this condition, when the voltage V _DV is changed for volume adjustment, for example, the voltage V _DV = 1V, the voltage of the source electrode of the transistor Q110 becomes 1V. Therefore, the gate of the transistor Q110 - source voltage _{V GS} is, 3V, and the gate of the transistor Q110 - becomes possible to vary the voltage _{V GS} between source. As a result, the ON resistance of the transistor Q110 changes.

Here, as an output characteristic of the class D amplifier circuit, one of the factors that determine the distortion is the balance between the ON resistance of the Hi-side transistor Q10 and the ON resistance of the Lo-side transistor Q11. When the balance of the ON resistance is lost between these transistors Q10 and Q11, the distortion rate also deteriorates. That is, if V _DV is made variable to adjust the volume, the ON resistance of the transistor Q10 on the Hi side changes greatly, and the distortion rate in the output signal deteriorates. This deterioration of distortion is caused by changing the power supply voltage, so that even if an input for turning on the gate input is input, the transistor is not completely turned on and operates in the analog region. Conceivable.

FIG. 7 shows an example of the relationship between the power supply voltage V _DV supplied to the Hi-side transistor Q10 and the distortion rate of the output signal based on actual measurement values. The vertical axis represents the distortion rate THD%, and the horizontal axis represents the voltage V _DV . Note that the conditions of the voltage V _DV and the ON voltages of the transistors Q110 and Q111 are the same as in the above-described example of FIG. As described above, the distortion rate THD% greatly changes between about 0.04% and about 0.2% with respect to the change of the voltage V _DV . The distortion is minimized when the ON resistance of the Hi-side transistor Q10 and the ON resistance of the Lo-side transistor Q11 are well balanced. Note that the point at which the distortion rate is minimized deviates from 2 V, which is the ON voltage of the transistors Q10 and Q11, due to factors such as variation in characteristics between elements.

  As described above, it is not preferable that the distortion is changed by changing the volume by adjusting the volume when applied to an audio product.

In a second embodiment of the present invention, as shown schematically in Figure 8, the gate of the transistor Q10 of the Hi Side of the output stage of the class D amplifier circuit - a voltage Vgs _b-source, Lo side of the transistor Q11 the gate - source voltage Vgs _a is, to be equal to each other regardless of the change in the power supply voltage V _DV for the transistors Q10 and Q11, for controlling the gate drive voltage. In other words, the amplitude region of the gate drive voltage for the Hi-side transistor Q10 is constant regardless of the change in the power supply voltage V _DV .

Lo Side transistor Q11, the source electrode is the ground voltage GND, the gate drive voltage VG _a is uniquely determined. On the other hand, the gate drive voltage VG _b for the Hi-side transistor Q10 is linked to the power supply voltage V _DV . Therefore, the gate drive voltage VG _a relative Lo side transistors Q11, between the gate drive voltage VG _b for the transistor Q10 of the Hi side, holds the relationship of formula (1) below.
VG _b = VG _a + V _DV (1)

In other words, the gate drive voltage VG _a is kept constant, and the voltage value obtained by adding the voltage value of the power supply voltage V _DV to the gate drive voltage VG _a is used as the gate drive voltage VG _b , thereby realizing this equation (1). Will be.

FIG. 9 schematically shows an example of the configuration in the output stage of the class D amplifier circuit for realizing the above-described equation (1). Note that, in FIG. 9, the same reference numerals are given to portions common to FIG. 2 described above, and detailed description thereof is omitted. The power supply voltage V _DV is supplied to the drain electrode of the Hi-side transistor Q10 and input to one input terminal of the adder circuit 11. The power supply voltage V _DV is variable for adjusting the volume. Here, it is assumed that the power supply voltage V _DV is variable in the range of 0V to 2V. The source electrode of the Hi-side transistor Q10 and the drain electrode of the Lo-side transistor Q11 are connected, and the output is taken out from the connection point. The source electrode of the Lo-side transistor Q11 is connected to the ground voltage GND.

The ramp generation circuit 20 generates a ramp signal in which the voltage at the rise and fall of the circuit changes linearly. This ramp signal is supplied to the VG generation circuit 10 and is converted from 0V to a signal that gradually increases, for example, exponentially (at the time of rising) by the gate voltage waveform shaping circuit in the VG generation circuit 10. This signal is pulled up to, for example, the ON voltage of the transistors Q10 and Q11 by the VG generation circuit 10, and is input to the other input terminal of the addition circuit 11 as the voltage VG, and at the same time, the gate drive voltage VG that drives the Lo-side transistor Q11. _A is supplied to the gate drive circuit 13 as a.

The adder circuit 11 adds the power supply voltage V _DV input to one input end and the voltage VG input to the other input end. A voltage obtained by adding the power supply voltage V _DV and the voltage VG in the adding circuit 11 is supplied to the gate driving circuit 12 as a gate driving voltage VG _b for driving the Hi-side transistor Q10. As a result, the gate drive voltage VG _b maintains the amplitude range from 0 V to the voltage VG regardless of the change in the power supply voltage V _DV . The gate drive circuits 12 and 13 are respectively supplied with 1-bit digital signals that are inverted from each other from a preceding circuit (not shown).

In the output stage, transistor Q10 of Hi side is driven by the output of the gate drive circuit 12 based on the gate drive voltage VG _b. Similarly, Lo side of the transistor Q11 is driven by the output of the gate drive circuit 13 based on the gate drive voltage VG _a. The output of the output stage is taken from the middle point of transistors Q10 and Q11. The output of the output stage is taken out from the middle point of the transistors Q10 and Q11, integrated by a filter circuit including the inductor L and the capacitor C1, the harmonic component is removed, and applied to the coupling capacitor C2.

According to the configuration of the second embodiment, the power supply voltage V _DV and the value of the gate drive voltage VG _a for the Lo-side transistor Q11 are added by the adder circuit 11, and the gate drive for the Hi-side transistor Q10 is performed. since the voltage VG _b, oN resistance of the transistors Q10 and Q11 regardless of changes in the power supply voltage V _DV is equal, it is possible to maintain a substantially constant strain rate to changes in the supply voltage V _DV.

Figure 10 is a circuit of FIG. 9 described above, the maximum value the power voltage _{V DV} from 0V in the case of changing to (2V in this example), the change in gate drive voltage VG _a and VG _b of each transistor Q10 and Q11 An example result of simulating is shown. This corresponds to a case where the volume is changed from 0 to the maximum in the volume adjustment. In FIG. 10, the horizontal axis represents the power supply voltage V _DV and the vertical axis represents the voltage value at each measurement point.

As can be seen from FIG. 10, even when the power supply voltage V _DV is changed, the gate drive voltage VG _a for the Lo-side transistor Q11 is constant at a potential of 2V. On the other hand, the gate drive voltage VG _b for the transistor Q10 of the Hi side, with the change of the power supply voltage _{V DV,} has changed while keeping the potential difference between the supply voltage _{V DV} and 2V (i.e. voltage VG = gate drive voltage VG _a) . In other words, the gate drive voltage VG _b, the amplitude range of 2V (voltage VG) regardless of changes in supply voltage VDV is maintained. Thereby, it can be confirmed that the above-described equation (1) is realized in the circuit configuration of FIG.

FIG. 11 corresponds to the circuit of FIG. 9 described above, and shows an example relationship based on measured values of the power supply voltage V _DV and the distortion rate of the output signal. The vertical axis represents the distortion rate THD% of the output audio signal, and the horizontal axis represents the power supply voltage V _DV . FIG. 11 shows that the distortion rate THD% is substantially constant with respect to the change in the power supply voltage V _DV . As described above, according to the first embodiment of the present invention, in the configuration in which the volume is adjusted by changing the power supply voltage supplied to the transistor in the output stage, the distortion rate with respect to the volume adjustment can be made substantially constant. As a result, it was possible to obtain characteristics suitable for audio equipment.

That is, as described above, the value of the power supply voltage V _DV for the output stage and the value of the gate drive voltage VG _a for the Lo-side transistor Q11 are added by the adder circuit 11, and the gate drive for the Hi-side transistor Q10 is performed. with voltage VG _b, the voltage of the gate drive voltage VG _b changes according to the change in voltage while the power supply voltage V _DV maintaining its amplitude width. Therefore, the gate drive voltage VG _b for the Hi-side transistor Q10 can always be higher than the gate drive voltage VG _a for the Lo-side transistor Q11 by the power supply voltage V _DV .

Thus, according to the second embodiment, the gate-source voltages Vgs in transistors Q10 and Q11 are equal, and the ON resistances of transistors Q10 and Q11 are equal. As a result, even when the power supply voltage V _DV for the output stage is changed by adjusting the volume, the balance of the ON resistance in the transistors Q10 and Q11 on the Hi side and the Lo side is not lost, and the change in the power supply voltage V _DV is not affected. It is possible to keep the distortion rate substantially constant.

In the configuration illustrated in FIG. 9, the power supply voltage V _DV is controlled to 0 V (not shown) until the output voltage of the VG generation circuit 10 is stabilized at the predetermined voltage VG. In this case, by Equation (1) described above, the gate drive voltage VG _b supplied to the gate drive circuit 12, and gate drive voltage VG _a supplied to the gate drive circuit 13 is equal. Therefore, the peak values of the 1-bit digital signals output from the gate drive circuits 12 and 13 are both controlled so as to increase exponentially from 0 V as illustrated in FIG. 5 described above. As a result, when the power is turned on, a current gradually flows into the coupling capacitor C2, and pop noise can be suppressed.

FIGS. 12 and 13 show results of an example in which changes in the gate drive voltages VG _a and VG _b are simulated when the voltage VG output from the VG generation unit 10 is gradually increased and changed as described above. Show. In FIGS. 12 and 13, for the sake of simplicity, the simulation is performed on the assumption that the output voltage VG from the VG generation unit 10 changes linearly. The voltage VG in FIGS. 12 and 13 is the output voltage of the ramp generation circuit 20 in FIG. 9, and the VG generation circuit 10 raises the stable voltage of the voltage VG to the ON voltage of the transistors Q10 and Q11. Output.

FIG. 12 shows an exemplary simulation result when the power supply voltage V _DV supplied to the output stage is 0V. A gate drive voltage VG _b for the transistor Q10 of the Hi side, the gate drive voltage VG _a relative Lo side of the transistor Q11 is, in accordance with the change in the voltage VG output from VG generator 10 has changed completely equal I understand.

FIG. 13 shows an exemplary simulation result when the power supply voltage V _DV is the maximum value, that is, when the volume is adjusted to the maximum in the volume adjustment. The gate drive voltage VG _b for the Hi-side transistor Q10 and the gate drive voltage VGa for the Lo-side transistor Q11 maintain the potential difference corresponding to the power supply voltage V _DV while maintaining the voltage VG output from the VG generation unit 10. It can be seen that the change is exactly the same according to the change.

From the simulation results illustrated in FIGS. 12 and 13, even when the gate drive voltages VG _a and VG _b are changed from 0 V to a predetermined value, the gate drive for the power supply voltage V _DV and the Lo-side transistor Q11 is performed. by adding the value and the adding circuit 11 of the voltage VG _a, by a gate drive voltage VG _b for the transistor Q10 of the Hi side, it can be equal to the oN resistance of the transistors Q10 and Q11 regardless of changes in the power supply voltage _{V DV} I understand. Therefore, even in the configuration of the second embodiment, the distortion rate can be kept substantially constant with respect to the change in the power supply voltage V _DV .

  Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 14 schematically shows a configuration of an example of a playback apparatus 100 to which the present invention is applied. The reproduction unit 101 reproduces compressed audio data that has been compression-encoded and recorded on a recording medium from the recording medium. The recording medium is not particularly limited as long as audio data can be recorded. For example, it is conceivable to use a disk recording medium such as MD (Mini Disc) or DVD (Digital Versatile Disc), a non-volatile memory such as a flash memory, a hard disk, or a magnetic tape as a recording medium. The reproduction unit 101 performs predetermined demodulation processing, recording code decoding processing, and the like on the data read from the recording medium, and outputs the data as reproduction compressed audio data.

  The reproduction compressed audio data output from the reproduction unit 101 is supplied to the decoder unit 102, for example. The decoder unit 102 performs a decoding process corresponding to the compression encoding method on the reproduced compressed audio data, decompresses the compressed audio data, and outputs the decompressed audio data as baseband audio data.

  The baseband audio data output from the decoder unit 102 is supplied to the modulation unit 103. The modulation unit 103 performs 1-bit digital signal processing on the supplied audio data, converts the audio data into a 1-bit digital signal, and outputs it. For example, the modulation unit 103 performs PWM on the supplied audio data, and generates a PWM wave in which amplitude information is converted into time information. Not limited to this, the modulation unit 103 may modulate audio data using a Δ-Σ modulation method that also modulates the time axis, or may use PWM and Δ-Σ modulation in combination. Good. Here, the modulation | alteration part 103 shall perform PWM.

  The audio data modulated into the PWM signal by the modulation unit 103 is supplied to the amplifier unit 104 to which the present invention is applied. In the amplifier unit 104, any of the configurations of the first and second embodiments described above can be applied as the configuration of the output stage. That is, the amplifier unit 104 is driven by a drive circuit including, for example, a dead time generation circuit, a level shifter, and a gate drive circuit, and a gate drive voltage output from the drive circuit, and amplifies the PWM signal according to the power supply voltage. The half-bridge type output stage and the PWM signal extracted from the output stage are integrated to remove harmonic components, and the DC voltage component is removed by the coupling capacitor C2 to convert the PWM signal to an analog audio signal. And a filter circuit for outputting. The analog audio signal output from the amplifier unit 104 is supplied to, for example, the speaker 105 and drives the driving unit of the speaker 105.

  In the amplifier unit 104, for example, when the power is turned on, the gate drive voltage for the Hi-side transistor is controlled to gradually increase exponentially from 0V. For this reason, it is possible to suppress pop noise that is generated when the duty of the PWM signal at the time of power-on changes abruptly.

  The amplifier unit 104 can adjust the volume of the output signal by changing the power supply voltage supplied to the output stage in accordance with an operation on the volume controller 106. In this case, it is preferable to apply the configuration of the second embodiment described above as the configuration of the output stage because the distortion rate of the output audio signal can be made substantially constant regardless of the volume adjustment. That is, the gate drive voltage for the Hi-side transistor is set according to the value of the power supply voltage. Thus, as the power supply voltage supplied to the Hi-side transistor is changed from the minimum value (0 V) to the voltage corresponding to the maximum value of the volume, the gate drive voltage for the Hi-side transistor is changed to the power supply voltage. In contrast, the potential difference corresponding to the ON voltage is changed.

  In the above description, the playback apparatus 100 is described as playing back the compressed audio data that has been compressed and recorded on the recording medium. However, the present invention is not limited to this example. For example, the fourth embodiment can be applied to a reproducing apparatus that reproduces audio data recorded in a recording medium without compression. For example, it is conceivable to apply the present invention to a reproducing apparatus that reproduces CD-DA (Compact Disc-Digital Audio). In this case, for example, a configuration in which the decoder unit 102 is omitted from the configuration of FIG.

  In the above description, the playback apparatus 100 is described as playing back compressed or uncompressed audio data from a recording medium. However, this is not limited to this example. For example, the playback device 100 may be a device that plays back compressed or non-compressed audio data transmitted by wire or wireless via the Internet or the like. Furthermore, the present invention can be applied to an amplifier device that amplifies and outputs an audio signal input in an analog or digital manner. In this case, for example, a configuration in which the reproduction unit 101 and the decoder unit 102 are omitted from the configuration of FIG.

It is a basic diagram which shows the voltage control method of an example by this invention. It is a circuit diagram which shows the example of a structure in the output stage of the class D amplifier circuit by the 1st Embodiment of invention. It is a basic diagram which shows the voltage control method of an example by the 1st Embodiment. It is a circuit diagram which shows the more specific structural example for implement | achieving control by the 1st Embodiment. It is a basic diagram which shows the result of the example which simulated the change of the voltage VG and the change of the 1-bit digital signal output of the gate drive circuit driven by the voltage VG by 1st Embodiment. In the class D amplifier circuit, it is a schematic diagram for explaining the case where the power supply voltage V _DD is variable for volume adjustment. It is a basic diagram which shows the change of the distortion factor of an output signal when the power supply voltage _VDD is variable for volume adjustment based on an actual measurement value. It is a basic diagram for demonstrating schematically the 2nd Embodiment of invention. It is a circuit diagram which shows roughly the structure of an example in the output stage of the class D amplifier circuit by the 2nd Embodiment. FIG. 6 is a schematic diagram illustrating a result of an example simulating changes in the gate-source voltage Vsg in each transistor when the power supply voltage V _DV is changed from 0 V to the maximum value in the configuration of the second embodiment. is there. It is a basic diagram which shows the relationship of an example based on the measured value of the power supply voltage _VDV and the distortion factor of the signal output in the structure of the 2nd Embodiment. It is a basic diagram which shows the result of an example which changed the gate drive voltage at the time of making the voltage VG increase gradually, and it was muted by 2nd Embodiment. It is a basic diagram which shows the result of an example which changed the gate drive voltage at the time of making the voltage VG increase gradually, and it was muted by 2nd Embodiment. It is a block diagram which shows roughly the structure of an example of the reproducing | regenerating apparatus applicable to the 3rd Embodiment of invention. It is a basic diagram which shows roughly the structure of an example of the class D amplifier circuit by a prior art. It is an approximate line figure for explaining pop noise generated at the time of power-on etc. in a half-bridge class D amplifier circuit. It is a circuit diagram which shows an example of the pop noise countermeasure by a prior art. It is a circuit diagram which shows an example of the pop noise countermeasure by a prior art more concretely.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 VG generation circuit 11 Adder circuit 12 Hi side gate drive circuit 13 Lo side gate drive circuit 20 Ramp generation circuit 101 Reproduction part 102 Decoder part 103 Modulation part 104 Amplifier part 106 Volume controller Q10 Hi side transistor Q11 Lo side transistor C2 coupling capacitor

Claims (8)

In an amplifier circuit for amplifying a 1-bit digital signal processed audio signal by class D operation,
First and second switching elements connected in cascade between a power supply voltage and a ground voltage;
A drive voltage output unit for outputting a drive voltage for driving the first and second switching elements,
The amplifier circuit according to claim 1, wherein the drive voltage output unit gradually increases the drive voltage at the time of rising and stabilizes the drive voltage at a predetermined voltage value. The amplifier circuit according to claim 1,
The drive voltage output unit is
An amplifier circuit characterized in that the drive voltage is increased exponentially at the start of the increase of the drive voltage. The amplifier circuit according to claim 1,
An amplifier circuit characterized in that the rise time corresponds to when the power is turned on. The amplifier circuit according to claim 1,
An amplifier circuit, wherein an output signal is taken out from a middle point of the first and second switching elements, and the output signal is supplied to a coupling capacitor through a filter. The amplifier circuit according to claim 4,
The amplifier circuit characterized in that the drive voltage output unit stabilizes the drive voltage at the predetermined voltage value for a time corresponding to a charging time of the coupling capacitor. In a control method of an amplifier circuit for amplifying a 1-bit digital signal processed audio signal by a class D operation,
The drive voltage for driving the first and second switching elements connected in cascade between the power supply voltage and the ground voltage is gradually increased at the time of rising so as to be stabilized at a predetermined voltage value. A method for controlling an amplifier circuit, characterized by comprising: A 1-bit digital signal processor for modulating an audio signal into a 1-bit digital signal;
First and second switching elements connected in cascade between a power supply voltage and a ground voltage, and a drive voltage for driving the first and second switching elements are gradually increased at the time of rising, A drive voltage output unit that outputs the voltage value so as to be stabilized, and amplifies the audio signal modulated by the 1-bit digital signal processing unit by a class D operation using the first and second switching elements. An amplification unit;
A filter unit that removes harmonic components from the output signal extracted from the midpoint of the first and second switching elements;
An amplifying apparatus comprising: a coupling capacitor for removing a DC voltage component from the output of the filter unit. A playback unit for playing back audio data from a recording medium;
A 1-bit digital signal processing unit for modulating the audio data reproduced by the reproduction unit into a 1-bit digital signal;
First and second switching elements connected in cascade between a power supply voltage and a ground voltage, and a drive voltage for driving the first and second switching elements are gradually increased at the time of rising, A drive voltage output unit that outputs the voltage value so as to be stabilized, and amplifies the audio signal modulated by the 1-bit digital signal processing unit by a class D operation using the first and second switching elements. An amplification unit;
A filter unit that removes harmonic components from the output signal extracted from the midpoint of the first and second switching elements;
And a coupling capacitor for removing a DC voltage component from the output of the filter unit.

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