JP2009027085A - Field-effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor which is used as an RF dual-band device and has both a microstructure and higher performance. <P>SOLUTION: The field-effect transistor has a compound semiconductor layer 11 which is formed on a substrate (w) and has a source region 12, a drain region 13, and a fin-shaped region 14 formed therebetween, a first gate electrode 16 which is formed on a first side surface of the fin-shaped region 14 and to which a first signal is input, and a second gate electrode 17 which is formed on a second side surface of the fin-shaped region 14 and to which a second signal is input. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor used as a high frequency power device (hereinafter referred to as an RF device) using a compound semiconductor such as GaAs.

  In recent years, with the enhancement of functions of inverter circuits and switching elements, field effect transistors (Tr) used as RF devices, such as HEMT (High Electron Mobility Transistor) and FET (Field Effect Transistor), are further miniaturized and high performance. Is required.

  In such an RF device, as a dual-band device for amplifying two different signals, a method of inserting a filter so that only signals in two specific frequency bands enter one FET (for example, Non-Patent Document 1). Etc.) is used. In this case, the FET used must be capable of amplifying the entire two frequency bands, i.e. it must have optimized characteristics in both of the two frequency bands. However, when these two frequencies are different from each other by 10 times, for example, 1 GHz and 10 GHz, it is difficult for the FET to have uniform amplification characteristics in such a frequency band.

  Further, a technique of inputting signals separately to two FETs having different characteristics (see, for example, Patent Document 1) is used. In this case, it is possible to use an optimized FET in each frequency band, but it is necessary to arrange two FETs, and it is difficult to achieve miniaturization.

  Thus, there is a problem that it is difficult to realize both miniaturization and high performance in the RF dual-band device.

On the other hand, in recent years, FinFET has attracted attention as a next-generation transistor in Si-LSI. In the FinFET, for example, as described in Patent Document 2, a fin-like convex semiconductor layer is formed on an SOI (Silicon on Insulator) substrate, and a gate electrode is formed so as to sandwich the fin-like semiconductor layer. This is a three-dimensional double gate type device in which a channel region is formed in a region sandwiched between gate electrodes by connecting both ends to source / drain electrodes. By adopting such a structure, it can be formed by existing semiconductor manufacturing technology, and high efficiency and high speed can be expected. However, application to RF devices has not yet been studied.
US Pat. No. 6,665,528 JP 2006-13303 A Microwave Conference Proceedings, 2005. APMC. Asia-Pacific Conferencing Proceedings, Vol. 1, 4-7 Dec. 2005 Page (s): 4 pp

  An object of the present invention is to provide a field-effect transistor that can be used as an RF dual-band device and can realize both miniaturization and high performance.

  According to one embodiment of the present invention, a compound semiconductor layer formed over a substrate and having a source region, a drain region, and a fin-like region formed therebetween, and formed on a first side surface of the fin-like region, A first gate electrode for inputting a first signal and a second gate electrode formed on the second side surface of the fin-like region for receiving a second signal are provided. A field effect transistor is provided.

  According to one embodiment of the present invention, a compound semiconductor layer is formed over a substrate, a mask is formed over the compound semiconductor layer, the compound semiconductor layer is patterned using the mask, and a source region, a drain region, and a region between them are disposed. The present invention provides a method for manufacturing a field effect transistor, in which a fin-like region is formed at the same time, and gate electrodes for inputting different signals are formed on the side surfaces of the fin-like region.

  According to the field-effect transistor of one embodiment of the present invention, both miniaturization and high performance can be realized, and it can be used as an RF dual-band device having favorable characteristics.

  In addition, according to the method for manufacturing a field effect transistor of one embodiment of the present invention, both miniaturization and high performance can be realized, and an RF dual-band device having favorable characteristics can be formed.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a perspective view of the FET element of this embodiment, and FIG. 2 is a top view thereof. As shown in the figure, a semiconductor layer 11 made of GaAs, GaN or the like is formed on a substrate w such as Si or GaAs. The semiconductor layer 11 includes a source region 12, a drain region 13, and a fin-like region 14 in which a recess is formed. The fin-like region 14 is formed with a recess so as to have a steep slope in the drain direction and symmetrical in the width direction, and gate electrodes 16 and 17 are formed on the side surfaces so as to sandwich the recess. ing. The gate electrodes 16 and 17 are electrically separated by an insulating film 18. Channel regions 19 are formed on the fin electrodes 14 on the gate electrodes 16 and 17 side, respectively.

Such an FET element is formed as follows. First, as shown in FIG. 3, a semiconductor layer 11 made of GaAs, GaN or the like, an insulating film 18 such as SiN, SiO ₂ , or a photoresist are sequentially formed on a substrate w such as Si or GaAs. The insulating film 18 is patterned by a lithography method using light or EB (Electron Beam).

  Then, by etching using the insulating film 18 as a mask, the semiconductor layer 11 is patterned to form the fin region 14 together with the source region 12 and the drain region 13, and in this state, doping of impurities is performed. For example, assuming that two FET elements are an element A and an element B, FET impurity ions are implanted as shown in FIG. In this case, a predetermined angle that is not horizontal with respect to the side surface of the fin-like region is set. When ion implantation is performed on the element A, the element A itself becomes a shadow on the element B or acts as a mask. Therefore, the element B is not doped, and only the element A is doped. It is formed. Similarly, when ion implantation is performed on the element B, only the element B is doped, and, for example, an n-type region having a concentration different from that of the element A is formed.

  Then, after forming n + regions at both ends of the source region 12 and the drain region 13, a metal layer is formed and annealed, whereby a source electrode (not shown) having an ohmic contact with the semiconductor layer 11, After forming the drain electrode (not shown), gate electrodes 16 and 17 are formed which are electrically separated from each other by the insulating film 18 so as to sandwich the channel region 19, and as shown in FIGS. An FET element is formed.

  In the two FET elements formed in this way, different voltage signals are applied from both wall surfaces of the fin-like region 14 by the gate electrodes 16 and 17, respectively, and the channel current is controlled, whereby each signal is amplified. Is done.

  In the FET element of the present embodiment, since the gate electrode is only separated by an insulating film, two Tr functions having a space equivalent to one Tr can be formed, and space saving is possible. Become. Further, in such two FET elements, since the recess is formed in the fin-like region 14 where the channel is formed, the surface of the semiconductor layer is similar to the recess structure (embedded gate structure) applied in the planar type. It is possible to reduce the influence of the surface state existing on the surface of the semiconductor layer and improve the strain characteristics by moving the channel layer away from the surface. Unlike the planar type, the recess can be formed with one mask, so that the recess positions of the two Tr elements can be controlled with high accuracy, and the cost, time, and energy required for the recess processing step can be controlled. Can be reduced.

  In this embodiment, the semiconductor layer 11 is patterned using the insulating film 18 and used as an insulating film for insulating the gate electrodes 16 and 17. However, a mask for patterning is separately formed. The semiconductor layer 11 may be patterned using this mask.

  Further, mode control can be further performed using such two FET elements. When a signal is input to one FET element and amplified, there are two modes, that is, whether the remaining FET elements are in an OFF state or an ON state. For example, a mode in which two FET elements are an element A and an element B, and when a signal is input to the element A and amplified, a voltage of the same type as the gate voltage of the element A is applied to the element B (OFF mode) Then, the channel under the gate of the element A can be made shallow (halved). As a result, it is possible to react even to a small gate signal, so that it is possible to reduce energy consumption and increase the mutual conductance (gm) by suppressing useless current. On the contrary, in the mode in which no voltage is applied to the element B (ON mode), the channel under the gate of the element A can be deepened. This makes it possible to increase the current and drive at high power. In this way, it is possible to control to the two modes of the high gm mode and the high power mode.

  Further, in this embodiment, the doping levels of the two FET elements are changed to control different desired characteristics. However, as shown in FIG. 5, the recess shapes of the elements A and B are changed. That is, it may be controlled to have different desired characteristics by making it asymmetric. Such a recess shape can be formed by one patterning by using an asymmetric mask. Since the doping level and the recess shape of the FET element can be changed as appropriate, the design freedom of the FET element can be improved.

(Embodiment 2)
FIG. 6 is a perspective view of the FET element of this embodiment, and FIG. 7 is a top view thereof. As shown in the figure, a semiconductor layer 21 made of GaAs, GaN or the like is formed on a substrate w such as Si or GaAs. The semiconductor layer 21 includes a source region 22, a drain region 23, and fin-like regions 24 and 25 in which a channel is formed therebetween. Recesses (openings) are formed in the fin-like regions 24 and 25, and gate electrodes 26 and 27 are formed on the side surfaces so as to face each other.

  Such an FET element is formed in the same manner as in the first embodiment only by changing the mask pattern.

  In the FET element of the present embodiment, the same effects as those other than the mode control in Example 1 can be obtained, and interference between the two signals can be suppressed when two signals are input simultaneously.

  In these embodiments, a pair of FET elements is used. As shown in FIG. 8, a plurality of gate electrodes 36 separated by an insulating film 38 are arranged by connecting a source region 32 and a drain region 33 in parallel. Also good. By arranging in this manner, a larger current can be obtained, and application to a high power amplifier is possible.

  In these embodiments, the semiconductor layer is formed on the substrate w to form the fin-like region, but it is also possible to form a similar structure using a bulk substrate.

  Further, the HEMT element may be formed by forming an electron supply layer made of a compound semiconductor such as n ± AlGaAs that is heterojunction with the fin-like region on the wall surface of the fin-like region. In this case as well, it is possible to function as an RF dual-band device as with the above-described FET element.

  Further, the distance between the source and the drain can be changed by changing the length of the stripe portion (fin-like region), and can be appropriately set depending on the required breakdown voltage.

  As shown in FIGS. 9 and 10, in the recess formed in the fin-like region 44, the recess angle θ is not necessarily 90 degrees and may have a taper. For example, the angle may be greater than 90 degrees as shown in FIG. 9 or smaller than 90 degrees as shown in FIG. Furthermore, as shown in FIG. 11, the angle (surface angle) of the surface 45 through which the current flows does not necessarily have to be parallel to the source-drain direction, and may have a taper. This is because the charge distribution on the surface where current flows in the fin-like region is considered to greatly affect the breakdown voltage of the device. That is, since the charge distribution on the surface can be changed by changing the recess angle and the surface angle, it is possible to set a predetermined angle as required to obtain a predetermined device withstand voltage.

  As described above, when the recess angle θ is not 90 degrees, or when the current flowing surface is not parallel to the source-drain direction, the conventional planar structure can control the recess angle and the surface angle with high accuracy and high reproducibility. It is difficult to do. However, in such a Fin structure, patterning can be performed by using a mask having a desired angle, so that it is possible to control with high accuracy and high reproducibility.

  Furthermore, it is also possible to form field plate electrodes on the source and drain sides of the gate electrode as appropriate between the source and drain.

  In addition to Si and GaAs, GaN used for RF devices, SiC, diamond, and other substrates can be used as the substrate.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

The perspective view which shows the FET element in 1 aspect of this invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. The perspective view which shows the manufacturing process of the FET element in 1 aspect of this invention. The perspective view which shows the manufacturing process of the FET element in 1 aspect of this invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. The perspective view which shows the FET element in 1 aspect of this invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention. FIG. 6 is a top view illustrating an FET element according to one embodiment of the present invention.

Explanation of symbols

  w ... substrate, 11, 21 ... semiconductor layer, 12, 22, 32 ... source region, 13, 23, 33 ... drain region, 14, 24, 25, 44 ... fin-like region, 16, 17, 26, 27, 36 ... Gate electrode, 18, 38 ... Insulating film, 45 ... Surface through which current flows.

Claims (8)

A compound semiconductor layer formed on a substrate and having a source region, a drain region, and a fin-like region formed therebetween;
A first gate electrode formed on a first side surface of the fin-like region for receiving a first signal;
A field effect transistor, comprising: a second gate electrode formed on a second side surface of the fin-like region for receiving a second signal. Recesses are formed on both side surfaces of the fin-shaped region,
2. The field effect transistor according to claim 1, wherein the recess on the first gate electrode side and the recess on the second gate electrode side are asymmetric.   3. The field effect transistor according to claim 2, wherein a recess angle is greater than 90 degrees or smaller than 90 degrees in the recess on the first gate electrode side or the recess on the second gate electrode side. .   4. The field effect type according to claim 1, wherein the first gate electrode side and the second gate electrode side have different impurity concentrations in the fin-like region. 5. Transistor.   5. The field effect transistor according to claim 1, wherein the first signal and the second signal have different frequencies. 6. Forming a compound semiconductor layer on the substrate;
Forming a mask on the compound semiconductor layer;
Patterning the compound semiconductor layer using the mask, and simultaneously forming a source region, a drain region and a fin-like region disposed therebetween;
A method of manufacturing a field effect transistor, comprising forming a gate electrode for inputting different signals on side surfaces of the fin-like region.   7. The method of manufacturing a field effect transistor according to claim 6, wherein the fin-like region has a recess.   8. The method of manufacturing a field effect transistor according to claim 7, wherein the recess angle is greater than 90 degrees or less than 90 degrees.

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