JP2009027084A - Metal pattern generating method and generating apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a metal pattern generating method and generating apparatus capable of shortening the time required for generating a metal pattern including a dummy metal. <P>SOLUTION: The metal pattern generating method has: a step of reading cell arrangement data and setting a region where wiring is possible ; a step of arranging the rectangular pattern of a prescribed dimension in a matrix shape at the grid point of a wiring grid for layout design on the entire surface of the region where wiring is possible; a step of arranging a wiring pattern for signal wiring and for power wiring on the wiring grid of the region where wiring is possible; and a step of generating the metal pattern by combining the generated rectangular pattern and wiring pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a metal pattern generation method and a generation apparatus.

  In recent years, with the progress of miniaturization and higher density of semiconductor integrated circuits, in the process of manufacturing semiconductor integrated circuits, CMP (Chemical Mechanical Polishing) processing is performed in order to flatten each layer of the multilayer wiring. Done.

  In this CMP process, it is desirable that the distribution of the metal material of the wiring is substantially uniform over the entire chip. This is because if the distribution of the metal material is not uniform, the height difference in the cross-sectional direction of the wiring layer becomes significant due to the difference in material between the metal layer and the insulating layer.

  Therefore, in order to make the distribution of the metal material of the wiring uniform, a metal (dummy metal) unrelated to signal transmission is inserted into the metal wiring layer. Therefore, a dummy metal pattern is generated in the layout design process of the semiconductor integrated circuit.

  Conventionally, generation of a dummy metal pattern in such a dalay layout design process is performed by adding a dummy metal pattern to an area without the wiring after the layout of the original wiring pattern for signal transmission is completed (for example, , See Patent Document 1).

However, in the above-described method, a region where a dummy metal pattern needs to be added must be extracted from the wiring pattern after the layout is completed. Further, the number of dummy metals to be arranged must be determined according to the size of the extracted area. Therefore, there has been a problem that it takes a lot of time for the design process for generating the metal pattern.
JP 2000-338646 A (Page 4-5, FIG. 5)

  Accordingly, an object of the present invention is to provide a metal pattern generation method and a generation apparatus capable of reducing the time required for generating a metal pattern including a dummy metal.

  According to one aspect of the present invention, a step of setting a routable area based on a cell arrangement result, and a rectangular pattern of a predetermined size is arranged in a matrix on the grid points of a layout grid for layout design over the entire routable area. A step of arranging a wiring pattern for signal wiring and a power wiring on the wiring grid of the routable area, and a step of generating a metal pattern by synthesizing the rectangular pattern and the wiring pattern A metal pattern generation method is provided.

  Further, according to one aspect of the present invention, a means for setting a routable area based on a cell arrangement result, a rectangular pattern generating means for generating a rectangular pattern of a predetermined dimension, and the rectangular on the entire surface of the routable area Means for arranging patterns in a matrix at grid points of a wiring grid for layout design, means for arranging wiring patterns for signal wiring and power wiring on the wiring grid of the routable area, and the rectangular pattern There is provided a metal pattern generating apparatus comprising means for generating a metal pattern by synthesizing the wiring pattern.

  According to the present invention, the time required for generating a metal pattern including a dummy metal can be shortened.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a metal pattern generation apparatus according to an embodiment of the present invention. Here, the semiconductor integrated circuit to be processed by the metal pattern generation apparatus is designed using cells registered in the library, and the layout design is such that the input / output terminals are connected after the cells are arranged. Wiring shall be performed. At this time, the input / output terminals of the cells are on a preset wiring grid, and the wiring pattern connecting the input / output terminals of the cells is arranged on the wiring grid. The cells include primitive cells such as logic gates, mega cells such as memories and multi-bit multipliers, and IO cells for external interfaces. In general, since high-density wiring is performed in the megacell, the processing is performed here by excluding from the wiring-able area described later. The IO cell is also excluded from the routable area.

  The metal pattern generation apparatus 1 shown in FIG. 1 includes a routable area setting unit 11 that sets a routable area based on the cell arrangement data 1000 storing the result of the cell arrangement process of the layout design, and the input dummy metal minimum wiring In accordance with the interval information 3000, the rectangular pattern generation unit 12 that generates a rectangular pattern of a predetermined size and the above described rectangular pattern in a matrix form on the grid points of the wiring grid for layout design, on the entire area of the above described wiring available area. The wiring pattern for signal wiring generated based on the signal connection data 4000 and the wiring pattern for power wiring generated based on the power wiring information 5000 on the rectangular pattern placement unit 13 to be arranged and the wiring grid of the above-described routable area. Are generated by the wiring pattern placement unit 14 and the rectangular pattern placement unit 13. And a pattern arrangement data 20 and the wiring pattern arrangement data 30 generated by the wiring pattern disposed portion 14 combined to generate a metal pattern has a metal pattern generating unit 15 to output as a metal pattern data 40.

  Next, a method for generating a metal pattern including a dummy metal using the metal pattern generating apparatus 1 of the present embodiment will be described with reference to FIGS.

  FIG. 2 is a flowchart showing a procedure for generating a metal pattern including a dummy metal using the metal pattern generating apparatus 1 of the present embodiment.

  When generation of the metal pattern is started, first, the routable area setting unit 11 reads the cell arrangement data 1000 (step S01), refers to the layout cell library 2000, and is an area where the megacells and IO cells are arranged. An area excluding the area is set as an routable area (step S02).

  FIG. 3 shows an image of the routable area set by the routable area setting unit 11.

  In the example shown in FIG. 3, an area excluding the megacell arrangement areas 101 and 102 and the IO cell arrangement area 103 in the chip layout area of the semiconductor integrated circuit 100 is set as the routable area 110.

  The routable area 110 is an area where a rectangular pattern and a wiring pattern are arranged. Therefore, the arrangement of the rectangular pattern and the wiring pattern will be described next.

  Returning to the flow of FIG. 2, the rectangular pattern generation unit 12 determines the size of the rectangular pattern based on the dummy metal minimum wiring interval information 3000, and generates a rectangular pattern of that size (step S03).

  Here, the dummy metal minimum wiring interval indicates a minimum wiring interval necessary for suppressing the height difference of the wiring layer within an allowable range when the CMP process is performed.

When the horizontal and vertical intervals of the wiring grid are g1 and g2, respectively, and the dummy metal minimum wiring interval described in the dummy metal minimum wiring interval information 3000 is d, the rectangular pattern generation unit 12 has a rectangular pattern. The horizontal side length a and the vertical side length b of the pattern are
a = g1-d
b = g2-d
Asking.

  Subsequently, the rectangular pattern arrangement unit 13 arranges the rectangular pattern generated by the rectangular pattern generation unit 12 in a matrix form on the grid points of the wiring grid for layout design over the entire routable area 110 (step S04).

  FIG. 4 shows an image of the rectangular pattern arrangement arranged by the rectangular pattern arrangement unit 13.

  As shown in FIG. 4, rectangular patterns 130 are arranged in a matrix at lattice points of the wiring grid 120 in the routable area 110.

  This arrangement result is stored as rectangular pattern arrangement data 20.

  Returning to the flow of FIG. 2, next, the wiring pattern placement unit 14 places a wiring pattern (step S05).

  FIG. 5 shows an image of the wiring pattern arrangement arranged by the wiring pattern arrangement unit 14.

  At this time, the wiring pattern placement unit 14 determines a wiring route on the wiring grid 120 in the routable area 110 with respect to the connection between the input / output terminals of the arranged cells based on the signal connection data 4000, and the signal wiring. A wiring pattern 141 is generated. Further, the wiring pattern placement unit 14 generates the power wiring pattern 142 for the power wiring corresponding to the required current capacity on the wiring grid 120 in the routable area 110 based on the power wiring information 5000.

  This arrangement result is stored as wiring pattern arrangement data 30.

  At this time, the layer of the wiring pattern arrangement data 30 is set to a layer different from the layer of the rectangular pattern arrangement data 20. As a result, when performing a signal connection check at the time of design verification using layout design data, it is sufficient to use only the wiring pattern arrangement data 30, and the amount of verification target data can be reduced.

  Returning to the flow of FIG. 2, finally, the metal pattern generation unit 15 generates a metal pattern by synthesizing the rectangular pattern arrangement data 20 and the wiring pattern arrangement data 30 and outputs it as the metal pattern data 40 (step S06). ).

  FIG. 6 shows an image of the metal pattern arrangement generated by the metal pattern generation unit 15.

  The metal pattern 150 is obtained by merging the signal wiring pattern 141 or the power supply wiring pattern 142 with the rectangular pattern 130.

  Accordingly, where the signal wiring pattern 141 or the power wiring pattern 142 is disposed, the rectangular pattern 130 is absorbed by the pattern, and the signal wiring pattern 141 or the power wiring pattern 142 remains as it is.

  On the other hand, the rectangular pattern 130 remains as it is in an area where the signal wiring pattern 141 or the power wiring pattern 142 is not disposed. At this time, the interval between the rectangular patterns 130 satisfies the dummy metal minimum wiring interval. Therefore, the rectangular pattern 130 functions as a dummy metal in the CMP process.

  Here, no dummy metal is arranged in the megacell arrangement regions 101 and 102. However, since the megacell has essentially high wiring density, it is not necessary to arrange the dummy metal in the megacell arrangement regions 101 and 102.

  According to the present embodiment, since the rectangular pattern is arranged in advance on the entire routable area, the signal wiring or the power wiring can be extracted without extracting the dummy metal placement area after the signal wiring and the power wiring. A dummy metal is automatically placed in the unwired area. That is, the extraction process of the dummy metal arrangement region is not necessary, and the time required for generating the metal pattern including the dummy metal can be shortened.

  In addition, even if the wiring route of the signal wiring or power supply wiring is changed due to a design change etc., it is possible to create a metal pattern in which dummy metal that conforms to the new wiring pattern is created simply by creating new wiring pattern placement data. You can get it immediately. As a result, the processing time associated with the design change can be shortened.

The block diagram which shows the example of a structure of the metal pattern production | generation apparatus which concerns on the Example of this invention. The flowchart which shows the example of the procedure of the metal pattern production | generation method concerning the Example of this invention. The schematic diagram which shows the image of the wiring possible area | region of a semiconductor integrated circuit. The schematic diagram which shows the arrangement | positioning image of the rectangular pattern in the Example of this invention. The schematic diagram which shows the arrangement | positioning image of the wiring pattern in the Example of this invention. The schematic diagram which shows the example of the metal pattern production | generation in the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Metal pattern production | generation apparatus 11 Routable area setting part 12 Rectangular pattern production | generation part 13 Rectangular pattern arrangement | positioning part 14 Wiring pattern arrangement | positioning part 15 Pattern synthetic | combination part 20 Rectangular pattern arrangement | positioning data 30 Wiring pattern arrangement | positioning data 40 Metal pattern data 100 Semiconductor integrated circuit 101, 102 Megacell Arrangement Area 103 IO Cell Arrangement Area 110 Wiring Available Area 120 Wiring Grid 130 Rectangular Pattern 141 Signal Wiring Pattern 142 Power Wiring Pattern 150 Metal Pattern

Claims (5)

Setting a routable area based on the cell placement result;
Arranging a rectangular pattern of a predetermined dimension on the entire surface of the routable area in a matrix at the grid points of a wiring grid for layout design;
Placing wiring patterns for signal wiring and power wiring on the wiring grid in the routable area; and
Synthesizing the rectangular pattern and the wiring pattern to generate a metal pattern;
A metal pattern generation method characterized by comprising: The metal pattern generation method according to claim 1, wherein the predetermined dimension of the rectangular pattern is determined according to a minimum dummy metal wiring interval. Means for setting a routable area based on the cell placement result;
Rectangular pattern generating means for generating a rectangular pattern of a predetermined dimension;
Means for arranging the rectangular pattern in the form of a matrix at lattice points of a wiring grid for layout design on the entire surface of the routable area;
Means for arranging wiring patterns for signal wiring and power wiring on the wiring grid in the routable area;
Means for synthesizing the rectangular pattern and the wiring pattern to generate a metal pattern;
A metal pattern generation apparatus characterized by comprising: The rectangular pattern generation means includes
The metal pattern generation apparatus according to claim 4, wherein the size of the rectangular pattern is determined according to the input dummy metal minimum wiring interval information. 5. The metal pattern generation apparatus according to claim 3, wherein the pattern design layer for arranging the rectangular pattern and the pattern design layer for arranging the metal pattern are different layers.

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