JP2009026425A - Sense amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the access time of a sense amplifier by suppressing the output of dummy data when shifting from a standby state to an active state. <P>SOLUTION: The sense amplifier including: a current detection part 40 made inactive during standby and, active during normal operation, and generating a reference voltage REF on the basis of a current output from a reference memory array 20; a current detection part 30 generating a detection voltage DTO on the basis of a current output from a memory array 10 to be read and the reference voltage REF; and a differential amplification part 50 amplifying the voltage of the difference between the reference voltage REF and the detection voltage DTO to output readout RD. A current detection part 70 is provided, which generates a voltage DTA according to the current output from the memory cell array 10 for a fixed time when shifting from standby to a normal operation and provides it to the differential amplification part 50 as the detection voltage DT. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a current detection type sense amplifier that reads data by comparing a current based on data stored in a selected memory array with a current based on data in a reference memory array.

FIG. 2 is a configuration diagram of a conventional sense amplifier.
This sense amplifier compares the current based on the data stored in the selected memory array 10 with the current based on the data in the reference memory array 20 in a ROM (read only memory) or the like. This is a current detection type that reads data stored in a memory cell, and includes current detection units 30 and 40 and a differential amplification unit 50.

  The memory array 10 has a plurality of memory cells (transistors) MCi (i is an integer of 1 or more) arranged in a matrix, the drains of these memory cells MCi are connected to the drain lines DL, and the sources are bit lines. Commonly connected to BL. The gate of the memory cell MCi is connected to the corresponding word line WLi. In each memory cell MCi, the threshold voltage of the transistor is controlled by ion implantation or the like, and when selected by the corresponding word line WLi, the memory cell MCi is turned on without the ion implantation (data “1”) and turned off with the ion implantation ( Data is written so as to be data “0”.

  On the other hand, the reference memory array 20 has a plurality of memory cells DMCi arranged in a matrix, the drains of these memory cells DMCi are connected to the drain line DDL, and the sources are commonly connected to the bit line DBL. Yes. The gate of the memory cell DMCi is connected to the same word line WLi as the corresponding memory cell MCi of the memory array 10. The memory cell DMCi is turned on when the threshold voltage is not controlled by ion implantation and is selected by the corresponding word line WLi.

  The current detection unit 30 detects a current flowing out from the selected memory cell MCi of the memory array 10 to the bit line BL and converts it into a voltage. P is connected in series between the power supply voltage VDD and the ground potential GND. A channel MOS transistor (hereinafter referred to as “PMOS”) 31 and N-channel MOS transistors (hereinafter referred to as “NMOS”) 32 and 33 are configured. A chip enable signal CEB obtained by inverting the chip enable signal CE is applied to the gate of the PMOS 31, and a reference voltage REF is applied to the gate of the NMOS 32.

  In addition, a bit line BL is connected to a connection point between the NMOSs 32 and 33, and a current of the bit line BL flows into the NMOS 33. Further, the gate of the NMOS 33 is connected to a connection point N1 between the PMOS 31 and the NMOS 32, and a detection voltage DTO corresponding to the current flowing through the bit line BL is output from the connection point N1.

  The current detection unit 40 generates the reference voltage REF based on the current that flows from the selected memory cell DMCi of the memory array 20 to the bit line DBL, and is connected in series between the power supply voltage VDD and the ground potential GND. It has a PMOS 41a and NMOSs 42a and 43a. Further, a PMOS 41b and NMOSs 42b and 43b are connected in parallel with the PMOS 41a and NMOSs 42a and 43a, respectively.

  A chip enable signal CEB is applied to the gates of the PMOSs 41a and 41b, and a bit line DBL is connected to a connection point between the NMOSs 42a and 43a and a connection point between the NMOSs 42b and 43b. It has become. The gates of the NMOSs 42a, 43a, 42b, and 43b are connected to a common connection point N2 between the PMOS 41a and the NMOS 42a and between the PMOS 41b and the NMOS 42b, and the reference voltage REF is output from the connection point N2.

  The corresponding transistors of the current detectors 30 and 40 are set to the same dimension (gate width and gate length). That is, the PMOSs 31, 41a, and 41b have the same dimensions, the NMOSs 32, 42a, and 42b have the same dimensions, and the NMOSs 33, 43a, and 43b have the same dimensions.

  The differential amplifying unit 50 differentially amplifies the detection voltage DTO output from the connection point N1 of the current detection unit 30 and the reference voltage REF output from the connection point N2 of the current detection unit 40 to obtain read data RD. The output device includes NMOSs 51 and 52 to which a detection voltage DTO and a reference voltage REF are applied to gates, respectively. The drains of the NMOSs 51 and 52 are connected to the power supply voltage VDD via the PMOSs 53 and 54, respectively. The sources of the NMOSs 51 and 52 are connected in common and connected to the ground potential GND via the NMOS 55 controlled by the chip enable signal CE.

  The gates of the PMOSs 53 and 54 are connected to the drain of the NMOS 52, and the signal of the drain of the NMOS 51 is output as read data RD via the inverter 56.

  3A and 3B are signal waveform diagrams showing the operation of FIG. 2. FIG. 3A shows that the chip enable signal CE is “H” and the sense amplifier is in an active (normal operation) state. FIG. 5B shows the signal waveform when the address signal is accessed (at the time of address access) when the chip enable signal CE changes from “L” to “H”. The signal waveforms when transitioning from the (standby operation) state to the active state (during chip enable access) are shown.

  In the active state, as shown in FIG. 3A, when the word line WLi is selected and becomes level “H” (power supply voltage VDD), the memory cell DMCi of the memory array 20 is always on. The current Im flows into the current detection unit 40 from the 20 bit lines DBL. On the other hand, in the memory array 10, if the data of the selected memory cell MCi is “1”, the current Im flows through the current detection unit 30 via the bit line BL. If the data in the memory cell MCi is “0”, no current flows.

  Since the corresponding transistors of the current detection units 30 and 40 are set to the same dimension, the current I having the same magnitude flows from the power supply potential VDD to the NMOSs 32, 42a, and 42b. In addition to the current I, the current Im from the bit line DBL flows in half into the NMOS 43a and 43b of the current detection unit 40. On the other hand, the current flowing through the NMOS 33 of the current detection unit 30 is I + Im when the data of the memory cell MCi is “1”, and is I when the data is “0”.

Here, if the operating resistance of the NMOSs 32, 42a, and 42b is RA and the operating resistance of the NMOSs 33, 43a, and 43b is RB, the reference voltage REF, the detection voltage DTO1 when the data is “1”, and the data are “0”. The detection voltage DTO0 at the time is as follows.
REF = I · RA + (I + Im / 2) · RB
DTO1 = I.RA + (I + Im) .RB = REF + Im.RB / 2
DTO0 = I.RA + I.RB = REF-Im.RB / 2

  Therefore, the reference voltage REF is an intermediate level between the two detection voltages DTO1 and DTO0. Thereby, by comparing the reference voltage REF and the detection voltage DTO in the differential amplifier 50, the stored contents of the memory cell MCi in the read memory array 10 can be output as the read data RD.

  On the other hand, when it is not necessary to read the memory, the chip enable signal CE is set to “L” to turn off the PMOSs 31, 41a, 41b of the current detection units 30, 40 and the NMOS 55 of the differential amplification unit 50. Thus, the power consumption of the sense amplifier can be reduced.

  The following Patent Documents 1 to 3 describe current detection type sense amplifiers. Among these, Patent Document 2 describes that a standby signal is delayed to control the output from the output circuit, so A differential amplifying device is described that aims to increase the rate of change to normal and reduce the generation of distortion waveforms.

JP-A-8-77779 JP 11-41039 A JP 2004-206860 A

  However, the sense amplifier has a problem that, as shown in FIG. 3B, the detection voltage DTO fluctuates when shifting from the standby state to the active state, and erroneous data is output.

  That is, when the chip enable signal CEB changes from “H” to “L” and shifts from the standby state to the active state, the reference voltage REF applied to the gate of the NMOS 32 of the current detection unit 30 is “L”. Since this is (ground potential GND), the NMOS 32 is in an off state. However, since the “L” chip enable signal CEB is applied to the gate of the PMOS 31, the PMOS 31 is turned on. As a result, the level of the connection point N1 rises rapidly.

  The node N1 is connected to the gate of the NMOS 33, and when the reference voltage REF of the gate of the NMOS 32 rises, a feedback circuit is configured to turn on the NMOS 33 and lower the level of the node N1.

  For this reason, the NMOS 33 is turned on by the rapid increase in the level of the connection point N1, and operates so as to rapidly decrease the level of the connection point N1. When the level of the connection point N1 falls below the reference voltage REF, the NMOS 33 is turned off and the level of the connection point N1 increases again. Such a level increase and decrease is repeated, and the level of the connection point N1 settles to a predetermined detection voltage DTO level.

  During the level fluctuation period of the connection point N1, the correct read data RD of the memory cell MCi cannot be output, which causes the access time to be delayed as a pseudo data output period.

  An object of the present invention is to provide a sense amplifier that can shorten the access time by suppressing the output of pseudo data at the time of transition from the standby state to the active state.

  The present invention includes a first current detection unit that generates a reference voltage based on a current output from a first memory cell for reference during a standby time, and stops during a standby time. Sometimes a second current detection unit that generates a detection voltage based on the current output from the second memory cell to be read and the reference voltage, and the reference voltage that is one input during the normal time and the other input In a sense amplifier having a differential amplifier for amplifying a voltage of the difference between the detection voltages and outputting read data, a current output from the second memory cell when a transition is made from a standby state to a normal state. According to another aspect of the present invention, there is provided a current detection unit that generates a corresponding voltage and temporarily supplies the voltage as the other input of the differential amplifier.

  In the present invention, when a transition is made from the standby state to the normal state, a voltage corresponding to the current output from the second memory cell to be read is generated, and this generated voltage is used as a sense amplifier instead of the detection voltage. A current detecting means is provided. Thus, immediately after the transition from the standby state to the normal state, when the reference voltage output from the first current detection unit is low, the variation in the detection voltage output from the second current detection unit is the differential amplification unit. The pseudo data output period is eliminated and the access time can be shortened.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of a sense amplifier showing Embodiment 1 of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  This sense amplifier compares the current based on the data stored in the selected memory array 10 with the current based on the data in the reference memory array 20, and reads out the data stored in the memory cells of the memory array 10. In the detection type, in addition to the current detection units 30 and 40 and the differential amplification unit 50 similar to those in FIG. 2, a switch unit 60, an additional current detection unit 70, and a delay control unit 80 as a control unit are provided. It has become.

  The memory array 10 has a plurality of memory cells (data storage transistors) MCi arranged in a matrix, the drains of these memory cells MCi are connected to the drain line DL, and the sources are commonly connected to the bit line BL. Has been. The gate of the memory cell MCi is connected to the corresponding word line WLi. In each memory cell MCi, the threshold voltage of the transistor is controlled by ion implantation or the like. When selected by the corresponding word line WLi, the memory cell MCi is turned on without ion implantation (for example, data “1”) and has ion implantation. Data is written so as to be off (for example, data “0”).

  On the other hand, the reference memory array 20 has a plurality of memory cells DMCi arranged in a matrix, the drains of these memory cells DMCi are connected to the drain line DDL, and the sources are commonly connected to the bit line DBL. Yes. The gate of the memory cell DMCi is connected to the same word line WLi as the corresponding memory cell MCi of the memory array 10. The memory cell DMCi is turned on when the threshold voltage is not controlled by ion implantation and is selected by the corresponding word line WLi.

  The current detection unit 30 detects a current flowing from the selected memory cell MCi of the memory array 10 to the bit line BL and converts it into a voltage. The PMOS 31 is connected in series between the power supply voltage VDD and the ground potential GND. And NMOSs 32 and 33. A chip enable signal CEB is supplied to the gate of the PMOS 31, and a reference voltage REF from the current detection unit 40 is supplied to the gate of the NMOS 32 so that the conduction state is controlled.

  In addition, a bit line BL is connected to a connection point between the NMOSs 32 and 33, and a current of the bit line BL flows into the NMOS 33. Further, the gate of the NMOS 33 is connected to a connection point N1 between the PMOS 31 and the NMOS 32, and the conduction state is controlled by the level of the connection point N1. A detection voltage DTO corresponding to the current flowing through the bit line BL is output from the connection point N1.

  The current detection unit 40 generates the reference voltage REF based on the current that flows from the selected memory cell DMCi of the memory array 20 to the bit line DBL, and is connected in series between the power supply voltage VDD and the ground potential GND. A PMOS 41a and NMOSs 42a and 43a are provided. Further, the PMOS 41b and the NMOSs 42b and 43b are connected in parallel with the PMOS 41a and the NMOSs 42a and 43a.

  A chip enable signal CEB is applied to the gates of the PMOSs 41a and 41b, and a bit line DBL is connected to a connection point between the NMOSs 42a and 43a and a connection point between the NMOSs 42b and 43b. It has become. The gates of the NMOSs 42a, 43a, 42b, and 43b are connected to a common connection point N2 between the PMOS 41a and the NMOS 42a and between the PMOS 41b and the NMOS 42b, and the conduction state is controlled by the level of the connection point N2. The level of the connection point N2 is given to the current detection unit 30 and the differential amplification unit 50 as the reference voltage REF. Here, the corresponding transistors of the current detection units 30 and 40 are set to the same dimension. That is, the PMOSs 31, 41a, and 41b have the same dimensions, the NMOSs 32, 42a, and 42b have the same dimensions, and the NMOSs 33, 43a, and 43b have the same dimensions.

  The differential amplifying unit 50 differentially amplifies the detection voltage DT supplied via the switch unit 60 and the reference voltage REF supplied from the current detection unit 40 and outputs read data RD. The detection voltage DT and the reference voltage REF has NMOSs 51 and 52 which are respectively supplied to the gates. The drains of the NMOSs 51 and 52 are connected to the power supply voltage VDD via the PMOSs 53 and 54, respectively. The sources of the NMOSs 51 and 52 are connected in common and connected to the ground potential GND through the NMOS 55 controlled by the chip enable signal CE. The gates of the PMOSs 53 and 54 are connected to the drain of the NMOS 52, and the signal of the drain of the NMOS 51 is output as read data RD via the inverter 56.

  The switch unit 60 switches the detection voltage DTO output from the current detection unit 30 and the detection voltage DTA output from the current detection unit 70, and supplies the detection voltage DT to the differential amplification unit 50. The switch unit 60 includes a switching NMOS 61 for controlling the connection between the connection point N1 of the current detection unit 30 and the gate of the NMOS 51 of the differential amplification unit 50 by a control signal CED, and a connection point N3 of the current detection unit 70. The switching amplifying NMOS 62 controls the connection between the gates of the NMOS 51 of the differential amplifying unit 50 by a control signal CEDB.

  The current detection unit 70 is connected to the bit line BL of the memory array 10 for a certain period of time at the time of transition from the standby state to the active state, and the current flowing out to the bit line BL with the same circuit configuration as the current detection unit 40. A corresponding detection voltage DTA is generated. The current detector 70 includes a PMOS 71a and NMOSs 72a and 73a connected in series between the power supply voltage VDD and the ground potential GND. Further, a PMOS 71b and NMOSs 72b and 73b are connected in parallel to the PMOS 71a and NMOSs 72a and 73a.

  A chip enable signal CEB is applied to the gates of the PMOSs 71a and 71b, and the connection points of the NMOSs 72a and 73a and the connection points of the NMOSs 72b and 73b are connected to the bit lines via the switching NMOSs 74 that are on / off controlled by the control signal CEDB. BL is connected, and the current of the bit line BL flows into the NMOS 73a and 73b. The gates of the NMOSs 72a, 73a, 72b, and 73b are connected to a common connection point N3 of the PMOS 71a and the NMOS 72a and between the PMOS 71b and the NMOS 72b, and the conduction state is controlled by the level of the connection point N3. The level of the connection point N3 is given to the switch unit 60 as the detection voltage DTA. Here, the PMOSs 71a and 71b and the NMOSs 72a, 72b, 73a and 73b of the current detection unit 70 are set to the same dimensions as the corresponding PMOSs 41a and 41b and NMOSs 42a, 42b, 43a and 43b of the current detection unit 40.

  The delay control unit 80 generates control signals CED and CEDB for the switch unit 60 and the current detection unit 70 based on the chip enable signal CE. The delay control unit 80 delays the chip enable signal CE, and a chip. A negative logical product gate (hereinafter referred to as “NAND”) 82 that inverts and outputs the logical product of the enable signal CE and the chip enable signal CE delayed by the delay element 81 is provided. The output signal of the NAND 82 is inverted by the inverter 83 and output as the control signal CED, and is delayed by the delay element 84 and output as the control signal CEDB.

  FIG. 4 is a signal waveform diagram showing the operation of FIG. Hereinafter, the operation when the sense amplifier of FIG. 1 shifts from the standby state to the active state will be described with reference to FIG.

  In the standby state, the chip enable signals CE and CEB are “L” and “H”, respectively, and no current flows through the current detection units 30, 40, and 70 and the differential amplification unit 50, and the operation is stopped. Yes. At this time, the control signals CED and CEDB output from the delay control unit 80 are “L” and “H”, respectively. Accordingly, the NMOS 61 of the switch unit 60 is off, and the NMOS 62 of the switch unit 60 and the NMOS 74 of the current detection unit 70 are on.

  When the chip enable signal CE changes from “L” to “H” to become an active state, the chip enable signal CEB changes from “H” to “L”, and the current detection units 30, 40, and 70 and the differential amplification unit 50 operations are started. At this time, the control signals CED and CEDB are “L” and “H”, respectively, due to the delay time τ 1 of the delay element 81. Therefore, the NMOS 61 is off and the NMOSs 62 and 74 are on.

  Thereby, the level of the connection point N1 of the current detection unit 30 repeatedly rises and falls similarly to the conventional circuit, and settles to a predetermined detection voltage DTO level. Further, the level of the connection point N2 of the current detection unit 40 gradually increases and reaches the reference voltage REF. Further, in the current detection unit 70, the same operation as that of the current detection unit 40 is performed, and the level of the connection point N3 gradually increases and settles at the detection voltage DTA corresponding to the data of the memory cell MCi.

  At this time, since the NMOS 61 is off, the detection voltage DTO that fluctuates at the connection point N1 of the current detection unit 40 is not supplied to the differential amplification unit 50, and the connection point N3 of the current detection unit 70 is stably detected. The voltage DTA is supplied to the differential amplifier unit 50.

  Next, when the delay time τ1 of the delay element 81 elapses, the control signal CED changes from “L” to “H”. At this time, the control signal CEDB is “H” by the delay element 84. As a result, the NMOSs 61, 62, and 74 are all turned on, and the detection voltage DTO of the current supply unit 30 and the detection voltage VTA of the current detection unit 70 are supplied to the differential amplification unit 50.

  Further, when the delay time τ2 of the delay element 84 elapses, the control signal CEDB changes from “H” to “L”. As a result, the NMOSs 62 and 74 are turned off, and the current detection unit 70 is disconnected from the memory array 10 and the differential amplification unit 50. Thereafter, similarly to the conventional sense amplifier, the detection voltage DTO is generated by the current detection unit 30 based on the data of the memory cell MCi read by the memory array 10, and the detection voltage DTO is referred to by the differential amplification unit 50. The voltage REF is compared and the read data RD is output.

  As described above, the sense amplifier according to the first embodiment has a configuration similar to that of the current detection unit 40 that generates the reference voltage RFE, and current detection that generates the detection voltage DTA according to the current flowing through the bit line BL of the memory array 10. A unit 70 is added, and the detection voltage DTA generated by the current detection unit 70 is supplied to the differential amplification unit 50 for a certain time (τ1) immediately after the transition from the standby state to the active state. Further, the detection voltage DT of the current detection unit 70 and the detection voltage DTO of the current detection unit 30 are given to the differential amplification unit 50 for a certain time (τ2) thereafter, and then the current detection unit 70 is disconnected. As a result, immediately after the transition from the standby state to the active state, the detection voltage DTO that fluctuates in the current detection unit 30 is not applied to the differential amplifier 50, and the access time can be shortened by suppressing the output of pseudo data. There is an advantage that you can.

  FIG. 5 is a configuration diagram of a sense amplifier showing Embodiment 2 of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This sense amplifier has a configuration in which a simplified switch unit 60A (NMOS 62), a current detection unit 70A, and a delay control unit 80A are provided instead of the switch unit 60, the current detection unit 70, and the delay control unit 80 in FIG. It has become.

  The switch unit 60A is obtained by removing the NMOS 61 of the switch unit 60 in FIG. 1 and directly connecting the connection point N1 of the current detection unit 30 to the differential amplification unit 50. As a result, the connection point N1 is connected to the connection point N3 of the current detection unit 70A via the NMOS 62.

  The current detector 70A includes a PMOS 71 and NMOSs 72 and 73 connected in series between the power supply voltage VDD and the ground potential GND. A chip enable signal CEB is given to the gate of the PMOS 71. The gates of the NMOSs 72 and 73 are connected to the connection point N3 between the PMOS 71 and the NMOS 72, and the conduction state is controlled by the level of the connection point N3. A bit line BL is connected to a connection point between the NMOSs 72 and 73 via a switching NMOS 74. The connection point N3 is supplied with the reference voltage REF via the switching NMOS 75, and is connected to the connection point N1 of the current detection unit 30 and the gate of the NMOS 51 of the differential amplification unit 50 via the NMOS 62 of the switch unit 60A. It is connected. The PMOS 71 and the NMOSs 72 and 73 of the current detection unit 70A are set to the same dimensions as the corresponding PMOS 41a and NMOSs 42a and 43a of the current detection unit 40.

  The delay control unit 80A generates a control signal CEDB for the switching NMOSs 62, 74, and 75, and is delayed by the delay element 81 that delays the chip enable signal CE by a predetermined time, the chip enable signal CE, and the delay element 81. The NAND 82 inverts the logical product of the chip enable signals. A control signal CEDB is output from the NAND 82. Other configurations are the same as those in FIG.

  FIG. 6 is a signal waveform diagram showing the operation of FIG. Hereinafter, the operation when the sense amplifier of FIG. 5 shifts from the standby state to the active state will be described with reference to FIG.

  In the standby state, the chip enable signals CE and CEB are “L” and “H”, respectively, and the operations of the current detectors 30, 40, 70A and the differential amplifier 50 are stopped. At this time, the control signal CEDB output from the delay control unit 80A is “H”, and the NMOS 62 of the switch unit 60A and the NMOSs 74 and 75 of the current detection unit 70A are on. Therefore, the current detection units 30 and 70A are connected in parallel.

  When the chip enable signal CE changes from “L” to “H” to become an active state, the chip enable signal CEB changes from “H” to “L”, and the current detection units 30, 40, 70A and the differential amplification unit 50 operations are started. At this time, due to the delay element 81, the control signal CEDB is “H”, and the NMOSs 62, 74, and 75 are on.

  Thereby, the level of the connection point N2 of the current detection unit 40 gradually increases and reaches the reference voltage REF. In the current detection unit 70A, the level of the connection point N3 gradually increases and reaches the reference voltage REF by the same operation as that of the current detection unit 40. On the other hand, the connection point N1 of the current detection unit 30 is connected to the connection point N3 of the current detection unit 70A by the NMOS 62 in the on state. REF is reached.

  When the delay time of the delay element 81 elapses, the control signal CEDB changes from “H” to “L”. Thereby, the NMOSs 62, 74, and 75 are turned off, and the current detection unit 70A is disconnected from the memory array 10 and the differential amplification unit 50. Thereafter, similarly to the conventional sense amplifier, the detection voltage DTO is generated by the current detection unit 30 based on the data of the memory cell MCi read by the memory array 10, and the detection voltage DTO is referred to by the differential amplification unit 50. The voltage REF is compared and the read data RD is output.

  As described above, in the sense amplifier according to the second embodiment, the current detection unit 70A having the same configuration as that of the current detection unit 40 that generates the reference voltage REF has this current for a certain time immediately after the transition from the standby state to the active state. The reference voltage REF generated by the detection unit 70A is output to the connection point N1, and is supplied to the differential amplification unit 50 as the detection voltage DTO. Thus, immediately after the transition from the standby state to the active state, the detection voltage DTO that fluctuates is not output from the current detection unit 30, and the pseudo data is output with a circuit configuration simplified compared to the first embodiment. There is an advantage that the access time can be shortened by suppressing.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although the example of the sense amplifier applied to the ROM has been described, the memory arrays 10 and 20 are not limited to the ROM as long as the current arrays 10 and 20 flow.
(B) Specific circuit configurations of the current detection units 30 and 40 and the differential amplification unit 50 are not limited to those illustrated.
(C) In the current detection unit 40, two transistors having the same dimension are connected in parallel, such as PMOS 41a and 41b, for example, but can be replaced with a transistor having double driving capability. The same applies to the current detection unit 70.

1 is a configuration diagram of a sense amplifier showing Embodiment 1 of the present invention. FIG. It is a block diagram of the conventional sense amplifier. FIG. 3 is a signal waveform diagram illustrating the operation of FIG. 2. It is a signal waveform diagram which shows the operation | movement of FIG. It is a block diagram of the sense amplifier which shows Example 2 of this invention. FIG. 6 is a signal waveform diagram illustrating the operation of FIG. 5.

Explanation of symbols

10, 20 Memory array 30, 40, 70, 70A Current detection unit 50 Differential amplification unit 60, 60A Switch unit 80, 80A Delay control unit

Claims (9)

A first current detection unit that stops operation during standby and generates a reference voltage based on a current output from the first memory cell for reference during normal operation;
A second current detection unit that stops operation during standby and generates a detection voltage based on the current output from the second memory cell to be read and the reference voltage in normal time;
In a sense amplifier having a differential amplifying unit that amplifies a voltage difference between the reference voltage that is one input and the voltage that is the other input and outputs read data at a normal time,
Current detection that generates a voltage corresponding to the current output from the second memory cell when the transition from the standby state to the normal state is performed, and temporarily applies the voltage as the other input of the differential amplifier A sense amplifier characterized in that means are provided.   2. The sense amplifier according to claim 1, wherein the first and second current detection units and the current detection unit are controlled in a standby state and a normal state in accordance with an enable signal.   The current detection means is a switch that selectively supplies the differential amplifier with a third current detector that generates the voltage and a voltage generated by the third current detector according to a control signal. The sense amplifier according to claim 2, further comprising: a control unit configured to generate the control signal based on the enable signal. The first current detector is
A first transistor connected between a first node from which the reference voltage is output and a power supply voltage, the operation of which is controlled by an enable signal;
A second transistor connected between a second node to which a current from the first memory cell is applied and the first node, the conduction state of which is controlled by the voltage of the first node;
A third transistor connected between the second node and a ground potential, the conduction state of which is controlled by the voltage of the first node;
The second current detector is
A fourth transistor connected between a third node from which the detection voltage is output and a power supply voltage and whose operation is controlled by the enable signal;
A fifth transistor connected between a fourth node to which a current from the second memory cell is applied and the third node and whose conduction state is controlled by the reference voltage;
A sixth transistor connected between the fourth node and a ground potential, the conduction state of which is controlled by the voltage of the third node;
The current detection means includes
A seventh transistor connected between a power supply voltage and a fifth node and controlled in operation by the enable signal;
An eighth transistor connected between the fifth node and the sixth node, the conduction state of which is controlled by the voltage of the fifth node;
A ninth transistor connected between the sixth node and a ground potential, the conduction state of which is controlled by the voltage of the fifth node;
Provided between the differential amplifying unit and the third node, and when a transition is made from the standby state to the normal state, it is turned off for a first time and the output of the detection voltage to the differential amplifying unit is stopped. A first switch;
Provided between the differential amplifying unit and the fifth node, and when the transition from the standby state to the normal state, the second node is turned on for a second time longer than the first time, and the voltage of the fifth node is A second switch that outputs the detected voltage to the differential amplifier;
A third switch provided between the second memory cell and the sixth node, which is turned on together with the second switch and outputs a current of the second memory cell to the sixth node; Have
The sense amplifier according to claim 1.   The first, second, and third transistors and the seventh, eighth, and ninth transistors each have a current drive capability twice that of the fourth, fifth, and sixth transistors. The sense amplifier according to claim 4.   The first, second, and third transistors and the seventh, eighth, and ninth transistors are two transistors having the same dimensions as the fourth, fifth, and sixth transistors, respectively, in parallel. 5. The sense amplifier according to claim 4, wherein the sense amplifiers are connected. The first current detector is
A first transistor connected between a first node from which the reference voltage is output and a power supply voltage, the operation of which is controlled by an enable signal;
A second transistor connected between a second node to which a current from the first memory cell is applied and the first node, the conduction state of which is controlled by the voltage of the first node;
A third transistor connected between the second node and a ground potential, the conduction state of which is controlled by the voltage of the first node;
The second current detector is
A fourth transistor connected between a third node from which the detection voltage is output and a power supply voltage and whose operation is controlled by the enable signal;
A fifth transistor connected between a fourth node to which a current from the second memory cell is applied and the third node and whose conduction state is controlled by the reference voltage;
A sixth transistor connected between the fourth node and a ground potential, the conduction state of which is controlled by the voltage of the third node;
The current detection means includes
A seventh transistor connected between a power supply voltage and a fifth node and controlled in operation by the enable signal;
An eighth transistor connected between the fifth node and the sixth node, the conduction state of which is controlled by the voltage of the fifth node;
A ninth transistor connected between the sixth node and a ground potential, the conduction state of which is controlled by the voltage of the fifth node;
A first switch that is provided between the third node and the fifth node and is turned on for a predetermined time when the standby state is shifted to the normal state;
A second switch provided between the first node and the fifth node, which is turned on together with the first switch and outputs the reference voltage to the fifth node;
A third switch provided between the second memory cell and the sixth node, which is turned on together with the first switch and outputs a current of the second memory cell to the sixth node; Have
The sense amplifier according to claim 1.   The first, second, and third transistors have a current drive capability twice that of the fourth, fifth, and sixth transistors, respectively, and the seventh, eighth, and ninth transistors are respectively 8. The sense amplifier according to claim 7, wherein the sense amplifier has the same current drive capability as the fourth, fifth and sixth transistors.   The first, second, and third transistors are configured by connecting two transistors having the same dimensions as the fourth, fifth, and sixth transistors, respectively, in parallel. 8. The sense amplifier according to claim 7, wherein each of the ninth transistors is a transistor having the same dimension as each of the fourth, fifth, and sixth transistors.

Images