JP2009021755A - Difference signal transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is difficult to make a device compact owing to increase of a wiring area because the number of signal lines becomes large when the number of signals becomes large, that is, a number of signal lines as many as two times a number of difference signals are needed to transmit the difference signals. <P>SOLUTION: A resistor is arranged in a path of current caused to flow to a differential input part of a differential output buffer, the value of current caused to flow to the resistor is changed on the basis of a difference input signal to change common mode voltage, a common mode detection buffer detects a change in the common mode voltage, and the difference signal is reconfigured and outputted. The number of signal lines can be reduced to 2/3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a circuit for transmitting a differential digital signal, and relates to a differential signal transmission circuit capable of reducing the number of signal lines.

  FIG. 3 shows a differential signal transmission circuit. This transmission circuit is used for differential signal transmission between semiconductor chips and the like. In FIG. 3, reference numeral 10 denotes a semiconductor chip, in which differential output buffers 11 to 13 are formed. The differential signal is output to the outside of the semiconductor chip 10 through the differential output buffers 11 to 13. Reference numeral 20 denotes a semiconductor chip in which differential input buffers 21 to 23 are formed. The differential signal is taken into the semiconductor chip 20 through the differential input buffers 21-23.

  The output terminals of the differential output buffers 11 to 13 are connected to the input terminals of the differential input buffers 21 to 23, respectively. Differential input signals 1 to 3 are input to the differential output buffers 11 to 13, respectively. The differential input signals 1 to 3 are buffered by the differential output buffers 11 to 13 and input to the differential input buffers 21 to 23 through signal lines. Differential output signals 1 to 3 are output from the differential input buffers 21 to 23 to the semiconductor chip 20. In this way, the differential signal is transmitted from the semiconductor chip 10 into the semiconductor chip 20.

  The differential output buffers 11 to 13 and the differential input buffers 21 to 23 have the same configuration. One ends of the resistors R1 and R2 are connected to the positive power supply VCC, and the other ends are connected to the collectors of the transistors Tr1 and Tr2, respectively. The emitters of the transistors Tr1 and Tr2 are connected in common and connected to one end of the constant current source Is1. The other end of the constant current source Is1 is connected to a negative power source VEE. The differential signal is input to the bases of the transistors Tr1 and Tr2.

  The collectors of the transistors Tr3 and Tr4 are connected to the positive power supply VCC, and their emitters are connected to one ends of the constant current sources Is2 and Is3, respectively. The other ends of the constant current sources Is2 and Is3 are connected to a negative power source VEE. The base of the transistor Tr3 is connected to the connection point between the resistor R2 and the transistor Tr2, and the base of the transistor Tr4 is connected to the connection point between the resistor R1 and the transistor Tr1. The differential signal is output from the emitters of the transistors Tr3 and Tr4.

  In such a configuration, when the base potential of the transistor Tr1 is higher than that of the transistor Tr2, the transistor Tr1 is turned on, the Tr2 is turned off, the transistor Tr3 is turned on, and the Tr4 is turned off. When the base potential of the transistor Tr1 is lower than that of the transistor Tr2, the transistor Tr3 is turned off and the Tr4 is turned on. In this way, the differential signal is buffered.

Since such a differential signal transmission circuit transmits a signal as a differential signal, even if the common mode voltage changes due to noise or the like, this change is eliminated by the differential input buffer. Therefore, the signal can be transmitted reliably without being affected by external conditions such as noise.
JP 2003-018224 A Japanese Patent Laid-Open No. 2004-356714

  However, such a differential signal transmission circuit requires two signal lines in order to transmit one signal. Usually, several tens or more signals are input / output from the semiconductor chip, and therefore, several tens or more signal lines are required between the semiconductor chips. Therefore, the installation area of the signal line is increased, and there is a problem that the device cannot be reduced in size.

  Accordingly, an object of the present invention is to provide a differential signal transmission circuit capable of reducing the number of signal lines.

In order to solve such a problem, the invention according to claim 1 of the present invention,
A first differential signal is input;
A differential input section for causing a current to flow through one of the two paths by the first differential signal and extracting a differential output signal from the two current paths;
A constant current source that outputs a current flowing through the differential input section;
A resistor arranged in the middle of a path through which the output current of the constant current source flows;
A first differential output buffer comprising:
A second differential output buffer that receives a second differential signal and has a configuration similar to that of the first differential output buffer;
A third differential signal is input, and either the current in the first differential output buffer or the current flowing through the resistor in the second differential output buffer according to the third differential signal is input. A common mode voltage controller that changes the value by a certain value;
A first differential input buffer to which an output of the first differential output buffer is input;
A second differential input buffer to which an output of the second differential output buffer is input;
A common mode detection buffer that receives the outputs of the first and second differential output buffers, generates a differential signal from the common mode voltage of the input signals, and outputs the differential signal;
Is provided. The number of signal lines for transmitting differential signals can be reduced.

The invention according to claim 2 is the invention according to claim 1, wherein l,
The resistors in the first and second differential output buffers are arranged between a positive power source and a differential input unit. The circuit configuration is simplified.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
The common mode voltage controller is
Two transistors having the third differential signal input to the base and commonly connected emitters;
A constant current source having one end connected to the emitters of these transistors;
It is made up of. The circuit configuration can be simplified.

The invention according to claim 4 is the invention according to any one of claims 1 to 3,
The common mode detection buffer is:
A differential buffer to which a differential signal is input;
First and second resistors having one end connected in common and connected to one input terminal of the differential buffer and the other end applied with the output of the first differential output buffer;
Third and fourth resistors having one end connected in common and connected to the other input terminal of the differential buffer, and the other end applied with the output of the second differential output buffer;
It is made up of. The circuit configuration is simplified and no termination resistor is required.

The invention according to claim 5 is the invention according to any one of claims 1 to 3,
The common mode detection buffer is:
First and second transistors having a collector connected to one end of a first resistor and an output of the first differential output buffer being input to a base;
Third and fourth transistors, each having a collector connected to one end of the second resistor, and an output of the second differential output buffer being input to the base;
A constant current source having one end connected to the emitters of all of the first to fourth transistors;
Is provided. The circuit configuration is simplified.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, fourth, and fifth inventions, a resistor is disposed in a path of a current flowing through the differential input portion of the differential output buffer, and a current flowing through the resistor based on the differential input signal The common mode voltage was changed by changing the value, the change of the common mode voltage was detected by the common mode detection buffer, and the differential signal was reconfigured and output.

  Since one of the three differential signals is transmitted by changing the common mode voltage, the number of signal lines for transmitting the differential signal can be reduced to 2/3. When the present invention is applied to a semiconductor device including a plurality of semiconductor chips, an area for arranging signal lines can be reduced, so that the semiconductor device can be reduced in size.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a differential signal transmission circuit according to the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 3, and description is abbreviate | omitted. In FIG. 1, the differential signal transmission circuit includes differential output buffers 30a and 30b, a common mode voltage controller 40, differential input buffers 21 and 23, and a common mode detection buffer 50. As in FIG. 3, the differential output buffers 30a and 30b and the common mode voltage control unit 40 are arranged on one semiconductor chip, and the differential input buffers 21 and 23 and the common mode detection buffer 50 are arranged on another semiconductor chip. Although not shown in FIG. The differential output buffers 30a and 30b correspond to first and second differential output buffers, respectively, and the differential input buffers 21 and 23 correspond to first and second differential input buffers, respectively.

  The differential output buffer 30a includes a resistor 31a, a differential input unit 32a, a constant current source 33a, and a differential output unit 34a. The differential input part 32a has the same configuration as the input part of the differential output buffer 11 of FIG. That is, one ends of the resistors R1 and R2 are connected in common, and the other ends are connected to the collectors of the transistors Tr1 and Tr2, respectively. The emitters of the transistors Tr1 and Tr2 are commonly connected. One end of the constant current source 33a is connected to the common connection point of the emitter, and the other end is connected to the negative power source VEE. The differential input signal is applied to the bases of the transistors Tr1 and Tr2.

  The resistor 31a is connected between the common connection point of the positive power supply VCC and the resistors R1 and R2. Therefore, a current is supplied to the differential input unit 32a via the resistor 31a. The current value flowing through the differential input part 32a is equal to the output current value of the constant current source 33a.

  The differential output unit 34a has the same configuration as the output unit of the differential output buffer 11 shown in FIG. That is, the collectors of the transistors Tr3 and Tr4 are connected to the positive power supply VCC, and the emitters are connected to one ends of the constant current sources Is2 and Is3, respectively. The other ends of the constant current sources Is2 and Is3 are connected to a negative power source VEE. The output of the differential input unit 32 is input to the bases of the transistors Tr3 and Tr4. That is, the voltage at the connection point between the resistor R2 and the collector of the transistor Tr2 is input to the base of the transistor Tr3, and the voltage at the connection point between the resistor R1 and the collector of the transistor Tr1 is input to the base of the transistor Tr4.

  The differential output buffer 30b has the same configuration as the differential output buffer 30a. Differential input signal 1 is input to differential output buffer 30a, and differential input signal 2 is input to differential output buffer 30b. In the differential output buffer 30b, the differential input unit is 32b, the constant current source is 33b, the output unit is 34b, and the resistor corresponding to the resistor 31a is 31b.

  The common mode voltage controller 40 includes transistors 41 and 42 and a constant current source 43. The collector of the transistor 41 is connected to the connection point between the resistor 31a and the differential input unit 32a, and the collector of the transistor 42 is connected to the connection point between the resistor 31b and the differential input unit 32b. The emitters of these transistors 41 and 42 are connected in common and connected to one end of a constant current source 43. The other end of the constant current source 43 is connected to a negative power source VEE. The differential input signal 3 is input to the bases of the transistors 41 and 42.

  3, the output of the differential output buffer 30 a is input to the differential input buffer 21, and the output of the differential output buffer 30 b is input to the differential input buffer 23. Differential output signals 1 and 2 are output from the differential input buffers 21 and 23, respectively.

  The common mode detection buffer includes four resistors 51 to 54 and a differential buffer 55 having the same configuration as that of the differential input buffer 21. One ends of the resistors 51 and 52 are connected to one input terminal of the differential buffer 55, and one ends of the resistors 53 and 54 are connected to the other input terminal of the differential buffer 55. The output of the differential output buffer 30a is applied to the other ends of the resistors 51 and 52, and the output of the differential output buffer 30b is applied to the other ends of the resistors 53 and 54. The common mode detection buffer 50 outputs a differential output signal 3 corresponding to the differential input signal 3.

  Next, the operation of this embodiment will be described. The configuration of the differential output buffers 30a and 30b is the same as that of the differential output buffers 11 and 13 except that the resistors 31a and 31b are inserted. The differential input signals 1 and 2 are input to the differential output buffers 30a and 30b, and the outputs are input to the differential input buffers 21 and 23. This operation is the same as the conventional example of FIG. Although the common mode voltage of the differential output buffers 30a and 30b changes due to the resistors 31a and 31b, the signal to be transmitted is not affected by the change of the common mode voltage because it is transmitted as a differential signal.

Assuming that the resistance value of the resistor 31a is R and the output current of the constant current source 43 is I, when the transistor 41 is turned on, the current flowing through the resistor 31a increases by I, and the common mode voltage at the output of the differential output buffer 30a changes. When the common mode voltage of the differential output buffer 30a output when the transistor 41 is off is Vcom, and when it is on, Vc is Vc, the following equation (1) is obtained.
Vc = Vcom−R · I (1)

  The differential output of the differential output buffer 30a is added by resistors 51 and 52 and applied to one input terminal of the differential buffer 55. Since the two signals of the differential output are opposite to each other, the differential component of the signal input to the differential buffer 55 does not appear, and only the common mode voltage Vc of the expression (1) is obtained. Since ON / OFF of the transistor 41 is controlled by the differential input signal 3, this Vc changes according to the differential input signal 3.

  The same is true for the differential output buffer 30b. When the resistance value of the resistor 31b is R, the common mode voltage of the differential output buffer 30b output when the transistor 42 is off is Vcom, and the common mode voltage of the differential output buffer 30b output when the transistor 42 is on is Vc. This Vc is expressed by the above equation (1).

  The differential output of the differential output buffer 30 b is added by the resistors 53 and 54 and applied to the other input terminal of the differential buffer 55. Since the two signals of the differential output are opposite to each other, the differential component of the signal input to the differential buffer 55 does not appear, and only the common mode voltage Vc of the expression (1) is obtained. Since ON / OFF of the transistor 42 is controlled by the differential input signal 3, this Vc changes according to the differential input signal 3.

  That is, the differential input signal 3 can be transmitted using the common mode voltage of the differential output buffers 30a and 30b. As can be seen from the conventional example of FIG. 3, six signal lines are conventionally required to transmit three differential signals. In this embodiment, three differential signals are transmitted by four signal lines. And the number of signal lines can be reduced to 2/3. When there are four or more differential signals to be transmitted, three differential signals are grouped as one set, and the present invention is applied to each set.

  FIG. 2 shows the configuration of another embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted. In FIG. 2, reference numeral 60 denotes a common mode detection buffer, which receives the outputs of the differential output buffers 30 a and 30 b and outputs a differential output signal 3.

  One end of the resistor 61 is connected to the positive power supply VCC, and the other end is connected to the collectors of the transistors 63 and 65. Similarly, one end of the resistor 62 is connected to the positive power supply VCC, and the other end is connected to the collectors of the transistors 64 and 66. The output of the differential output buffer 30a is input to the bases of the transistors 63 and 65, and the output of the differential output buffer 30b is input to the bases of the transistors 64 and 66.

  The emitters of the transistors 63 to 66 are connected to one end of a constant current source 67. The other end of the constant current source 67 is connected to a negative power source VEE. This configuration can be considered as the addition of transistors 65 and 66 to the differential input buffer 21.

The resistance values of the resistors in the differential input sections 32a and 32b are Rs, the output currents of the constant current sources 33a and 33b are Is, the resistance values of the resistors 31a and 31b are Ra and Rb, and the output current of the constant current source 43 is I. , Vcm = (VCC−transistor base-emitter voltage), and select each constant so that the following equation (2) is established.
Ra · I = Rb · I = Rs · Is (2)

In this way, the two outputs Va and Vax of the differential output buffer 30a and the two outputs Vb and Vbx of the differential output buffer 30b are Va = Vcm−Rs · Is / Vcm−2 · Rs when the transistor 41 is on.・ Is
Vax = Vcm−2 · Rs · Is / Vcm−Rs · Is
Vb = Vcm / Vcm-Rs.Is
Vbx = Vcm−Rs · Is / Vcm
When the transistor 41 is off, Va = Vcm / Vcm−Rs · Is
Vax = Vcm−Rs · Is / Vcm
Vb = Vcm−Rs · Is / Vcm−2 · Rs · Is
Vbx = Vcm−2 · Rs · Is / Vcm−Rs · Is
become. There are two values because they change depending on the differential input signals 1 and 2.

  These voltages are compared by transistors 63-66. The aforementioned Va, Vax, Vb, and Vbx are different by a multiple of Rs · Is. If Rs · Is is selected to be a sufficiently large value, the transistor having the highest base potential among the transistors 63 to 66. Only turned on.

  Therefore, when the transistor 41 is on, one of the transistors 64 and 66 is on, and when the transistor 41 is off, one of the transistors 63 and 65 is on. Since ON / OFF of the transistor 41 is controlled by the differential input signal 3, the output of the common mode detection buffer 60 becomes the differential output signal 3 corresponding to the differential input signal 3. For this reason, three differential signals can be transmitted with four signal lines.

  The differential input units 32a and 32b, the differential output units 34a and 34b, and the differential input buffers 21 and 23 are not limited to this configuration. Any configuration can be used as long as a differential output signal corresponding to the input differential signal can be obtained.

  Further, the positions of the resistors 31a and 31b are not limited to those shown in FIGS. 1 and 2, and are negative between the differential input portions 32a and 32b and the constant current sources 33a and 33b, or negative with the constant current sources 33a and 33b. It may be during the power supply VEE. In short, the common mode voltage of the differential output signal may be changed. However, the circuit configuration can be simplified if arranged at the positions shown in FIGS.

  Further, the common mode voltage controller 40 is not limited to the configuration of this embodiment, and any configuration may be used as long as the current is distributed to the differential output buffers 30a and 30b by the differential input signal 3. Further, the configuration of the common mode detection buffer is not limited to that shown in FIGS. Any configuration that detects a change in the common mode voltage and outputs a differential signal may be used.

  Further, in these embodiments, transmission of differential signals between semiconductor chips has been described, but the present invention is not limited to this, and can be applied to other differential signal transmissions.

It is a block diagram which shows one Example of this invention. It is a block diagram which shows the other Example of this invention. It is a block diagram of the conventional differential signal transmission circuit.

Explanation of symbols

21, 23 Differential input buffers 30a, 30b Differential output buffers 31a, 31b, R1, R2, 51-54, 61, 62 Resistors 32a, 32b Differential inputs 33a, 33b, 43, 67 Constant current sources 34a, 34b Differential output unit 40 Common mode voltage control units 41, 42, 63 to 66, Tr1, Tr2 Transistors 50, 60 Common mode detection buffer 55 Differential buffer

Claims (5)

A first differential signal is input;
A differential input section for causing a current to flow through one of the two paths by the first differential signal and extracting a differential output signal from the two current paths;
A constant current source that outputs a current flowing through the differential input section;
A resistor arranged in the middle of a path through which the output current of the constant current source flows;
A first differential output buffer comprising:
A second differential output buffer that receives a second differential signal and has a configuration similar to that of the first differential output buffer;
A third differential signal is input, and either the current in the first differential output buffer or the current flowing through the resistor in the second differential output buffer according to the third differential signal is input. A common mode voltage controller that changes the value by a certain value;
A first differential input buffer to which an output of the first differential output buffer is input;
A second differential input buffer to which an output of the second differential output buffer is input;
A common mode detection buffer that receives the outputs of the first and second differential output buffers, generates a differential signal from the common mode voltage of the input signals, and outputs the differential signal;
A differential signal transmission circuit comprising:   2. The differential signal transmission circuit according to claim 1, wherein the resistors in the first and second differential output buffers are disposed between a positive power source and a differential input unit. The common mode voltage controller is
Two transistors having the third differential signal input to the base and commonly connected emitters;
A constant current source having one end connected to the emitters of these transistors;
The differential transmission circuit according to claim 1, wherein the differential transmission circuit is configured as follows. The common mode detection buffer is:
A differential buffer to which a differential signal is input;
First and second resistors having one end connected in common and connected to one input terminal of the differential buffer and the other end applied with the output of the first differential output buffer;
Third and fourth resistors having one end connected in common and connected to the other input terminal of the differential buffer, and the other end applied with the output of the second differential output buffer;
The differential signal transmission circuit according to claim 1, wherein the differential signal transmission circuit is configured as follows. The common mode detection buffer is:
First and second transistors having a collector connected to one end of a first resistor and an output of the first differential output buffer being input to a base;
Third and fourth transistors, each having a collector connected to one end of the second resistor, and an output of the second differential output buffer being input to the base;
A constant current source having one end connected to the emitters of all of the first to fourth transistors;
The differential signal transmission circuit according to claim 1, further comprising:

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