JP2009017014A - Device, method and program for decoding video and device for receiving broadcasting signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To internally monitor a time required for decoding a frame, and to decide whether there is enough time or decoding processing fails due to lack of time on the basis of an actual time required for decoding processing. <P>SOLUTION: Differences among the decoding processing times of each frame within an accumulation range and the intervals of vertical synchronizing signals Vsync are accumulated to compute accumulation delays, wherein a fixed number of frames are defined as the range (the accumulation range) of a time monitor. The accumulation delay indicates the degree of margin of decoding processing times to the intervals of the vertical synchronizing signals Vsync. The frames to be monitored within the accumulation range are slid while decoding the frames. When the accumulation delay is larger than a failure-accumulation threshold value VTH indicating the failure of the decoding processing, the decoding processing failure is decided because of accumulation of delay with time. When the accumulation delay is smaller than a margin accumulation value STH indicating decoding processing margin, then, there is a margin in the decoding section, and an idle time is generated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video decoding device, a video decoding method, a video decoding program, and a broadcast signal receiving device.

Depending on the nature of the compressed video signal, the decoding process may take some time, and the decoding process cannot be completed before the vertical sync signal, so the video display cannot be performed in synchronization with the vertical sync signal, and the video display In some cases, it may cause problems that can be recognized even by appearance, such as delays in frames and dropped frames.
That is, if the decoding process of a frame with a large amount of information frequently occurs, the time delay of the decoding process will continuously occur, the time delay of the entire decoding process accumulates, and the time of the entire system will increase. Failure may occur.

  In addition, when an error occurs in the video decoding process, the error recovery process is loaded in some cases, and the processing delay further increases.

  In order to avoid such a failure, the bit rate of the input stream containing the compressed video is measured, the measured bit rate is compared with a predetermined threshold, and the frame to be decoded is thinned out to display the video. A method for preventing a failure such as a delay in the time period has been considered (see, for example, paragraphs [0059] and [0060] of Patent Document 1). However, in this case, since it is not the failure determination in real time required for the decoding process of the frame, it cannot be said that the technology can accurately determine the failure.

On the other hand, if the amount of information in the input stream is small and the amount of information in each encoded frame is small, the time required for the decoding process becomes very short, compared to the period of the vertical synchronization signal. Thus, it is expected that there will be a margin in the time required for the decoding process.
Japanese Patent Laid-Open No. 11-275518

  If the time required to decode the frame is monitored internally and it can be determined that the decoding process has broken down in time, the operating frequency is increased to reduce the time required to decode the frame, or all Instead of performing a frame decoding process, any one of the coping methods can be taken, in which only an IDR (Instantaneous Decoder Refresh) picture is decoded (decimation process).

  In portable devices, it is also important to reduce power consumption. However, if it is not possible to accurately determine the failure of the decoding process, it is not easy to dynamically change the system operating frequency, and even if the load on the decoding process is light, the power consumption can be reduced. Is difficult. If the time required to decode a frame can be monitored internally and it can be determined that there is a margin in the decoding process, the operating frequency can be lowered to reduce power consumption.

  Based on the above, the time required to decode the frame is internally monitored, and based on the actual time required for the decoding process, it is determined that the decoding process has failed in time or that there is room in the decoding process. There is a demand for a video decoding device, a video decoding method, a video decoding program, and a broadcast signal receiving device that can decode video under conditions according to the determination result.

  Each time a new frame is decoded, the video decoding device of the present invention calculates a decoding delay that is a difference between a decoding processing time required to decode the new frame and an input interval of a predetermined interrupt signal. , For the accumulation range including the new frame and a predetermined number of consecutive frames decoded before the new frame is decoded, the decoding delay of the new frame and the predetermined number of consecutive frames An accumulated delay calculating unit that adds a decoding delay to obtain an accumulated delay, and a selecting unit that compares the accumulated delay with a predetermined accumulated threshold and selects a predetermined decoding processing condition according to the comparison result. A control unit including the decoding unit, and a decoding unit configured to decode the video under the predetermined decoding processing condition.

  Preferably, in the video decoding device according to the present invention, the control unit compares a decoding interval between the completion of decoding of the previous frame and the start of decoding of the next frame with a predetermined interval threshold, and the decoding When the interval is larger than the interval threshold, an accumulated delay initialization unit that initializes internal information related to the accumulated delay and causes the accumulated delay calculation unit to calculate an accumulated delay from the next frame is included.

  Preferably, the video decoding apparatus according to the present invention includes a clock supply unit that supplies a clock having a frequency corresponding to a frequency instruction signal to the decoding unit, and the selection unit supplies the decoding unit as the decoding processing condition. The frequency of the clock to be selected is selected, and the frequency instruction signal is output to the clock supply unit so as to supply a clock corresponding to the selected frequency.

  Preferably, in the video decoding device according to the present invention, the selection unit is configured to increase the frequency of the clock supplied to the decoding unit when the accumulated delay is greater than the predetermined accumulation threshold. A signal is output to the clock supply unit.

  Preferably, in the video decoding device according to the present invention, the selection unit is configured to reduce the frequency of the clock supplied to the decoding unit when the accumulated delay is smaller than the predetermined accumulation threshold. A signal is output to the clock supply unit.

  Preferably, in the video decoding device according to the present invention, the selection unit is configured to reduce the frequency of the clock supplied to the decoding unit when the accumulated delay is smaller than a first accumulation threshold. A signal is output to the clock supply unit, and the frequency of the clock supplied to the decoding unit is maintained when the accumulated delay is greater than or equal to the first accumulation threshold and less than or equal to the second accumulation threshold. The frequency instruction signal is output to the clock supply unit, and when the accumulated delay is larger than the second accumulation threshold, the frequency of the clock supplied to the decoding unit is increased. The frequency instruction signal is output to the clock supply unit.

  Preferably, in the video decoding device according to the present invention, when the accumulation delay is larger than the predetermined accumulation threshold, the selection unit does not refer to information of another frame when encoded as the decoding processing condition. Choose to decode the frame.

  Preferably, in the video decoding device of the present invention, when the power saving mode is set, the selection unit decodes a frame that does not refer to information of another frame when being encoded, as the decoding processing condition. select.

  Preferably, the video decoding apparatus according to the present invention generates the predetermined interrupt signal to be input to the control unit when a vertical synchronization signal is generated or is input, and the predetermined interrupt signal causes the predetermined interrupt signal to be generated. A vertical synchronization signal unit that notifies the control unit that the vertical synchronization signal has been generated or input; and the control unit measures the decoding processing time, the input interval of the predetermined interrupt signal, and the decoding interval Includes a timer to perform.

  The video decoding method of the present invention is a video decoding method in a video decoding device including a decoding unit that decodes video, and is required to decode a new frame each time a new frame is decoded. A step of calculating a decoding delay which is a difference between a decoding processing time and an input interval of a predetermined interrupt signal; and a predetermined number of consecutive frames decoded before the new frame and the new frame are decoded. Adding a decoding delay of the new frame and a decoding delay of the predetermined number of consecutive frames to obtain an accumulation delay, and comparing the accumulated delay with a predetermined accumulation threshold. The step of selecting a predetermined decoding process condition according to the comparison result, and the step of the decoding unit performing a decoding process under the predetermined decoding process condition.

  The video decoding program of the present invention is a video decoding program for causing a computer to execute a video decoding process, and a decoding process required for decoding a new frame each time a new frame is decoded. Calculating a decoding delay, which is a difference between the time and an input interval of a predetermined interrupt signal, and a cumulative number including the new frame and a predetermined number of consecutive frames decoded before the new frame is decoded. Adding a decoding delay of the new frame and a decoding delay of the predetermined number of consecutive frames to obtain an accumulation delay for the calculation range; comparing the accumulated delay with a predetermined accumulation threshold; A step of selecting a predetermined decoding process condition according to the comparison result and a step of performing a decoding process under the predetermined decoding process condition are executed by a computer.

  The broadcast signal receiving apparatus of the present invention includes a receiving unit that receives a broadcast signal including an input stream, a separating unit that separates an encoded video from the input stream, and a control unit that selects a predetermined decoding processing condition. And a decoding unit that decodes the video under the predetermined decoding processing condition, and each time the control unit decodes a new frame, a decoding processing time required to decode the new frame; Calculate a decoding delay that is a difference from an input interval of a predetermined interrupt signal, and an accumulation range including a predetermined number of consecutive frames decoded before the new frame and the new frame are decoded, An accumulated delay calculation unit that obtains an accumulated delay by adding the decoded delay of the new frame and the predetermined number of consecutive frames, and compares the accumulated delay with a predetermined accumulated threshold; Comparison And a selector for selecting the predetermined decoding processing conditions in accordance with the result.

According to the present invention, every time a new frame is decoded, the accumulated delay calculation unit decodes a decoding processing time required to decode the new frame and a predetermined interrupt signal input interval (vertical synchronization signal A decoding delay that is a difference between the new frame and an accumulation range including a predetermined number of consecutive frames decoded before the new frame is decoded. The accumulated delay is obtained by adding the decoding delay and the decoding delay of the predetermined number of consecutive frames. Thus, as the frame decoding process proceeds, the monitoring target frame included in the accumulation range is slid while the accumulation range remains unchanged. The accumulated delay represents a margin of time required for the decoding process with respect to the interval of the vertical synchronization signal, with a plurality of frames included in the accumulated range as a group.
Then, the selection unit compares the accumulated delay with a predetermined accumulation threshold, selects a predetermined decoding processing condition according to the comparison result, and the decoding unit decodes the video under the predetermined decoding processing condition.
For this reason, the time required to decode the frame is monitored internally by the accumulated delay, and it is determined based on the accumulated delay that the decoding process has failed in time or that there is a margin in the decoding process. The video can be decoded under conditions according to the result.

  As described above, according to the present invention, the time required to decode a frame is internally monitored, and based on the actual time required for the decoding process, the decoding process has failed in time or the decoding process. It is possible to determine that there is a margin, and to decode the video under conditions according to the determination result.

FIG. 1 is a block diagram showing an example of the configuration of a 1-segment broadcast receiving apparatus according to an embodiment of the present invention.
The 1-segment broadcast receiving apparatus 10 includes a tuner unit 20, a host unit 30, a video unit 40, a clock supply unit 50, and a memory 60.
One-segment broadcasting (one-segment broadcasting) broadcasts a program (simple moving picture) for mobile terminals using radio waves of terrestrial digital broadcasting. The video of 1-segment broadcasting is H.264, which is a video encoding standard. It is encoded by H.264 and includes 15 frames per second.

  The tuner unit 20 receives a 1-segment broadcast signal including an input stream. The tuner unit 20 includes a buffer memory and accumulates an input stream. When there is an input stream input request c 1 from the host unit 30, the tuner unit 20 outputs the input stream stored in the buffer memory to the host unit 30.

  The host unit 30 includes a host control unit 31 and a Demux (Demultiplexer) 32. The host control unit 31 performs an instruction c2 such as a mode setting of the Demux 32 and an address for writing the separated audio and video to the memory 60. The host control unit 31 includes a CPU and a memory. The Demux 32 separates audio and video, and writes the separated audio and video to the memory 60. When the separation of audio and video is completed, the Demux 32 notifies the host control unit 31 with an interrupt signal i1.

  The video unit 40 includes a decoding unit 41, a video control unit 42, a vertical synchronization signal unit 43, and a video I / F (video interface) 44. The video unit 40 and the host unit 30 communicate with each other by the interrupt signal i2 regarding video decoding processing.

  The decoding unit 41 reads the encoded video from the memory 60 and decodes it. When the decoding of the video is completed, the decoding unit 41 notifies the video control unit 42 with an interrupt signal i3.

The video control unit 42 includes a CPU, a memory, and a timer 421.
The video control unit 42 sets modes such as later-described decoding processing conditions to the decoding unit 41, and gives an instruction c3 such as the address and size of the video data stored in the memory 60. The setting of the decoding processing condition will be described later in detail.
In addition, the video control unit 42 outputs a frequency instruction signal c <b> 5 that indicates the frequency of the clock supplied to the decoding unit 41 to the clock supply unit 50.
Further, the video control unit 42 gives an instruction c4 such as mode setting and scaling of the video I / F 44.

  The vertical synchronization signal unit 43 notifies the video control unit 42 of the generation of the vertical synchronization signal Vsync by the interrupt signal i4. The vertical synchronization signal unit 43 may periodically generate the vertical synchronization signal Vsync internally, or may be one in which the vertical synchronization signal Vsync is input from the outside of the 1-segment broadcasting receiver 10. .

  The video I / F 44 receives the decoded video from the decoding unit 41, performs mode setting for the display device, and outputs the video to the display device.

The clock supply unit 50 includes a clock generation circuit 51, a frequency divider 52, and a frequency register 53.
The clock generation circuit 51 includes a PLL (Phase Locked Loop), and generates an internal clock by multiplying an external clock by an integer. The generated internal clock is supplied to the tuner unit 20, the host unit 30, and the video unit 40. A frequency divider may be provided for each block of the video unit 40, etc., and an internal clock may be divided as necessary for each block, and the frequency may be changed and supplied to each block. When an external clock having a sufficiently high frequency can be supplied from the outside of the 1-segment broadcast receiving apparatus 10, the clock generation circuit 51 may be omitted and the external clock may be directly used as the internal clock.

The generated internal clock is frequency-divided by the frequency divider 52 and also supplied to the decoding unit 41.
The frequency divider 52 divides the internal clock supplied from the clock generation circuit 51 by the frequency dividing ratio stored in the frequency register 53, and changes the frequency of the internal clock.
In the frequency register 53, the frequency division ratio is set by the frequency instruction signal c5 output from the video control unit. Note that the operating frequency of the decoding unit 41 may be set in the frequency register 53, and the set operating frequency may be converted into a frequency dividing ratio and supplied to the frequency divider 52.

  The tuner unit 20 is an example of the receiving unit of the present invention, the Demux 32 is an example of the separating unit of the present invention, the video control unit 42 is an example of the controlling unit of the present invention, and the decoding unit 41 is the decoding unit of the present invention. The clock supply unit 50 is an example of the clock supply unit of the present invention, the vertical synchronization signal unit 43 is an example of the vertical synchronization signal unit of the present invention, and the timer 421 is an example of the timer of the present invention. The frequency instruction signal c5 is an example of the frequency instruction signal of the present invention, and the vertical synchronization signal Vsync is an example of the predetermined interrupt signal of the present invention.

FIG. 2 is a diagram illustrating an example of a change in the video signal from reception of the 1-segment broadcast signal to video output.
The tuner unit 20 receives a 1-segment broadcast signal. One-segment broadcasting signal includes a transport stream of the MPEG-2 system.
The transport stream is a sequence of 188-byte fixed-length packets called TS (transport stream) packets. PAT (Program Association Table), PMT (Program Map Table), PCR (Program Clock Reference, program standard reference value), audio and video bit stream, etc. are transmitted by TS packet .
The bit stream of audio and video is multiplexed into a PES (Packetized Elementary Stream) packet and further multiplexed into a TS packet.

  The Demux 32 separates the audio and video bit streams from the TS packets in units of access units (AU) and writes them to the data holding area of the memory 60.

  The host control unit 31 analyzes the information of each access unit in advance, and acquires the header information of the access unit and the address on the memory 60 of the video data to be decoded. Address ADR1, address ADR2, and address ADR3 are examples of head addresses of video data to be decoded. The header information of these access units and the video data address to be decoded are notified to the video unit 40 using interrupt i2 based communication. The AU delimiter indicates the start of an access unit, and EOS (End Of Sequence) indicates the end of one sequence.

  The decoding unit 41 is notified of the address of the video data to be decoded on the memory 60 via the video control unit 42, reads the video data to be decoded from the memory 60, and decodes each frame. In FIG. 2, the frame FR1 is decoded from the video data read from the address ADR1 of the memory 60, and the frames FR2 and FR3 are decoded from the video data read from the addresses ADR2 and ADR3 of the memory 60, respectively.

FIG. 3 is a diagram illustrating an example in which it is determined that the decoding process has not failed based on the actual time required for the video decoding process according to an embodiment of the present invention.
A predetermined number of frames (for example, 5 frames) is set as a time monitoring range (hereinafter referred to as an accumulation range), and a decoding delay that is a difference between the decoding processing time of each frame in the accumulation range and the interval of the vertical synchronization signal Vsync is accumulated. Calculate the accumulated delay. That is, as the frame decoding process proceeds, the monitoring target frame included in the accumulation range is slid while the accumulation range (for example, 5 frames) remains unchanged. The accumulated delay indicates a margin of time required for the decoding process with respect to the interval of the vertical synchronization signal Vsync by taking a plurality of frames included in the accumulated range as a group.
When the accumulated delay is larger than the failure accumulation threshold VTH indicating the failure of the decoding process, it is determined that the decoding process has failed as a result of the accumulation of time delay. On the other hand, when the accumulated delay is smaller than the margin accumulation threshold value STH indicating that there is a margin in the decoding process, it is determined that there is a margin in the processing of the decoding unit and the idle time has occurred.

  FIG. 3 shows a case where no failure occurs in the decoding processing of the frames FR1 to FR7. In FIG. 3, the accumulation range is 5 frames, and the accumulation range RNG1 to be determined first includes the frames FR1 to FR5. The accumulated decoding delay, which is the difference between the “decoding processing time of each frame” included in the accumulation range RNG1 and the “interval of the vertical synchronization signal Vsync”, is the accumulated delay DLY1, and the accumulated delay DLY1 is failed accumulated. The determination of failure is made based on whether or not the threshold value is greater than VTH. Next, when the frame FR6 is newly decoded, one target frame in the accumulation range is updated. That is, the accumulation range RNG2 covers the frames FR2 to FR6, and the accumulated difference is the accumulation delay DLY2. Similarly, when the frame FR7 is decoded, the target frame in the accumulation range is further updated, and the accumulation range RNG3 is subject to the frames FR3 to FR7, and the accumulated difference becomes the accumulation delay DLY3.

  In 1-segment broadcasting, the interval of the vertical synchronization signal Vsync is 66 ms. In FIG. 3, for example, the failure accumulation threshold VTH is set to 165 ms, and the time required for decoding the frame FR1, the frame FR2, the frame FR3, the frame FR4, the frame FR5, the frame FR6, and the frame FR7 is 198 ms, 66 ms, 99 ms, 33 ms, respectively. 33 ms, 33 ms, and 165 ms. At this time, the decoding delays of the frames FR1 to FR7 are 132 ms, 0 ms, 33 ms, −33 ms, −33 ms, −33 ms, and 99 ms, respectively, and the accumulated delay DLY1, the accumulated delay DLY2, and the accumulated delay DLY3 are respectively 99 ms, −66 ms, and 33 ms. Accordingly, the accumulated delay DLY1, the accumulated delay DLY2, and the accumulated delay DLY3 are all smaller than the failed accumulation threshold VTH, so that no failure has occurred in the accumulated range RNG1, the accumulated range RNG2, and the accumulated range RNG3. It is determined.

  FIG. 4 is a diagram illustrating an example in which it is determined that the decoding process has failed based on the actual time required for the video decoding process according to an embodiment of the present invention. It is determined that the frame FR11 to frame FR15 included in the accumulation range RNG11 has failed. In FIG. 4, for example, the failure accumulation threshold VTH is set to 165 ms, and the time required to decode the frame FR10, the frame FR11, the frame FR12, the frame FR13, the frame FR14, and the frame FR15 is 99 ms, 198 ms, 33 ms, 66 ms, 33 ms, and 198 ms, respectively. And At this time, the decoding delays of the frames FR10 to FR15 are 33 ms, 132 ms, −33 ms, 0 ms, −33 ms, and 132 ms, respectively, and the accumulated delay DLY10 and the accumulated delay DLY11 are 99 ms and 198 ms, respectively. Accordingly, since the accumulated delay DLY10 is smaller than the failure accumulation threshold VTH, it is determined that no failure has occurred in the decoding processing of the frames FR10 to FR14 included in the accumulation range RNG10. On the other hand, since the accumulated delay DLY11 is larger than the failed accumulation threshold VTH, it is determined that a failure has occurred in the decoding processing of the frames FR11 to FR15 included in the accumulated range RNG11.

FIG. 5 is a diagram showing a flowchart of processing for changing the operating frequency of the decoding unit according to an embodiment of the present invention.
The video control unit 42 receives the decoding of the frame (step ST1). At this time, the decoding process has not yet been executed for the accepted frame.
Next, the decoding start time of the accepted frame is acquired (step ST2), and the frame is decoded (step ST3). The decoding start time is obtained by reading the count value of the timer 421 included in the video control unit 42.
Next, the decoding completion time of the frame is acquired (step ST4), and the decoding processing time of the frame is calculated by subtracting the decoding start time from the decoding completion time (step ST5). The decoding completion time is obtained by reading the count value of the timer 421 included in the video control unit 42.
Next, a decoding delay that is the difference between the decoding processing time of the frame and the interval of the vertical synchronization signal Vsync is calculated (step ST6), and the accumulation range is updated to calculate the accumulation delay (step ST7).

Next, the calculated accumulated delay is compared with the failure accumulation threshold VTH (step ST8). When the accumulated delay is greater than the failure accumulation threshold VTH, it is determined that a time failure has occurred in the decoding process, and error recovery processing is performed (step ST9). As error recovery processing, initialization of internal information relating to accumulated delay, skipping decoding processing to the nearest IDR picture, and the like can be considered. In some cases, an error concealment process in the decoding unit 41 also occurs.
After the error recovery process, the frequency instruction signal c5 is output to the clock supply unit 50 so that the frequency of the clock supplied to the decoding unit 41 is increased, and the operating frequency of the decoding unit 41 is increased (step ST10). As a result, since the decoding processing time is shortened, it is possible to prevent another time failure.

  In step ST10, instead of increasing the operating frequency of the decoding unit 41, only the IDR picture may be decoded (decimation process) instead of decoding all the frames. This method can also prevent the occurrence of time failure again.

  In step ST8, when the accumulated delay is not more than the failure accumulation threshold VTH, the accumulated delay is compared with the margin accumulated threshold STH (step ST11). When the accumulated delay is smaller than the margin accumulated threshold value STH, the frequency instruction signal c5 is output to the clock supply unit 50 so that the frequency of the clock supplied to the decoding unit 41 is decreased, and the operating frequency of the decoding unit 41 is decreased. (Step ST12). The margin accumulation threshold value STH is, for example, a negative value. When the accumulation delay is smaller than the margin accumulation threshold value STH, there is a margin in the decoding process of the decoding unit 41, indicating that the decoding unit 41 has idle time. Show. At this time, the power consumption of the decoding unit 41 can be reduced by lowering the operating frequency.

  The accumulation range and the failure accumulation threshold VTH are adjusted according to the contents of the 1-segment broadcasting and the performance of the decoding unit 41. For example, the video included in the received broadcast is decoded for a certain period of time, and an appropriate accumulation range and failure accumulation threshold VTH in the video are determined. For example, when the video included in the broadcast is complicated and includes many frames that require time for decoding, the number of frames in the accumulation range is increased or the failure accumulation threshold VTH is decreased.

Steps ST1 to ST7 are examples of processing performed by the accumulated delay calculation unit of the present invention. Steps ST8 to ST12 are examples of processing performed by the selection unit of the present invention. It is an example of the frame which does not refer to the information of other frames when being encoded according to the present invention.
The failure accumulation threshold VTH is an example of the predetermined accumulation threshold and the second accumulation threshold according to the present invention, and the margin accumulation threshold STH is an example of the predetermined accumulation threshold and the first accumulation threshold according to the present invention. It is an example.

FIG. 6 is a diagram illustrating an example of an initialization process according to a frame decoding interval according to an embodiment of the present invention.
In FIG. 6, frame FR20 to frame FR23 are decoded. The decoding start time and decoding completion time of the frame FR20 are T0 and T1, respectively. Further, the decoding start time and decoding completion time of the frame FR21 are T2 and T3, respectively, the decoding start time and decoding completion time of the frame FR22 are T4 and T5, respectively, and the decoding start time and decoding completion time of the frame FR23 are respectively T6 and T7.
The difference (T2-T1) between the decoding completion time T1 of the frame FR20 and the decoding start time T2 of the frame FR21 is the decoding interval between the frames FR20 and FR21, which is 30 ms. Similarly, the decoding interval (T4-T3) between the frames FR21 and FR22 is 100 ms, and the decoding interval (T6-T5) between the frames FR22 and FR23 is 40 ms.

  When receiving 1-segment broadcasting, radio waves may not be received due to the presence of radio wave obstructions or radio wave reflections, and the input stream may be interrupted. In this case, as shown in FIG. 6, the decoding interval of the frame decoding process is free. For this reason, in the 1-segment broadcast receiving apparatus 10, normally, the allowable break time of the input stream is defined.

  Therefore, when monitoring the time required for the video decoding process using the accumulation range, if the decoding interval of the frame decoding process becomes long, the internal information regarding the accumulated delay is initialized and the frame for starting decoding Recalculate the accumulated delay from. This is because, if there is a sufficient interval between the decoding processes of frames, even if the decoding process of complex frames has occurred frequently and a time failure is about to occur, the time of this decoding interval will increase the time. This is based on the idea that a major bankruptcy is avoided.

That is, the time interval from the time when the decoding process of the immediately previous frame is completed to the time when the decoding process of the current frame is started is monitored, and it is determined whether or not the interval threshold ITH is exceeded. This interval threshold value ITH is determined by the allowable break time of the input stream.
If the frame decoding interval is longer than the interval threshold ITH, even if the accumulated delay is likely to exceed the failure accumulated threshold VTH, the internal information on the accumulated delay is initialized and decoding is started. Recalculate the accumulated delay from the frame you are trying to do.

  In FIG. 6, when the interval threshold ITH is 50 ms, the decoding interval (T4-T3) for decoding the frames FR21 and FR22 is 100 ms, which is longer than the interval threshold ITH. For this reason, when decoding of the frame FR22 is started, internal information regarding the accumulated delay is initialized, and a new accumulated delay is calculated from the frame FR22.

FIG. 7 is a diagram showing a flowchart of initialization processing according to a frame decoding interval according to an embodiment of the present invention.
The video control unit 42 accepts decoding of the first frame (step ST20). At this time, the decoding process has not yet been executed for the accepted frame.
Next, the received frame is decoded (step ST21), and the decoding completion time of the frame is acquired (step ST22). The decoding completion time is obtained by reading the count value of the timer 421 included in the video control unit 42.
Next, the decoding of the next frame is accepted (step ST23). At this time, the decoding process has not yet been executed for the accepted frame.
Next, the decoding start time of the received frame is acquired (step ST24), and the decoding interval of the frame decoding process is calculated by subtracting the decoding completion time of the previous frame from the decoding start time of the current frame (step ST24). ST25).

Next, the calculated decoding interval is compared with the interval threshold ITH (step ST26). When the decoding interval is larger than the interval threshold ITH, internal information regarding the accumulated delay is initialized (step ST27), and the accumulated delay is recalculated from the current frame.
In step ST26, when the decoding interval is equal to or smaller than the interval threshold ITH, internal information regarding the accumulated delay so far is held.

It is also conceivable to monitor the actual time required for video decoding processing to detect failure of the decoding processing and to provide a power saving mode. For example, when the power saving mode is set by the user, the operating frequency is forcibly decreased regardless of the accumulated delay.
However, it is necessary to avoid the occurrence of a temporal failure due to a decrease in the decoding processing capability due to a decrease in the operating frequency. Therefore, when the power saving mode is set, the method is switched from the method of decoding all frames as normally performed to the method of decoding only the IDR picture.

  Even when only the IDR picture is decoded, a temporal failure may occur. For this reason, a method of monitoring the actual time required for video decoding processing and detecting failure of the decoding processing can be used in combination with the power saving mode. Specifically, when a temporal failure of the decoding process is detected during the operation in the power saving mode, the operating frequency of the decoding unit 41 is increased. At this time, with the mode transition (from the power saving mode to the normal mode), it is possible to select whether to decode all frames or only the IDR picture until a certain amount of processing time can be grasped. May be.

  Steps ST25 to ST27 are examples of processing in the accumulated delay initialization unit of the present invention. The interval threshold ITH is an example of a predetermined interval threshold according to the present invention.

FIG. 8 is a block diagram showing an example of the configuration of a video unit according to an embodiment of the present invention.
The video unit 40 includes a decoding unit 41, a video control unit 42, a vertical synchronization signal unit 43, and a video I / F 44. 1 and 8 indicate the same components.

  The vertical synchronization signal unit 43 and the video I / F 44 are realized by hardware (HW). Although the decoding unit 41 is realized by hardware in FIG. 8, it may be realized by a DSP (Digital Signal Processor) or software on the CPU.

  The video control unit 42 includes a CPU, a memory, and a timer 421 as hardware. The accumulated delay calculation unit 422, the accumulated delay initialization unit 423, and the selection unit 424 included in the video control unit 42 are realized as software (SW).

  Each time a new frame is decoded, the accumulated delay calculation unit 422 calculates a decoding delay that is the difference between the decoding processing time required to decode this frame and the interval of the vertical synchronization signal Vsync. An accumulation delay is obtained by adding a decoding delay to an accumulation range including a new frame and a predetermined number of frames decoded before the new frame is decoded.

  The accumulated delay initialization unit 423 compares the decoding interval from the completion of decoding of the previous frame to the start of decoding of the next frame with the interval threshold ITH, and when the decoding interval is larger than the interval threshold ITH, The internal information about the accumulated delay is initialized, and the accumulated delay is calculated from the next frame.

The selection unit 424 compares the accumulated delay with the failure accumulation threshold VTH or the margin accumulation threshold STH, and selects a decoding processing condition according to the comparison result. Decoding processing conditions include, for example, the operating frequency of the decoding unit 41, selection of whether to decode all frames or only IDR pictures, and the like.
In addition, when the power saving mode is set, the selection unit 424 decodes only the IDR picture. Even when operating in the power saving mode, the accumulated delay calculating unit 422 and the accumulated delay initializing unit 423 are operating, and when the temporal failure of the decoding process is detected, the selecting unit 424 Increase operating frequency.

  The accumulated delay calculation unit 422 is an example of the accumulated delay calculation unit of the present invention, the accumulated delay initialization unit 423 is an example of the accumulated delay initialization unit of the present invention, and the selection unit 424 is the present invention. It is an example of a selection part.

  In addition, although the 1-segment broadcasting signal includes audio, the change in the video decoding process condition described above does not affect the audio decoding, and therefore, processing such as initialization is not necessary for the audio decoding portion.

  As described above, according to the present invention, the video decoding processing time is internally monitored, and based on the actual time required for the decoding processing, the decoding processing has failed in time and the decoding processing has a margin. It is possible to determine that there is a video and decode the video under conditions according to the determination result. Therefore, it is possible to dynamically change the operating frequency of the decoding unit 41 according to the complexity of the frame to be decoded, or to select whether to decode all frames or only the IDR picture.

  In the above description, the 1-segment broadcasting receiving apparatus has been described as an example. However, the present invention can also be applied to a satellite broadcasting for mobile objects and a broadcasting receiving apparatus via a network based on the IP (Internet Protocol) system.

  Although the embodiments of the present invention have been described above, various modifications and combinations necessary for design reasons and other factors are described in the inventions described in the claims and the specific embodiments described in the embodiments of the invention. It should be understood that it falls within the scope of the invention corresponding to the examples.

It is a block diagram which shows an example of a structure of the 1-segment broadcast receiver which concerns on one Embodiment of this invention. It is a figure which shows an example of the change of the video signal from reception of 1 segment broadcast signal to video output. It is a figure which shows the example determined with the decoding process not failing based on the actual time which the decoding process of the image | video which concerns on one Embodiment of this invention requires. It is a figure which shows the example determined with the decoding process having failed based on the actual time which the decoding process of the image | video which concerns on one Embodiment of this invention requires. It is a figure which shows the flowchart of the process which changes the operating frequency of the decoding part which concerns on one Embodiment of this invention. It is a figure which shows an example of the initialization process according to the decoding interval of the frame which concerns on one Embodiment of this invention. It is a figure which shows the flowchart of the initialization process according to the decoding interval of the frame which concerns on one Embodiment of this invention. It is a block diagram which shows an example of a structure of the video part which concerns on one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Tuner part, 32 ... Demux, 41 ... Decoding part, 42 ... Video control part, 421 ... Timer, 422 ... Accumulated delay calculation part, 423 ... Accumulated delay initialization part, 424 ... Selection part, 43 ... Vertical synchronization Signal unit, 50... Clock supply unit

Claims (12)

Each time a new frame is decoded, a decoding delay that is the difference between the decoding processing time required to decode the new frame and the input interval of the predetermined interrupt signal is calculated, and the new frame and the new frame are calculated. For an accumulation range that includes a predetermined number of consecutive frames decoded before a new frame is decoded, add the decoding delay of the new frame and the decoding delay of the predetermined number of consecutive frames to accumulate An accumulated delay calculation unit for obtaining a delay;
A control unit including: a selection unit that compares the accumulated delay with a predetermined accumulation threshold and selects a predetermined decoding processing condition according to the comparison result;
A video decoding device comprising: a decoding unit configured to decode video under the predetermined decoding processing condition. The control unit compares the decoding interval from the completion of decoding of the previous frame to the start of decoding of the next frame with a predetermined interval threshold, and when the decoding interval is greater than the interval threshold, The video decoding apparatus according to claim 1, further comprising: an accumulated delay initialization unit that initializes internal information relating to an arithmetic delay and causes the accumulated delay calculation unit to calculate an accumulated delay from the next frame. A clock supply unit that supplies a clock having a frequency according to a frequency instruction signal to the decoding unit;
The selection unit selects the frequency of a clock to be supplied to the decoding unit as the decoding processing condition, and supplies the frequency instruction signal to the clock supply unit so as to supply a clock according to the selected frequency. The video decoding device according to claim 2, which outputs the video decoding device. The selection unit outputs the frequency instruction signal to the clock supply unit so that a frequency of a clock supplied to the decoding unit increases when the accumulated delay is larger than the predetermined accumulation threshold. 4. The video decoding device according to 3. The selection unit outputs the frequency instruction signal to the clock supply unit so that a frequency of a clock supplied to the decoding unit decreases when the accumulated delay is smaller than the predetermined accumulation threshold. 4. The video decoding device according to 3. The selection unit includes:
When the accumulated delay is smaller than a first accumulated threshold, the frequency instruction signal is output to the clock supply unit so that the frequency of the clock supplied to the decoding unit is decreased.
When the accumulated delay is greater than or equal to the first accumulated threshold and less than or equal to the second accumulated threshold, the frequency indicating signal is set so that the frequency of the clock supplied to the decoding unit is maintained. Output to the clock supply unit,
The frequency instruction signal is output to the clock supply unit so that the frequency of the clock supplied to the decoding unit increases when the accumulated delay is larger than the second accumulation threshold. Video decoding device. The selection unit selects decoding of a frame that does not refer to information of another frame when being encoded as the decoding processing condition when the accumulated delay is greater than the predetermined accumulation threshold. The video decoding device according to 1. 3. The video decoding device according to claim 2, wherein when the power saving mode is set, the selection unit selects to decode a frame that does not refer to information of another frame when being encoded, as the decoding processing condition. . When the vertical synchronization signal is generated or the vertical synchronization signal is input, the predetermined interrupt signal to be input to the control unit is generated, and the vertical synchronization signal is generated or input to the control unit by the predetermined interrupt signal Has a vertical sync signal section to notify
The video decoding device according to claim 2, wherein the control unit includes a timer that measures the decoding processing time, an input interval of the predetermined interrupt signal, and the decoding interval. A video decoding method in a video decoding device including a decoding unit for decoding video,
Each time a new frame is decoded, calculating a decoding delay that is a difference between a decoding processing time required to decode the new frame and an input interval of a predetermined interrupt signal;
For the accumulation range including the new frame and a predetermined number of consecutive frames decoded before the new frame is decoded, the decoding delay of the new frame and the decoding of the predetermined number of consecutive frames Adding a delay to obtain an accumulated delay;
Comparing the accumulated delay with a predetermined accumulated threshold and selecting a predetermined decoding processing condition according to the comparison result;
A video decoding method comprising: the decoding unit performing a decoding process under the predetermined decoding process condition. A video decoding program for causing a computer to execute a video decoding process,
Each time a new frame is decoded, calculating a decoding delay that is a difference between a decoding processing time required to decode the new frame and an input interval of a predetermined interrupt signal;
For the accumulation range including the new frame and a predetermined number of consecutive frames decoded before the new frame is decoded, the decoding delay of the new frame and the decoding of the predetermined number of consecutive frames Adding a delay to obtain an accumulated delay;
Comparing the accumulated delay with a predetermined accumulated threshold and selecting a predetermined decoding processing condition according to the comparison result;
A video decoding program that causes a computer to execute a decoding process under the predetermined decoding process condition. A receiver for receiving a broadcast signal including an input stream;
A separation unit for separating the encoded video from the input stream;
A control unit for selecting predetermined decoding processing conditions;
A decoding unit for decoding video under the predetermined decoding processing conditions,
The control unit is
Each time a new frame is decoded, a decoding delay that is the difference between the decoding processing time required to decode the new frame and the input interval of the predetermined interrupt signal is calculated, and the new frame and the new frame are calculated. For an accumulation range that includes a predetermined number of consecutive frames decoded before a new frame is decoded, add the decoding delay of the new frame and the decoding delay of the predetermined number of consecutive frames to accumulate An accumulated delay calculation unit for obtaining a delay;
A broadcast signal receiving apparatus comprising: a selection unit that compares the accumulated delay with a predetermined accumulated threshold value and selects the predetermined decoding processing condition according to the comparison result.

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