JP2009016991A - Decoding processing apparatus, decoding processing method, and digital broadcast receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly output images when a stand-by state changes to an operating state. <P>SOLUTION: A main CPU 11 in a digital broadcast receiver is provided with an initialization execution part 111 for executing initialization processing of an IC card when a main power supply is turned on. A sub-CPU 21 is provided with an initialization decision part 213 for deciding whether the initialization processing has been completed by the initialization execution part 111 or not, a state setting part 214 for setting either one of the operating state and the stand-by state which is a power saving state on the basis of operation input received through a remote controller 4, and a completion state holding part 215 for holding the completion state of the initialization processing of the IC card 3 when the initialization decision part 213 decides the completion of the initialization processing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In recent years, with the spread of digital broadcasting, two-way communication between broadcasting stations and viewers has become possible, and pay broadcasting that charges for each program has become possible. In a broadcasting system that performs pay broadcasting, a mechanism that enables viewing of a program only for a viewer who is permitted to identify and view the viewer is required. For example, when receiving BS digital broadcasting, an IC card called a B-CAS (BS Conditional Access System) card is required for each receiving device, and the encrypted (= scrambled) broadcast signal is decrypted. In order to achieve (= descramble), a B-CAS card that contracts with the broadcasting station (= program provider) side and stores information for decoding is indispensable.

Various apparatuses, methods, and the like have been proposed for broadcast systems that perform pay broadcasting. For example, when an IC card having a B-CAS card function and an S-CAS card function is inserted therein and a digital broadcast is received, the B-CAS card function inside the conditional access broadcast IC card is received as a server type broadcast. A receiving apparatus that receives viewer authentication using an S-CAS card function inside a conditional access broadcast IC card and decodes a content signal is disclosed (see Patent Document 1).
Japanese Patent Laid-Open No. 2007-13685

  However, in a conventional digital broadcast receiving apparatus such as the above-described receiving apparatus, the state changes from a standby state (= power saving state) to a power ON state (= receivable state: hereinafter referred to as “operating state”) via a remote controller or the like. In this case, it is necessary to perform initialization processing of an IC card (here, a PC (Personal Computer) card on which a CPU (Central Processing Unit) is mounted) for setting a communication speed, etc. Since it takes time until the descrambling process can be performed, it takes time until the video is output, and the convenience may not be sufficient.

  The present invention has been made in view of the above-described problems, and is a decoding processing device, a decoding processing method, and a digital broadcast receiving device that can output video at an early stage when a transition from a standby state to an operation state occurs. The purpose is to provide.

  In order to achieve the above object, a decryption processing apparatus according to claim 1 accepts encrypted AV (Audio / Visual) information, and accepts the accepted AV information as a detachable PC card. A decryption processing device for decrypting and outputting via the initialization execution means for executing the initialization processing of the PC card when the main power is turned on; and the initialization processing by the initialization execution means Initialization determination means for determining whether or not it is completed, and an operation input from the outside is received, and the apparatus is in a state capable of decoding and outputting AV information based on the received operation input. A state setting means for setting to one of a certain operating state and a standby state which is a power saving state in which AV information cannot be decoded and output; A completion state holding unit that holds the state where the initialization process of the PC card is completed when the initialization determination unit determines that the initialization process has been completed. It is characterized by that.

  The decryption processing device according to claim 2 is the decryption processing device according to claim 1, further comprising supply means for supplying power and a clock signal for controlling communication to the PC card. When the completion state holding means is set to the standby state by the state setting means and the initialization determination means determines that the initialization process is completed, the supply means It is characterized in that the supply of power and a clock signal to the PC card is continued.

  The decryption processing device according to claim 3 is the decryption processing device according to claim 2, wherein the decryption processing device is set to an operating state by the state setting unit, and the initialization process is completed by the initialization determination unit. When it is determined that the PC card has not been performed, the initialization execution unit is provided with an initialization instruction unit that causes the PC card initialization process to be executed.

  The decryption processing device according to claim 4 is the decryption processing device according to claim 3, further comprising attachment / detachment determination means for determining whether or not the PC card is attached, and the initialization instruction means. However, when it is determined by the attachment / detachment determination means that the PC card is inserted, the initialization execution means is caused to execute the initialization process of the PC card.

  The decoding processing device according to claim 5 is the decoding processing device according to claim 4, wherein the main CPU that controls the entire decoding processing device and the power control of the decoding processing device are performed. A sub CPU, and the sub CPU functions as at least the initialization determination unit, the state setting unit, the attachment / detachment determination unit, the completion state holding unit, and the initialization instruction unit.

  A decoding processing device according to a sixth aspect is the decoding processing device according to the fifth aspect, wherein the sub CPU further functions as the initialization execution means.

  The digital broadcast receiving apparatus according to claim 7 includes a receiving unit that receives the AV information via digital broadcasting, and the decoding processing apparatus according to any one of claims 1 to 6, AV information received by the receiving means and decrypted via the PC card is output to a monitor and a speaker.

  The decryption processing method according to claim 8 accepts encrypted AV (Audio / Visual) information, decrypts the accepted AV information via a detachable PC card, and outputs the decrypted AV information. In the decryption processing method, when the main power is turned on, an initialization execution step for executing the initialization processing of the PC card, and whether or not the initialization processing is completed in the initialization execution step. An initialization determination step for determining, an operation state from which an external operation input is received, and the apparatus is capable of decoding and outputting AV information based on the received operation input; and AV A state setting step for setting one of a standby state, which is a power saving state in which information cannot be decoded and output, and a standby state in the state setting step. And when the initialization determination step determines that the initialization process has been completed, a completion state holding step of holding a state where the initialization process of the PC card has been completed is executed. It is characterized by that.

  According to the decryption processing device of claim 1, when the main power is turned on, the initialization process of the PC card is executed, and it is determined whether or not the initialization process is completed. An operation input is accepted, and on the basis of the accepted operation input, the apparatus is in an operating state where AV information can be decoded and output, and AV information cannot be decoded and output. One of the standby states, which is a possible power saving state, is set. When the standby state is set and it is determined that the initialization process has been completed, the state where the initialization process of the PC card has been completed is maintained, so that the standby state is shifted to the operating state. In addition, video can be output early.

  In other words, when it is determined that the initialization process has been completed when the standby state is set and the PC card initialization process is completed, the transition from the standby state to the operating state is maintained. In addition, since it is not necessary to perform initialization processing of the PC card, video can be output at an early stage.

  According to the decoding processing device according to claim 2, when the standby processing is set and it is determined that the initialization processing is completed, the clock for controlling the power and communication to the PC card Since the signal supply is continued, the PC card can hold the state where the initialization process is completed.

  That is, when the standby state is set and it is determined that the initialization process is completed, the supply of the clock signal for controlling the power and communication to the PC card is continued. Even if it is set, the PC card can continue to operate, so that the PC card can hold the state where the initialization process is completed.

  According to the decryption processing device of the third aspect, when the standby state is set to the operation state and it is determined that the initialization process is not completed, the PC card initialization process is executed. Therefore, the initialization process can be executed at an appropriate timing.

  According to the decryption processing device of the fourth aspect, when it is determined that the PC card is inserted, the initialization process of the PC card is executed. Therefore, the initialization process can be executed at an appropriate timing. it can.

  According to the decoding processing device according to claim 5, the decoding processing device includes a main CPU that controls the entire decoding processing device and a sub CPU that performs power control of the decoding processing device, and the sub CPU includes at least An initialization determination means for determining whether or not the initialization process has been completed, accepting an operation input from the outside, and decoding and outputting the AV information based on the received operation input. It is determined whether or not a PC card is attached, state setting means for setting one of an operating state that is a possible state and a standby state that is a power saving state in which AV information cannot be decoded and output. Attaching / detaching determining means, completion status holding means for holding a state where the initialization process of the PC card is completed, and initialization instruction means for causing the initialization execution means to execute the initialization process of the PC card To function in, there is no need to supply power to the main CPU in the standby state, it is possible to realize power saving.

  That is, since all the processes necessary for holding the PC card initialization process in the sub CPU can be executed, the main CPU is in order to hold the PC card initialization process completed. Therefore, it is not necessary to supply the power, so that power saving can be realized.

  According to the decryption processing device of the sixth aspect, since the sub CPU further functions as initialization execution means for executing the initialization processing of the PC card, the transition from the standby state to the operation state (or the main state) Since the load on the main CPU at the time of power-on can be reduced, video can be output earlier.

  That is, at the time of transition from the standby state to the operating state (or when the main power is turned on), the sub CPU initializes the PC card before the process for enabling communication between the main CPU and the sub CPU is completed. Therefore, it is possible to output the video at an earlier stage.

  According to the digital broadcast receiving device according to claim 7, since the decoding processing device according to any one of claims 1 to 6 is provided, AV information received via digital broadcast is transmitted via a PC card. In a digital broadcast receiving apparatus that outputs a composite and output to a monitor and a speaker, an image can be output at an early stage when the standby state is shifted to the operating state.

  According to the decryption processing method of claim 8, when the main power is turned on, the initialization process of the PC card is executed, and it is determined whether or not the initialization process is completed. An operation input is accepted, and on the basis of the accepted operation input, the apparatus is in an operating state where AV information can be decoded and output, and AV information cannot be decoded and output. One of the standby states, which is a possible power saving state, is set. When the standby state is set and it is determined that the initialization process has been completed, the state where the initialization process of the PC card has been completed is maintained, so that the standby state is shifted to the operating state. In addition, video can be output early.

  In other words, when it is determined that the initialization process has been completed when the standby state is set and the PC card initialization process is completed, the transition from the standby state to the operating state is maintained. In addition, since it is not necessary to perform initialization processing of the PC card, video can be output at an early stage.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of a digital broadcast receiver according to the present invention. A digital broadcast receiver 100 (corresponding to a decoding processing device or a digital broadcast reception device) is configured so that an IC card 3 is detachable, and is connected to a remote controller (= remote controller: hereinafter referred to as “remote controller”) 4 via infrared communication. Are communicably connected, and are communicably connected to the output device 5.

  The digital broadcast receiver 100 receives an operation input from the user via the remote controller 4, receives an encrypted (= scrambled) television broadcast based on the received operation input, and receives the received program The information is decrypted via the IC card 3 (= descrambled), and video and audio are output to the output device 5.

  The IC card 3 (corresponding to a PC card) is a so-called PC card on which a CPU (Central Processing Unit) 31 is mounted, and is a key for decrypting program information received by the digital broadcast receiver 100 ( Key) information and the like are communicated with the digital broadcast receiver 100 (descrambler 154 described later).

  Further, the IC card 3 is configured to be detachable from the digital broadcast receiver 100, and operates by being supplied with a clock signal for controlling power and communication from the digital broadcast receiver 100 (power control unit 26 described later). is there.

  The remote controller 4 (corresponding to a part of the state setting means) receives an operation input from the user, generates an infrared signal corresponding to the received operation input, and outputs it to the digital broadcast receiver 100. It is.

  The output device 5 includes a display 51 and a speaker 52, and outputs audio information and video information input from the digital broadcast receiver 100. A display 51 (corresponding to a monitor) includes an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), and the like, and displays video information input from the digital broadcast receiver 100 so as to be visible from the outside. The speaker 52 outputs audio information input from the digital broadcast receiver 100.

  The digital broadcast receiver 100 includes a main block 1 and a sub block 2, and the main block 1 and the sub block 2 are configured to be supplied with power independently. Specifically, power is supplied to the main block 1 and the sub-block 2 in the operating state by the power supply control unit 26 described later, but power supply to the main block 1 is cut off in the standby state. Is. The main block 1 includes a main CPU 11, a RAM 12, a ROM 13, a communication unit 14, and a receiving unit 15.

  The main CPU 11 controls the operation of the entire digital broadcast receiver 100 and is configured to be able to communicate with the sub CPU 21 arranged in the sub block 2 via the communication unit 14. A RAM (Random Access Memory) 12 stores information such as audio information and video information in a readable and writable manner. A ROM (Read Only Memory) 13 stores a control program for operating the main CPU 11 and the like.

  The communication unit 14 performs communication with the communication unit 24 disposed in the sub-block 2. The receiving unit 15 (corresponding to receiving means) receives and demodulates a television broadcast, and includes an antenna unit 151, a tuner unit 152, a demodulating unit 153, a descrambler 154, a demultiplexer 155, and A decoder 156 is provided.

  The antenna unit 151 receives a television broadcast wave. The tuner unit 152 selects a channel broadcast set via the remote controller 4 from the television broadcast wave received by the antenna unit 151. The demodulator 153 demodulates the output information from the tuner unit 152. The descrambler 154 performs a decoding process (= descrambling process) on the information demodulated by the demodulator 153 via the IC card 3. The demultiplexer 155 outputs the output information decoded by the descrambler 154 separately for each type. The decoder 156 decodes the video information output from the demultiplexer 155 into video information before compression, and outputs the video information to the output device 5.

  The sub block 2 includes a sub CPU 21, a RAM 22, a ROM 23, a communication unit 24, a remote control receiving unit 25, and a power supply control unit 26. The sub CPU 21 performs power supply control, control of initialization processing of the IC card 3, and the like, and is configured to be able to communicate with the main CPU 11 disposed in the main block 1 via the communication unit 24. ing. The RAM 22 stores various information in a readable and writable manner. The ROM 23 stores a control program for operating the sub CPU 21 and the like.

  The communication unit 24 performs communication with the communication unit 14 disposed in the main block 1. The remote control receiving unit 25 receives an operation signal from the remote control 4 via infrared communication, and outputs information corresponding to the received operation signal to the sub CPU 21 (or the main CPU 11). A power supply control unit 26 (corresponding to a supply unit) controls power and communication with respect to the main block 1 and the IC card 3 in accordance with an instruction from the sub CPU 21 (attachment / detachment determination unit 211 and state setting unit 214 described later). A clock signal is supplied.

  Next, an operation when the digital broadcast receiver 100 receives a broadcast will be described. First, the transmitted digital broadcast wave is received by the antenna unit 151. When a channel selection operation is accepted via the remote controller 4, the tuner 152 switches the transponder (Transponder) received. The received digital broadcast wave is demodulated by the demodulator 153 and decoded by the descrambler 154. The demultiplexer 155 separates and outputs the output information for each type, the decoder 156 decodes the output information before compression, and the video and audio are output to the output device 5 (the display 51 and the speaker 52). .

  FIG. 2 is a block diagram showing an example of a functional configuration of a main part (corresponding to a decoding processing device) in the digital broadcast receiver 100 according to the present invention. The main CPU 11 of the digital broadcast receiver 100 functionally includes an initialization execution unit 111 and a decoding processing unit 112, and the sub CPU 21 functionally includes an attachment / detachment determination unit 211, an initialization instruction unit 212, and an initial stage. A determination determination unit 213, a state setting unit 214, and a completion state holding unit 215.

  Here, the main CPU 11 reads out and executes a control program stored in advance in the ROM 13 or the like shown in FIG. 1, thereby functioning as functional units such as an initialization execution unit 111 and a decoding processing unit 112, and a sub CPU 21. However, by reading and executing a control program stored in advance in the ROM 23 or the like shown in FIG. 1, the attachment / detachment determination unit 211, the initialization instruction unit 212, the initialization determination unit 213, the state setting unit 214, and the completion state holding unit 215 It functions as a functional part.

  Among various data stored in the RAM 12, ROM 13, RAM 22, ROM 23, etc. shown in FIG. 1, data that can be stored in a removable recording medium includes, for example, a hard disk drive, an optical disk drive, a flexible disk drive, a silicon disk drive, The recording medium may be readable by a driver such as a cassette medium reader. In this case, the recording medium is, for example, a hard disk, an optical disk, a flexible disk, a CD (Compact Disk), a DVD (Digital Versatile Disk), a semiconductor memory, or the like.

  The initialization execution unit 111 (corresponding to the initialization execution unit) establishes communication with the sub CPU 21 when power reception is started, and when the main power is turned on, and an initialization instruction unit When an instruction to execute the initialization process is received from 212, the initialization process of the IC card 3 is executed. In addition, when the initialization process is completed, the initialization execution unit 111 transmits information to that effect to the sub CPU 21.

  Note that “when the instruction to execute the initialization process is received from the initialization instruction unit 212” specifically means that “the state setting unit 214 sets the standby state to the operating state and the initialization is performed. This is “when the determination unit 213 determines that the initialization process of the IC card 3 has not been completed” or “when the attachment / detachment determination unit 211 determines that the IC card 3 is mounted”.

Here, the initialization process of the IC card 3 will be described. The initialization process includes the following five steps.
(1) Transmission of reset signal to IC card 3 (2) Reception of ATR (Answer To Reset) signal from IC card 3 (3) Setting of communication speed with IC card 3 based on ATR signal (4) IFSD (Information Field Size for Interface Device: Receivable Information Field Length) Change Process (5) Send / Receive Initial Setting Condition Command to / from IC Card 3

  The decryption processing unit 112 causes the descrambler 154 to execute decryption processing via the IC card 3 for which initialization processing has been completed.

  The attachment / detachment determination unit 211 (corresponding to attachment / detachment determination means) determines whether or not the IC card 3 is attached to the digital broadcast receiver 100. Further, when it is determined that the IC card 3 is not attached to the digital broadcast receiver 100, the attachment / detachment determination unit 211 transmits information to that effect to the main CPU 11.

  The initialization instruction unit 212 (corresponding to the initialization instruction unit) is set from the standby state to the operating state by the state setting unit 214, and the initialization process of the IC card 3 is not completed by the initialization determination unit 213. When it is determined that, the initialization execution unit 111 executes the initialization process of the IC card 3. Further, the initialization instruction unit 212 causes the initialization execution unit 111 to execute the initialization process of the IC card 3 when the attachment determination unit 211 determines that the IC card 3 is mounted.

  Further, the initialization instruction unit 212 establishes communication with the main CPU 11 when the state setting unit 214 sets the standby state to the operating state or when the main power is turned on.

  The initialization determination unit 213 (corresponding to the initialization determination unit) determines whether or not the initialization processing unit 111 has completed the initialization process. Here, the initialization determination unit 213 sets an initialization completion flag (= set to “1”) when the initialization process is completed by the initialization execution unit 111, and the initialization process is completed. If not, the initialization completion flag is cleared or reset (= set to “0”). The initialization determination unit 213 clears the initialization completion flag when the attachment / detachment determination unit 211 determines that the IC card 3 is not attached. In addition, the initialization determination unit 213 transmits information on whether or not the initialization process has been completed to the main CPU 11 in a timely manner.

  The state setting unit 214 (corresponding to a part of the state setting means) receives an operation input from the user via the remote controller 4, and based on the received operation input, the digital broadcast receiver 100 decodes the AV information. It is set to one of an operating state in which it is possible to convert and output, and a standby state, which is a power saving state in which AV information cannot be decoded and output.

  Specifically, the state setting unit 214 sets the “operating state” (or when the main power is turned on) to the main block 1 and the IC card 3 with respect to the power control unit 26. When the clock signal for power and communication control is supplied and set to the “standby state”, the power control unit 26 supplies the clock signal for power and communication control to the main block 1. Is to stop.

  However, when setting to the “standby state”, the state setting unit 214 transmits information indicating the transition to the “standby state” to the main CPU 11, and the main CPU 11 shifts to the “standby state”. When the information indicating that the power supply to the main block 1 may be cut off is received, the power control unit 26 controls power and communication for the main block 1. The supply of the clock signal is stopped.

  The completion state holding unit 215 (corresponding to the completion state holding unit) is set to the standby state by the state setting unit 214 and when the initialization determination unit 213 determines that the initialization process has been completed. The state where the initialization process of the IC card 3 is completed is held. Specifically, the completion state holding unit 215 is set to a standby state by the state setting unit 214 and when the initialization determination unit 213 determines that the initialization process has been completed, the power supply control unit 26. On the other hand, the supply of power and clock signals to the IC card 3 is continued.

  FIG. 3 is a flowchart showing an example of an operation outline of the digital broadcast receiver 100 (mainly the main CPU 11 and the sub CPU 21). Note that the step numbers assigned to the processes of the main CPU 11 and the sub CPU 21 shown in FIG. 3 correspond to the step numbers assigned to the processes of the main CPU 11 and the sub CPU 21 shown in FIGS.

  First, when the main power is turned on, power supply from the sub CPU 21 to the main CPU 11 is started (S107, S139), and the main CPU starts receiving power (S201). Then, communication between the sub CPU 21 and the main CPU 11 is established (S109, S203). Then, the initialization completion state of the IC card 3 is transmitted from the sub CPU 21 to the main CPU 11 (S115, S143), and the initialization completion state is received by the main CPU 11 (S205).

  Next, power supply from the sub CPU 21 to the IC card 3 is started (S111), and power reception is started in the IC card 3 (S301). Next, the main CPU 11 determines whether or not the initialization of the IC card 3 is completed (S207). If the initialization is not completed, the initialization process of the IC card 3 is executed (S207). S209). When the initialization of the IC card 3 is completed, information indicating that the initialization is completed is transmitted from the main CPU 11 to the sub CPU 21 (S213). The sub CPU 21 receives this information, and the IC card 3 The initialization flag is set (S119). On the other hand, when the initialization of the IC card 3 is completed, the main CPU 11 executes a decoding process via the IC card 3 and outputs video and audio (S221).

  When the sub CPU 21 receives an instruction to shift to the standby state, information to that effect is transmitted to the main CPU 11 (S129), and the main CPU 11 receives the information to shift to the standby state. (S231). When the main CPU 11 completes the process of shifting to the standby state, information indicating that the transition to the standby state is permitted is transmitted to the sub CPU 21 (S235), and is received by the sub CPU 21 to start the transition to the standby state. (S133). Next, the power supply from the sub CPU 21 to the main CPU 11 is stopped (S135). When the sub CPU 21 receives an instruction to shift to the operating state (S137), the process returns to step S139.

  4 and 5 are flowcharts showing an example of the operation of the sub CPU 21. First, as shown in FIG. 4, the state setting unit 214 determines whether or not the main power is turned on (S101). If it is determined that the main power is not turned on (NO in S101), the process is set to a standby state. If it is determined that the main power supply is turned on (NO in S101), power supply to the sub-block 2 is started (S103). Then, the initialization determination unit 213 clears the initialization completion flag (S105). Next, supply of a clock signal for controlling power and communication to the main block 1 is started by the state setting unit 214 via the power control unit 26 (S107). Next, communication with the main CPU 11 is established by the initialization instruction unit 212 (S109).

  Then, the attachment / detachment determination unit 211 determines whether or not the IC card 3 is attached (S111). When it is determined that the IC card 3 is not attached (NO in S111), the process is in a standby state. When it is determined that the IC card 3 is mounted (YES in S111), the state setting unit 214 starts supplying a clock signal for controlling power and communication to the IC card 3 (S113). ). Then, the initialization determination unit 213 transmits information indicating that the initialization of the IC card 3 is not completed to the main CPU 11 (S115). Next, the initialization determination unit 213 determines whether information indicating that the initialization of the IC card 3 has been received is received from the main CPU 11 (S117).

  If it is determined that information indicating that the initialization of the IC card 3 has been completed has not been received (NO in S117), the process is set to a standby state. If it is determined that the information indicating that the initialization of the IC card 3 has been completed is received (YES in S117), the initialization determination unit 213 sets an initialization completion flag (S119).

  Then, as shown in FIG. 5, the attachment / detachment determination unit 211 determines whether or not the IC card 3 has been removed (S121). If it is determined that the IC card 3 has not been removed (NO in S121), the process proceeds to step S127. If it is determined that the IC card 3 has been removed (YES in S121), the initialization determination unit 213 clears the initialization completion flag (S123), and the attachment / detachment determination unit 211 mounts the IC card 3. Information indicating that the process has not been performed is transmitted to the main CPU 11 (S125), the process returns to step S111 shown in FIG. 4, and the processes after step S111 are repeatedly executed.

  In the case of NO in S121, the completion state holding unit 215 holds the state where the initialization process of the IC card 3 is completed (S127), and the state setting unit 214 sets the “operation state” to the “standby state”. It is determined whether or not it has been done (S129). If it is determined that the “standby state” is not set (NO in S129), the process proceeds to step S137. If it is determined that the “standby state” is set (YES in S129), the state setting unit 214 transmits information indicating that the state is to be shifted to the “standby state” to the main CPU 11 (S131). Then, it is determined whether or not information indicating that the power supply to the main block 1 may be shut off is received (S133).

  If information indicating that the power supply may be shut off has not been received (NO in S133), the process is set to a standby state. When information indicating that the power supply may be shut off is received (YES in S133), the state setting unit 214 controls power and communication for the main block 1 via the power control unit 26. The supply of the clock signal is stopped (S135), the process is returned to step S121, and the processes after step S121 are repeatedly executed.

  In the case of NO in step S129, the state setting unit 214 determines whether or not the “standby state” has been set to the “operation state” (S137). If it is determined that the “operating state” is not set (NO in S137), the process returns to step S121, and the processes after step S121 are repeatedly executed. If it is determined that the “operation state” is set (YES in S137), the state setting unit 214 causes the clock signal for controlling power and communication to the main block 1 via the power control unit 26. Supply is started (S139). Then, the communication with the main CPU 11 is established by the initialization instruction unit 212 (S141). Next, the initialization determination unit 213 transmits information indicating that the initialization of the IC card 3 is completed to the main CPU 11 (S143), the process returns to step S121, and the processes after step S121 are performed. It is executed repeatedly.

  6 and 7 are flowcharts showing an example of the operation of the main CPU 11. First, as illustrated in FIG. 6, the initialization execution unit 111 determines whether or not power reception is started (S201). If it is determined that power reception has not started (NO in S201), the process is set to a standby state. If it is determined that power reception has started (YES in S201), the initialization execution unit 111 establishes communication with the sub CPU 21 (S203). Then, the initialization execution unit 111 receives the initialization completion state of the IC card 3 from the sub CPU 21 (S205).

  Then, the initialization execution unit 111 determines whether or not the information indicating that the initialization of the IC card 3 is completed in step S205 (S207). If it is determined that information indicating that initialization has been completed is received (YES in S207), the process proceeds to step S215. When it is determined that the information indicating that the initialization is not completed is received (NO in S207), the initialization executing unit 111 executes the initialization process of the IC card 3 (S209). Then, the initialization execution unit 111 determines whether or not the initialization process has been completed (S211). If it is determined that the initialization process has not been completed (NO in S211), the process enters a standby state. If it is determined that the initialization process has been completed (YES in S211), the initialization execution unit 111 transmits information indicating that the initialization process has been completed to the sub CPU 21 (S213), and the initial channel selection is performed. (S215).

  Next, as shown in FIG. 7, control of the tuner unit 152 (= broadcast wave reception operation) is performed (S217), and PSI (Program Specific Information) is acquired by the decoding processing unit 112 (S219). . Then, decoding processing is executed by the decoding processing unit 112 (S221), and AV information is output to the output device 5 (S223).

  Then, it is determined whether an instruction to shift to the standby state has been received from the sub CPU 21 (S225). If it is determined that an instruction to shift to the standby state has been received (YES in S225), the process proceeds to step S231. If it is determined that the instruction to shift to the standby state has not been received (NO in S225), it is determined whether information indicating that the IC card 3 has been removed has been received (S227). If it is determined that information indicating that the IC card 3 has been removed has been received (YES in S227), the process proceeds to step S237. If it is determined that the information indicating that the IC card 3 has been removed has not been received (NO in S227), it is determined whether or not channel selection from the remote controller 4 has been accepted (S229).

  If it is determined that channel selection from the remote controller 4 has been accepted (YES in S229), the process returns to step S217, and the processes after step S217 are repeatedly executed. If it is determined that channel selection from the remote controller 4 has not been accepted (NO in S229), the process returns to step S221, and the processes after step S221 are repeatedly executed.

  In the case of NO in step S225, a process for shifting to the standby state is executed (S231), and it is determined whether or not the process for shifting to the standby state is completed (S233). If it is determined that the transition process to the standby state has not been completed (NO in S233), the process returns to step S231, and the transition process is continued. If it is determined that the transition process to the standby state has been completed (YES in S233), information indicating that the transition to the standby state may be performed is transmitted to the sub CPU 21 (S235), and the process is returned. The

  In the case of YES at step S227, the decoding processing unit 112 stops the decoding process (S237), and the output of AV information to the output device 5 is stopped (S239). Then, it is determined whether or not information indicating that the IC card 3 is attached is received from the sub CPU 21 (S241). If it is determined that the information indicating that the IC card 3 is attached has not been received (NO in S241), the process is set in a standby state. If it is determined that the information indicating that the IC card 3 has been installed has been received (YES in S241), the process returns to step S209 shown in FIG. 6, and the processes after step S209 are repeatedly executed.

  In this way, when the main power is turned on, the initialization process of the IC card 3 is executed, it is determined whether or not the initialization process is completed, and an operation input from the user via the remote controller 4 is received. Based on the received operation input, the digital broadcast receiver 100 is in an operating state in which AV information can be decoded and output, and AV information cannot be decoded and output. One of the standby states, which is a possible power saving state, is set. When the standby state is set and it is determined that the initialization process is completed, the state where the initialization process of the IC card 3 is completed is maintained, so the state has shifted from the standby state to the operating state. In some cases, video can be output early.

  That is, when the standby state is set and it is determined that the initialization process has been completed, the state where the initialization process of the IC card 3 has been completed is maintained, so that the standby state is shifted to the operating state. In this case, it is not necessary to perform the initialization process of the IC card 3, so that the video can be output at an early stage.

  In addition, when the standby state is set and it is determined that the initialization process is completed, the supply of the clock signal for controlling the power and communication to the IC card 3 is continued. 3, the state where the initialization process is completed can be held.

  That is, when the standby state is set and it is determined that the initialization process is completed, the supply of the clock signal for controlling the power and communication to the IC card 3 is continued. Even if it is set to, since the IC card 3 can continue to operate, the IC card 3 can hold the state where the initialization process has been completed.

  Furthermore, since the initialization process of the IC card 3 is executed when it is determined from the standby state to the operation state and the initialization process is not completed, the initialization process is executed at an appropriate timing. can do.

  In addition, when it is determined that the IC card 3 is attached, the initialization process of the IC card 3 is executed, so that the initialization process can be executed at an appropriate timing.

  The main CPU 11 that controls the entire digital broadcast receiver 100 and a sub CPU 21 that controls the power of the digital broadcast receiver 100 are provided, and the sub CPU 21 determines whether or not the initialization process has been completed. This is a state in which an operation input from the user is received via the initialization determination unit 213 and the remote controller 4 and the digital broadcast receiver 100 can decode and output the AV information based on the received operation input. Detachment determination for determining whether or not the state setting unit 214 and the IC card 3 are set to the operating state and the standby state, which is a power saving state in which AV information cannot be decoded and output. Unit 211, a completion state holding unit 215 that holds the completion state of the initialization process of the IC card 3, and an IC card for the initialization execution unit 111 To function as a third initialization instruction section 212 to execute the initialization process, it is not necessary to supply power to the main CPU11 in the standby state, it is possible to realize power saving.

  That is, since the sub CPU 21 can execute all the processes necessary for maintaining the state where the initialization process of the IC card 3 is completed, the main CPU is used to maintain the state where the initialization process of the IC card 3 is completed. Since it is not necessary to supply power to the CPU 11, power saving can be realized.

The present invention can also be applied to the following forms.
(A) In the present embodiment, the case where the decoding processing device is the digital broadcast receiver 100 that receives digital television broadcasts has been described. However, the decoding processing device may be operated in other methods (for example, the Internet). It is also possible to obtain encrypted AV information (via

  (B) In the present embodiment, the digital broadcast receiver 100 has been described as having two CPUs (the main CPU 11 and the sub CPU 21). However, the digital broadcast receiver 100 may have one CPU, and may include three or more CPUs. It may be provided.

  (C) In this embodiment, the case where the sub CPU 21 functionally includes the attachment / detachment determination unit 211, the initialization instruction unit 212, the initialization determination unit 213, the state setting unit 214, and the completion state holding unit 215 has been described. The sub CPU 21 may further include an initialization execution unit that is a functional unit that executes the initialization process of the IC card 3.

  In this case, since the sub CPU 11 further functions as an initialization execution unit that executes the initialization process of the IC card 3, the main CPU 11 is switched from the standby state to the operating state (or when the main power is turned on). Since the load can be reduced, the video can be output at an earlier stage.

  That is, at the time of transition from the standby state to the operating state (or when the main power is turned on), the sub CPU initializes the IC card 3 before the processing for enabling communication between the main CPU and the sub CPU is completed. Since the process can be executed, the video can be output at an earlier stage.

  (D) In this embodiment, the main CPU 11 functions as functional units such as the initialization execution unit 111 and the decryption processing unit 112, and the sub CPU 21 includes the attachment / detachment determination unit 211, the initialization instruction unit 212, and the initialization determination unit. 213, the state setting unit 214, the completion state holding unit 215, and the like have been described as functioning. However, the initialization execution unit 111, the decoding processing unit 112, the attachment / detachment determination unit 211, the initialization instruction unit 212, and the initialization Of the determination unit 213, the state setting unit 214, and the completion state holding unit 215, at least one functional unit may be configured by hardware such as a circuit.

These are block diagrams which show an example of a structure of the digital broadcast receiver which concerns on this invention. These are block diagrams which show an example of a function structure of the principal part (equivalent to a decoding processing apparatus) in the digital broadcast receiver which concerns on this invention. These are flowcharts which show an example of the operation | movement outline | summary of a digital broadcasting receiver (mainly main CPU, sub CPU). These are flowcharts (first half) which show an example of operation of a sub CPU. These are the flowcharts (latter half part) which show an example of operation | movement of a sub CPU. These are flowcharts (first half part) which show an example of operation | movement of main CPU. These are the flowcharts (second half part) which show an example of operation | movement of main CPU.

Explanation of symbols

100 Digital broadcast receiver (decoding processor, digital broadcast receiver)
1 Main block 15 Receiver (Receiving means)
151 Antenna Unit 152 Tuner Unit 153 Demodulator 154 Descrambler 155 Demultiplexer 156 Decoder 11 Main CPU
111 Initialization execution unit (initialization execution means)
112 Decoding processor 2 Sub-block 21 Sub-CPU
211 Detachment determination unit (detachment determination means)
212 Initialization instruction unit (initialization instruction means)
213 Initialization determination unit (initialization determination means)
214 State setting unit (part of state setting means)
215 Completion state holding unit 25 Remote control receiving unit 26 Power supply control unit 3 IC card (PC card)
31 CPU
4 Remote control (part of status setting means)
5 Output device 51 Display (monitor)
52 Speaker

Claims (8)

A decryption processing device that receives encrypted AV (Audio / Visual) information, decrypts the received AV information via a detachable PC card, and outputs the decrypted AV information.
An initialization execution means for performing initialization processing of the PC card when the main power is turned on;
Initialization determination means for determining whether or not initialization processing is completed by the initialization execution means;
An operation input from outside is received, and based on the received operation input, the apparatus is in a state where it can decode and output AV information, and AV information is decoded and output. State setting means for setting one of the standby states, which is a power saving state in which
A completion state that holds the state where the initialization process of the PC card is completed when the state setting unit sets the standby state and the initialization determination unit determines that the initialization process is completed Holding means;
A decryption processing apparatus comprising: Supply means for supplying power and a clock signal for controlling communication to the PC card,
The completion state holding unit sets the PC to the supply unit when the state setting unit sets the standby state and the initialization determination unit determines that the initialization process is completed. 2. The decoding processing apparatus according to claim 1, wherein the supply of power and a clock signal to the card is continued.   When the state setting unit sets the operating state and the initialization determination unit determines that the initialization process is not completed, the initialization execution unit performs initialization processing of the PC card. The decryption processing apparatus according to claim 2, further comprising an initialization instruction unit to be executed. An attachment / detachment determining means for determining whether or not the PC card is mounted;
The initialization instruction means causes the initialization execution means to execute an initialization process of the PC card when the attachment determination means determines that the PC card is inserted. 4. The decryption processing device according to 3. A main CPU for controlling the entire decoding processing apparatus;
A sub CPU that performs power control of the decoding processing device;
With
5. The decoding processing apparatus according to claim 4, wherein the sub CPU functions as at least the initialization determination unit, the state setting unit, the attachment / detachment determination unit, the completion state holding unit, and the initialization instruction unit. .   The decoding processing apparatus according to claim 5, wherein the sub CPU further functions as the initialization execution unit. Receiving means for receiving the AV information via digital broadcasting;
The decoding processing device according to any one of claims 1 to 6,
With
A digital broadcast receiving apparatus, wherein a digital broadcast is received by the receiving means, and AV information decoded via the PC card is output to a monitor and a speaker. A decryption processing method for receiving encrypted AV (Audio / Visual) information, decrypting the received AV information via a detachable PC card, and outputting the decrypted AV information,
An initialization execution step of executing initialization processing of the PC card when the main power is turned on;
An initialization determination step of determining whether or not an initialization process is completed in the initialization execution step;
An operation input from outside is received, and based on the received operation input, the apparatus is in a state where it can decode and output AV information, and AV information is decoded and output. A state setting step for setting one of the standby states, which is a power saving state in which
A completion state in which the PC card initialization process is held when the standby state is set in the state setting step and the initialization process is determined to be completed in the initialization determination step. Holding step;
The decoding processing method characterized by performing these.

Images