JP2009010283A - Field-effect transistor, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor where yield is high and high drain current is possible, and to provide a method for manufacturing the same. <P>SOLUTION: The field-effect transistor having a substrate 1, a first electrode 2 provided on the substrate 1, a first insulating layer 3 provided on a surface of the electrode 2, a second insulating layer 4 provided on a surface of the layer 3, a second electrode 5 that is positioned above the electrode 2 and provided on the layer 4, a third electrode 6 that is isolated from the electrode 5 and is provided on the substrate 1 through the layer 3 or the layer 4 or directly, and an organic semiconductor layer 8 that is provided so as to contact the electrode 5 and the electrode 6 and is insulated from the electrode 2 through the layer 3 and the layer 4, wherein an upper surface of the electrode 6 is positioned lower than that of the electrode 2 and the layer 4 is thinner than the layer 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor having a high yield and a high drain current and a method for manufacturing the same.

  In recent years, attention has been focused on organic thin film elements using organic semiconductor materials as active materials instead of conventional inorganic materials. Typical examples of the organic thin film element include an organic thin film transistor and an organic EL element. Organic thin film elements can be formed at low temperatures compared to inorganic semiconductor elements such as silicon, and can also be formed on ultra-lightweight, thin and flexible plastic substrates. It is expected in terms of cost reduction.

  One of the most promising applications of organic thin film transistors is an application to a drive circuit board of an active matrix flat panel display. Specifically, an organic thin film transistor may be used as a pixel transistor for driving a display element such as a liquid crystal, an organic EL element, or an electrochromic element. However, organic semiconductor materials generally have low conductivity or carrier mobility, and have a higher resistance value than inorganic semiconductors. Therefore, the driving voltage tends to increase, and the current value between the source and drain of the thin film transistor decreases. It has been difficult to realize a display having a large pixel area.

  Examples of organic thin film transistors using organic semiconductor materials include field effect transistors using polythiophene, which is a polymer material, and field effect transistors using pentacene, which is a low molecular material. Since the MOS-FET (Metal Oxide Semiconductor Field Effect Transistor) structure in which the region is provided horizontally with respect to the substrate is used, the operating voltage is as high as about 20 to 30 V, and sufficient drain current is not obtained. It was.

The drain current I _d of the organic thin film transistor is expressed by the following equation in the saturation region.

（但し、Ｉ_ｄ：ドレイン電流、Ｗ：チャネル幅、ε_０：真空の誘電率、ε_ｒ：比誘電率、μ：電界効果移動度、Ｖ_ｇ：ゲート電圧、Ｖ_ｔｈ：しきい値電圧、ｄ：ゲート絶縁層膜厚、Ｌ：チャネル長）
有機薄膜トランジスタを有機ＥＬパネルの画素駆動用トランジスタとして用いる場合、ドレイン電流と画素面積の不足が問題となってくる。有機ＥＬ素子は電流量に応じた輝度を示すため、画素駆動用のトランジスタにおいては、一定以上のドレイン電流を必要とする。ドレイン電流を増加させるためには、チャネル幅Ｗを増加させることが有効であるが、チャネル幅を増やせば、その分有機薄膜トランジスタの占有面積が増大し、有機ＥＬ素子に割く面積が減少して、画素面積の減少を招く。また、小さい画素面積のままパネル輝度を上げようとすれば、個々の有機ＥＬ素子の負荷が増え、有機ＥＬ素子の発光不良を招いて、パネルの短寿命化をもたらす。

(Where, I _d : drain current, W: channel width, ε ₀ : vacuum dielectric constant, ε _r : relative dielectric constant, μ: field effect mobility, V _g : gate voltage, V _th : threshold voltage, d: thickness of gate insulating layer, L: channel length)
When an organic thin film transistor is used as a pixel driving transistor of an organic EL panel, there is a problem of insufficient drain current and pixel area. Since the organic EL element exhibits luminance in accordance with the amount of current, the pixel driving transistor requires a drain current of a certain level or more. In order to increase the drain current, it is effective to increase the channel width W. However, if the channel width is increased, the occupied area of the organic thin film transistor increases correspondingly, and the area divided by the organic EL element decreases, The pixel area is reduced. Further, if the panel luminance is increased with a small pixel area, the load on each organic EL element increases, leading to a light emission failure of the organic EL element, resulting in a short panel life.

  According to equation (1), in order to increase the drain current, a method of reducing the channel length L or reducing the thickness d of the gate insulating layer can be considered.

  In conventional MOS-FETs in which the channel region is provided horizontally, there is a limit to shortening the channel due to difficulty in processing, but the channel is provided in the vertical direction and the channel length is controlled by the film thickness of the gate electrode and the like As a result, a shorter channel can be formed with good reproducibility. For example, a method has been reported in which a thin film of about 200 nm of copper phthalocyanine is used as an organic semiconductor, source / drain electrodes are provided above and below the thin film, and a semitransparent or comb-shaped Al gate electrode is provided in the middle of the thin film. Patent Document 1).

  In addition, a so-called vertical field effect transistor is disclosed in which a rectangular or triangular gate electrode is used and a channel region is provided in a vertical direction (Patent Document 1). According to this method, it is described that a short channel length can be easily obtained with high accuracy, and that the source / drain electrode and the gate electrode can be formed in a self-aligned manner. Thus, although the drain current increases due to the shortening of the channel, it is not sufficient for causing the organic EL element to emit light with high luminance, and it is necessary to increase the channel width in order to obtain high luminance light emission. As a result, the area occupied by the pixel increases and the pixel area cannot be improved.

On the other hand, although the gate capacitance is increased by the method of reducing the thickness of the gate insulating layer, the gate insulating layer is deteriorated in insulation property, so that the leakage current increases or the breakdown occurs and the transistor collapses. Inconveniences such as a significant decrease in yield occurred. As a method for solving this problem, a field effect transistor (Patent Document 2) in which the gate insulating layer is composed of an anodized film of a metal material constituting the gate electrode and an organic polymer film or the like, or a gate dielectric layer having a high dielectric constant is used. A field effect transistor (Patent Document 3) having a two-layer structure of a material and an insulating organic polymer is disclosed.
However, each of the field effect transistors disclosed in these documents has a MOS-FET structure in which a channel region is provided horizontally. In a vertical transistor, when forming a source / drain electrode, a gate electrode In order to make use of the shape of the transistor, it is difficult to form an insulating layer that is thin enough to conform to the shape of the gate electrode, reducing defects, and forming an insulating layer. It wasn't.
JP 2004-349292 A JP 2004-128124 A Japanese Laid-Open Patent Publication No. 2005-26698 K. Kudo, M.M. Iizuka, S .; Kuniyoshi, and K.K. Tanaka, Thin Solid Films, Vol. 393, p. 362, 2001.

  An object of the present invention is to provide a field effect transistor having a vertical field effect transistor structure that can achieve a high drain current and a high yield, and a method for manufacturing the same.

  In order to solve the conventional problems, a field effect transistor of the present invention includes a substrate, a first electrode provided on the substrate, a first insulating layer provided on the surface of the first electrode, A second insulating layer made of an organic material provided on the surface of the first insulating layer; a second electrode located above the first electrode and provided on the second insulating layer; A third electrode provided on the substrate via the first insulating layer or the second insulating layer or directly, and in contact with the second electrode and the third electrode. And an organic semiconductor layer provided so as to be insulated from the first electrode via the first insulating layer and the second insulating layer, and the upper surface of the third electrode is the upper surface of the first electrode And the thickness of the second insulating layer is smaller than the thickness of the first insulating layer. A.

  Thus, since the upper surface of the third electrode is provided at a position lower than the upper surface of the first electrode, a vertical organic field effect transistor having a channel region on the side surface of the first electrode functioning as a gate electrode is provided. Since the second insulating layer is configured to be thinner than the first insulating layer, the gate insulating layer can be made thin while maintaining a sufficient insulating property. And the yield can be increased.

The second insulating layer is preferably formed by a wet method. Thereby, a defect or the like in the first insulating layer can be repaired. Here, the wet method is, for example, a method of forming a film by dissolving the material of the second insulating layer in a solvent or the like and applying it, and examples thereof include a spin coating method, a printing method, and a spray method. .
Furthermore, the sum of the thicknesses of the first insulating layer and the second insulating layer is preferably 30 nm or more and 200 nm or less. Thereby, a yield can be kept high.

  In addition, the field effect transistor manufacturing method of the present invention includes a step of forming a first electrode on a substrate, a step of forming a first insulating layer on the surface of the first electrode, and a surface of the first insulating layer. Forming a second insulating layer thereon, forming a second electrode on the second insulating layer located above the first electrode, and simultaneously separating the second electrode from the second electrode; The organic semiconductor layer so as to be in contact with the second electrode and the third electrode and to be insulated from the first electrode through the first insulating layer and the second insulating layer. And a forming step.

  Thus, a vertical organic field effect transistor having the side surface of the first electrode functioning as the gate electrode as a channel region can be easily manufactured. Furthermore, the step of forming the second insulating layer is preferably performed by a wet method. Thereby, a defect or the like in the first insulating layer can be repaired.

  In the field effect transistor of the present invention, the gate insulating layer can be made thin while maintaining sufficient insulation, so that a high drain current can be achieved and a yield can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by this embodiment.
(Embodiment)
1A and 1B are diagrams showing an example of a field effect transistor according to an embodiment of the present invention (FIG. 1A is a top view, and FIG. 1B is a cross-sectional view taken along the line AA). The field effect transistor includes a first electrode 2 that functions as a gate electrode on a substrate 1, and is formed on the upper surface and side surfaces of the first electrode 2 and on the surface of the substrate 1 on both sides of the first electrode 2. A first insulating layer 3 is formed across the gate. A second insulating layer 4 is formed on the first insulating layer 3 so as to cover the first insulating layer 3. A second electrode 5 that is formed on the second insulating layer 4 and functions as a source / drain electrode located above the first electrode 2, and the first insulating layer 3 on both sides of the first electrode 2. In addition, a third electrode 6 and a fourth electrode 7 which are located via the second insulating layer 4 and function as source / drain electrodes are provided.

  Here, the first insulating layer 3 or the second insulating layer 4 may be formed so as to cover only the upper surface and the side surface of the first electrode 2 and not the substrate 1. In this case, the third electrode 6 and the fourth electrode 7 are provided directly on the substrate 1 or on the first insulating layer 3.

  Note that only one of the third electrode 6 and the fourth electrode 7 may be used, and the second electrode 5 functions as a floating electrode, and the third electrode 6 and the fourth electrode function as source / drain electrodes. A structure may be used in which the electrode 7 is electrically mediated.

  Further, as shown in FIG. 2, the second electrode 5 and the third electrode 6 may be electrically connected. In this case, since the second electrode 5 and the third electrode 6 are short-circuited, the channel length between the third electrode 6 and the fourth electrode 7 is approximately halved, and a drain current can be increased. it can.

  An organic semiconductor layer 8 is formed on the surface of the second electrode 5, the third electrode 6, the fourth electrode 7, and the second insulating layer 4. The organic semiconductor layer 8 is in electrical contact with the second electrode 5 and the third electrode 6 and the fourth electrode 7, and the first electrode 2 is connected to the first insulating layer 3 and the second insulating layer 8. Electrically separated by layer 4.

  When a voltage is applied to the first electrode 2, the field effect transistor having such a configuration is separated from the first insulating layer 3 and the second insulating layer 4 and opposed to the first electrode 2. In this region (channel region), charge is induced. As a result, a current (according to the voltage applied to the first electrode 2 between the electrodes functioning as the source or drain electrode, for example, between the second electrode 5 and the third electrode 6 and the fourth electrode 7 ( As a drain current flows, the transistor operates as a field effect transistor.

  In addition, by using two insulating layers as described above, the generation of leakage current between the electrodes is suppressed, the yield is improved, and the total thickness of the first insulating layer and the second insulating layer is reduced. Thus, the current value between the source and the drain can be increased.

<Constituent Material of Field Effect Transistor in this Embodiment>
As the substrate 1, it is sufficient that at least the surface has an insulating property. Various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, a surface Examples thereof include a silicon substrate having an insulating layer formed thereon and a metal substrate having an insulating layer formed on the surface thereof. In addition, mention may be made of plastic films, plastic sheets and plastic substrates composed of polymer materials exemplified by polyethersulfone (PES), polyimide, polycarbonate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN). If the substrate 1 made of such a flexible polymer material is used, for example, a field effect transistor can be incorporated or integrated into a display device or electronic device having a curved shape. .

  As materials constituting the first electrode 2, the second electrode 5, the third electrode 6 and the fourth electrode 7, gold (Au), platinum (Pt), aluminum (Al), copper (Cu), From metals such as palladium (Pd), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), alloys containing these metal elements, from these metals Or conductive particles of an alloy containing these metals. Moreover, when forming in a transparent electrode, metal oxides, such as indium tin oxide (ITO), fluorine-doped tin oxide, zinc oxide, and tin oxide, are used, for example. Furthermore, the various conductive polymers mentioned above can also be mentioned. The electrode material is also selected depending on the electrical properties (such as ohmic property and Schottky property) with the organic semiconductor layer 8.

The first insulating layer 3 includes organic insulating materials such as parylene resin, polycarbonate resin, polyvinyl acetal resin, polyester resin, modified ether type polyester resin, polyarylate resin, phenoxy resin, polyvinyl chloride resin, polyvinyl acetate resin, Polyvinylidene chloride resin Polystyrene resin, acrylic resin, methacrylic resin, cellulose resin, urea resin, polyurethane resin, silicone resin, epoxy resin, polyamide resin, polyacrylamide resin, polyvinylphenol resin and polyvinyl alcohol resin, and these materials Copolymers and cross-linked products can be used.
As the first insulating layer 3, the above material may be used alone, but examples of the material include inorganic materials such as titanium oxide, zirconium oxide, and barium titanate, and organic metals such as tetrabutyl titanate and titanium ethoxide. High dielectric constant material fine particles of a compound may be added. Examples of the binder organic material or the high molecular organic compound as the main chain include polycarbonate resin, polyvinyl acetal resin, polyvinyl phenol resin, polyester resin, modified ether type polyester resin, polyarylate resin, phenoxy resin, polyvinyl chloride resin, and polyacetic acid. Vinyl resin, polyvinylidene chloride resin polystyrene resin, acrylic resin, methacrylic resin, cellulose resin, urea resin, polyurethane resin, silicone resin, epoxy resin, polyamide resin, polyacrylamide resin, polyvinyl alcohol resin, etc. A cross-linked product or a photoconductive polymer such as polyvinyl carbazole or polysilane is used. Further, it can be formed by oxidizing or nitriding the surface of the first electrode 2, and can also be obtained by forming an oxide film or a nitride film on the surface of the first electrode 2.

  Examples of the material of the second insulating layer 4 formed on the first insulating layer 3 include organic insulating materials such as polyvinyl alcohol (PVA), polyvinyl butyrate (PVB), polymethyl methacrylate (PMMA), and parylene. Resin, polycarbonate resin, polyvinyl acetal resin, polyester resin, modified ether type polyester resin, polyarylate resin, phenoxy resin, polyvinyl chloride resin, polyvinyl acetate resin, polyvinylidene chloride resin polystyrene resin, acrylic resin, methacrylic resin, cellulose resin Organic materials such as urea resin, polyurethane resin, silicon resin, epoxy resin, polyamide resin, polyacrylamide resin, polyvinylphenol resin and polyvinyl alcohol resin, and copolymers and cross-linked materials thereof can be used. As the second insulating layer 4, the above material may be used alone, but examples of the material include inorganic materials such as titanium oxide, zirconium oxide, and barium titanate, and organic metals such as tetrabutyl titanate and titanium ethoxide. High dielectric constant material fine particles of a compound may be added. Examples of the binder organic material or the high molecular organic compound as the main chain include polycarbonate resin, polyvinyl acetal resin, polyvinyl phenol resin, polyester resin, modified ether type polyester resin, polyarylate resin, phenoxy resin, polyvinyl chloride resin, and polyacetic acid. Vinyl resin, polyvinylidene chloride resin polystyrene resin, acrylic resin, methacrylic resin, cellulose resin, urea resin, polyurethane resin, silicone resin, epoxy resin, polyamide resin, polyacrylamide resin, polyvinyl alcohol resin, etc. A cross-linked product or a photoconductive polymer such as polyvinyl carbazole or polysilane is used.

  The thickness of the first insulating layer 3 is 10 to 300 nm, preferably 10 to 150 nm. When the thickness is less than 10 nm, the insulation cannot be maintained, and when the thickness is more than 300 nm, the source-drain current becomes too small. The thickness of the second insulating layer 4 formed on the first insulating layer 3 is 5 to 50 nm, preferably 5 to 10 nm. If the thickness is less than 5 nm, the insulation cannot be maintained, and if it is greater than 50 nm, the source-drain current becomes too small. In addition, the film thickness of the 2nd insulating layer 4 is 10 nm or less, and even if it forms into a film by a wet method, the shape of the 1st electrode 2 can be hold | maintained.

  Furthermore, the sum of the thicknesses of the first insulating layer 3 and the second insulating layer 4 is preferably 30 to 200 nm. If the thickness is less than 30 nm, the insulation cannot be maintained. If the thickness is more than 200 nm, the source-drain current becomes too small.

  As the organic semiconductor material constituting the organic semiconductor layer 8, both an organic material having semiconductor characteristics and having an electron accepting function and a material having an electron donating function can be used. The materials exemplified below can be used.

  Examples of the material having an electron-accepting function include oligomers and polymers having pyridine and derivatives thereof as skeletons, oligomers and polymers having quinoline and derivatives thereof as skeletons, ladder polymers based on benzophenanthrolines and derivatives thereof, cyano- Small molecules such as polymers such as polyphenylene vinylene, fluorinated metal-free phthalocyanines, fluorinated metal phthalocyanines and derivatives thereof, perylene and derivatives thereof (PTCDA, PTCDI, etc.), naphthalene derivatives (NTCDA, NTCDI, etc.), bathocuproin and derivatives thereof Organic compounds can be used.

  In addition, as materials having an electron donating function, oligomers and polymers having thiophene and its derivatives in the skeleton, oligomers and polymers having phenylene-vinylene and its derivatives in the skeleton, oligomers and polymers having fluorene and its derivatives in the skeleton, Oligomers and polymers having benzofuran and its derivatives in the backbone, oligomers and polymers having thienylene-vinylene and its derivatives in the backbone, aromatic tertiary amines such as triphenylamine and their derivatives, carbazole and polymers Oligomers and polymers having their derivatives in the backbone, oligomers and polymers having the backbone of vinylcarbazole and its derivatives, oligomers and polymers having the backbone of pyrrole and its derivatives, acetylene and derivatives thereof Oligomers and polymers having skeletons, oligomers and polymers having skeletons of isothiaphene and its derivatives, polymers such as oligomers and polymers having skeletons of heptadiene and its derivatives, metal-free phthalocyanines, metal phthalocyanines and their derivatives Diamines, phenyldiamines and derivatives thereof, acenes such as rubrene and pentacene and derivatives thereof, porphyrin, tetramethylporphyrin, tetraphenylporphyrin, tetrabenzporphyrin, monoazotetrabenzporphyrin, diazotetrabenzporphine, triazotetra Benzporphyrin, octaethylporphyrin, octaalkylthioporphyrazine, octaalkylaminoporphyrazine, hemiporphyrazine, chlorophyll Metal-free porphyrins, metal porphyrins and their derivatives, cyanine dyes, merocyanine dyes, squarylium dyes, quinacridone dyes, azo dyes, anthraquinone, benzoquinone, low molecular organic compounds such as quinone-based dyes naphthoquinone or the like can be used.

As the central metal of metal phthalocyanine and metal porphyrin, magnesium, zinc, copper, silver, aluminum, silicon, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, tin, platinum, lead and other metals, metal oxides, Metal halides can be used.
As the organic semiconductor layer 8, the above materials may be used alone, or a material obtained by dispersing and mixing the above materials in an appropriate binder material may be used. Moreover, you may use the material which incorporated the said low molecular weight organic compound in the principal chain or side chain of a suitable high molecular organic compound. Examples of the binder organic material or the high molecular organic compound as the main chain include polycarbonate resin, polyvinyl acetal resin, polyvinyl phenol resin, polyester resin, modified ether type polyester resin, polyarylate resin, phenoxy resin, polyvinyl chloride resin, and polyacetic acid. Vinyl resin, polyvinylidene chloride resin polystyrene resin, acrylic resin, methacrylic resin, cellulose resin, urea resin, polyurethane resin, silicone resin, epoxy resin, polyamide resin, polyacrylamide resin, polyvinyl alcohol resin, etc. A cross-linked product or a photoconductive polymer such as polyvinyl carbazole or polysilane is used.

<Method for Manufacturing Field Effect Transistor in the Present Embodiment>
FIG. 3 shows a method for manufacturing the field effect transistor according to this embodiment.

  A first electrode 2 functioning as a gate electrode is formed on the substrate 1 (see FIG. 3A). The formation method of the first electrode 2 depends on the constituent materials, but a combination of a physical vapor deposition method (PVD) method and an etching technique exemplified by a vacuum deposition method and a sputtering method, and various chemical gases. Combination of phase growth method (CVD method) and etching technology, combination of spin coating method and etching technology, screen printing method and ink jet printing method using conductive paste and various conductive polymer solutions mentioned above Examples thereof include a printing method, a lift-off method, a shadow mask method, a combination of the above-described various coating methods and an etching technique, and a combination of a spray method and an etching technique.

  Next, the first insulating layer 3 is formed on the first electrode 2 and the substrate 1 (see FIG. 3B). As a method for forming the first insulating layer 3, a PVD method exemplified by a vacuum deposition method and a sputtering method, various CVD methods, a spin coating method, a printing method such as a screen printing method and an inkjet printing method, and the various coating methods described above. Any of a dipping method, a casting method, and a spray method can be given.

Further, the first insulating layer 3 can be formed by oxidizing or nitriding the surface of the first electrode 2. Examples of the method for oxidizing the surface of the first electrode 2 include an oxidation method using an O ₂ plasma and an anodic oxidation method, although depending on the material constituting the first electrode 2. In addition, as a method of nitriding the surface of the first electrode 2, a nitriding method using N ₂ plasma can be exemplified although it depends on the material constituting the first electrode 2. The above method is effective when the substrate 1 is a material having heat resistance.

  Alternatively, for example, when an Au electrode is used as the first electrode 2, a chemical bond is formed with the first electrode 2 (Au electrode) like a linear hydrocarbon modified at one end with a mercapto group. An insulating layer can also be formed on the surface of the first electrode 2 by covering the surface of the first electrode 2 with an insulating molecule having a functional group that can be used by a method such as an immersion method.

  A second insulating layer 4 is formed on the first insulating layer 3 thus formed (see FIG. 3C). As a method for forming the second insulating layer 4, as in the first insulating layer 3, a PVD method exemplified by a vacuum deposition method and a sputtering method, various CVD methods, a spin coating method, a screen printing method, and an inkjet printing method. Any one of a printing method such as a printing method, the various coating methods described above, a dipping method, a casting method, and a spray method can be used.

  In addition, as a formation method of the 2nd insulating layer 4, wet methods, such as a spin coat method, a printing method, and a spray method, are preferable. As shown in FIG. 4, when the second insulating layer 4 is formed by applying a solution of an organic insulating material by a wet method, a pinhole or the like of the first insulating layer 3 that causes a leak or the like Since the solution penetrates into the defect or the like and can be repaired, the insulating property of the insulating layer can be improved. As a solvent for dissolving the organic insulating material, it is preferable to use a solvent having good wettability (small contact angle) with the first insulating layer 3.

Next, the second electrode 5, the third electrode 6, and the fourth electrode 7 are formed on the second insulating layer 4 (see FIG. 3D). The method for forming these electrodes is the same as the method for forming the first electrode 2. The second electrode 5, the third electrode 6, and the fourth electrode 7 are formed at the same time, but the second insulating layer 4 on the side surface of the first electrode 2 has an electrode depending on the shape of the first electrode 2. Is formed or only extremely thin, and then by performing light etching, the second electrode 5, the third electrode 6 and the fourth electrode 7 are separated from each other and insulated from each other. Become.
Here, when the second insulating layer 4 is formed by a wet method, a solution of the organic insulating material is accumulated in a portion of the side surface of the first electrode 2 that is in contact with the substrate 1, and the radius of curvature in the portion is large. Become. Thus, when the third electrode 6 and the fourth electrode 7 are formed by vapor deposition or the like, the third electrode 6 and the fourth electrode 7 are extended to a position where they are located on the side surface of the first electrode 2. The distance between the second electrode 5 and the third electrode 6 or the fourth electrode 7 is reduced and the current between the source and the drain can be increased. In addition, it is possible to reduce the occurrence of inconvenience such as a film breakage or a crack in the portion where the organic semiconductor layer 8 formed thereafter contacts the substrate 1 on the side surface of the first electrode 2.

  Finally, the organic semiconductor layer 8 is in electrical contact with the second electrode 5 and the third electrode 6 and the fourth electrode 7, while the first electrode 2 is in contact with the first insulating layer 3 and the second electrode 5. 2 insulating layers 4 so as to be electrically separated (see FIG. 3E). As a method for forming the organic semiconductor layer 8, although depending on the material constituting the organic semiconductor layer 8, a PVD method exemplified by a vacuum deposition method and a sputtering method, various CVD methods, a spin coating method, a screen printing method, and an inkjet printing method. Printing method, air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method Any of various coating methods such as a slit orifice coater method, a calendar coater method, and an immersion method, and a spray method can be given.

Example 1
Hereinafter, an embodiment of the field effect transistor of the present invention will be described with reference to FIG. This field effect transistor includes a first electrode 2 (height: 1 μm, width: 10 μm) made of aluminum on a substrate 1 made of glass. The first electrode 2 was formed by depositing aluminum on the substrate 1 by vapor deposition or sputtering. Thereafter, a mask was formed with a resist, and a pattern of the first electrode 2 was formed by wet etching.

  A first insulating layer 3 was formed across the upper surface and side surfaces of the first electrode 2 and the surface of the substrate 1 on both sides of the first electrode 2. As the first insulating layer 3, a poly-2-chloroparaxylylene (parylene C) film was formed to a thickness of 50 nm by a CVD method. On the first insulating layer 3, the second insulating layer 4 is formed by spin coating at a rotational speed of 2000 rpm using a polymer material as a 5 mg / ml toluene solution as the second insulating layer 4. Was formed to be 10 nm.

  Polymer materials include polyvinylphenol (PVP), polymethyl methacrylate (PMMA), a copolymer of polyvinylphenol and polymethyl methacrylate (PVP-PMMA), and a copolymer of polymethyl methacrylate and methacrylic acid (PMMA). -MAA) was used.

  Next, gold was deposited to a thickness of 800 mm by a vapor deposition method while rotating the substrate. Film formation was performed using a mask so that the channel width was 3 mm. After the film formation, the gold electrode on the side surface of the first electrode 2 was etched. As an etchant solution, AURUM302 manufactured by Kanto Chemical was used. The second electrode 5, the third electrode 6, and the fourth electrode 7 were formed by etching.

  Finally, an organic semiconductor layer 8 was formed on the surfaces of the second electrode 5, the third electrode 6, the fourth electrode 7 and the second insulating layer 4. For the organic semiconductor layer 8, pentacene was used and evaporated while rotating the substrate to form a film having a thickness of 240 nm.

(Example 2)
The material of the first insulating layer 3 in Example 1 is a mixture of an organic material and an inorganic material.

A method for manufacturing the first insulating layer 3 will be described. Polyvinyl butyral (PVB) and tetrabutyl titanate (Ti (OC ₄ H ₉ ) ₄ ) were mixed at a composition ratio of 1: 9, and the resulting mixture was dissolved in isopropyl alcohol to obtain a solution having a concentration of 10 to 20 wt%. Manufactured. The solution is applied onto a glass substrate 1 on which a first electrode 2 made of aluminum is formed using a spin coating method to form a film having a thickness of 900 mm, and the film is formed at 70 ° C. for 1 hour and further at 150 ° C. The first insulating layer 3 was manufactured by thermosetting for 30 minutes. A field effect transistor was formed in the same manner as in Example 1 except for the material and manufacturing method of the first insulating layer 3.

(Example 3)
The first insulating layer material in Example 1 is an inorganic material.

A method for manufacturing the first insulating layer 3 will be described. A tantalum oxide film (Ta ₂ O ₅ ) obtained by anodizing tantalum of the first electrode 2 is used as the first insulating layer 3. In this case, a 1.0 wt% ammonium borate aqueous solution is used as a chemical conversion solution, and the substrate on which the first electrode 2 is formed is immersed in this chemical conversion solution. The first electrode 2 was used as an anode, and a DC electric field of 40 V was applied between the cathode prepared separately and the first insulating layer 3 having a thickness of 500 mm was manufactured. A field effect transistor was formed in the same manner as in Example 1 except for the material and manufacturing method of the first insulating layer 3.

Example 4
As the first insulating layer 3, a film of poly-2-chloroparaxylylene (parylene C) was formed to a thickness of 20 nm by a CVD method. On this 1st insulating layer 3, as the 2nd insulating layer 4, polyvinyl phenyl (PVP) was formed like Example 1 so that it might become 10 nm by the spin coat method. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Comparative Example 1)
In the structure having no second insulating layer 4 in Example 1, 50 nm of poly-2-chloroparaxylylene (parylene C) was formed as the first insulating layer 3 by a CVD method. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Comparative Example 2)
In the structure having no second insulating layer 4 in Example 1, polyvinyl phenyl (PVP) was deposited to a thickness of 50 nm as the first insulating layer 3 by spin coating. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Comparative Example 3)
In the structure having no second insulating layer 4 in Example 2, a mixed layer of polyvinyl butyral (PVB) and tetrabutyl titanate (Ti (OC ₄ H ₉ ) ₄ ) is used as the first insulating layer 3. This was formed in the same manner as in Example 2. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Comparative Example 4)
A tantalum oxide film (Ta ₂ O ₅ ) was formed in the same manner as in Example 3 as the first insulating layer 3 with the structure without the second insulating layer 4 in Example 3. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Comparative Example 5)
As the first insulating layer 3, a poly-2-chloroparaxylylene (parylene C) film having a thickness of 30 nm was formed by a CVD method. On this first insulating layer 3, as the second insulating layer 4, polyvinylphenyl (PVP) is formed to a thickness of 30 nm by the spin coating method in the same manner as in Example 1, and the total film thickness of the Example 60 nm which is the same as 1. The other layers and structures were the same as in Example 1 to form a field effect transistor.

(Evaluation results)
Using the first electrode 2 as a gate electrode, the second electrode 5 as a source electrode, and the third electrode 6 as a drain electrode, a source-drain current at a gate voltage V _g = −10 V and a drain voltage V _d = −15 V The value was measured as the maximum current value _Idmax . Also, a defective product having a source-drain current value (in this case, a leakage current) at a gate voltage V _g = 10 V and a drain voltage V _d = 0 V applied to the first electrode 2 is 10 μA or more. We defined several tens of field-effect transistors, and yielded the yield as follows: The results are shown in Table 1 and FIG.

表１中の最大電流量は、作製した電界効果トランジスタでの測定値の平均値を用い、実施例１における第２の絶縁層４材料にＰＶＰを用いた場合の最大電流値で規格化した。表１より、第１の絶縁層３としてパリレンＣをＣＶＤ法により５０ｎｍの膜厚で形成し、第２の絶縁層４として各種高分子材料をスピンコート法により１０ｎｍの膜厚で形成した実施例１では、どの高分子を用いた場合でも、歩留りが１００％と高く、規格化された最大電流値も０．９５〜１．２１と高い値が得られた。また、第１の絶縁層３としてＰＶＢとＴｉ（ＯＣ_４Ｈ_９）_４の混合層を９０ｎｍの膜厚で形成し、第２の絶縁層４としてＰＶＰをスピンコート法により１０ｎｍの膜厚で形成した実施例２では、歩留りが８０％、規格化された最大電流値が０．８８と若干低い値であるが、比較的高い値が得られた。さらに、第１の絶縁層３として酸化タンタル膜（Ｔａ_２Ｏ_５）を陽極酸化により５０ｎｍの膜厚で形成し、第２の絶縁層４としてＰＶＰをスピンコート法により１０ｎｍの膜厚で形成した実施例３では、歩留りは１００％と高く、規格化された最大電流値は、１．５と最も高い値を示した。

The maximum current amount in Table 1 was normalized by the maximum current value when PVP was used as the material of the second insulating layer 4 in Example 1, using the average value of the measured values of the manufactured field effect transistor. From Table 1, an example in which parylene C was formed as a first insulating layer 3 with a thickness of 50 nm by a CVD method, and various polymer materials were formed as a second insulating layer 4 with a thickness of 10 nm by a spin coating method. In No. 1, in any polymer, the yield was as high as 100%, and the standardized maximum current value was as high as 0.95 to 1.21. Further, a mixed layer of PVB and Ti (OC ₄ H ₉ ) ₄ is formed as the first insulating layer 3 with a thickness of 90 nm, and PVP is formed as the second insulating layer 4 with a thickness of 10 nm by a spin coating method. In Example 2, the yield was 80% and the standardized maximum current value was slightly low, 0.88, but a relatively high value was obtained. Furthermore, a tantalum oxide film (Ta ₂ O ₅ ) was formed as the first insulating layer 3 with a thickness of 50 nm by anodic oxidation, and PVP was formed as the second insulating layer 4 with a thickness of 10 nm by spin coating. In Example 3, the yield was as high as 100%, and the standardized maximum current value was as high as 1.5.

On the other hand, as in Comparative Examples 1 to _{4, when} a mixed layer of parylene C, PVP, PVB and Ti (OC ₄ H ₉ ) ₄ and a tantalum oxide film (Ta ₂ O ₅ ) were formed to 50 nm, It became a defective product, and the yield was 0%. This is considered to be because the leakage current was increased due to defects such as pinholes and cracks in the film due to the thin film thickness.

This is because even if the insulating layer is made of two layers, the second insulating layer 4 can be insulated by making the film thickness uniform or repairing defects, etc., even in a thin insulating layer where leakage current is likely to occur. It is considered that the yield was increased in order to suppress the leakage current of the layer.
As for the film thickness of the insulating layer, as shown in Example 4, Parylene C is formed as the first insulating layer 3 with a film thickness of 20 nm, and PVP is formed as the second insulating layer 4 by spin coating to 10 nm. When the film thickness was formed, the yield was slightly reduced, but the standardized maximum current value was as high as 1.2 compared to the same material of Example 1. This is presumably because the current value increased from Equation (1), although the leakage current was likely to occur because the total thickness of the insulating layer was reduced. FIG. 5 shows the relationship between the total thickness of the insulating layer, the yield, and the maximum current value. Parylene C was formed as the first insulating layer 3 by a CVD method, and PVP was formed as the second insulating layer 4 by a spin coating method. Regarding the thickness of each insulating layer, the thickness of the second insulating layer 4 was set to 10 nm, and the thickness of the first insulating layer 3 was set to (total thickness of the insulating layers−10 nm). Thus, the yield and the maximum current value were measured while changing the total film thickness of the insulating layer. The maximum current value was normalized by setting the value when the total thickness of the insulating layer is 60 nm as 100. As can be seen from FIG. 5, when the total film thickness of the insulating layer becomes thinner than 30 nm, the yield rapidly decreases. Also, the normalized maximum current value increases as the film thickness decreases. For this reason, it is preferable to set the minimum film thickness that can keep the yield high.

  For reference, FIG. 6 shows the relationship between the total thickness of the insulating layer, the yield, and the maximum current value in the case where only the parylene C is used without laminating the second insulating layer 4, which is a conventional structure. Compared with the embodiment of the present invention shown in FIG. 5, the yield decreases as the film thickness is reduced. From this, it can be seen that the yield when the film thickness is small can be drastically improved by using two insulating layers as in the present invention.

  On the other hand, as shown in Comparative Example 5, when the thickness of the second insulating layer 4 was increased even when the total thickness of the insulating layer was the same, the yield decreased to 50%. As shown in FIG. 7, when the second insulating layer 4 is thick, the shape of the edge of the first electrode 2 is distorted by the second insulating layer 4, and then the second electrode 5, When the third electrode 6 and the fourth electrode 7 are formed, the respective electrodes are not separated as shown in FIG. 7A, and the first electrode 2 side surface as shown in FIG. It is considered that the yield was lowered because the electrodes were formed up to the second insulating layer 4 and each electrode could not be separated even by the subsequent light etching.

  As described above, the field effect transistor according to the present invention has a high yield and can achieve a high drain current, and therefore can be applied to applications such as a drive circuit board of a current drive type element such as an organic EL element.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure ((a) is a top view, (b) is sectional drawing in an AA cross section) which shows an example of the field effect transistor which concerns on embodiment of this invention. It is a figure ((a) is a top view and (b) is a sectional view in an AA section) showing other examples of a field effect transistor concerning an embodiment of the invention. It is a figure which shows the manufacturing process of an example of the field effect transistor which concerns on embodiment of this invention. It is a conceptual diagram of the defect repair of the 1st insulating layer 3 by the 2nd insulating layer 4 of the field effect transistor which concerns on embodiment of this invention. 3 shows the relationship between the total thickness of the insulating layer, the maximum amount of current, and the yield in the structure according to the embodiment of the present invention. This shows the relationship between the total thickness of the insulating layer, the maximum amount of current, and the yield in the conventional structure. FIG. 5 is a conceptual diagram showing a difference in electrode formation depending on the thickness of a second insulating layer 4. (A) It is a figure which shows the structure after the light etching of the field effect transistor which concerns on embodiment of this invention. (B) It is a conceptual diagram which shows the structure after the light etching in case the 2nd insulating layer 4 is an inappropriate film thickness.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 1st electrode 3 1st insulating layer 4 2nd insulating layer 5 2nd electrode 6 3rd electrode 7 4th electrode 8 Organic-semiconductor layer

Claims (7)

A substrate,
A first electrode provided on a substrate;
A first insulating layer provided on the surface of the first electrode;
A second insulating layer made of an organic material provided on the surface of the first insulating layer;
A second electrode located above the first electrode and provided on a second insulating layer;
A third electrode separated from the second electrode and provided on the substrate via the first insulating layer or the second insulating layer or directly;
An organic semiconductor layer provided in contact with the second electrode and the third electrode and insulated from the first electrode via the first insulating layer and the second insulating layer; With
The upper surface of the third electrode is provided at a position lower than the upper surface of the first electrode,
2. The field effect transistor according to claim 1, wherein the thickness of the second insulating layer is smaller than the thickness of the first insulating layer. The field effect transistor according to claim 1, wherein the second insulating layer is formed by a wet method. 3. The field effect transistor according to claim 1, wherein a sum of thicknesses of the first insulating layer and the second insulating layer is 30 nm or more and 200 nm or less. The field effect transistor according to claim 1, wherein the second insulating layer has a thickness of 10 nm or less. The field effect transistor according to claim 1, wherein the first insulating layer is made of an organic material. Forming a first electrode on a substrate;
Forming a first insulating layer on the surface of the first electrode;
Forming a second insulating layer on the surface of the first insulating layer;
Simultaneously forming the second electrode on the second insulating layer located above the first electrode;
Forming a third electrode so as to be separated from the second electrode;
Forming an organic semiconductor layer so as to be in contact with the second electrode and the third electrode and insulated from the first electrode via the first insulating layer and the second insulating layer;
A method of manufacturing a field effect transistor comprising: The method of manufacturing a field effect transistor according to claim 6, wherein the step of forming the second insulating layer is performed by a wet method.

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