JP2009004834A - Solid-state imaging device and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device having a wide dynamic range and a large SN ratio. <P>SOLUTION: A pixel 90 includes: a photodiode (1) for generating charges depending on the strength of an incident light; signal generating sections (2, 4, 6, 7) for generating a first voltage level in accordance with the amount of charges generated during an exposure period T1 by the photodiode (1) and a second voltage level in accordance with the amount of charges generated during an exposure period T2 by the photdiode (1); signal compositing sections (M1-Mn, 9, 11, 13, 14) for compositing the first and second voltage levels generated by the signal generating sections (2, 4, 6, 7); and a level limiting section (70) for limiting the signal level so that the signal levels of the first and second voltage signals to be composited in the signal compositing section may not exceed a signal level equivalent the maximum accumulating quantity of the photodiode (1). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device used for a digital camera or the like, and more particularly to a technique for expanding a dynamic range.

The dynamic range of a conventional solid-state imaging device is about 60 dB to 80 dB, and is improved to about 100 dB to 120 dB comparable to the naked eye or a silver salt film, or higher than that depending on the use of an in-vehicle camera or a surveillance camera. Is desired. Therefore, Patent Document 1 discloses a technique for capturing a plurality of frames while varying the length of the exposure period and combining the captured frames. The luminance range that can be photographed in one frame changes according to the length of the exposure period. With the technique of Patent Document 1, the dynamic range can be expanded by combining a plurality of frames with different luminance ranges that can be photographed.
Japanese Patent Laid-Open No. 2004-15298

  However, in the technique of Patent Document 1, since a frame memory for storing a plurality of frames and a signal synthesis unit for synthesizing a plurality of frames are provided outside the solid-state imaging device, chip area and power consumption are reduced. There is a problem that it increases. In addition, since it is necessary to read out a plurality of frames of pixel signals from the solid-state imaging device in order to create one frame, there is also a problem that the frame rate is reduced if there is no room for reading speed.

  If the signal level of long exposure and the signal level of short exposure are simply combined, if the intensity of the incident light exceeds the maximum accumulated amount of the photodiode and generates charge, it will be excessive. The signal level of long exposure may be pushed up due to the influence of the generated charge. In such a case, there is a problem that the contribution ratio of the signal level of short-time exposure in the signal level after synthesis is relatively lowered, and the SN ratio of the signal level after synthesis is lowered.

Accordingly, a first object of the present invention is to provide a solid-state imaging device and a camera that can expand the dynamic range while minimizing the occurrence of the above problems.
Furthermore, the present invention provides a solid-state imaging device and a camera that can suppress a decrease in the S / N ratio even when the intensity of incident light exceeds the maximum accumulation amount of the photodiode to generate charges. The purpose of 2.

  A solid-state imaging device according to the present invention is a solid-state imaging device including a plurality of pixels, each pixel including a photodiode that generates a charge according to the intensity of incident light, and the photodiode in one frame period. The first voltage signal is generated according to the amount of charge generated during the first exposure period, and the amount of charge generated during the second exposure period that is different in length from the first exposure period by the photodiode. In response to the signal generator, a signal generator for combining the first and second voltage signals generated by the signal generator, and the intensity of the incident light of the photodiode. A signal in which the signal levels of the first and second voltage signals synthesized by the signal synthesis unit correspond to the maximum accumulation amount of the photodiode when the intensity exceeds the maximum accumulation amount and generates electric charge. And a level limiting unit for limiting the signal level does not exceed the bell.

  A camera according to the present invention is a camera including a solid-state imaging device, and the solid-state imaging device includes a plurality of pixels, each pixel generating a charge according to the intensity of incident light, and 1 In the frame period, a first voltage signal is generated according to the amount of electric charge generated by the photodiode during the first exposure period, and a second length different from the first exposure period is generated by the photodiode. A signal generator that generates a second voltage signal according to the amount of charge generated during the exposure period; a signal combiner that combines the first and second voltage signals generated by the signal generator; When the intensity of the incident light exceeds the maximum accumulation amount of the photodiode and generates an electric charge, the signal levels of the first and second voltage signals synthesized by the signal synthesis unit are the photodiodes. So as not to exceed the signal level corresponding to the maximum amount of accumulated and a level limiting unit for limiting the signal level.

  According to the above configuration, since the first pixel signal and the second pixel signal are combined, the dynamic range can be expanded. Further, since the first pixel signal and the second pixel signal are synthesized by the pixels, it is not necessary to provide a frame memory or a signal synthesis unit outside the solid-state imaging device. Furthermore, since the combined pixel signal is read out, it is possible to suppress a reduction in the frame rate.

  Furthermore, according to the above configuration, even when the intensity of the incident light exceeds the maximum accumulation amount of the photodiode and generates a charge, the signal levels of the first and second voltage signals are set to the maximum accumulation amount of the photodiode. The signal level is limited so as not to exceed the corresponding signal level. Accordingly, it is possible to suppress a decrease in the contribution rate of the signal level of short-time exposure in the signal level after synthesis, and as a result, it is possible to suppress a decrease in the SN ratio of the signal level after synthesis.

  The first and second voltage signals are transmitted from the signal generation unit to the signal synthesis unit through a signal path, and the level limiting unit has a signal level appearing in the signal path that is a maximum accumulation amount of the photodiode. When a reference level equal to or less than the signal level corresponding to is exceeded, the signal path is connected to a reference power source having a reference level equal to or less than the signal level corresponding to the maximum accumulation amount of the photodiode. It is good to do.

According to the above configuration, even if a signal level exceeding the reference level appears in the signal path, the signal path and the reference power source are connected, and as a result, the reference level appears in the signal path. Therefore, the signal levels of the first and second voltage signals can be prevented from exceeding the reference level.
The level limiting unit includes a comparison circuit that compares the signal level appearing in the signal path with the reference level, and a switch element inserted in a path connecting the signal path and the reference power source, The switch element is turned on when a comparison result by the comparison circuit indicates that a signal level appearing in the signal path exceeds the reference level, and a signal level at which the comparison result by the comparison circuit appears in the signal path May be turned off when indicating that the reference level does not exceed the reference level.

  With the above configuration, the signal level can be limited with relatively high accuracy. The reference level is equal to the reference level, and the level limiting unit includes a diode element inserted in a path connecting the signal path and the reference power source, and the diode element is a signal appearing in the signal path. Only when the level exceeds the reference level, a current in the direction from the signal path to the reference power supply may be passed.

With the above configuration, the signal level can be limited with a relatively simple configuration.
The signal synthesizer includes a first capacitor that holds the first voltage signal and a second capacitor that holds the second voltage signal. The first voltage signal is a first capacitor The signal is transmitted from the signal generator to the first capacitor through a signal path, the second voltage signal is transmitted from the signal generator to the second capacitor through a second signal path, and the level limiter is When the signal level appearing in the first signal path exceeds a first reference level equal to or less than the signal level corresponding to the maximum accumulation amount of the photodiode, the first signal path is A signal level appearing in the second signal path is connected to a first reference power source having a first reference level equal to or smaller than a signal level corresponding to the maximum accumulation amount of the photodiode. When the second reference level different from the first reference level, which is equal to or smaller than the signal level corresponding to the maximum accumulation amount of the photodiode, is exceeded, the second signal path is connected to the photodiode. It may be connected to a second reference power source having a second reference level different from the first reference level, which is the same as or smaller than the signal level corresponding to the maximum accumulation amount.

With the above configuration, it is possible to individually set the limit of the signal level of the first voltage signal and the limit of the signal level of the second voltage signal.
The signal generation unit includes a transfer transistor inserted in a signal path connecting the photodiode and the floating diffusion, and the level limiting unit is an overflow drain for discharging the charge generated by the photodiode. The overflow drain barrier may be lower than the barrier when the transfer transistor is in the OFF state.

According to the above configuration, even if the charge is generated exceeding the maximum accumulation amount of the photodiode, the excess charge is discharged by the overflow drain. Therefore, the signal levels of the first and second voltage signals can be prevented from exceeding the level determined by the height of the overflow drain barrier.
The signal generation unit is inserted in a path connecting the first pole of the power source and the output node, and generates a current according to the amount of charge generated by the photodiode, the output node, A load resistor inserted in a path connecting to the second pole of the power source, and the level limiting unit includes a signal level output from the output node and a signal level corresponding to a maximum accumulation amount of the photodiode. A comparison circuit that compares a reference level equal to or smaller than the reference level, and a switch element inserted in a path connecting the output node and the second pole of the power supply, the switch element comprising the comparison circuit Is turned off when the result of comparison indicates that the signal level output from the output node exceeds the reference level, and the result of comparison by the comparison circuit is output from the output node. It may be turned on when indicating that the force signal level does not exceed the reference level.

  According to the above configuration, when the signal level output from the output node exceeds the reference level, the switch element is turned off. Therefore, the signal level of the output node changes so as not to exceed the reference level. When the signal level of the output node does not exceed the reference level, the switch element is turned on. By repeating such an operation, the signal levels of the first and second voltage signals can be prevented from exceeding the reference level.

The best mode for carrying out the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a functional block diagram showing a configuration of a MOS type solid-state imaging device 100 according to Embodiment 1 of the present invention.
As shown in FIG. 1, in the MOS type solid-state imaging device 100 according to the present embodiment, (L × M) imaging pixels 90 (11) to 90 (LM) are provided in a matrix. Each imaging pixel is connected to common vertical signal lines 92 (1) to 92 (L) via MOS transistors 91 (11) to 91 (LM), respectively.

The common vertical signal lines 92 (1) to 92 (L) are connected to the common signal line 95 via noise cancel circuits 93 (1) to 93 (L) and MOS transistors 94 (1) to 94 (L), respectively. ing.
In the MOS type solid-state imaging device 100, a vertical scanning circuit 96 and a horizontal scanning circuit 98 are provided in the peripheral portion of the (L × M) imaging pixels 90 (11) to 90 (LM) arranged in a matrix. ing. Among these, signal output lines 97 (1) to 97 (M) extending in the X-axis direction are extended from the vertical scanning circuit 96. The signal output lines 97 (1) to 97 (M) are connected to the gates of the MOS transistors 91 (11) to 91 (LM).

On the other hand, signal output lines 99 (1) to 99 (L) extending in the Y-axis direction are extended from the horizontal scanning circuit 98. The signal output lines 99 (1) to 99 (L) are connected to the gates of the MOS transistors 94 (1) to 94 (L).
FIG. 2 is a diagram showing a configuration of the imaging pixel 90 according to Embodiment 1 of the present invention.
The imaging pixel 90 includes a photodiode 1, a signal generation unit, a signal synthesis unit, and a level limiting unit 70.

  The signal generation unit includes MOS transistors 2, 4, 6, 7 and a floating diffusion F. The MOS transistor 2 is inserted in a path connecting the photodiode 1 and the floating diffusion F. The MOS transistor 4 is inserted in a path connecting the floating diffusion F and the reference voltage power source. The MOS transistors 6 and 7 constitute a source follower. The gate of the MOS transistor 6 is supplied with the voltage VF of the floating diffusion F, and the drain of the MOS transistor 6 is supplied with the power supply voltage VDD. A bias voltage is supplied to the gate of the MOS transistor 7, and a ground voltage is supplied to the source of the MOS transistor 7. The source follower constituted by the MOS transistors 6 and 7 outputs a voltage signal obtained by multiplying the voltage VF of the floating diffusion F by a gain.

  The signal synthesis unit includes MOS transistors 9, 11, 13, and 14, memories M1 to Mn, and a signal synthesis capacitor C0. The MOS transistor 9 is inserted in a path connecting the drain of the MOS transistor 7 and the point M. The MOS transistor 11 is inserted in a path connecting the point M and the reference voltage power source. The MOS transistors 13 and 14 constitute a source follower. The power supply voltage VDD is supplied to the drain of the MOS transistor 13, and the voltage VM at the point M is supplied to the gate of the MOS transistor 13. A bias voltage is supplied to the gate of the MOS transistor 14, and a ground voltage is supplied to the source of the MOS transistor 14. The source follower constituted by the MOS transistors 13 and 14 outputs a voltage V16 obtained by multiplying the voltage VM at the point M by a gain. Memory M1 includes a capacitor 19 (1) and a MOS transistor 17 (1). The MOS transistor 17 (1) is inserted in a path connecting the capacitor 19 (1) and the point M. The memories M2 to Mn have the same configuration as the memory M1, and the capacitors 19 (1) to 19 (n) have the same capacity. The signal combining capacitor C0 is a stray capacitance.

  Level limiting unit 70 includes a comparison circuit 71 and a MOS transistor 72. The comparison circuit 71 compares the voltage VM at the point M with the reference voltage VREF. The MOS transistor 72 is inserted in a path connecting the point M and the reference voltage power source. The output signal of the comparison circuit 71 is supplied to the gate of the MOS transistor 72. The MOS transistor 72 is turned on when the output signal of the comparison circuit 71 indicates that the voltage VM is lower than the reference voltage VREF, and the output signal of the comparison circuit 71 indicates that the voltage VM is equal to or higher than the reference voltage VREF. When turned off, it turns off. When the MOS transistor 72 is turned on, the voltage VM at the point M is fixed to the reference voltage VREF, so that the voltage VM at the point M does not fall below the reference voltage VREF. As described above, the level limiting unit 70 can define the lower limit of the voltage VM at the point M. By setting the reference voltage VREF to a level corresponding to the maximum accumulation amount of the photodiode 1, it is possible to prevent the voltage VM at the point M from dropping beyond a level corresponding to the maximum accumulation amount of the photodiode 1. .

FIG. 3 is a timing chart showing a drive signal for driving the image pickup pixel 90 according to Embodiment 1 of the present invention and a voltage signal appearing at each part of the image pickup pixel 90 when the image pickup pixel 90 is driven by the drive signal. It is.
In FIG. 3, a period A is a period for holding the voltage signal at the time of reading in the memory, a period B is a period for outputting the voltage signal at the time of reading held in the memory, and a period C is a period for holding the voltage signal at the time of resetting in the memory. The period D is a period for outputting a voltage signal at reset held in the memory.

  The drive signal S10 is a signal supplied to the gate 10 of the MOS transistor 9, the drive signal S12 is a signal supplied to the gate 12 of the MOS transistor 11, the drive signal S5 is a signal supplied to the gate 5 of the MOS transistor 4, and the drive signal. S3 is a signal supplied to the gate 3 of the MOS transistor 2, a drive signal S18 (1) is a signal supplied to the gate 18 (1) of the MOS transistor 17 (1), and a drive signal S18 (2) is the MOS transistor 17 ( The signal supplied to the gate 18 (2) of 2) and the drive signal S18 (3) are signals supplied to the gate 18 (3) of the MOS transistor 17 (3).

  The voltage signal VF is a signal appearing at the floating diffusion F, the voltage signal V19 (1) is a signal appearing at the capacitor 19 (1), the voltage signal V19 (2) is a signal appearing at the capacitor 19 (2), and the voltage signal V19 (3) is The signal appearing at the capacitor 19 (3), the voltage signal VM is a signal appearing at the point M, and the voltage signal V16 is a signal appearing at the output node of the source follower constituted by the MOS transistors 13 and 14.

At time t2, the MOS transistor 2 remains off and the MOS transistor 4 is on for a predetermined period. As a result, the voltage VF of the floating diffusion F becomes the reference level VR.
From time t3 to time t4, the MOS transistor 4 remains off and the MOS transistor 2 turns on. Then, the charge generated by the photodiode 1 during the exposure period T1 is transferred to the floating diffusion F. As a result, the voltage VF of the floating diffusion F is lowered from the reference level VR by an amount corresponding to the amount of charge generated during the exposure period T1, and becomes the read level VF1. At this time, the MOS transistors 11, 17 (2), 17 (3) are in the off state, and the MOS transistors 9, 17 (1) are in the on state. Therefore, the voltage VM at the point M becomes a level VM1 obtained by multiplying the read level VF1 by the gain of the source follower, and the voltage V19 (1) of the capacitor 19 (1) is substantially the same level V19 (1) 1 as the level VM1. become. When the MOS transistor 17 (1) is turned off after the time t4, the level V19 (1) 1 is held in the capacitor 19 (1).

Next, at time t5, the MOS transistor 2 remains off, and the MOS transistor 4 is turned on for a predetermined period. As a result, the voltage VF of the floating diffusion F becomes the reference level VR.
From time t6 to time t7, the MOS transistor 4 remains off and the MOS transistor 2 turns on. Then, the charge generated by the photodiode 1 during the exposure period T2 is transferred to the floating diffusion F. As a result, the voltage VF of the floating diffusion F is lowered from the reference level VR by an amount corresponding to the amount of charge generated during the exposure period T2, and becomes the read level VF2. At this time, the MOS transistors 11, 17 (1), 17 (3) are in the off state, and the MOS transistors 9, 17 (2) are in the on state. Therefore, the voltage VM at the point M becomes a level VM2 obtained by multiplying the read level VF2 by the gain of the source follower, and the voltage V19 (2) of the capacitor 19 (2) is substantially the same level V19 (2) 1 as the level VM2. become. If the MOS transistor 17 (2) is turned off after the time t7, the level V19 (2) 1 is held in the capacitor 19 (2).

Next, at time t8, the MOS transistor 2 remains off and the MOS transistor 4 remains on for a predetermined period. As a result, the voltage VF of the floating diffusion F becomes the reference level VR.
From time t9 to time t10, the MOS transistor 4 remains off and the MOS transistor 2 turns on. Then, charges generated by the photodiode 1 during the exposure period T3 are transferred to the floating diffusion F. As a result, the voltage VF of the floating diffusion F is lowered from the reference level VR by an amount corresponding to the amount of charge generated during the exposure period T3, and reaches the read level VF3. At this time, the MOS transistors 11, 17 (1), 17 (2) are in an off state, and the MOS transistors 9, 17 (3) are in an on state. Therefore, the voltage VM at the point M becomes a level VM3 obtained by multiplying the read level VF3 by the gain of the source follower, and the voltage V19 (3) of the capacitor 19 (3) is substantially the same level V19 (3) 1 as the level VM2. become. When the MOS transistor 17 (3) is turned off after the time t10, the level V19 (3) 1 is held in the capacitor 19 (3).

Next, at time t12, the MOS transistor 9 remains off and the MOS transistor 11 remains on for a predetermined period. As a result, the voltage VM at the point M becomes the reference level VB.
From time t13 to time t14, the MOS transistors 9 and 11 remain in the off state, and the MOS transistors 17 (1), 17 (2), and 17 (3) are in the on state. At this time, capacitors 19 (1), 19 (2), 19 (3), and C0 are connected in parallel. As a result, the voltage VM at the point M becomes the average voltage VM4 of the levels V19 (1) 1, V19 (2) 1, V19 (3) 1, and VB.

  Next, from time t16 to time t17, the MOS transistor 2 remains off and the MOS transistor 4 turns on. Therefore, the voltage VF of the floating diffusion F becomes the reference level VR. At this time, the MOS transistor 11 is in an OFF state, and the MOS transistors 9, 17 (1), 17 (2), and 17 (3) are in an ON state. Therefore, the voltage VM at the point M becomes a level VM5 obtained by multiplying the reference level VR by the gain of the source follower, and the voltage V19 (1) of the capacitor 19 (1), the voltage V19 (2) of the capacitor 19 (2), The voltage V19 (3) of the capacitor 19 becomes the same level V19 (1) 3, V19 (2) 3, V19 (3) 3 as the level VM5. When the MOS transistors 17 (1), 17 (2), and 17 (3) are turned off after the time t17, the capacitors 19 (1), 19 (2), and 19 (3) have levels V19 (1), respectively. 3, V19 (2) 3, V19 (3) 3 are held.

Next, at time t19, the MOS transistor 9 remains off and the MOS transistor 11 remains on for a predetermined period. As a result, the voltage VM at the point M becomes the reference level VB.
From time t20 to time t21, the MOS transistors 9 and 11 remain in the off state, and the MOS transistors 17 (1), 17 (2), and 17 (3) are in the on state. At this time, capacitors 19 (1), 19 (2), 19 (3), and C0 are connected in parallel. As a result, the voltage VM at the point M becomes the average voltage VM6 of the levels V19 (1) 3, V19 (2) 3, V19 (3) 3, and VB.

  The source follower constituted by the MOS transistors 13 and 14 outputs a voltage V16 obtained by multiplying the voltage VM at the point M by a gain. The voltage V16 is sampled by the noise cancellation circuit 93 at time t16 and time t21. The noise cancellation circuit 93 obtains the difference between the level V161 at time t16 and the level V162 at time t21 as a pixel signal.

FIG. 4 is a diagram for explaining a comparison between the case where the level limiting unit 70 according to Embodiment 1 of the present invention is present and the case where it does not exist.
FIG. 4A shows the voltage VF of the floating diffusion F and the voltage VM at the point M when the level limiting unit 70 exists.
If the intensity of the incident light exceeds the maximum accumulation amount of the photodiode 1 and generates a charge, the photodiode 1 exceeds the barrier formed in the channel of the MOS transistor 2 even when the MOS transistor 2 is off. The charge may leak from the floating diffusion F into the floating diffusion F. In such a case, the voltage VF of the floating diffusion is reduced from the reference level VR by the amount of leakage charge ΔV1. Further, the voltage VM at the point M decreases from the level VMR obtained by multiplying the reference level VR by the gain of the source follower by a level ΔV2 corresponding to the amount of leakage charge ΔV1.

  From time t3 to time t4, the MOS transistor 2 is turned on, and the charge generated by the photodiode 1 during the exposure period T1 (the same amount of charge as the maximum accumulated amount of the photodiode 1) is transferred to the floating diffusion F. . At this time, if there is no leakage charge, the voltage VF decreases from the reference level VR by an amount corresponding to the maximum accumulation amount of the photodiode 1 to become the level VFS. However, since there is leakage charge, the voltage VF is higher than the level VFS. It is lowered by the minute ΔV1 (VF1). On the other hand, even if there is a leakage charge, the voltage VM does not fall below the level VMS (reference level VREF) obtained by multiplying the level VFS by the gain of the source follower due to the presence of the level limiting unit 70. Therefore, the memory 1 holds the reference level VREF that is a level corresponding to the maximum accumulation amount of the photodiode 1 (VM1).

FIG. 4B shows the voltage VF of the floating diffusion F and the voltage VM at the point M when the level limiting unit 70 is not present.
When the level limiting unit 70 is not present, the voltage VM decreases from the level VMS by the amount of leakage charge ΔV2 if there is leakage charge. Accordingly, the memory 1 retains a level that has decreased beyond the level corresponding to the maximum accumulation amount of the photodiode 1 (VM1).

FIG. 5 is a diagram showing the relationship between the accumulated charge of the imaging pixel 90 and the exposure time according to Embodiment 1 of the present invention.
The upper limit d of the accumulated charge of the imaging pixel 90 is determined by the maximum accumulated amount of the photodiode 1. The slope of the straight line a indicates the upper limit of the light intensity at which the charge is not saturated in the exposure period T1. Similarly, the slopes of the straight lines b and c indicate the upper limit of the light intensity at which the charge is not saturated in the exposure periods T2 and T3. Thus, as the exposure period is shorter, the charge is less likely to be saturated even if the light intensity is high.

FIG. 6 is a diagram showing a relationship between the signal level (before synthesis) and the light intensity of the imaging pixel 90 according to Embodiment 1 of the present invention.
The upper limit h of the signal level of the imaging pixel 90 is the reference voltage VREF. Here, the reference voltage VREF is set to a level corresponding to the maximum accumulation amount of the photodiode 1. A straight line e indicates a signal level with respect to the light intensity in the exposure period T1. Similarly, the straight lines f and g indicate signal levels with respect to light intensity in the exposure periods T2 and T3. Thus, the shorter the exposure period, the less the signal level becomes saturated even if the light intensity is high. Broken lines p and q indicate signal levels in the exposure periods T1 and T2 when the level limiting unit 70 is not present. When the level limiting unit 70 does not exist, a signal level exceeding the level (upper limit h) corresponding to the maximum accumulation amount of the photodiode 1 appears due to the influence of leakage charge.

FIG. 7 is a diagram showing the relationship between the signal level (after synthesis) and the light intensity of the imaging pixel 90 according to Embodiment 1 of the present invention.
A curve i indicates the signal level with respect to the light intensity when the signal levels of the exposure periods T1, T2, and T3 are combined. In this way, by combining the signal levels having different exposure periods, it is possible to prevent saturation of the signal level even if the light intensity is strong while securing a certain signal level even if the light intensity is weak. This means that the dynamic range is widened. In the first embodiment, the capacitors 19 (1) to 19 (n) have the same capacitance. Therefore, the contribution rates of the signal levels in the exposure periods T1, T2, and T3 in the combined signal level are all equal. A broken line r indicates a signal level with respect to the light intensity when the signal levels of the exposure periods T1, T2, and T3 are combined when the level limiting unit 70 is not present. When the level limiting unit 70 is not present, the contribution ratio of the signal levels in the exposure periods T1 and T2 increases due to the influence of leakage charges, and the contribution ratio of the signal level in the exposure period T3 relatively decreases. As described above, when the level limiting unit 70 exists, the contribution ratio of the exposure period T3 is higher than when the level limiting unit 70 does not exist, and as a result, the SN ratio increases.

FIG. 8 is a diagram showing the configuration of the camera according to Embodiment 1 of the present invention.
The camera includes an imaging chip 102, a signal processing chip 103, and an optical system 105. On the imaging chip 102, a MOS type solid-state imaging device 100 and a timing generation unit 101 are mounted. The timing generation unit 101 generates a drive signal. The generated drive signal is supplied to the MOS type solid-state imaging device 100. The signal processing chip 103 performs predetermined signal processing on the pixel signal output from the MOS type solid-state imaging device 100.
(Embodiment 2)
In the second embodiment, the configuration of the level limiting unit 70 is different from that of the first embodiment. Since the other points are the same as those in the first embodiment, the description thereof is omitted.

FIG. 9 is a diagram showing a configuration of the imaging pixel 90 according to Embodiment 2 of the present invention.
Level limiting unit 70 includes an inverter circuit 73 and a MOS transistor 74. The inverter circuit 73 inverts and outputs the output signal of the source follower constituted by the MOS transistors 6 and 7. Therefore, the more charge generated by the photodiode 1, the higher the voltage VM at the point M. The MOS transistor 74 is inserted in a path connecting the point M and the reference voltage power source. A voltage VM is supplied to the gate of the MOS transistor 74. Therefore, the MOS transistor 74 functions as a diode element, and when the voltage VM is higher than the reference voltage VH, a current flows from the voltage VM toward the reference voltage power supply. When the current flows, the voltage VM at the point M does not rise above the reference voltage VH. As described above, the level limiting unit 70 can define the upper limit of the voltage at the point M. By setting the reference voltage VH to a level corresponding to the maximum accumulation amount of the photodiode 1, it is possible to prevent the voltage VM at the point M from rising beyond a level corresponding to the maximum accumulation amount of the photodiode 1. .

As shown in FIG. 10, the same effect can be obtained by adopting a Zener diode 75 instead of the MOS transistor 74.
Further, as shown in FIG. 11, if an inverter amplifier is constituted by the MOS transistors 6 and 7, the pixel configuration can be simplified and the voltage can be amplified with a high gain depending on the design. Since the memory unit holds the voltage-amplified output signal, the signal level held in the memory unit can be synthesized with high accuracy. The Zener diode 75 allows a current to flow from the voltage VM toward the reference voltage power supply when the voltage VM is higher than the reference voltage VH. When the current flows, the voltage VM at the point M does not rise above the reference voltage VH. A similar effect can be obtained by making a MOS transistor function as a diode element instead of the Zener diode 75.
(Embodiment 3)
The third embodiment is different from the first embodiment in that the reference level is different for each exposure period. Since the other points are the same as those in the first embodiment, the description thereof is omitted.

FIG. 12 is a diagram illustrating a configuration of the imaging pixel 90 according to Embodiment 3 of the present invention.
Level limiters 70 (1) to 70 (n) exist corresponding to the memories M1 to Mn, respectively, and set the lower limits of the voltages V19 (1) to V19 (n) of the capacitors 19 (1) to 19 (n). It prescribes. The individual configurations of the level limiting units 70 (1) to 70 (n) are the same as those in the first embodiment.

Note that the imaging pixel 90 may obtain the reference voltages VREF (1) to VREF (n) from the outside, or may internally generate them by resistance division.
Similarly to the first embodiment, only one level limiting unit 70 may be provided at the M point, and the reference voltage VREF may be changed for each exposure period. For example, during the period in which the MOS transistor 17 (1) of the memory M1 is in the ON state (from time t2 to time t4 in FIG. 3), the reference voltage VREF (1) is output to the reference voltage power supply, and the MOS transistor 17 (2 ) Is in the ON state (from time t5 to time t7 in FIG. 3), the reference voltage power supply is caused to output the reference voltage VREF (2). Even if it does in this way, the effect similar to Embodiment 3 can be acquired.
(Embodiment 4)
In the fourth embodiment, the configuration of the level limiting unit 70 is different from that of the first embodiment. Since the other points are the same as those in the first embodiment, the description thereof is omitted.

FIG. 13 is a diagram showing a configuration of the imaging pixel 90 according to Embodiment 4 of the present invention.
Level limiting unit 70 includes a MOS transistor 76. The MOS transistor is inserted in a path connecting the photodiode 1 and the bias power source. A bias voltage is supplied to the gate 77 of the MOS transistor 76. The bias voltage is set so that the barrier formed in the channel of the MOS transistor 76 is lower than the barrier formed in the channel of the MOS transistor 2 when the MOS transistor 2 is in the OFF state. Therefore, the charge generated excessively by the photodiode 1 is discharged to the bias power supply via the MOS transistor 76 without leaking to the floating diffusion F via the MOS transistor 2. By providing the overflow drain in this way, it is possible to prevent the voltage VM at the point M from dropping beyond a level corresponding to the maximum accumulation amount of the photodiode 1.
(Embodiment 5)
In the fifth embodiment, the configuration of the level limiting unit 70 is different from that of the first embodiment. Since the other points are the same as those in the first embodiment, the description thereof is omitted.

FIG. 14 is a diagram showing the configuration of the imaging pixel 90 according to Embodiment 5 of the present invention.
Level limiting unit 70 includes a comparison circuit 78 and a MOS transistor 79. The comparison circuit 78 compares the voltage VM at the point M with the reference voltage VRER. The MOS transistor 79 is inserted in a path connecting the MOS transistor 7 and the ground. The output signal of the comparison circuit 78 is supplied to the gate of the MOS transistor 79. The MOS transistor 79 is turned off when the output signal of the comparison circuit 78 indicates that the voltage VM is lower than the reference voltage VREF, and the output signal of the comparison circuit 78 indicates that the voltage VM is equal to or higher than the reference voltage VREF. It turns on when indicating. When the MOS transistor 79 is turned off, the voltage VM at the point M increases. When the voltage VM at the point M rises and becomes equal to or higher than the reference voltage VREF, the MOS transistor 79 is turned on. As described above, the level limiting unit 70 can define the lower limit of the voltage VM at the point M. By setting the reference voltage VREF to a level corresponding to the maximum accumulation amount of the photodiode 1, it is possible to prevent the voltage VM at the point M from dropping beyond a level corresponding to the maximum accumulation amount of the photodiode 1. .

As described above, the solid-state imaging device and the camera according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. For example, the following modifications can be considered.
(1) In the first embodiment, the level limiting unit 70 compares the voltage VM at the M point with the reference voltage VREF, and if the voltage VM at the M point is lower than the reference voltage VREF, the level VM is changed to the reference voltage VREF. It is supposed to be fixed. That is, the voltage to be compared with the voltage VM is common to the voltage for fixing the voltage VM. However, the present invention is not limited to this example, and the voltage to be compared may be different from the fixed voltage.

In the fourth embodiment, the level limiting unit 70 discharges charges to the bias power source. However, the present invention is not limited to this example, and a bias power source and a charge / discharge power source may be provided separately.
(2) In the fourth embodiment, the height of the overflow drain barrier is set by appropriately setting the bias voltage supplied to the gate of the MOS transistor 76. However, the present invention is not limited to this example, and the height of the overflow drain barrier may be set by providing a diffusion region around the photodiode 1 and appropriately setting the potential of the diffusion region.

  The present invention can be used for digital cameras, mobile phone built-in cameras, vehicle-mounted cameras, surveillance cameras, and the like.

It is a functional block diagram which shows the structure of the MOS type solid-state imaging device 100 which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on Embodiment 1 of this invention. 3 is a timing chart showing a drive signal for driving the imaging pixel 90 according to Embodiment 1 of the present invention and a voltage signal appearing in each part of the imaging pixel 90 when the imaging pixel 90 is driven by the drive signal. FIG. It is a figure for demonstrating the comparison with the case where the level limiting part 70 which concerns on Embodiment 1 of this invention exists, and the case where it does not exist. It is a figure which shows the relationship between the accumulation charge of the imaging pixel 90 which concerns on Embodiment 1 of this invention, and exposure time. It is a figure which shows the relationship between the signal level (before synthetic | combination) of the imaging pixel 90 which concerns on Embodiment 1 of this invention, and light intensity. It is a figure which shows the relationship between the signal level (after a synthesis | combination) and light intensity of the imaging pixel 90 which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the camera which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on Embodiment 2 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on the modification of Embodiment 2 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on the modification of Embodiment 2 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on Embodiment 3 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on Embodiment 4 of this invention. It is a figure which shows the structure of the imaging pixel 90 which concerns on Embodiment 5 of this invention.

Explanation of symbols

70 Level Limiting Unit 90 Imaging Pixel 91 MOS Transistor 92 Common Vertical Signal Line 93 Noise Canceling Circuit 94 MOS Transistor 95 Common Signal Line 96 Vertical Scanning Circuit 97 Signal Output Line 98 Horizontal Scanning Circuit 99 Signal Output Line 100 MOS Type Solid State Imaging Device 101 Timing Generation unit 102 Imaging chip 103 Signal processing chip 105 Optical system

Claims (8)

A solid-state imaging device including a plurality of pixels,
Each pixel is
A photodiode that generates charge according to the intensity of incident light;
In one frame period, a first voltage signal is generated according to the amount of charge generated by the photodiode during the first exposure period, and a second length different from the first exposure period is generated by the photodiode. A signal generator that generates a second voltage signal in accordance with the amount of charge generated during the exposure period;
A signal synthesis unit that synthesizes the first and second voltage signals generated by the signal generation unit;
When the intensity of the incident light exceeds the maximum accumulation amount of the photodiode and generates a charge, the signal levels of the first and second voltage signals synthesized by the signal synthesis unit are A solid-state imaging device comprising: a level limiting unit that limits a signal level so as not to exceed a signal level corresponding to a maximum accumulation amount. The first and second voltage signals are transmitted from the signal generation unit to the signal synthesis unit through a signal path,
The level limiter is
When the signal level appearing in the signal path exceeds a reference level equal to or smaller than the signal level corresponding to the maximum accumulation amount of the photodiode, the signal path is changed to a signal corresponding to the maximum accumulation amount of the photodiode. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to a reference power source having a reference level equal to or lower than the level. The level limiter is
A comparison circuit for comparing a signal level appearing in the signal path with the reference level;
Including a switch element inserted in a path connecting the signal path and the reference power source,
The switch element is turned on when the comparison result by the comparison circuit indicates that the signal level appearing in the signal path exceeds the reference level, and the comparison element by the comparison circuit appears in the signal path. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is turned off when it indicates that the level does not exceed the reference level. The reference level and the reference level are equal;
The level limiter is
Including a diode element inserted in a path connecting the signal path and the reference power source;
3. The solid-state imaging device according to claim 2, wherein the diode element flows a current in a direction from the signal path to the reference power supply only when a signal level appearing in the signal path exceeds the reference level. . The signal synthesis unit includes a first capacitor that holds the first voltage signal and a second capacitor that holds the second voltage signal;
The first voltage signal is transmitted from the signal generator to the first capacitor through a first signal path;
The second voltage signal is transmitted from the signal generation unit to the second capacitor through a second signal path,
The level limiter is
When the signal level appearing in the first signal path exceeds a first reference level equal to or less than a signal level corresponding to the maximum accumulation amount of the photodiode, the first signal path is A first reference power supply having a first reference level equal to or less than a signal level corresponding to the maximum accumulation amount of the diode;
When a signal level appearing in the second signal path exceeds a second reference level different from the first reference level, which is equal to or less than a signal level corresponding to the maximum accumulation amount of the photodiode, The second signal path is connected to a second reference power source having a second reference level different from the first reference level that is equal to or less than a signal level corresponding to the maximum accumulation amount of the photodiode. The solid-state imaging device according to claim 1. The signal generation unit includes a transfer transistor inserted in a signal path connecting the photodiode and the floating diffusion,
The level limiter is
An overflow drain that drains the charge generated by the photodiode;
The solid-state imaging device according to claim 1, wherein a barrier of the overflow drain is lower than a barrier when the transfer transistor is in an off state. The signal generator is
A current source that is inserted in a path connecting the first pole of the power supply and the output node, and generates a current according to the amount of charge generated by the photodiode;
A load resistor inserted in a path connecting the output node and the second pole of the power source,
The level limiter is
A comparison circuit that compares a signal level output from the output node with a reference level equal to or less than a signal level corresponding to the maximum accumulation amount of the photodiode;
A switch element inserted in a path connecting the output node and the second pole of the power source,
The switch element is turned off when the comparison result by the comparison circuit indicates that the signal level output from the output node exceeds the reference level, and the comparison result by the comparison circuit is output from the output node. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is turned on when the output signal level indicates that the reference level does not exceed the reference level. A camera equipped with a solid-state imaging device,
The solid-state imaging device includes a plurality of pixels,
Each pixel is
A photodiode that generates charge according to the intensity of incident light;
In one frame period, a first voltage signal is generated according to the amount of charge generated by the photodiode during the first exposure period, and a second length different from the first exposure period is generated by the photodiode. A signal generator that generates a second voltage signal in accordance with the amount of charge generated during the exposure period;
A signal synthesis unit that synthesizes the first and second voltage signals generated by the signal generation unit;
When the intensity of the incident light exceeds the maximum accumulation amount of the photodiode and generates a charge, the signal levels of the first and second voltage signals synthesized by the signal synthesis unit are A camera comprising: a level limiting unit that limits a signal level so as not to exceed a signal level corresponding to a maximum accumulation amount.

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