JP2008311454A - Layout designing method and layout designing program for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout designing method for a semiconductor integrated circuit in which a wiring occupation area is reduced and redundant via wiring rule violation places can be eliminated or reduced. <P>SOLUTION: The layout designing method makes preparations (second to twelfth steps) for making wiring corrections for eliminating a redundant via wiring rule violation place by changing the direction of a cell if a redundant via wiring rule is violated during detailed wiring (first steps), and then making the wiring corrections by changing the direction of the cell (thirteenth to fifteenth steps) and performing route update (sixteenth step). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for designing a layout of a semiconductor integrated circuit having a global routing process and a detailed routing process, and a semiconductor integrated circuit including a program for causing a computer to execute the schematic routing process and the detailed routing process. The present invention relates to a circuit layout design program.

  For example, in the layout design of a semiconductor integrated circuit by the standard cell method, the cell tends to be made as small as possible within the range of the design rule. For this reason, in the cell region, cell terminals to be connected to the wiring are densely packed, and there is a case in which a space usable for wiring is insufficient in the vicinity of the cell terminal, and a short circuit between wirings cannot be solved by automatic wiring.

  On the other hand, in order to improve reliability and product life at the time of wiring formation, instead of standard vias with a small occupied area, make a circuit using vias with a redundant structure with a large occupied area (so-called redundant vias). Is generalized. For this reason, it is more important to perform wiring near the cell terminals without waste and to reduce the wiring occupation area as much as possible.

  One of the causes of the increase in the area occupied by the wiring is that when there are multiple wirings that must be connected to the cell terminals in the same cell, those paths inefficiently occupy the wiring area near the cell terminals and interfere with each other. There are situations where it looks cool.

Here, in general, the wiring entry path and access direction to the cell terminal are assumed from the positional relationship between the cell terminals forming the connection section before actual wiring, and the cell arrangement direction is based on this assumed wiring. The detailed wiring is performed after the cell arrangement direction is determined. When a short circuit between wirings remains after detailed wiring, it is common to erase the peripheral wiring and execute a rewiring process to search for an alternative route to solve the short circuit between the wirings.
Japanese Patent Laid-Open No. 01-292472 JP 04-160684 A JP 09-319786 A Japanese Patent Laid-Open No. 60-062136

  However, when the short circuit between wiring remains after the detailed wiring, the conventional wiring short circuit solving method of solving the short circuit between wirings by erasing the peripheral wiring and executing the rewiring process to find the alternative route, The area occupied by the wiring near the cell terminals cannot be reduced, and in order to eliminate the short circuit between wirings, it is necessary to use standard vias, and it may be difficult to realize redundant via wiring. There was a problem.

  SUMMARY OF THE INVENTION In view of the above, the present invention has an object to provide a semiconductor integrated circuit layout design method and layout design program capable of reducing a wiring occupation area and eliminating or reducing redundant via wiring rule violation points. And

  The method for designing a layout of a semiconductor integrated circuit according to the present invention includes a schematic wiring process and a detailed wiring process, and after the detailed wiring process, the direction of the cell is changed to eliminate a redundant via wiring rule violation location. The wiring correction process is included.

  The layout design program for a semiconductor integrated circuit according to the present invention includes a program for causing a computer to execute a rough wiring process and a detailed wiring process, and after the detailed wiring process, the direction of the cell is changed to change the redundant via wiring rule. It includes a program for causing a computer to execute a wiring correction process for eliminating the violation portion.

  According to the semiconductor integrated circuit layout design method of the present invention, even if the redundant via wiring rule violation occurs in the detailed wiring process, the wiring correction process for changing the cell direction and eliminating the redundant via wiring rule violation portion Therefore, the wiring occupation area can be reduced and the redundant via wiring rule violation part can be eliminated or reduced.

  According to the semiconductor integrated circuit layout design program of the present invention, even if a redundant via wiring rule violation occurs in the detailed wiring process, the wiring correction process for changing the cell direction and eliminating the redundant via wiring rule violation portion Therefore, the wiring occupation area can be reduced, and the redundant via wiring rule violation location can be eliminated or reduced.

  FIG. 1 is a schematic configuration diagram of a part of a layout design apparatus for a semiconductor integrated circuit for carrying out an embodiment of a layout design method for a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram illustrating a layout design method for a semiconductor integrated circuit according to the present invention. FIG. 3 to FIG. 20 are layout diagrams for explaining a specific example of an embodiment of a layout design method for a semiconductor integrated circuit according to the present invention.

  As shown in FIG. 1, a semiconductor integrated circuit layout design apparatus for carrying out an embodiment of a semiconductor integrated circuit layout design method of the present invention comprises a detailed wiring means 1, a redundant via wiring rule violation location extracting means 2, Redundant via wiring rule violation location inclusion area definition means 3, wiring correction untrial area presence determination means 4, redundant via wiring rule violation location inclusion area selection means 5, wiring correction target area definition means 6, connection point / intersection Extraction means 7, intersection extraction means 8, first linear distance sum calculation means 9, cell flip means 10, second linear distance sum calculation means 11, linear distance sum comparison means 12, cell orientation A change unit 13, a wiring discard unit 14, a route re-search unit 15, and a route update unit 16 are included.

  One embodiment of the layout design method for a semiconductor integrated circuit according to the present invention is based on the standard cell method, and includes the first to sixteenth steps shown in FIG. Hereinafter, an embodiment of a layout design method for a semiconductor integrated circuit according to the present invention will be described step by step.

[First step]
In one embodiment of a method for designing a layout of a semiconductor integrated circuit according to the present invention, a detailed wiring means is firstly provided for a semiconductor integrated circuit subject to layout design in which cell arrangement and rough wiring for determining a rough route of signal wiring are executed. 1, the detailed wiring for determining the route pattern of the signal wiring is performed.

  Detailed wiring means 1 performs detailed wiring under the redundant via wiring rule using redundant vias as a rule, but if a short between wirings occurs due to the use of redundant vias, use standard vias as an exception. Thus, detailed wiring is performed so as to eliminate a short circuit between wirings.

  For example, FIG. 3 shows a part of an example of a wiring result when detailed wiring is executed under the redundant via wiring rule, and C1 is a cell frame of the cell of interest, 20-1, 20-2, 20-3, 21. Is a cell terminal provided in the first wiring layer, 22 is a wiring of the second wiring layer, 23-1, 23-2, 23-3, 24, 25 and 26 are wirings of the third wiring layer, and 27 to 34 are It is a redundant via.

  In this example, a double-cut via in which two cuts (via holes) are arranged in the vertical direction (Y-axis direction) or the horizontal direction (X-axis direction) is used as the redundant via. The redundant via in which the two cuts are arranged in the vertical direction is for connecting the wiring in the third wiring layer and the wiring in the second wiring layer, and the redundant via in which the two cuts are arranged in the horizontal direction is This is for connecting the wiring of the second wiring layer and the cell terminal of the third wiring layer.

  4 shows only the cell frame C1, the cell terminals 20-1, 20-2, 20-3, and 21 and the wirings 23-1, 23-2, 23-3, 24, 25, and 26 of the third wiring layer. FIG. 5 shows a state in which the wiring 22 of the second wiring layer and the redundant vias 27 to 31 are added to the layout diagram shown in FIG. FIG. 3 shows a state in which redundant vias 32, 33, and 34 are added to the layout diagram shown in FIG.

  In this example, the wiring 23-1 is connected to the cell terminal 20-1, the wiring 23-2 is connected to the cell terminal 20-2, and the wiring 23-3 is connected to the cell terminal 20-3. Yes. Although the wiring 24 is connected to the wiring 25, these wirings 24 and 25 are not connected to any of the cell terminals 20-1, 20-2, 20-3, and 21. The wiring 26 is not connected to any of the cell terminals 20-1, 20-2, 20-3, and 21.

  Here, if the redundant via wiring rule is applied without exception, the wiring 23-1 can be connected to the cell terminal 20-1 through the redundant vias 27 and 32 as shown in FIG. Then, a short circuit occurs between the wirings 23-1 and 23-2 through the redundant via 27. In addition, the wiring 23-2 can be connected to the cell terminal 20-2 via the redundant vias 28 and 33. In this case, the wiring 23-2 is connected between the wirings 23-1 and 23-2 via the redundant via 28. Short circuit will occur.

  In addition, the wiring 23-3 can be connected to the cell terminal 20-3 via the redundant vias 29 and 34. In this way, a short circuit with other wiring does not occur. In addition, the wiring 24 can be connected to the wiring 25 via the redundant via 30, the wiring 22 and the redundant via 31, but if this is done, a short circuit will occur between the wirings 24 and 23-2 via the redundant via 30. Will occur.

  Therefore, in such a case, the detailed wiring means 1 violates the redundant via wiring rule, and instead of the redundant vias 27, 28, and 30, as shown in FIG. The detailed wiring is performed so as to eliminate the short circuit between the wirings 23-1 and 23-2 and the short circuit between the wirings 24 and 23-2.

[Second step]
After the first step, the redundant via wiring rule violation location extraction means 2 performs a design rule check and extracts a location that uses the standard via in violation of the redundant via wiring rule as a redundant via wiring rule violation location. To do. If there is no redundant via wiring rule violation location, the third and subsequent steps are not performed.

  In the case as shown in FIG. 6, the locations using the standard vias 35, 36, and 37 are extracted as redundant via wiring rule violation locations P1, P2, and P3 as shown in FIG. 8 schematically shows the entire layout area, C1 to C18 are cell frames, P1 to P8 are redundant via wiring rule violation locations, C1 is the cell frame shown in FIG. 7, and P1, P2, and P3 are diagrams. The redundant via wiring rule violation location shown in FIG. 7 is extracted for the entire layout area in the second process.

[Third step]
Subsequent to the second step, redundant via wiring rule violation location inclusion area defining means 3 divides redundant via wiring rule violation locations into groups, and for each group, a rectangle containing redundant via wiring rule violation locations is redundant. It is defined as the via wiring rule violation location inclusion area.

  The redundant via wiring rule violation location inclusion area defining means 3 sets a mesh composed of vertical lines and horizontal lines at predetermined intervals in the layout area, and sets a small area divided by the vertical lines and horizontal lines of the mesh as a unit of grouping, Performs grouping of redundant via wiring rule violation locations. Note that the size of the small area divided by the vertical and horizontal lines of the mesh is, for example, about one time based on the average cell size, but is suitable for the size of the cell being arranged. It may be non-uniform to reflect the bias.

  When the redundant via wiring rule violation locations are as shown in FIG. 8, as shown in FIG. 9, the redundant via wiring rule violation locations P1, P2, and P3 are grouped together and the redundant via wiring rule violation locations P1, P2,. A rectangle including P3 is defined as a redundant via wiring rule violation location inclusion region R1. Further, the redundant via wiring rule violation places P4 and P5 are grouped, and a rectangle including the redundant via wiring rule violation places P4 and P5 is defined as a redundant via wiring rule violation place inclusion region R2.

  Further, the redundant via wiring rule violation places P6 and P7 are grouped, and a rectangle including the redundant via wiring rule violation places P6 and P7 is defined as a redundant via wiring rule violation place inclusion region R3. Further, the redundant via wiring rule violation location P8 is defined as one group, and a rectangle including the redundant via wiring rule violation location P8 is defined as a redundant via wiring rule violation location inclusion region R4. FIG. 10 is an enlarged view of the cell frame C1 and the redundant via wiring rule violation location inclusion region R1.

[Fourth step]
Next to the third step, the routing correction untrial area presence / absence determination means 4 determines whether or not there is a redundant via wiring rule violation location inclusion area for which wiring correction has not been attempted. If there is not, the process according to the embodiment of the semiconductor integrated circuit layout design method of the present invention is terminated.

[Fifth step]
In the fourth step, if it is determined that there is a redundant via wiring rule violation location inclusion area for which no wiring correction has been attempted, the redundant via wiring rule violation location inclusion area selection means 5 causes the redundant via wiring rule violation for which no wiring correction has been attempted. Select one of the location inclusion areas.

[Sixth step]
After the fifth step, the wiring correction target area defining means 6 selects one of the cell frames that overlaps the selected redundant via wiring rule violation location inclusion area, and selects the selected redundant via wiring rule violation location inclusion area and A region including the selected cell frame is defined as a wiring correction target region.

  In the state shown in FIG. 9 before the sixth step, as shown in FIG. 11, for example, the area including the redundant via wiring rule violation location inclusion area R1 and the cell frame C1 is set as the wiring correction target area. It is defined as A1. FIG. 12 is an enlarged view of a portion of the wiring correction target area A1. The size of the wiring correction target area A1 is set to allow for a margin in the minimum size area including the redundant via violation portion inclusion area R1 and the cell frame C1.

[Seventh step]
Next to the sixth step, the connection point / intersection extraction means 7 causes the intersection Si between the connection point Ti on the cell terminal in the wiring correction target area and the boundary of the wiring correction target area of the wiring to be connected to the connection point Ti. Is extracted and stored in the storage means.

  12 before the seventh step, as shown in FIG. 13, the connection point T1 on the cell terminal 20-1, the connection point T2 on the cell terminal 20-2, the cell terminal 20 -3, the intersection S1 of the boundary between the wiring 23-1 and the wiring correction target area A1, the intersection S2 of the wiring 23-2 and the boundary of the wiring correction target area A1, the wiring 23-3 and the wiring correction The intersection S3 with the boundary of the target area A1 is extracted and stored in the storage means.

[Eighth step]
After the seventh step, the intersection point extraction means 8 uses the intersection Pi between the wiring not connected to the cell terminal in the wiring correction target area, the wiring not connected to the cell terminal in the wiring correction target area, and the wiring correction target area. The intersection point Qi with the boundary is extracted and stored in the storage means.

  In the case shown in FIG. 13 before the eighth step, as shown in FIG. 14, the intersection P1 between the wiring 24 and the boundary of the wiring correction target area A1, the wiring 25 and the wiring correction target area A1 The intersection point Q1 with the boundary is extracted and stored in the storage means.

[Ninth step]
After the eighth step, the first linear distance sum calculation means 9 calculates the linear distance sum Σ (the linear distance between SiTi) between the connection point Ti and the intersection point Si as the first linear distance sum Lorg. 14 before the ninth step, as shown in FIG. 15, the sum of linear distances Lorg = Lorg1 (straight distance between S1T1) + Lorg2 (straight distance between S2T2) + Lorg3 (between S3T3) Linear distance).

[Tenth step]
After the ninth step, the cell flip means 10 flips the cells in the wiring correction target region, that is, horizontally flips or vertically flips.

[Eleventh step]
Following the tenth step, the second linear distance sum calculation means 11 calculates the linear distance sum Σ (the linear distance between SiTi) between the connection point Ti and the intersection Si as the second linear distance sum Lflip.

  FIG. 16 shows connection points T1, T2, T3 and intersections S1, S2, S3, P1, Q1 when the cell in the cell frame C1 is reversed left and right. In this case, the linear distance sum Lflip = Lflip1 (Linear distance between S1T1) + Lflip2 (Linear distance between S2T2) + Lflip3 (Linear distance between S3T3).

[12th step]
Following the eleventh step, the first straight distance sum Lorg and the second straight distance sum Lflip are compared by the straight distance sum comparison / determination means 12, and the second straight distance sum Lflip <the first straight distance sum. It is determined whether or not it is Lorg. Here, if it is determined that the second straight line distance sum Lflip <the first straight line distance sum Lorg, the 14th process described later is executed.

[13th step]
If it is determined in the twelfth step that the second straight line distance sum Lflip <the first straight line distance sum Lorg, the cell orientation changing means 13 changes the cell orientation to the state flipped in the tenth step. . If it is determined in the twelfth step that the second straight line distance sum Lflip ≧ the first straight line distance sum Lorg, the thirteenth step is skipped and the process proceeds to the fourteenth step without changing the cell direction.

[14th step]
If it is determined that the second straight line distance sum Lflip ≧ the first straight line distance sum Lorg in the twelfth process or in the twelfth process, the process proceeds to the fourteenth process and the wiring discarding unit 14 Discard the wiring in the wiring correction target area.

  FIG. 17 shows the state shown in FIG. 14 after the execution of the eighth step, and when it is determined in the twelfth step that the second linear distance sum Lflip <the first linear distance sum Lorg, The cell orientation is changed to a state where the left and right cells are reversed, and the wiring in the wiring correction target area A1 is discarded.

[15th step]
Following the 14th step, the route re-search means 15 sequentially re-searches the route between the connection point Ti and the intersection point Si and the route between the intersection point Pi and the intersection point Qi.

  FIG. 19 shows the result of re-searching the path between the connection point T1 and the intersection point S1, the path between the connection point T2 and the intersection point S2, and the path between the connection point T3 and the intersection point S3. 18 shows a state in which redundant vias 40, 41, 42 are added to the layout diagram shown in FIG. 17, and FIG. 19 shows a state in which redundant vias 43, 44, 45 are added to the layout diagram shown in FIG.

  Here, the wiring 23-1 is connected to the cell terminal 20-1 through the redundant vias 40 and 43, and the short circuit between the wirings 23-1 and 23-2 due to the redundant via 27 shown in FIG. 3 is eliminated. The standard via 35 as shown in FIG. 6 is not required.

  Also, the wiring 23-2 is connected to the cell terminal 20-2 via the redundant vias 41 and 44, and the short circuit between the wirings 23-1 and 23-2 due to the redundant via 28 shown in FIG. Nor is the standard via 36 as shown in FIG.

  Further, the wiring 23-3 is connected to the cell terminal 20-3 via the redundant vias 42 and 45, and no short circuit with other signal wirings occurs. In the case of this example, a region 46 in which redundant via wiring is provided for the path between the intersection P1 and the intersection Q1 is created.

  FIG. 20 shows a state in which a route between the intersection P1 and the intersection Q1 is searched again, and redundant vias 47 and 48 and the wiring 49 of the second wiring layer are added to the layout diagram shown in FIG. In this example, the wiring 24 is connected to the wiring 25 through the redundant via 47, the wiring 49, and the redundant via 48, and the short circuit between the signal wirings 24 and 23-2 shown in FIG. The standard via 37 as shown in FIG.

  As a result of the route re-search, the violation of the redundant via wiring rule cannot be completely eliminated and the standard via must be used. In the 15th step, this is accepted. To do.

[Step 16]
Following the fifteenth step, the route is updated by the route update means 16. In the case of the specific example shown in FIG. 6, the route shown in FIG. 20 is updated as a new route. Thereafter, the fifth to sixteenth steps are repeated until there is no redundant via wiring rule violation location inclusion region for which wiring correction has not been attempted.

  As described above, in one embodiment of the layout design method for a semiconductor integrated circuit according to the present invention, for a semiconductor integrated circuit to be designed for layout in which cell arrangement and schematic wiring are executed, first, the details of determining the route pattern of the signal wiring Wiring is performed (first step). Next, a design rule check is performed, and a location where the standard via is used in violation of the redundant via wiring rule is extracted as a redundant via wiring rule violation location (second step).

  Next, the redundant via wiring rule violation locations are grouped, and for each group, a rectangle including the redundant via wiring rule violation location in the group is defined as a redundant via wiring rule violation location inclusion region (third step). Next, it is determined whether or not there is a redundant via wiring rule violation location inclusion area for which wiring correction has not been attempted (step 4). If there is no redundant via wiring rule violation location inclusion area for which wiring correction has not been attempted, the semiconductor of the present invention The processing according to the embodiment of the integrated circuit layout design method is ended.

  In the fourth step, when it is determined that there is a redundant via wiring rule violation location inclusion area for which no wiring correction has been attempted, one of the redundant via wiring rule violation location inclusion areas for which wiring correction has not been attempted is selected (fifth step). ). Next, one of the cell frames that overlaps with the selected redundant via wiring rule violation location inclusion area is selected, and an area that includes the selected redundant via wiring rule violation location inclusion area and the selected cell frame is selected. It is defined as a wiring correction target area (sixth step).

  Next, the intersection Si between the connection point Ti and the boundary of the wiring correction target region of the wiring to be connected to the connection point Ti is extracted and stored (seventh step). Next, the intersection Pi between the wiring not connected to the cell terminal in the wiring correction target area and the intersection Qi between the wiring not connected to the cell terminal in the wiring correction target area and the boundary of the wiring correction target area are extracted and stored. (Eighth step). Next, the sum of the straight line distances between the connection point Ti and the intersection point Si is calculated as the first straight line distance sum Lorg (9th step).

  Next, the cells in the wiring correction target region are flipped (tenth process). Next, the sum of the straight line distances between the connection point Ti and the intersection point Si is calculated as a second straight line distance sum Lflip (11th step). Next, the first linear distance sum Lorg and the second linear distance sum Lflip are compared to determine whether or not Lflip <Lorg (step 12). If Lflip <Lorg is not satisfied, a 14th step described later is executed.

  In the twelfth step, if Lflip <Lorg, the cell orientation is changed to the flipped state (the thirteenth step). Next, regardless of whether the direction of the cell has been changed, the wiring in the wiring correction target area is discarded (14th step). Next, a search is again performed for a route between the connection point Ti and the intersection point Si and between the intersection point Pi and the intersection point Qi (15th step). Next, the route is updated (step 16). Thereafter, the fifth to sixteenth steps are repeated until there is no redundant via wiring rule violation location inclusion region for which wiring correction has not been attempted.

  FIG. 21 is a conceptual diagram of a computer constituting the layout design apparatus for the semiconductor integrated circuit shown in FIG. In FIG. 21, 51 is a central processing unit (CPU), 52 is a main memory composed of random access memory (RAM), 53 is an input device such as a keyboard or mouse, 54 is an output device such as a display or printer, and 55 is a communication device. 56 are auxiliary memories such as a hard disk drive. The auxiliary memory 56 stores an embodiment 57 of a layout design program for a semiconductor integrated circuit according to the present invention.

  An embodiment 57 of a semiconductor integrated circuit layout design program according to the present invention includes a detailed wiring program 58, a redundant via wiring rule violation location extraction program 59, a redundant via wiring rule violation location inclusion area definition program 60, and a wiring correction untrial area. Judgment program 61, redundant via wiring rule violation location inclusion region selection program 62, wiring correction target region definition program 63, connection point / intersection extraction program 64, intersection extraction program 65, first linear distance sum calculation program 66, cell flip A program 67, a second straight line distance sum calculation program 68, a straight line distance sum comparison program 69, a cell direction change program 70, a wiring discard program 71, a route re-search program 72, and a route update program 73 are included.

  The detailed wiring program 58 causes the CPU 51 to function as the detailed wiring unit 1 and execute the first step. The redundant via wiring rule violation location extraction program 59 causes the CPU 51 to function as the redundant via wiring rule violation location extraction means 2 to execute the second step. The redundant via wiring rule violation location inclusion area definition program 60 causes the CPU 51 to function as the redundant via wiring rule violation location inclusion area definition means 3 to execute the third step.

  The wiring correction untrial area presence / absence determination program 61 causes the CPU 51 to function as the wiring correction untrial area determination means 4 to execute the fourth step. The redundant via wiring rule violation location inclusion area selection program 62 causes the CPU 51 to function as the redundant via wiring rule violation location inclusion area selection means 5 and execute the fifth step. The wiring correction target area definition program 63 causes the CPU 51 to function as the wiring correction target area definition means 6 and execute the sixth step.

  The connection point / intersection extraction program 64 causes the CPU 51 to function as the connection point / intersection extraction means 7 to execute the seventh step. The intersection extraction program 65 causes the CPU 51 to function as the intersection extraction means 8 to execute the eighth step. The first straight-line distance sum calculation program 66 causes the CPU 51 to function as the first straight-line distance sum calculation means 9 and execute the ninth step.

  The cell flip program 67 causes the CPU 51 to function as the cell flip means 10 and execute the tenth step. The second straight line distance sum calculation program 68 causes the CPU 51 to function as the second straight line distance sum calculation means 11 and execute the eleventh step. The linear distance sum comparison program 69 causes the CPU 51 to function as the linear distance sum comparison means 12 to execute the twelfth step.

  The cell orientation changing program 70 causes the CPU 51 to function as the cell orientation changing means 13 and execute the thirteenth step. The wiring discard program 71 causes the CPU 51 to function as the wiring discarding unit 14 and execute the fourteenth step. The route re-search program 72 causes the CPU 51 to function as the route re-search means 15 and execute the fifteenth step. The route update program 73 causes the CPU 51 to function as the route update means 16 and execute the sixteenth step.

  According to one embodiment of the semiconductor integrated circuit layout design method of the present invention, even if a redundant via wiring rule violation occurs in the detailed wiring (first step), the direction of the cell is changed to change the redundant via wiring rule violation portion. Preparation process (second process to twelfth process) for correcting the wiring to eliminate the problem, a process of correcting the wiring by changing the cell direction (13th to 15th processes), and a process of updating the route ( Since the sixteenth step) is prepared, the wiring occupation area can be reduced, and the redundant via wiring rule violation location can be eliminated or reduced.

  According to one embodiment of the semiconductor integrated circuit layout design program of the present invention, it is possible to cause a computer to execute one embodiment of the semiconductor integrated circuit layout design method of the present invention.

1 is a schematic configuration diagram of a part of a semiconductor integrated circuit layout design apparatus for carrying out an embodiment of a semiconductor integrated circuit layout design method of the present invention; FIG. 3 is a flowchart showing an embodiment of a layout design method for a semiconductor integrated circuit according to the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a layout diagram for explaining a specific example of an embodiment of a layout design method of a semiconductor integrated circuit of the present invention. It is a conceptual diagram of the computer which makes the layout design apparatus of the semiconductor integrated circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Detailed wiring means 2 ... Redundant via wiring rule violation location extraction means 3 ... Redundant via wiring rule violation location inclusion area definition means 4 ... Wiring correction untrial area existence judgment means 5 ... Redundant via wiring rule violation location inclusion area selection means 6 ... Wiring correction target area definition means 7... Connection point / intersection point extraction means 8... Intersection point extraction means 9... First linear distance sum calculation means 10 ... Cell flip means 11 ... Second linear distance sum calculation means 12. Sum comparing means 13 ... Cell orientation changing means 14 ... Wiring discarding means 15 ... Path re-search means 16 ... Path updating means C1-C18 ... Cell frames 20-1 to 20-3, 21 ... Cells provided in the first wiring layer Terminal 22 ... Wiring of second wiring layer 23-1 to 23-3, 24-26 ... Wiring of third wiring layer 27-34 ... Redundant via 35-37 ... Standard via P1-P8 ... Redundant via wiring rule violation Location 40-45 ... Redundant via 51 ... CPU
DESCRIPTION OF SYMBOLS 52 ... Main memory 53 ... Input device 54 ... Output device 55 ... Communication apparatus 56 ... Auxiliary memory 57 ... One Embodiment of the layout design program of the semiconductor integrated circuit of this invention 58 ... Detailed wiring program 59 ... Redundant via wiring rule violation location extraction Program 60 ... Redundant via wiring rule violation location inclusion area definition program 61 ... Wiring correction untrial area presence determination program 62 ... Redundant via wiring rule violation location inclusion area selection program 63 ... Routing correction target area definition program 64 ... Connection point / intersection extraction Program 65 ... Intersection extraction program 66 ... First linear distance sum calculation program 67 ... Cell flip program 68 ... Second linear distance sum calculation program 69 ... Linear distance sum comparison program 70 ... Cell orientation change program 71 ... Wiring discard Program 72 ... Route re-search Program 73 ... route update program

Claims (6)

A layout design method for a semiconductor integrated circuit having a schematic wiring process and a detailed wiring process,
A layout design method for a semiconductor integrated circuit, comprising a wiring correction process for changing a cell direction and eliminating a redundant via wiring rule violation part after the detailed wiring process. The wiring correction step includes
Grouping the redundant via wiring rule violation locations into groups and defining a region including the redundant via wiring rule violation locations in the group as a first region;
Defining a region including the first region and one of the cell frames overlapping with the first region as a second region;
The layout design method for a semiconductor integrated circuit according to claim 1, further comprising a step of correcting a wiring by changing a direction of a cell in the second region. The step of correcting the wiring by changing the direction of the cells in the second region,
Calculating a sum of linear distances between a connection point on the cell terminal in the second region and an intersection of the boundary of the second region of the wiring to be connected to the connection point as a first sum of linear distances When,
Flipping the orientation of cells in the second region and calculating a sum of linear distances between the connection point and the intersection as a second linear distance sum;
When the second straight line distance sum is smaller than the first straight line distance sum, changing the cell orientation in the second region to a flipped state;
3. The method according to claim 2, further comprising: discarding the wiring in the second region, re-searching the wiring path between the connection point and the intersection, and updating the wiring path. Integrated circuit layout design method. A layout design program for a semiconductor integrated circuit including a program for causing a computer to execute a schematic wiring process and a detailed wiring process,
A layout design program for a semiconductor integrated circuit, comprising: a program for causing a computer to execute a wiring correction process for changing a cell direction and eliminating a redundant via wiring rule violation location after the detailed wiring process. The wiring correction step includes
Grouping the redundant via wiring rule violation locations into groups and defining a region including the redundant via wiring rule violation locations in the group as a first region;
Defining a region including the first region and one of the cell frames overlapping with the first region as a second region;
5. The layout design program for a semiconductor integrated circuit according to claim 4, further comprising a step of correcting a wiring by changing a direction of a cell in the second region. The step of correcting the wiring by changing the direction of the cells in the second region,
Calculating a sum of linear distances between a connection point on the cell terminal in the second region and an intersection of the boundary of the second region of the wiring to be connected to the connection point as a first sum of linear distances When,
Flipping the orientation of cells in the second region and calculating a sum of linear distances between the connection point and the intersection as a second linear distance sum;
When the second straight line distance sum is smaller than the first straight line distance sum, changing the cell orientation in the second region to a flipped state;
6. The method according to claim 5, further comprising: discarding the wiring in the second region, re-searching a wiring path between the connection point and the intersection, and updating the wiring path. Integrated circuit layout design program.

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