JP2008310894A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can reduce a processing time and a CPU load with a simple configuration for setting configuration information necessary for a normal operation of a non-volatile memory in starting up the power supply. <P>SOLUTION: The semiconductor storage device includes: a volatile semiconductor storage device 20 having a volatile mode register for storing configuration information necessary for executing the normal operation to a first volatile storage area 21; and a non-volatile semiconductor memory 10 having a second non-volatile data storage area 12 and a non-volatile configuration information storage area for storing the configuration information. The non-volatile semiconductor storage device 10 includes: a means 30 for detecting a start-up of the power supply; and a means 13 for automatically transmitting the configuration information to the volatile semiconductor device 20 before the normal operation when the power supply is started up. While the volatile semiconductor device 20 includes a means for receiving the configuration information from the non-volatile semiconductor device 10 to store it in the mode register before executing the normal operation after the power supply is started up. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and in particular, a function for setting setting information for a volatile memory that needs to set setting information necessary for executing normal operation in a mode register before executing normal operation. The present invention relates to a semiconductor memory device having

  Embedded in volatile memories such as SDRAM (Synchronous Dynamic Random Access Memory) that operates in synchronization with an external clock, and pseudo-SRAM having a DRAM structure memory cell and SRAM (Static Random Access Memory) control circuit Some perform normal operations such as read processing and write processing using the setting information set in the mode register.

  Specifically, for example, as setting information of the SDRAM, when setting a burst mode in which a plurality of unit data is continuously transferred with one command, the data length of the read data in the read process and the write data in the write process are set. Indicates the burst length indicating the data length and the time taken from the input of the read (read) command instructing the read process or the write (write) command instructing the write process to the actual execution of the data read or write process There is latency. The setting information of the pseudo SRAM having the burst mode includes, for example, a burst length and latency. The setting information of the pseudo SRAM not having the burst mode includes, for example, a storage area range in which the refresh operation is performed in the partial refresh process in which the refresh operation is performed only on a part of the storage areas in the standby mode.

  By the way, volatile memories such as SDRAM and pseudo-SRAM cannot normally hold data when power supply is stopped. For this reason, when the power supply is stopped, the setting information stored in the mode register is lost. Therefore, in a conventional volatile semiconductor memory device including a volatile memory that performs normal operation using setting information, it is necessary to execute an initial setting process for writing setting information to the mode register every time the power is turned on. Also, in such a volatile semiconductor memory device, normal operation becomes possible after setting information is set in the mode register. Therefore, after the power is turned on, a command for instructing normal operation from a CPU (Central Processing Unit) is issued. Before it is issued, it is necessary to complete the initial setting process for writing the setting information to the mode register.

  Hereinafter, a conventional volatile semiconductor memory device including a volatile memory that performs normal operation using setting information will be briefly described with reference to FIGS.

  First, the configuration of a conventional volatile semiconductor memory device will be briefly described with reference to FIG. Here, FIG. 5 shows a schematic connection configuration example with the CPU 200 in the volatile semiconductor memory device 100 according to the prior art. As shown in FIG. 5, the volatile semiconductor memory device 100 according to the prior art is connected so as to be able to accept a command input from the CPU 200, and performs an initial setting process for setting a mode register, a read process, a write process, and the like. It is configured to be able to execute normal operations.

  Next, a processing procedure of the conventional volatile semiconductor memory device 100 will be briefly described with reference to FIGS. Here, FIG. 6 shows a processing procedure of an initial setting process in the volatile semiconductor memory device 100 according to the conventional technique, and FIG. 7 shows a clock signal CLK and a mode register in the volatile semiconductor memory device 100 according to the conventional technique. Shows an example of a waveform of a command MRS for instructing the setting of the command CMD and a command CMD for instructing a predetermined normal operation.

  As shown in FIGS. 6 and 7, in the volatile semiconductor memory device 100, after the power is turned on, first, in an initial setting process, the CPU 200 issues a command MRS (step # 201), and the volatile semiconductor memory device 100 In response to the issue of the command MRS, the setting information is written in the mode register (step # 211). After completing the setting of the mode register, the CPU 200 issues a command CMD such as a read command or a write command (step # 202), and the volatile semiconductor memory device 100 executes a normal operation based on these commands CMD (step # 202). # 212).

  FIG. 8 shows an example of the composite semiconductor memory device 300 including the nonvolatile memory 110 on the same semiconductor substrate, in addition to the RAM 120 as an example of a volatile memory that performs normal operation using setting information. . As shown in FIG. 8, the composite semiconductor memory device 300 includes a RAM 120 including a mode register 120 for storing setting information and a nonvolatile memory 110, and an initial setting process or the like by command input from an external CPU 200, A normal operation such as a write process and a read process is executed.

  However, as described above, the conventional semiconductor memory device that executes the initial setting process for writing the setting information to the volatile mode register every time the power is turned on has a problem that the CPU is loaded for the initial setting process. It was.

  The technology related to the initial setting processing of the semiconductor memory device includes, for example, a semiconductor in which a ferroelectric nonvolatile memory is formed on the same semiconductor substrate separately from the volatile memory, and the nonvolatile memory is used as a mode register. There is a storage device (see, for example, Patent Document 1).

  This semiconductor memory device uses a non-volatile memory that can hold data when power supply is stopped as a mode register, thereby reducing the load on the CPU for writing setting information to the mode register during the initial setting process. Yes.

  Hereinafter, the semiconductor memory device described in Patent Document 1 will be briefly described with reference to FIGS. First, the configuration of the semiconductor memory device 400 described in Patent Document 1 will be briefly described with reference to FIG. Here, FIG. 9 shows a schematic configuration example of the semiconductor memory device 400.

  As shown in FIG. 9, the semiconductor memory device 400 includes a DRAM 430 as an example of a volatile memory, a mode register 410 composed of a ferroelectric nonvolatile memory, and a memory that controls operations of the DRAM 430 and the mode register 410. And a control circuit 420.

  Next, a processing procedure of the semiconductor memory device described in Patent Document 1 will be briefly described with reference to FIGS. Here, FIG. 10 shows a processing procedure of initial setting processing of the volatile memory in the semiconductor memory device 400, and FIG. 11 shows a command MRS for instructing setting of the clock signal CLK and the mode register in the semiconductor memory device 400. An example of a waveform of a command CMD instructing a predetermined normal operation is shown.

  As shown in FIGS. 10 and 11, in the semiconductor memory device 400, after the power is turned on, an external CPU issues a command CMD such as a read command or a write command without issuing a command MRS (step # 301). ), The semiconductor memory device 400 executes a normal operation based on these commands CMD (step # 311).

  Since the semiconductor memory device 400 uses a ferroelectric nonvolatile memory as the mode register 410, setting information is not lost even when power supply is stopped. For this reason, it is not necessary to execute the initial setting process for writing the setting information at the time of the initial setting, and it is possible to reduce the labor and time required for the setting information writing process, the load on the CPU, and the like. No need to build.

JP 2004-311002 A JP 2005-301739 A

  However, in the semiconductor memory device described in Patent Document 1, a volatile memory such as a DRAM 430 and a ferroelectric nonvolatile memory that needs to be formed in a process different from the volatile memory on the same semiconductor substrate ( Therefore, the process control in the manufacturing process becomes complicated and difficult.

  Specifically, in the semiconductor memory device 400 described in Patent Document 1, a ferroelectric material which is a thin film having a high dielectric constant is used as a capacitor such as a DRAM in order to form a ferroelectric nonvolatile memory. Yes. The ferroelectric can set the direction of spontaneous polarization by applying a voltage, and can maintain the direction of polarization even when power supply is stopped. By using such characteristics, the ferroelectric can be used as a capacitor such as a DRAM.

  However, if a ferroelectric thin film is used for forming a capacitor of a memory cell constituting a nonvolatile memory such as a DRAM, it is difficult to increase the degree of integration of the DRAM. Furthermore, formation of a nonvolatile memory using a ferroelectric requires advanced process control technology. For this reason, there is a possibility that it will be put to practical use in applications such as a mode register in the future, but at present, the nonvolatile memory using a ferroelectric thin film as a capacitor is the same as other volatile memories such as SDRAM. It is very difficult to form on a semiconductor substrate, which is not realistic. Further, in a process that is currently in practical use, in order to form a non-volatile memory other than the above-described non-volatile memory using a ferroelectric material on the same semiconductor substrate as another volatile memory such as an SDRAM, Since it requires a more advanced process technology than the case of using a ferroelectric, it is not practical.

  The present invention has been made in view of the above problems, and its purpose is to execute setting of setting information required for normal operation of a volatile memory with a simple configuration when power is turned on. The object is to provide a semiconductor memory device capable of reducing time and CPU load.

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a first data storage area composed of a volatile memory for storing predetermined data, and setting information necessary for executing a normal operation on the first data storage area. A volatile semiconductor memory device including a volatile mode register for storing data, a second data storage area including a nonvolatile memory for storing predetermined data, and execution of the normal operation of the volatile semiconductor memory device A non-volatile semiconductor memory device comprising a non-volatile setting information storage area having the setting information necessary for the non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device detects power-up A power-on detection means; and after the power-on, before the normal operation on the first data storage area of the volatile semiconductor memory device, Setting information sending means for automatically sending the setting information stored in the setting information storage area to the body storage device, and the volatile semiconductor memory device is configured to provide the first information after the power is turned on. Before the execution of the normal operation for the data area, the first configuration is configured to include setting information storage means for receiving the setting information from the nonvolatile semiconductor memory device and storing the received setting information in the mode register. It is characterized by.

  The semiconductor memory device according to the present invention having the above characteristics is characterized in that the nonvolatile semiconductor memory device includes a dedicated data output terminal for sending the setting information to the volatile semiconductor memory device. The setting information sending means sends out the setting information via the data output terminal, and the volatile semiconductor memory device has a dedicated data input terminal for receiving the setting information from the nonvolatile semiconductor memory device. The setting information storage means of the volatile semiconductor memory device receives the setting information via the data input terminal, and the data output terminal of the nonvolatile semiconductor memory device and the data of the volatile semiconductor memory device A second feature is that the data input terminals are connected by a dedicated data line.

  The semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the volatile semiconductor memory device and the nonvolatile semiconductor memory device are configured in the same package.

  The semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the package is a stack package.

  In order to achieve the above object, a volatile semiconductor memory device according to the present invention is necessary for executing a normal operation for a first data storage area composed of a volatile memory for storing predetermined data and the first data storage area. A volatile semiconductor memory device comprising a volatile mode register for storing setting information, and after the power is turned on, before the normal operation is performed on the first data storage area, It further comprises setting information storage means for receiving the setting information from an external nonvolatile semiconductor memory device having setting information sending means for automatically sending setting information, and storing the received setting information in the mode register. One feature.

  The volatile semiconductor memory device according to the present invention having the above characteristics includes a dedicated data input terminal for connecting the mode register and the nonvolatile semiconductor memory device and receiving the setting information from the nonvolatile semiconductor memory device, A second feature is that the setting information storage means receives the setting information via the data input terminal.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a second data storage area comprising a nonvolatile memory for storing predetermined data, and the volatile semiconductor memory device having the fifth or sixth characteristics. A non-volatile setting information storage area having the setting information necessary for execution of the normal operation of the non-volatile semiconductor memory device, a power-on detection means for detecting power-on, and the power-on Thereafter, the setting information stored in the setting information storage area is automatically sent to the volatile semiconductor storage device before the normal operation for the first data storage area of the volatile semiconductor storage device. An information sending means is a first feature.

  A non-volatile semiconductor memory device according to the present invention having the above characteristics is provided for connecting the mode register of the volatile semiconductor memory device and the setting information storage area and transmitting the setting information to the volatile semiconductor memory device. A second feature is that a dedicated data output terminal is provided, and the setting information sending means sends the setting information through the data output terminal.

  According to the semiconductor memory device having the above characteristics, the setting information necessary for the normal operation of the volatile semiconductor memory device is stored in the nonvolatile setting information storage area of the nonvolatile semiconductor memory device. Therefore, since the setting information is transferred from the nonvolatile semiconductor memory device to the volatile semiconductor memory device and stored in the volatile mode register of the volatile semiconductor memory device, the volatile semiconductor memory device is received from an external user by an external address. Based on an accessible general-purpose volatile semiconductor memory device, it can be configured with only simple changes. Similarly, a non-volatile semiconductor memory device can be configured based on a general-purpose non-volatile semiconductor memory device accessible from an external user by an external address. In addition, it can be configured with only simple changes such as adding a power-on detection means and setting information sending means. That is, according to the semiconductor memory device having the above characteristics, a special manufacturing process is not separately used as in the conventional semiconductor memory device in which both the volatile memory and the nonvolatile memory are formed on the same semiconductor substrate. The volatile semiconductor memory device can be manufactured by a normal volatile memory process, and the non-volatile semiconductor memory device can be manufactured by a normal non-volatile memory process different from the volatile memory process.

  Further, according to the semiconductor memory device having the above characteristics, the configuration information is automatically transferred from the nonvolatile semiconductor memory device to the volatile semiconductor memory device when the power is turned on. It is not necessary to execute the initial setting process for writing to the volatile mode register, and the load on the CPU can be reduced. Further, according to the semiconductor memory device having the above characteristics, since the mode register is automatically set, it is not necessary to provide a program for executing the setting of the volatile mode register, and the configuration of the semiconductor memory device is simplified. It becomes possible to become.

  Similarly, in the nonvolatile semiconductor memory device having the above characteristics and the volatile semiconductor memory device having the above characteristics, as described above, the volatile semiconductor memory device is used for a normal volatile memory as in the semiconductor memory device having the above characteristics. The nonvolatile semiconductor memory device can be manufactured by a normal nonvolatile memory process different from the volatile memory process. Furthermore, the load on the external CPU can be reduced, and it is not necessary to create a program for setting the volatile mode register, and it is not necessary to secure a storage area for the program.

  Further, according to the semiconductor memory device of the second feature, since the dedicated data input terminal, data output terminal and data line are provided for transferring the setting information, the setting information can be written to the mode register. During the initial setting process, the volatile semiconductor memory device does not occupy a data line or the like used in normal operation. Similarly, in the volatile semiconductor memory device having the second feature and the nonvolatile semiconductor memory device having the second feature, the normal operation is performed in the volatile semiconductor memory device during the initial setting process of writing the setting information to the mode register. The data line used in is not occupied.

  According to the semiconductor memory device having the third and fourth characteristics, the volatile semiconductor memory device and the non-volatile semiconductor memory device are configured in the same package, and thus the volatile semiconductor memory device manufactured by different processes. The nonvolatile semiconductor memory device can be manufactured without using a special process.

  Hereinafter, embodiments of a semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention”), a volatile semiconductor memory device, and a nonvolatile semiconductor memory device will be described with reference to the drawings.

  First, the configuration of the device of the present invention in this embodiment will be described with reference to FIGS. 1 and 2. Here, FIG. 1 shows a schematic configuration example of a part related to the initial setting of the device 1 of the present invention, and FIG. 2 shows a nonvolatile semiconductor memory device 10 and a volatile semiconductor memory device 20 constituting the device 1 of the present invention. The connection configuration is shown.

  As shown in FIG. 1, the device 1 of the present invention stores a first data storage area 21 composed of a volatile memory for storing predetermined data, and setting information necessary for executing a normal operation for the first data storage area 21. A volatile semiconductor memory device 20 including a volatile mode register 22 for performing the operation, a second data storage area 12 including a nonvolatile memory for storing predetermined data, and execution of a normal operation of the volatile semiconductor memory device 20 The nonvolatile semiconductor memory device 10 includes a nonvolatile mode register (corresponding to a setting information storage area) 11 having necessary setting information. The first data storage area 21 of the volatile semiconductor storage device 20 and the second data storage area 12 of the nonvolatile semiconductor storage device 10 are accessible by an external address and are configured to be used by the user. Has been.

  In the present embodiment, the device 1 of the present invention is manufactured using a stack type package in which a plurality of LSI chips including the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10 are stacked and mounted in the same package. The case is assumed.

  Further, as shown in FIGS. 1 and 2, the inventive device 1 of the present embodiment is configured to transmit setting information between the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10 inside the device. A dedicated data line 40 is provided. Although FIG. 1 illustrates the case where the data line 40 is configured to be capable of simultaneously transmitting bits for a unit word, the present invention is not limited to this, and the data line 40 is a 1-bit data line for transmitting serial data. There may be.

  Further, as shown in FIG. 2, the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10 are provided with a clock signal CLK, a chip select signal CS, a write enable signal WE, or an output enable signal for use by the user. The signal OE, the address signal A, and the data signal D are received. The address signal A and the data signal D are input using a common data line in the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10. It is configured to be.

  The non-volatile semiconductor memory device 10 includes a power-on circuit 30 (corresponding to a power-on detection means) that detects power-on, and after normal power-up before the first data storage area 21 of the volatile semiconductor memory device. Further, setting information sending means 13 for automatically sending the setting information stored in the mode register 11 to the volatile semiconductor memory device 20 and a dedicated information for sending the setting information to the volatile semiconductor memory device 20. A data output terminal 14 is provided. In this embodiment, the setting information sending means 13 is configured to send setting information via the data output terminal 14 and the dedicated data line 40.

  In this embodiment, when the power-on circuit 30 detects the power-on, the power-on circuit 30 detects an H level detection pulse having a pulse width of a time required to write setting information to the mode register 22 in the volatile semiconductor memory device 20 described later. And an L level signal is output except when the power is turned on.

  The setting information sending means 13 outputs a buffer circuit Bi (i = 1 to n) for amplifying an output signal from the mode register 11 and a detection pulse from the power-on circuit 30 for each output bit of the mode register 11. A transfer gate circuit Gi for controlling availability is provided. More specifically, the transfer gate circuit Gi is turned on when an H level detection pulse is output from the power-on circuit 30, and outputs the output of the mode register to the volatile semiconductor memory device 20. The transfer gate circuit Gi is turned on only during the H level period of the detection pulse, and is turned off during other periods. When the transfer gate circuit Gi is in the OFF state, the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10 are electrically separated.

  The volatile semiconductor memory device 20 receives setting information from the nonvolatile semiconductor memory device 10 and stores the received setting information in a mode register before the normal operation on the first data area is performed after the power is turned on. Means (not shown) and a dedicated data input terminal 23 for receiving setting information from the nonvolatile semiconductor memory device 10. In the present embodiment, the setting information storage means is configured to receive setting information via the data input terminal 23 and the dedicated data line 40.

  As shown in FIG. 1, since the nonvolatile semiconductor memory device 10 provided for use by the user includes the nonvolatile mode register 11 and the setting information sending means 13 and the like, the nonvolatile semiconductor memory device 10 The non-volatile memory can be manufactured by using this manufacturing process. Similarly, since the volatile mode register 22 is configured in the volatile semiconductor memory device 20 provided for use by the user, the volatile semiconductor memory device 20 is manufactured using a normal volatile memory manufacturing process. Can do. That is, the device 1 of the present invention can be manufactured using a normal manufacturing process without using a special manufacturing process.

  Next, the processing procedure of the initial setting process in the device 1 of the present embodiment of the present embodiment will be described with reference to FIGS. Here, FIG. 3 shows the processing procedure of the initial setting process of the device 1 of the present invention, and FIG. 4 shows the clock signal CLK of the device 1 of the present invention, the data SI indicating the setting information, and the volatile semiconductor memory device 20. Each waveform of the external command CMD input from the external CPU is shown.

  In the nonvolatile semiconductor memory device 10 of the present invention device 1, when the power-on circuit 30 detects the rise of the power supply and outputs an H level detection pulse (step # 111, time t 1 to t 2), the setting information sending means 13. However, the setting information is output to the volatile semiconductor memory device 20 via the dedicated data output terminal 14 and the data line 40 (step # 112, time t1 to t2).

  When the setting information is output from the nonvolatile semiconductor memory device 10 (step # 112), in the volatile semiconductor memory device 20 of the device 1 of the present invention, the setting information storage means sends the setting information via the dedicated data input terminal 23. (Step # 121) and stored in the mode register 22 (step # 122, time t1 to t2). Note that the detection pulse output from the power-on circuit 30 is configured to be output immediately after the power is turned on. In normal use, the CPU first accesses the volatile semiconductor memory device 20 (command issuance). Writing of the setting information to the mode register 22 of the volatile semiconductor memory device 20 is completed before performing the above, that is, by the time t3 shown in FIG.

  When a command instructing normal operation is output from the external CPU (step # 101, times t3 to t4), the volatile semiconductor memory device 20 executes normal operation based on the command (step # 123).

  By configuring the inventive device 1 in this way, the setting of the mode register 22 of the volatile semiconductor memory device 20 at the time of power-on is completed without the need to issue a special command or the like with an external device such as a CPU. Can be made.

<Another embodiment>
<1> In the above embodiment, the case where the package of the device 1 of the present invention is a stack type package in which a plurality of LSI chips are stacked and mounted in the same package has been described. However, the present invention is not limited to this. . For example, a package stack (POP) in which a plurality of packages are stacked may be used.

  <2> In the above embodiment, the case where the dedicated data line 40 is provided between the volatile semiconductor memory device 20 and the nonvolatile semiconductor memory device 10 to transmit the setting information has been described. However, the present invention is not limited to this. Absent. The configuration information may be transmitted using a data line through which write data, read data, and the like are transmitted in a normal operation. In this case, the volatile semiconductor storage device 20 causes the CPU to wait until the CPU issues a command for normal operation until the setting information is written to the mode register 22 of the volatile semiconductor storage device 20 is completed. On the other hand, it is desirable to configure so as to output a signal notifying the end of setting.

1 is a schematic partial block diagram showing a configuration example of a semiconductor memory device according to the present invention. Schematic partial block diagram showing a connection configuration between a volatile semiconductor memory device and a nonvolatile semiconductor memory device in a semiconductor memory device according to the present invention 7 is a flowchart showing a processing procedure of initial setting processing in the semiconductor memory device according to the present invention. Schematic waveform diagram showing an example of signal waveforms of various signals in the semiconductor memory device according to the present invention. Schematic partial block diagram showing a connection configuration example of a CPU and a volatile memory in a volatile semiconductor memory device according to the prior art 6 is a flowchart showing a processing procedure of initial setting processing of a volatile memory in a volatile semiconductor memory device according to the prior art. Schematic waveform diagram showing an example of a clock signal CLK and commands MRS and CMD input to a volatile semiconductor memory device according to the prior art Schematic partial block diagram showing a connection configuration example of a CPU and a volatile memory in a volatile semiconductor memory device according to the prior art Schematic partial block diagram showing a configuration example of a semiconductor memory device according to the prior art 6 is a flowchart showing a processing procedure of volatile memory initial setting processing in a semiconductor memory device according to the prior art. Schematic waveform diagram showing an example of a clock signal CLK and commands MRS and CMD input to a semiconductor memory device according to the prior art

Explanation of symbols

1 Semiconductor Memory Device 10 According to the Present Invention Nonvolatile Semiconductor Memory Device 11 According to the Present Invention Mode Register (Setting Information Storage Area)
12 Second data storage area 13 Setting information sending means 14 Dedicated data output terminal 20 Volatile semiconductor storage device 21 according to the present invention 21 First data storage area 22 Mode register 23 Dedicated data input terminal 30 Power-on circuit 40 Dedicated data Line 100 Volatile semiconductor memory device 110 according to prior art Non-volatile memory 120 RAM
121 Mode register 200 CPU
300 Compound Semiconductor Memory Device 400 According to Prior Art Volatile Semiconductor Memory Device 410 According to Prior Art Mode Register 420 Memory Control Circuit 430 DRAM
B Buffer circuit G Transfer gate circuit

Claims (8)

A volatile semiconductor comprising: a first data storage area comprising a volatile memory for storing predetermined data; and a volatile mode register for storing setting information necessary for executing a normal operation for the first data storage area A storage device;
A non-volatile configuration comprising: a second data storage area comprising a non-volatile memory for storing predetermined data; and a non-volatile setting information storage area having the setting information necessary for executing the normal operation of the volatile semiconductor memory device A semiconductor memory device, comprising:
The nonvolatile semiconductor memory device is
Power-on detection means for detecting power-on,
After the power is turned on, before the normal operation for the first data storage area of the volatile semiconductor memory device, the setting information stored in the setting information storage area is automatically stored in the volatile semiconductor memory device. And setting information sending means for sending to
The volatile semiconductor memory device is
Setting information storage means for receiving the setting information from the nonvolatile semiconductor memory device and storing the received setting information in the mode register after the power is turned on and before execution of the normal operation on the first data area A semiconductor memory device characterized by comprising. The nonvolatile semiconductor memory device includes a dedicated data output terminal for sending the setting information to the volatile semiconductor memory device,
The setting information sending means of the nonvolatile semiconductor memory device sends the setting information via the data output terminal;
The volatile semiconductor memory device includes a dedicated data input terminal for receiving the setting information from the nonvolatile semiconductor memory device,
The setting information storage means of the volatile semiconductor memory device accepts the setting information via the data input terminal;
2. The semiconductor memory device according to claim 1, wherein the data output terminal of the nonvolatile semiconductor memory device and the data input terminal of the volatile semiconductor memory device are connected by a dedicated data line.   3. The semiconductor memory device according to claim 1, wherein the volatile semiconductor memory device and the nonvolatile semiconductor memory device are configured in the same package.   4. The semiconductor memory device according to claim 3, wherein the package is a stack type package. A volatile semiconductor comprising: a first data storage area comprising a volatile memory for storing predetermined data; and a volatile mode register for storing setting information necessary for executing a normal operation for the first data storage area A storage device,
After the power is turned on and before executing the normal operation on the first data storage area, the external nonvolatile semiconductor memory device is provided with setting information sending means for automatically sending the setting information stored therein. A volatile semiconductor memory device comprising setting information storage means for receiving setting information and storing the received setting information in the mode register. A dedicated data input terminal for connecting the mode register and the nonvolatile semiconductor memory device and receiving the setting information from the nonvolatile semiconductor memory device;
The volatile semiconductor memory device according to claim 5, wherein the setting information storage unit receives the setting information via the data input terminal. A non-volatile setting information having a second data storage area composed of a non-volatile memory for storing predetermined data, and the setting information necessary for executing the normal operation of the volatile semiconductor memory device according to claim 5 or 6. A non-volatile semiconductor storage device comprising a storage area,
Power-on detection means for detecting power-on,
After the power is turned on, before the normal operation for the first data storage area of the volatile semiconductor memory device, the setting information stored in the setting information storage area is automatically stored in the volatile semiconductor memory device. A non-volatile semiconductor memory device comprising: setting information sending means for sending to the device. The mode register and the setting information storage area of the volatile semiconductor memory device are connected, and a dedicated data output terminal for sending the setting information to the volatile semiconductor memory device is provided.
8. The nonvolatile semiconductor memory device according to claim 7, wherein the setting information sending means sends the setting information through the data output terminal.

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