JP2008310718A - Instantaneous power failure protecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an instantaneous power failure protecting circuit of simple circuit configuration storing a small amount of data in preparation for instantaneous power failure. <P>SOLUTION: At the cutoff of a power source VDD, charge of a capacitor 2 is supplied to an FF 5 and a buffer 6 and discharged through a resistor 1, and the potential V1 of a node N1 gradually drops. Charge of a capacitor 4 is discharged through a resistor 3, but since the time constant of the resistor 3 and capacitor 4 is set smaller than that of the resistor 1 and capacitor 2, the potential drop of a node N2 is faster than that of the node N1. If power source potential VDD is restored while the potential V1 is voltage at which the FF5 and buffer 6 can be operated and the potential V2 is not less than the threshold voltage of the buffer 6, a data signal DI held to the FF 5 is output as it is as a data signal DO. If the instantaneous power failure is long, the potential V2 drops to the threshold of the buffer or lower to reset the FF 5, and the data signal DO turns to "L". <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power supply instantaneous power failure protection circuit that holds data in preparation for a case where a power supply voltage is momentarily cut off in a semiconductor integrated circuit.

  2. Description of the Related Art Conventionally, in a semiconductor integrated circuit such as a microcomputer, when data is to be protected in case the power supply voltage is momentarily cut off, the data to be protected is stored in a magnetic disk device or an EEPROM (electrically rewritable read only). The data is stored in a non-volatile memory such as a memory.

JP-A-8-237856

  Patent Document 1 discloses a digital motor protection control device that monitors a power supply voltage to detect a momentary power failure and does not stop the motor when the momentary power failure time is shorter than a preset time. Are listed.

  However, storing data to be protected in a conventional nonvolatile memory is suitable for protecting a large amount of data because the circuit scale becomes large. However, if a small amount of data needs to be protected, the cost is low. There was a problem of becoming larger.

  An object of the present invention is to provide an instantaneous power failure protection circuit having a simple circuit configuration for storing a small amount of data in preparation for an instantaneous power failure.

  The instantaneous power failure protection circuit of the present invention includes a first resistor connected between a power supply potential and a first internal node, and a first capacitor connected between the first internal node and a ground potential. A second resistor connected between the power supply potential and the second internal node; a second capacitor connected between the second internal node and the ground potential; and the first internal node From the first internal node, and holds the data signal to be protected in synchronization with the clock signal and resets the held data when a reset signal is applied. And a reset means for outputting the reset signal when the second internal node drops below a predetermined potential, and the time constant of the first resistor and capacitor is set to the second resistor and capacitor. It is characterized in that set larger than the time constant by capacitor.

  In the present invention, the data signal to be protected is held by the data holding means using the voltage of the first internal node generated by the integrating circuit formed of the first resistor and the first capacitor as the power source. Yes. Accordingly, there is an effect that a small amount of data can be stored in preparation for an instantaneous power failure with a simple circuit configuration.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of an instantaneous power failure protection circuit showing Embodiment 1 of the present invention.
This instantaneous power failure protection circuit has two sets of a resistor 1 and a capacitor 2, and a resistor 3 and a capacitor 4 connected in series between a power supply potential VDD and a ground potential GND. Here, the time constant of the integrating circuit including the resistor 1 and the capacitor 2 is set larger than the time constant of the integrating circuit including the resistor 3 and the capacitor 4.

  Power is supplied to a D-type flip-flop (hereinafter referred to as “FF”) 5 and a buffer 6 from a node N 1 that is a connection point between the resistor 1 and the capacitor 2. A data signal DI that needs to be protected during an instantaneous power failure is supplied to the input terminal D of the FF 5, and a clock signal CK is supplied to the clock terminal C. Further, the output signal of the buffer 6 is given to the reset terminal R of the FF 5. Note that the buffer 6 is a cascade connection of two stages of CMOS inverters, and its input side is connected to a node N 2, which is a connection point between the resistor 3 and the capacitor 4.

  Further, a buffer 7 is connected to the output terminal Q of the FF 5, and a protected data signal DO is output from the output side of the buffer 7. Note that the power of the buffer 7 is directly supplied from the power supply potential VDD.

  FIG. 2 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.

  When the power supply potential VDD is stably maintained at a predetermined voltage (for example, 5 V), the potential V1 of the node N1 is obtained by subtracting the voltage drop due to the operating current of the FF 5 and the buffer 6 flowing through the resistor 1 from the power supply potential. It becomes. If the resistance value of the resistor 1 is set to be relatively small, the operating current flowing through the FF 5 and the buffer 6 is very small, so that the potential V1 is substantially equal to the power supply potential VDD. Further, the potential V2 of the node N2 becomes the power supply potential VDD.

  In this state, since the potential V1 substantially equal to the power supply potential VDD is supplied to the power supply terminals of the FF5 and the buffer 6, the FF5 and the buffer 6 perform normal operation. As a result, the signal applied from the buffer 6 to the reset terminal R of the FF 5 becomes the level “H”, and the FF 5 takes in the data signal DI at every rising timing of the clock signal CK and outputs it from the output terminal Q. As for the signal output from the FF 5, the data signal DO is output via the buffer 7. Therefore, the timing of the data signal DI is adjusted by the clock signal CK and output as the data signal DO.

  Next, as shown in FIG. 2, when the power is cut off at the time t = 20 μs, the power supply to the buffer 7 is stopped, so that the data signal DO output from the buffer 7 Regardless of the output signal, the level immediately becomes “L”.

  On the other hand, the electric charge charged in the capacitor 2 is supplied as the power source for the FF 5 and the buffer 6 and is discharged to the power source side via the resistor 1. As a result, the potential V1 of the node N1 gradually decreases substantially from the power supply potential VDD. Further, the electric charge charged in the capacitor 4 is discharged to the power supply side through the resistor 3.

  Since the time constant of the integrating circuit composed of the resistor 1 (and the FF 5 and the buffer 6) and the capacitor 2 is set larger than the time constant of the integrating circuit composed of the resistor 3 and the capacitor 4, the potential V1 of the node N1 is It drops more slowly than the potential V2.

  Here, as shown at time t = 130 μs in FIG. 2A, the power supply is supplied while the potential V1 is a voltage sufficient to operate the FF 5 and the buffer 6 and the potential V2 does not fall below the threshold voltage of the buffer 6. When the potential VDD is restored, since the data signal DI is held in the FF 5, the same data signal DO as that before the momentary power interruption is output from the buffer 7.

  On the other hand, when the power supply instantaneous interruption time becomes longer, the potential V2 drops below the threshold voltage of the buffer 6 as shown at time t = 200 μs in FIG. As a result, the output signal of the buffer 6 becomes “L”, and the FF 5 is reset. Therefore, when the power supply potential VDD is restored at time t = 200 μs, the FF 5 is reset, so that the data signal DO output from the buffer 7 is reset to “L” regardless of the data signal DI before the instantaneous power interruption. "

  As described above, the instantaneous power failure protection circuit according to the first embodiment includes the resistor 1 and the capacitor 2 for supplying power to the data holding FF 5 for a predetermined time when the power supply potential VDD is cut off. A backup power supply is provided. Thereby, there is an advantage that a small amount of data can be stored in preparation for an instantaneous power failure with a simple circuit configuration.

  In addition, a reset circuit including a resistor 3 and a capacitor 4 having a time constant smaller than that of the backup power supply is provided. Thus, there is an advantage that when the instantaneous power interruption time becomes longer, the data holding FF 5 is reset, and abnormal data can be prevented from being output when the power is restored.

  FIG. 3 is a configuration diagram of a power supply instantaneous power failure protection circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This instantaneous power failure protection circuit is formed by connecting diodes 8 and 9 in the forward direction in parallel with resistors 1 and 3 in FIG.

  In this power supply instantaneous power failure protection circuit, when the power supply potential VDD is stably maintained at a predetermined voltage, the diodes 8 and 9 are in the forward direction. Therefore, the decrease in the potential V1 of the node N1 is extremely small, and almost the power supply The potential becomes VDD.

  When the power is shut off, the diodes 8 and 9 are in a reverse bias state, so that no current flows through these diodes 8 and 9, and the same operation as in FIG. 1 is performed.

  On the other hand, when the power supply potential VDD recovers from the instantaneous power failure state, the capacitors 2 and 4 are rapidly charged through the diodes 8 and 9 connected in the forward direction. Thereby, the capacitors 2 and 4 are recovered faster than the circuit of FIG.

  As described above, the instantaneous power failure protection circuit according to the second embodiment has the diodes 8 and 9 connected in the forward direction in parallel with the resistors 1 and 3, respectively. As a result, in addition to the same advantages as those of the first embodiment, there is an advantage that there is less possibility of malfunction even when the instantaneous power interruption is repeated.

  FIG. 4 is a configuration diagram of an instantaneous power failure protection circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This power supply instantaneous power failure protection circuit is provided with diodes 8 and 9 respectively connected in the forward direction instead of the resistors 1 and 3 in FIG. 1 and an FF 10 having the same configuration as the FF 5. Note that the capacitance of the capacitor 2 is set larger than the capacitance of the capacitor 4. The power of the FF 10 is supplied from the node N2, and the input terminal D, the clock terminal C, and the reset terminal R of the FF 10 are all connected to the ground potential GND and used as a dummy load circuit for the node N2. It has become.

  In this power supply instantaneous power failure protection circuit, when the power supply potential VDD is stably maintained at a predetermined voltage, the diodes 8 and 9 are in the forward direction. Therefore, the decrease in the potential V1 of the node N1 is extremely small, and almost the power supply The potential becomes VDD.

  Since the diodes 8 and 9 are in a reverse bias state when the power is shut off, the discharge current from the capacitor 2 is the operating current of the FF 5 and the reverse leakage current of the diode 8, and the discharge current from the capacitor 4 is Only the operating current and the leakage current in the reverse direction of the diode 9 are present. As a result, the decreasing speeds of the potential V1 of the node N1 and the potential V2 of the node N2 are slower than those in the first and second embodiments.

  On the other hand, when the power supply potential VDD recovers from the instantaneous power failure state, the capacitors 2 and 4 are rapidly charged through the diodes 8 and 9 connected in the forward direction. As a result, the capacitors 2 and 4 recover quickly as in the second embodiment.

  As described above, the instantaneous power failure protection circuit according to the third embodiment charges the capacitors 2 and 4 of the nodes N1 and N2 through the diodes 8 and 9, so that the potential V1 at the time of instantaneous power interruption is as follows. The rate of decrease in V2 can be reduced. Thereby, in addition to the same advantages as those of the first and second embodiments, there is an advantage that data can be retained even during a relatively long power interruption time.

  Further, an FF 10 having a circuit similar to the FF 5 connected to the node N 1 is connected to the node N 2 as a dummy load circuit. Thereby, the leakage currents flowing from the capacitors 2 and 4 to the diodes 8 and 9 and the FFs 5 and 10 when the power is shut off can be made substantially equal. In particular, since the leakage current in the semiconductor circuit is highly dependent on the ambient temperature, there is an advantage that a stable characteristic with little temperature dependence can be obtained by configuring with a similar circuit.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although a circuit that holds a 1-bit data signal DI is illustrated, an FF that simultaneously holds a plurality of bits of a data signal DI can be provided.
(B) Although the FF is used as the data holding circuit, any circuit may be used as long as it can hold data.
(C) Although the potential V2 of the node N2 is applied to the reset terminal R of the FF5 through the buffer 6, if the time constant by the capacitors 2 and 4 is appropriately set, the reset terminal R of the FF5 is connected to the node N2. Direct connection is also possible.
(D) The input terminal D, clock terminal C, and reset terminal R of the FF 10 may be fixedly connected to the power supply potential VDD.

It is a block diagram of the power supply instantaneous power failure protection circuit which shows Example 1 of this invention. It is a signal waveform diagram which shows the operation | movement of FIG. It is a block diagram of the power supply instantaneous power failure protection circuit which shows Example 2 of this invention. It is a block diagram of the power supply instantaneous power failure protection circuit which shows Example 3 of this invention.

Explanation of symbols

1,3 resistor 2,4 capacitor 5,10 FF
6,7 Buffer 8,9 Diode

Claims (3)

A first resistor connected between the power supply potential and the first internal node;
A first capacitor connected between the first internal node and a ground potential;
A second resistor connected between the power supply potential and a second internal node;
A second capacitor connected between the second internal node and the ground potential;
Data holding means for receiving power from the first internal node and holding the data signal to be protected in synchronization with the clock signal, and resetting the held data when a reset signal is given;
Resetting means for outputting the reset signal when power is supplied from the first internal node and the second internal node drops below a predetermined potential;
A power supply instantaneous power failure protection circuit, wherein a time constant by the first resistor and the capacitor is set larger than a time constant by the second resistor and the capacitor.   2. The instantaneous power failure protection circuit according to claim 1, wherein a first diode is connected in parallel in the forward direction to the first resistor, and a second diode is connected in parallel in the forward direction to the second resistor. . A first diode connected between the power supply potential and the first internal node;
A first capacitor connected between the first internal node and a ground potential;
A second diode connected in a forward direction between the power supply potential and a second internal node;
A second capacitor connected between the second internal node and the ground potential and having a smaller capacity than the first capacitor;
Data holding means for receiving power from the first internal node and holding the data signal to be protected in synchronization with the clock signal, and resetting the held data when a reset signal is given;
Resetting means for outputting the reset signal when power is supplied from the first internal node and the second internal node drops below a predetermined potential;
A dummy load means configured by the same circuit as the data holding means, to which power is supplied from the second internal node and whose input terminals are all fixed at a power supply potential or a ground potential;
An instantaneous power failure protection circuit comprising the power supply.

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