JP2008310460A - Control circuit, storage medium, processor, integrated system, and area management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control circuit for performing area management, such as exclusive control and sharing of an area in use among a plurality of applications to a storage medium, such as a flash memory, in addition to measurement against the cutoff of a power supply, and to provide an area management method. <P>SOLUTION: An address control circuit 130 sets a prescribed area of an EEPROM 140 as a domain and manages the domain and access requirements in the processor 120. The address control circuit 130 includes in the EEPROM 140: a domain setting register 133 for setting control information 151 for managing a domain; and a domain control register 131 for holding information on the domain to be processed now. Control information 151 is set in an address on the EEPROM 140 by using information in the domain setting register 133. Whether or not access by programs is permitted or rejected is determined based on the control information 151 set in the address and the information in a domain control register 131. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a control circuit that performs area management of a storage medium having an erasable and rewritable storage area, in particular, a nonvolatile storage medium such as a flash memory, a processing device for a general purpose or embedded system having the control circuit, and the processing The present invention relates to an embedded system having a device and a technique effective when applied to the storage medium area management method.

  A flash memory widely used in PCs and embedded systems is a kind of semiconductor memory, and data is usually managed in units of blocks. Therefore, when data is read, written, or erased, processing is performed for each data block.

  In addition, when writing data, the flash memory is normally written from the erased state. If the original data is overwritten, the result of AND or OR between the original data and the written data is flashed. Written on memory. Therefore, if you want to update a data block, you need to erase the block and then write the update data back, or write to another data block and then erase the original data block. I need it.

  However, there is a problem in that when power is interrupted while data is being erased, the data to be written back and information on its address are lost and cannot be updated correctly. This is one of the problems in constructing a system using a flash memory. JP 2006-323499 A (Patent Document 1), JP 2006-39983 A (Patent Document 2), Various solution means have been proposed as seen in JP 2005-258851 A (Patent Document 3), JP 2004-310477 A (Patent Document 4), JP 2004-265162 A (Patent Document 5), and the like. Yes.

  However, these solutions are effective techniques mainly when using flash memory as data storage, such as a memory card or USB memory. However, in recent years, flash memory has been incorporated into CPUs and IC card chips for embedded systems. In the current situation of incorporating and using, it is not necessarily suitable.

When the erasable and rewritable non-volatile memory that manages data such as flash memory is used for embedded system CPUs and IC card chips, the software for embedded systems is becoming larger. It will be used as a device having a larger capacity and lower cost than the conventional EEPROM. In that case, the flash memory is expected not as a device for merely storing data, but as a device used to execute a program as a replacement of ROM or RAM.
JP 2006-323499 A JP 2006-39983 A Japanese Patent Laying-Open No. 2005-258851 JP 2004-310477 A JP 2004-265162 A

  Under these circumstances, when using a flash memory with an embedded system CPU or IC card chip, various technologies are required, such as measures for shutting down the power supply, error correction function, and distribution of the number of rewrites. Therefore, software and hardware for control tend to be enlarged.

  In addition to the problem of ensuring availability as such a storage medium, there is a problem to be considered in terms of security. Conventional CPUs and IC card chips for embedded systems are mainly used for specific purposes, and in most cases, a single application is executed on the minimum hardware resources. It was. However, there are increasing demands on systems such as the complexity of embedded systems and the use of IC cards for multipurpose purposes, and the CPU and IC card chip for embedded systems also take into consideration the case where multiple applications operate simultaneously. The need has arisen.

  Normally, these applications are expected to be controlled so that system resources can be shared exclusively or cooperatively by an OS running on a CPU or IC card chip for an embedded system. In many cases, CPUs and IC card chips for embedded systems, which have severe resource restrictions, cannot introduce complex software processing. However, considering the security of CPUs and IC card chips for embedded systems, a mechanism that enables exclusive control of hardware resources at a lower cost is an important issue when considering system safety.

  Therefore, an object of the present invention is to provide a use area between a plurality of applications in addition to a power shutdown measure for ensuring availability of a storage medium such as a flash memory used in a CPU or IC card chip for an embedded system. To provide a control circuit that performs area management such as exclusive control and sharing, a processing device for a general-purpose or embedded system having the control circuit, an embedded system having the processing apparatus, and an area management method for the storage medium is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention provides a processing apparatus having a CPU and a erasable and rewritable storage medium, setting a predetermined area of the storage medium as a domain, and managing the domain and access requirements when the program uses the domain A control circuit and a region management method for managing a first register for setting control information for managing the domain in the storage medium, and the current processing target A second register for holding information about the domain, and using the information in the first register, the domain to which the data area assigned to the address belongs to the address on the storage medium The control information is set and the program accesses the data area assigned to the address on the storage medium. And the control information set to the address, based on the information of the second register, and is characterized in that to determine whether the said access.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, when a storage medium such as a flash memory is used for execution of an application in a CPU or IC card chip for an embedded system, the application is on a domain that is an individual area where the setting cannot be changed by itself. Therefore, it is possible to operate without fear that data on another domain is destroyed or illegally accessed due to an unauthorized operation of an application.

  In addition, by combining a mechanism for multiplexing virtual addresses and data areas, it is possible to ensure availability against failures such as power interruption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a diagram illustrating a configuration of a processing apparatus according to an embodiment of the present invention and a storage medium connected to the processing apparatus. The IC card 100 has an input / output IF 110 and a processing device 120. Here, the IC card 100 is a typical example of an embedded system that is a subject of the present invention, and there are various types depending on its shape, specifications of an interface with an external device, the type of the processing device 120, the presence or absence of other devices, and the like. It can be applied to embedded systems.

  The input / output IF 110 has physical and electrical characteristics standardized by ISO7816, and is an interface that transmits and receives commands and data in a message format defined by the standard. The interface corresponding to the input / output IF 110 in the embedded system does not need to be limited to this, and is compliant with standards such as USB (Universal Serial Bus), MMC (MultiMedia Card), ATA (AT Attachment), PCI, etc. An interface having no physical terminal such as a bus in the apparatus, a non-contact IC card interface standardized by ISO 14443, Bluetooth, or wireless LAN may be used.

  The input / output IF 110 includes a VCC line 111, a reset signal line (denoted as RST in the figure) 112, a clock signal line (denoted as CLK in the figure) 113, a GND line 114, an input / output line (denoted as I / O in the figure). (Notation) 115 is connected to the processing device 120.

  The processing device 120 includes a UART control circuit 121 that is a control circuit for the input / output IF 110, a CPU 122, a RAM 123, a ROM 124, a coprocessor 125, and an address control circuit 130, which are connected by an internal bus 126. In addition, an EEPROM 140 is provided, and the EEPROM 140 is connected to the address control circuit 130.

  The processing device 120 is a representative example of a processing device group in an embedded system. Even if these devices are modularized on one chip, one or a plurality of modules are configured as separate chips, and so on. By adopting a simple configuration, each chip may be connected by a plurality of buses. The EEPROM 140 is not limited to a flash memory, and may be a device composed of other elements such as FeRAM and MRAM, or may be a magnetic medium such as an HDD. Further, the flash memory does not depend on the difference between the NAND type, the AND type, the NOR type, and the like.

  Here, when the EEPROM 140 is an erasable and rewritable nonvolatile storage medium that performs reading, writing, and erasing in units of data blocks corresponding to a certain physical address, the data block 141 on the EEPROM 140 is the data block. 141 includes control information 151 and a data area 152 assigned to 141.

  The control information 151 may be an object of an erase operation when the data block 141 is designated to be erased, but is not an object of reading and writing when the data block 141 is accessed from an application or the like. Information 151 is read and written using a register managed by an address control circuit 130 described later. The control information 151 may be assigned for each 1-byte data referred to by an address, or may be assigned for each page block in which a data block consisting of several KB or a data block consisting of several tens of KB is collected. Good.

  The address control circuit 130 is a module for performing domain management of the EEPROM 140, and includes a domain control register 131, a virtual address space register 132, and a domain setting register 133. Here, the domain is an individual area on the EEPROM 140 used by the application, and as a general rule, an area other than the application cannot be accessed, and a setting cannot be changed by the application itself. Point to. Details of the domain will be described later.

  The address control circuit 130 is an extension of a module for performing control such as reading from, writing to, deleting from the EEPROM 140, management of the protection state, interrupt control during processing, address scrambling, encryption / decryption processing, error detection, It is not implemented in place of these modules, nor does it limit the operation of these modules. The address control circuit 130 may be a logic circuit, but may be a configuration including a CPU or a reconfigurable logic circuit whose internal configuration can be changed by processing.

  The domain control register 131 is a register that is set before accessing the domain on the EEPROM 140, and stores the domain number 134, the access type 135, and the like of the domain currently being processed. The access type 135 is information relating to operations such as reading, writing, and erasing performed by the CPU 122 on the domain on the EEPROM 140, and can be determined by judgment based on the value of the program counter, the domain number 134, and the domain number 153 described later. Is a register that can be set from the currently executing application.

  When an access to a domain on the EEPROM 140 occurs, the address control circuit 130 determines that the content of the specified access type 135 is based on the access type 135 and a domain type flag 156 (to be described later). It is determined whether the access requirement set in the flag 156 is satisfied. By not making this determination to the CPU 122 that executes general-purpose processing, it is possible to prevent unauthorized access to the EEPROM 140.

  The domain number 134 is a value set when control is transferred to a certain domain, and only the number of the domain currently being processed and the child domain of the domain can be set. When the application changes the domain number 134 of the domain control register 131, the control information 151 corresponding to the address on the EEPROM 140 referred to by the current program counter is read, and the domain number 153 therein is referred to. The numbering system of the domain and the domain number 153 is hierarchized as described later, and the value of the referenced domain number 153 is the domain number of the domain in which the application whose setting is to be changed is stored. The relationship can be examined by comparing with the value set in the domain number 134 of the domain control register 131.

  For example, if the domain number 153 has a value of 12 bits and is assigned as a value representing the domain of the first layer, the domain of the second layer, the domain of the third layer in order from the upper layer every 4 bits, the domain number If 153 is 110h, the values that can be set as the domain number 134 are 110h and 111h to 11Fh. If any other value is set, an error occurs. Note that the method for determining the domain relationship is not limited to this, and the address control circuit 130 may have a table for storing the domain relationship and determine based on the correspondence relationship of this table. Good.

  The virtual address space register 132 is a register for realizing a virtual address space for making an address space by a domain on the EEPROM 140 look like another EEPROM 140, and stores a start address and an end address.

  When the embedded system is controlled by an OS that executes a program on a virtual address such as Java (registered trademark), the dynamic conversion of the address on the EEPROM 140 by Java VM becomes a large overhead. Therefore, if an independent domain for each application formed on the EEPROM 140 looks like another EEPROM 140 and has an individual address space, even if the physical addresses are complicatedly distributed, the OS can There is no need to consider, and there is an advantage that performance improvement can be expected. In particular, when taking measures against power shutdown of the EEPROM 140 and error block substitution processing, it is difficult to manage the logical address and the physical address in a consistent manner, so that the effect becomes greater.

  The virtual address space register 132 is a mechanism used when reading an intra-domain address 155 (to be described later) stored in the control information 151 and performing address conversion between a physical address and a virtual address in hardware. If the address translation is not performed because the virtual address space is not used, or if a table is provided on the RAM 123 and the CPU 122 performs the address translation, it may not be necessary.

  The domain setting register 133 holds a value set as the control information 151 when writing data to the EEPROM 140. Normally, when the EEPROM 140 is read, the domain setting register 133 is automatically updated according to the contents of the control information 151 of the read data block 141, so the same control information 151 is written to a certain data block 141. In such a case, the data may be written after reading once.

  When generating a new domain or the like, it is necessary to set appropriate information in the domain setting register 133. In this case, only the information of its own domain or its own child domain can be specified. In addition, when the operation | movement by the virtual address mentioned later is performed, you may restrict | limit the change of the control information 151 about own domain. This is because when the address space is controlled by the virtual address, if the child domain changes the virtual address assigned from the parent domain, it causes a failure.

  In addition, the control information 151 can be configured to have two or more virtual addresses such as a virtual address of its own domain and a virtual address for its child domain. The virtual address for the child domain may be changed. Otherwise, the child domain controlled by the virtual address space from the parent domain cannot generate a child domain having an individual virtual address space. The address control circuit 130 uses these pieces of information to determine whether access to the EEPROM 140 is appropriate.

  The control information 151 includes a domain number 153, a control condition flag 154, and an intra-domain address 155. Here, the domain number 153 stores the domain number to which the data area 152 assigned to the target address on the EEPROM 140 belongs. The control condition flag 154 is a flag that describes the control conditions of the domain designated for the target address, and includes a domain type flag 156, a virtual address operation flag 157, and a back address flag 158.

  The domain type flag 156 stores the type of access to the domain, and for example, three states of read enable, read / rewrite enable, and access prohibition are set. These mainly indicate whether access from the child domain is possible, but increase the number of bits assigned to the flag, permit access from all lower domains, or allow access from the immediate child domain. It is also possible to set whether to allow various accesses according to conditions such as permitting access from domains belonging to the same parent domain.

  An area in which read permission is set in the domain type flag 156 can be accessed based on the set condition. This can be used to access a shared library that exists in the parent domain. Similarly, an area for which read / rewrite is set can be read and rewritten. This can be used when it is desired to share data between applications. In an area where access prohibition is set, access from a domain other than the parent domain as described above is prohibited.

  The virtual address operation flag 157 is for allocating an address space for an application in the domain. When this flag is set, the target data block 141 is used when the application accesses each logical address. It behaves as if it is an address described in the intra-domain address 155. The back address flag 158 indicates the address at which the latest data is stored in the case where the above-described virtual address is used and the physical address is duplicated for the purpose of multiplexing the data area 152. It is a flag indicating whether or not.

  The intra-domain address 155 stores the virtual address logically pointed to by the target physical address when address conversion between the virtual address and the physical address is performed by setting the virtual address operation flag 157 to be valid. Is. When the operation using the virtual address is not required, the virtual address operation flag 157, the back address flag 158, and the area for the intra-domain address 155 in the control condition flag 154 may not be allocated.

  With the configuration described above, the address control circuit 130 uses the information of each register in the address control circuit 130 and the control information 151 assigned to each data area 152, so that the power shutdown or illegal code can be detected. Even when executed, the EEPROM 140 can be controlled without interfering with each other for each domain, and the setting of each domain can be flexibly changed from the OS.

  The storage location of the control information 151 may be stored not at the beginning of the data area 152 but at the end, another data block, another memory, or the like. Further, the arrangement order of data in the control information 151 and the individual data sizes are not limited to the order shown in FIG.

  In recent embedded systems, various software modules are incorporated, and many of them are configured to be controlled by a real-time OS for an embedded system CPU. This includes devices such as mobile phones, cars, HDD recorders, and the like. The same applies to IC cards, SIM cards, and the like on which a plurality of applications are mounted. Each of these software modules is created and operated in a system after being created in a separate process. However, due to a bug in a certain software module or a problem in setting between the software module and the OS, another software module or OS May cause problems such as system shutdown or leakage of important information.

  However, considering that software modules and OSs operate independently but cooperate, a firewall with only simple access restrictions is not sufficient. In particular, when the EEPROM 140 becomes very fast and has a long life in the future, it is conceivable that the system is designed only with the EEPROM 140 instead of the ROM 124 and the RAM 123. In that case, domain management of the EEPROM 140 is required.

  The outline when the address control circuit 130 performs domain management of the EEPROM 140 using the information of each register in the address control circuit 130 and the control information 151 will be described below.

  The EEPROM 140 is managed in a hierarchical structure by domain, and information on which domain the target data block 141 belongs to is stored in the domain number 153. When the use of the EEPROM 140 in an embedded system including the operation of the OS is assumed, the address space of the EEPROM 140 that can be used by one application is usually allocated by the OS.

  The OS is stored in advance in the ROM 124 or the EEPROM 140, and normally, after the IC card 100 is issued, the domain is not dynamically assigned to the OS. 0 is assigned. As described above, the domain whose domain number is 0 operates as a root domain, and is the only domain in which settings cannot be changed from a domain other than itself.

  FIG. 2 is a diagram showing an example of the relationship between the domain hierarchical structure and the area of EEPROM 140 in the present embodiment. Domain # 0 (200) in FIG. 2 is a root domain and is usually a domain managed by the OS. This domain number information is stored in the domain number 153 of the address space # 0 (250) in the target EEPROM 140. In the example of FIG. 2, the entire EEPROM 140 belongs to the root domain. However, this address space does not necessarily have to be a single block, and may be unevenly distributed in the EEPROM 140.

  When a new application is added to the IC card 100 having such a configuration, the OS creates a new domain for the application. A domain number that is not used as its own domain number is assigned to a new domain generated with domain # 0 (200) as a parent. Domain # 1 (210), domain # 2 (220), and domain # 3 (230) are domains created in this way.

  Here, taking the domain # 2 (220) assigned to the address space # 2 (270) as an example, an application stored in the address space # 2 (270) is stored in the address space # 2 (270). Although executed, access to another address space cannot be performed unless permitted by the domain type flag 156 of the domain assigned to the address space. Domain # 2 (220) can create a child domain in its own domain. If the address space of domain # 2 (220) is not an area large enough to create a child domain, domain # 0 (210), the parent domain, adds an additional area to domain # 2 (220). Can be assigned.

  Domain # 21 (221) and domain # 22 (222) are domains generated by this operation with domain # 2 (220) as a parent. Address space # 21 (271) and address space # 22 (272) share an area with address space # 2 (270). This is because the parent domain assigns the child domain area to the child domain before assignment. The child domain # 21 (221) or the child domain # 22 (222) can operate in the same manner as the domain type flag 156 of the parent domain # 2 (220), unless it is permitted. This means that only the address space range can be manipulated.

  Domain management as described above is effective in the EEPROM 140 used for storing programs and data, and a rewritable nonvolatile device such as a flash memory, but can also be used for controlling the ROM 124 and RAM 123. It is. The advantage of incorporating the above-described mechanism in the ROM 124 is that, when individual middleware is installed for each application on the ROM 124, even a program on the ROM 124 limits the range that may affect each other. It is a point that can be. This point is significant in quality control of an embedded system that is becoming large-scaled. For example, when a module that requires certification is incorporated, the range of influence can be effectively limited.

  The advantage of incorporating the above-described mechanism into the RAM 123 is that the failure of the IC card 100 due to an application bug can be prevented by hardware. For example, a domain created for a stack that is readable and writable from the root domain cannot be operated beyond the area preset by the domain management. There is an effect that it can be avoided.

  Hereinafter, as detailed contents of the operation related to the address control circuit 130 and the EEPROM 140 having the control information 151 for the address control circuit 130, each process of setting a root domain, adding a domain, accessing a domain, and deleting a domain Will be described with reference to FIGS.

  First, the flow of the route domain setting process will be described with reference to FIG. In the initial state of the EEPROM 140, the values of the control information 151 are all 00h or FFh, as are the initial values of each data in the EEPROM 140. Whether the value is 00h or FFh is determined by the structure of the EEPROM 140, but the value of the domain number indicating the root domain ensures that the root domain is recognized even in the event of a failure. In consideration of this, it is desirable that the initial value of each data in the EEPROM 140 or a value after erasure is set.

  When the root domain setting process is started (step 301), the software for setting the root domain in the EEPROM 140 first sets the root domain in the domain control register 131 (step 302). When the root domain is set in the domain control register 131, the entire area of the EEPROM 140 becomes accessible. However, the domain control register 131 can be set only for a program in the root domain or a program on the ROM 124, and it is desirable that the user program cannot be changed by itself. If it is desired to limit the program in the ROM 124, domain management for the ROM 124 described above may be performed separately.

  Next, data is read from an address desired to be set in the root domain (step 303). At this time, the contents of the control information 151 of the target address are read into the domain setting register 133 at the same time. Next, the address control circuit 130 checks whether the current program counter refers to the ROM 124 or an area belonging to the root domain (step 304). If not, error processing is executed (step 309). When the error processing is performed by software, a register for setting an error state may be separately prepared and an NMI (Non-Maskable Interrupt) may be generated and processed.

  When the address referred to by the program counter is in the above area, the domain number 153 registered as the root domain, the control condition flag 154 and the value of the intra-domain address 155 are written in the domain setting register 133 (step 305) Data is written (step 306). In FIG. 3, 0 is specified as the domain number 153 in step 305, but this is an example setting, and the actual setting depends on the setting method of the root domain. At this time, the control information 151 is also written, and the setting of the data block 141 referred to by the address as the root domain is completed. In a system with only one OS, safety is improved by limiting addresses that can be a root domain to fixed values such as 00h and FFh.

  Next, it is confirmed whether there is another address to be set in the root domain (step 307). If there is, the process from step 303 to step 306 is repeated. If there is no other address to set, the process ends (step 308). In the processing flow of FIG. 3, for the sake of simplicity, the virtual address operation flag 157 and the back address flag 158 are set to invalid, and the intra-domain address 155 is not set. The operation when the virtual address operation flag 157 and the back address flag 158 are set will be described in the domain addition process.

  When the root domain setting process as described above is performed as part of the initialization process of the EEPROM 140, a series of processes from step 302 to step 307 may be automatically performed by hardware. In this case, the target address is incremented or decremented for each read unit, and the CPU is notified that the setting of the root domain for all target areas has been completed by setting or interrupting a dedicated register. It is also possible.

  Note that the setting process of the root domain is realized not only by the address control circuit 130 but also by the cooperation of the OS and the library operating on the root domain. Here, the process to be executed by the address control circuit 130 is step 304, and other processes may be executed by the OS or the like.

  Next, the flow of domain addition processing will be described with reference to FIG. First, when the domain addition process is started (step 401), the address control circuit 130 sets a parent domain in the domain control register 131 (step 402). When adding a domain, a child domain is usually created under the domain of its own, so that the domain of its own is set here, but this processing is performed when it is libraryed by the OS. Will set the root domain with the OS.

  In a normal implementation, the processing is prepared as an OS function, and is called from a request source program and executed. At this time, for the safety of the system, the software or hardware that performs the processing first determines whether the calling program belongs to the root domain or its child domain group. When the request source program belongs to the child domain group, the change of the domain control register 131 is permitted. Here, the child domain group is a general term for all the child domains directly in the domain and all child domains below the child domains.

  As a method for confirming whether or not it belongs to a child domain group, there are a method for determining based on the contents of the current domain control register 131, a method for confirming the integrity of a calling program, and the like. To check the integrity of the program here, the hash value of the target child domain program is managed in the root domain, and the hash value calculated from the calling program at the time of execution is managed in the root domain. For example, a method of comparing the stored hash value may be considered.

  These processes are performed in order to prevent a program illegally stored on the EEPROM 140 from adding a domain illegally using software or hardware for switching domains belonging to the root domain. As the scale of embedded systems increases, it is difficult for the OS to sequentially check the integrity of all storage areas. Therefore, by using the mechanism for adding the domain and the mechanism for confirming the integrity of programs and data in the domain by the root domain, there is an effect that the size of the storage area to be inspected can be reduced.

  Next, it is determined whether the address range to be newly added as a domain belongs to the requesting domain (step 403). Here, only the domain size may be specified, and the OS may determine the actual address space range. In this case, the OS confirms the erased state of the EEPROM 140 and determines whether or not a domain having a specified size can be added. In this case, the next step 404 may be omitted.

  Next, it is determined whether a range of addresses to be newly added as a domain can be secured in the request source domain (step 404). From the viewpoint of independence between domains, it is desirable that an address range for a new domain is not assigned from a range of addresses belonging to other domains excluding an area belonging to a requesting domain. If an address range is specified, the address range may be regarded as a free area and secured, or an error may occur if the data block 141 is not in an erased state. If the area cannot be secured due to a problem such as the size of the free area, error processing (step 411) is performed.

  If a sufficient free area for adding a new domain can be secured in the root domain and the domain of the request source program, the address is read (step 405). Here, it is determined whether or not the program counter refers to the ROM 124 or an area belonging to the root domain (step 406). If not, error processing is performed (step 411). When the execution of the domain addition process by the request source program is permitted, the domain of the request source program may be added to the reference destination of the program counter.

  When the program counter refers to the above area, the newly added domain number 153, control condition flag 154, and intra-domain address 155 are written to the domain setting register 133 (step 407), and data is written. (Step 408). At this time, the control information 151 is also written, and the domain addition of the block referred to by the address is completed.

  In FIG. 4, domain number 1 is specified in step 407, but this is an example. Alternatively, a domain number may be hierarchized and a number to be used in the domain number may be determined. For example, only the domain numbers 1, 11, 21... Are the child domains of the root domain (domain number 0), and the domain numbers 2-10, 12-20, 22-30,. Furthermore, it may be configured to be used when creating a child domain. In this case, since the domain hierarchy can be determined from the number, there is an effect that the table for domain number control can be simplified, and the consistency can be controlled by hardware.

  After the above processing, it is confirmed whether there is another address to be set in the domain (step 409). If there is, the process from step 405 to step 408 is repeated. If there is no other address to set, the process ends (step 410). If the allocation is performed according to the size as the process performed at the end, it may be reported which address is added as a domain to the request source program. The root domain may collectively manage the process of adding a domain to the EEPROM 140.

  The domain addition process is realized not only by the address control circuit 130 but also by the cooperation of the OS and the library operating on the root domain. Here, the process to be executed by the address control circuit 130 is step 406, and other processes may be executed by the OS or the like.

  Steps 403 and 404 can be realized by hardware if the domain structure is simple. In this case, it can be realized by setting the domain number of the domain to which the request source program belongs in the domain control register 131 when performing step 401. In this case, for example, if the hierarchy of the domain number system is managed so that the highest digit is the first generation domain number and the next digit is the second generation domain number as described above, the target The OS can determine from the domain number information whether the address to be included belongs to the child domain group of the domain to which the requesting program belongs, the domain management load by the OS is reduced, and the system safety is improved. There is an effect of doing. Such a mechanism is also effective in the domain deletion process described later.

  Next, in the domain addition process, a process for assigning a virtual address using the virtual address operation flag 157 and a process for multiplexing data using the back address flag 158 will be described.

  When performing address control using a virtual address, the value of the virtual address operation flag 157 is set to be valid. In this case, the OS sets the virtual address to be assigned to the intra-domain address 155 based on the size specified when the domain addition request is made. The virtual address at this time may be assigned from the top address of the EEPROM 140 so that it can be easily controlled by the OS.

  For example, if the OS wants an individual program to behave as if it can access all areas of the EEPROM 140, the start address of the virtual address space may be the same value as the start physical address of the EEPROM 140. . Further, when the OS prepares a virtual address space for each program and a certain address space is defined for the EEPROM 140 on the system, the address of the virtual address space is used as it is as the virtual address of the EEPROM 140. Can do.

  In the control of the flash memory, when accesses to the same physical address block are continued, the number of erasures of the address block increases, and a defect is likely to occur. Thus, when a certain number of rewrites occur, the number of rewrites can be distributed by replacing the target physical address. In such a case, operation using a virtual address may be used. In this case, the physical address for the virtual address may be assigned sequentially, or an algorithm that is uniformly distributed based on the size of the domain may be used.

  In addition, the address control circuit 130 and the OS make the domain size larger than the requested size and prepare an area to which no virtual address is allocated in the initial state. By writing data to the area and erasing the previous data after the write is completed, the system is designed to take measures against failures such as loss of previous data and data to be rewritten when the power is interrupted during rewriting. May be.

  As the size of the EEPROM 140 increases, it becomes difficult to manage the address space of the EEPROM 140. However, with domain management, the area where rewriting occurs frequently and the area where only read-out occurs are managed as separate domains, and a virtual address that is valid only within that domain is assigned to manage the load on that address space. Can be greatly reduced. This is effective not only for the method exemplified above but also for the whole mechanism using virtual addresses.

  When multiplexing the data block 141 using the back address, a valid value is set in the back address flag 158. In this case, the same virtual address is assigned to the intra-domain address 155 for a plurality of physical addresses, and the rewrite order is set by the back address flag 158 for the data block 141 to which the same virtual address is assigned. .

  For example, when the target virtual address is duplicated, the back address flag 158 needs at least 2 bits of information. In this case, for a plurality of data blocks 141 corresponding to the same virtual address, 01B (1) → 10B (2) → 11B (3) → 01B (1) →... According to the value of each back address flag 158. , Which data block 141 is the latest data.

  In this case, two data blocks 141, which are set to 01B in the back address flag 158 in the initial state, and a data block 141 which is set to 10B are prepared. Here, when rewriting occurs in the state where the back address flag 158 is 01B and 10B, the data is rewritten to the data block 141 of the older 01B, and after rewriting, the value of the back address flag 158 of the target data block 141 is rewritten. Is updated to 11B. In addition, when reading occurs in the state where the back address flag 158 is 01B and 10B, the newer 10B data block 141 is read.

  When rewriting occurs in the state where the back address flag 158 is 10B and 11B, rewriting to the data block 141 of the older 10B is performed, and after rewriting, the value of the back address flag 158 of the target data block 141 is changed. Update by wrapping in 01B. Further, when reading occurs in the state where the back address flag 158 is 10B and 11B, the data block 141 of the newer 11B is read. If rewriting occurs with the back address flag 158 being 01B and 11B, rewriting is performed to the data block 141 of the older 11B, and after rewriting, the value of the back address flag 158 of the target data block 141 is set. Update to 10B. In addition, when reading occurs in the state where the back address flag 158 is 01B and 11B, the newer data block 141 of 01B is read.

  Here, if the value of the back address flag 158 is 00B (0), it means that the back address flag 158 is not set. This is an example when the data value of the EEPROM 140 in the initial state or the erased state is 00B. Conversely, if the erase state value of the EEPROM 140 is 11B, 00B (0) → 01B (1) → 10B (2) → 00B (0) →... According to the value of the back address flag 158 in the above description. In this order, it indicates which is the latest data, and the state where the back address flag 158 is not set is 11B (3).

  The reason for determining the state where the back address flag 158 is not set as described above is whether the state of the back address flag 158 is valid or invalid when the power is cut off while the data is erased. This is for determining. If the status of the back address flag 158 is cleared due to power interruption during data erasure, etc., the value is not set in the check after restart even though the back address flag 158 is a registered domain An error can be detected by being in a state. Further, by examining the intra-domain address 155 of the data block 141 in the domain and finding the data block 141 in which the intra-domain address is not duplicated, which data block 141 in which the back address flag 158 is not set is originally set. It is also possible to grasp whether the virtual address has been assigned, and the data block 141 can be re-registered.

  Next, the flow of processing for accessing a domain will be described with reference to FIG. Access to a domain can be read, write, delete, etc., and access to a domain can be managed by preventing a program from freely changing programs and data on another domain, A mechanism to allow limited changes for sharing and delivery is required.

  When access to the domain occurs (step 501), the address control circuit 130 first reads the data block 141 of the address to be accessed (step 502), and when the domain type flag 156 is set, the access requirement (read, It is determined whether or not (write etc.) is satisfied (step 503).

  When an access to a domain other than its own domain occurs, the address control circuit 130 operates according to the setting of the domain type flag 156 if the access destination is a parent domain and a domain having the same parent domain. In other cases, the domain number is managed by a system in which the highest digit is the first generation domain number and the next digit is the second generation domain number, so that the access destination is the same route. Whether it belongs to a domain can be determined. In actual operation, it is desirable to rewrite data from the parent domain. If it is desired to share data and exchange data between child domains having the same parent domain, it is desirable to do so via the parent domain.

  When accessing a domain, in the case of access to a domain in which the virtual address operation flag 157 is set to be valid, the domain is searched, and the data block 141 having the in-domain address 155 that matches the target address is read out. . In the case of access to a domain for which the back address flag 158 is set to be valid, the data block 141 having the same intra-domain address 155 is read, the latest data block 141 is determined according to the above-described procedure, and the data Read block 141.

  The access type is set to the access type 135 in the domain control register 131. When the access type 135 is read, the domain type flag 156 needs to be set to “Readable”, and the write type In the case of erasing, it is necessary to set “reading / rewritable”. This is not the case when the access source domain is a direct higher domain such as a parent domain or a root domain.

  If this condition is not satisfied, error processing is performed (step 509). If the condition is satisfied, the process type is determined (step 504). If read, the read data is transferred to the request source (step 505), and the process ends (step 508). In the case of rewriting, the data to be rewritten and the contents of the read data are merged and written (step 506), and the process is terminated (step 508). In the case of erasure, data erasure processing is executed (step 507), and the processing is terminated (step 508).

  Note that the domain access processing is realized not only by the address control circuit 130 but also by the cooperation of the OS and the library operating on the root domain. Here, the processing to be executed by the address control circuit 130 is step 503, and the other processing may be executed by the OS or the like.

  Next, the flow of domain deletion processing will be described with reference to FIG. When there is no free space in the EEPROM 140 due to the addition of a domain, or when the domain becomes unnecessary, a process for deleting the domain is required. When deleting a domain (step 601), the OS first sets a root domain in the domain control register 131 (step 602). Next, it is determined whether the address to be deleted belongs to a child domain of the requesting domain (step 603). When deleting a domain, in order to maintain independence between the domains, it is desirable not to delete itself and a domain higher than itself. If it does not belong to the child domain of the requesting domain, error processing is performed (step 610).

  If it belongs to the child domain of the request source, it is checked whether or not the current program counter refers to the ROM 124 or an area belonging to the root domain (step 604). Otherwise, error processing is performed (step 610). When the execution of the deletion program in the request source domain is permitted, the request source domain may be added to the reference destination of the program counter. If the current program counter refers to the ROM 124 or an area belonging to the root domain, the data at the target address is deleted (step 605).

  Thereafter, the domain number of the request source is designated as the domain number 153, and information designating the contents of the control condition flag 154 in accordance with the criteria of the request source domain is written to the domain setting register 133 (step 606), and the contents are erased. The written data is written (step 607). The deleted domain area usually returns to the parent domain. Here, the setting contents described in step 606 of FIG. 6 are an example, and these settings depend on the setting of the domain to which the deleted address belongs.

  After the processing in step 607, it is determined whether there are other addresses to be deleted (step 608). If there are, addresses 603 to 607 are repeated. If there is no other address to be deleted, the process ends (step 609). When deleting a domain, not only the specified domain but also child domains belonging to the specified domain are included in the deletion target.

  Note that the domain deletion process is realized not only by the address control circuit 130 but also by the cooperation of the OS and the library operating on the root domain. Here, the process to be executed by the address control circuit 130 is step 604, and other processes can be executed by the OS or the like.

  As described above, step 603 can be realized by hardware when the domain structure is simple. In this case, this can be realized by setting the domain number of the domain to which the request source program belongs in the domain control register 131 when performing step 601. In this case, for example, if the domain number system is hierarchically managed such that the highest digit is the first generation domain number and the next digit is the second generation domain number, the target address is Whether the OS belongs to the child domain group of the domain to which the request source program belongs can be determined by the OS from the domain number information, and the domain management load by the OS is reduced, and the system safety is improved. is there.

  As described above, when a storage medium such as a flash memory is used to execute an application in a CPU or IC card chip for an embedded system, it operates on the domain by defining and managing the domain in the storage medium area. Each application can access the area of the storage medium only within the range permitted by the domain setting. In addition, the domain is managed hierarchically, and the domain settings cannot be changed by themselves, but can only be changed by the root domain or the parent domain. It can operate without fear of unauthorized access.

  In addition, since domain management settings can be made flexibly as described above, it is possible to manage the sharing of areas between applications, such as data exchange between applications and library sharing. . Furthermore, by using a virtual address in addition to the above domain management and duplicating data, it is possible to maintain data consistency against a failure such as a power shutdown during data rewriting, thereby ensuring availability.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a control circuit that performs area management of a storage medium having an erasable and rewritable storage area, in particular, a nonvolatile storage medium such as a flash memory, a processing device for a general purpose or embedded system having the control circuit, and the processing The present invention can be used for an embedded system having a device and an area management method for the storage medium.

It is a figure showing the structure of the processing apparatus which is one embodiment of this invention, and the storage medium connected to the said processing apparatus. It is a figure showing the example of the hierarchical structure of the domain in one embodiment of this invention, and the relationship with the area | region of EEPROM. It is a figure showing the flow of the setting process of the root domain in one embodiment of this invention. It is a figure showing the flow of the addition process of the domain in one embodiment of this invention. It is a figure showing the flow of the process at the time of access to the domain in one embodiment of this invention. It is a figure showing the flow of the deletion process of the domain in one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... IC card, 110 ... Input / output IF, 111 ... VCC line, 112 ... RST (reset signal line), 113 ... CLK (clock signal line), 114 ... GND line, 115 ... I / O (input / output line), DESCRIPTION OF SYMBOLS 120 ... Processor, 121 ... UART control circuit, 122 ... CPU, 123 ... RAM, 124 ... ROM, 125 ... Coprocessor, 126 ... Internal bus, 130 ... Address control circuit, 131 ... Domain control register, 132 ... Virtual address space Register, 133 ... Domain setting register, 134 ... Domain number, 135 ... Access type, 140 ... EEPROM, 141 ... Data block, 151 ... Control information, 152 ... Data area, 153 ... Domain number, 154 ... Control condition flag, 155 ... Intra-domain address, 156 ... domain type flag, 157 ... virtual Dress operation flag, 158 ... back address flag,
200 ... Domain # 0, 210 ... Domain # 1, 220 ... Domain # 2, 221 ... Domain # 21, 222 ... Domain # 22, 230 ... Domain # 3, 250 ... Address space # 0, 270 ... Address space # 2, 271: Address space # 21, 272: Address space # 22.

Claims (20)

In a processing apparatus having a CPU and a erasable and rewritable storage medium, a predetermined area of the storage medium is set as a domain, and management of the domain and management of access requirements when the program uses the domain A control circuit,
A first register for setting control information for management of the domain in the storage medium, and a second register for holding information about the domain that is the current processing target;
Using the information in the first register, for the address on the storage medium, set the control information for the domain to which the data area assigned to the address belongs,
When accessing a data area assigned to an address on the storage medium by a program, whether or not the access is possible is determined based on the control information set in the address and the information in the second register. A control circuit characterized by judging. In a processing apparatus having a CPU and a erasable and rewritable storage medium, a predetermined area of the storage medium is set as a domain, and management of the domain and management of access requirements when the program uses the domain A control circuit,
A first register for setting control information for management of the domain in the storage medium, and a second register for holding information about the domain that is the current processing target;
Using the information in the first register, for the address on the storage medium, set the control information for the domain to which the data area assigned to the address belongs,
When the program adds a new domain to the address on the storage medium or deletes the other domain from the address on the storage medium, the control information set in the address, and the first 2. A control circuit for determining whether or not the processing can be performed based on the information in the register 2 and the information on the storage location of the program. The control circuit according to claim 1 or 2,
A control circuit, wherein when a program attempts to change the values of the first register and the second register, whether or not the program is possible is determined based on information on a storage location of the program. The control circuit according to claim 1 or 3,
The domain is managed hierarchically, and the parent-child relationship between the domain used by the program and the domain to which the data area belongs when the program accesses the data area assigned to the address on the storage medium And determining whether or not the access is possible. The control circuit according to claim 2 or 3,
The domain is managed in a hierarchical manner, and is used by the program when the program adds a new domain to the address on the storage medium or deletes the other domain from the address on the storage medium. A control circuit, comprising: determining whether or not the processing is possible based on a parent-child relationship between the domain and the domain to which a data area assigned to the address belongs. The control circuit according to claim 4, wherein
When a program accesses a data area assigned to an address on the storage medium, access to a data area belonging to the domain below the domain used by the program is permitted, and other domains are allowed to access the data area. The access to the data area to which the data belongs belongs to determine whether or not the access is possible based on the control information set in the address corresponding to the data area and the information in the second register. Control circuit. The control circuit according to claim 5, wherein
The domain is managed in a hierarchical manner, and is used by the program when the program adds a new domain to the address on the storage medium or deletes the other domain from the address on the storage medium. Addition of a new domain under the domain or deletion of another domain under the domain is permitted, and addition of a new domain other than that or deletion of the other domain is not permitted. . The control circuit according to any one of claims 4 to 7,
A control circuit for discriminating a parent-child relationship between the domains based on a system of numbers assigned to the domains. The control circuit according to any one of claims 1 to 8,
A control circuit characterized in that a virtual address is assigned to an address on the storage medium so that a program accesses a data area assigned to the address by the virtual address. The control circuit according to claim 9, wherein
A control circuit that multiplexes a data area specified by a virtual address by assigning the same virtual address to a plurality of addresses on the storage medium.   11. An erasable and rewritable storage medium storing the control information set by the control circuit according to claim 1.   A processing apparatus comprising: the control circuit according to claim 1; and the erasable and rewritable storage medium according to claim 11.   An embedded system comprising the processing device according to claim 12. A processing device having a CPU and a erasable / rewritable storage medium sets a predetermined area of the storage medium as a domain, and manages the domain and management of access requirements when the program uses the domain An area management method,
The processing device sets, for an address on the storage medium, control information for the domain to which a data area assigned to the address belongs,
When accessing a data area assigned to an address on the storage medium by a program, based on the control information set to the address and information about the domain that is the current processing target, An area management method characterized by determining whether or not access is possible. A processing device having a CPU and a erasable / rewritable storage medium sets a predetermined area of the storage medium as a domain, and manages the domain and management of access requirements when the program uses the domain An area management method,
The processing device sets, for an address on the storage medium, control information for the domain to which a data area assigned to the address belongs,
When the program adds a new domain to an address on the storage medium or deletes another domain from the address on the storage medium, the control information set in the address and the current An area management method comprising: determining whether each process is possible based on information about the domain to be processed and information on a storage location of the program. The area management method according to claim 14 or 15,
The processing device, when the program tries to change the control information and the information about the domain that is the current processing target, determines whether or not the program is possible based on the storage location information of the program. Space management method. The area management method according to claim 14, wherein
The processing device manages the domain in a hierarchical manner, and when the program accesses a data area assigned to an address on the storage medium, the domain used by the program and the data area to which the data area belongs An area management method comprising: determining whether access is possible based on a parent-child relationship with a domain. The area management method according to claim 15, wherein
The processing device manages the domain in a hierarchical manner, and in the process of adding a new domain to an address on the storage medium by a program or deleting another domain from the address on the storage medium, An area management method comprising: determining whether or not the process is possible based on a parent-child relationship between the domain used by the program and the domain to which the data area assigned to the address belongs. The area management method according to claim 17, wherein
When the program accesses the data area assigned to the address on the storage medium by the program, the processor permits the access to the data area belonging to the domain below the domain used by the program, For the access to the data area belonging to the domain other than, based on the control information set in the address corresponding to the data area and the information about the domain that is the current processing target, A region management method characterized by determining whether or not it is possible. The area management method according to claim 18, wherein
The processing device manages the domain in a hierarchical manner, and in the process of adding a new domain to an address on the storage medium by a program or deleting another domain from the address on the storage medium, The addition of a new domain under the domain used by the program or the deletion of another domain under the domain is permitted, and the addition of another new domain or the deletion of another domain is not permitted. Characteristic area management method.

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