JP2008310414A - Computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce access request processing time by reducing the number of snoop issue for holding cache coherency. <P>SOLUTION: A computer system connected to a plurality of nodes comprises: an address in prescribed units of a cache; a fine grain snoop filter for managing state information indicating which processor has a memory data copy of the address; and a fine grain snoop filter that divides a memory area into a plurality of memory spaces, and has an entry for managing state information indicating that a data copy included in each memory space is present in the cache entry of the processor. For the cache address of the data copy accompanied by an access request and the state information indicating the processor caching the address, the fine grain snoop filter and a rough grain snoop filter are compared, and a snoop is issued to a related processor according to the result of comparison. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a computer system, and more particularly, to a snoop issue control using a snoop filter in a multiprocessor system.

A multiprocessor system having a shared memory architecture in which a plurality of nodes each having a main memory and one or more processors having a cache memory are connected via a network is known.

  In a multiprocessor system having multiple processors, one processor can perform another computational task while one processor performs another computational task. In addition, the execution time of the entire system can be reduced by distributing a specific calculation task to a plurality of processors.

  In order to increase the processing speed, a memory system having a multi-tier structure including a small-scale high-speed memory called a cache is employed. This cache is typically either physically embedded in the processor integrated circuit or physically implemented near the processor. In some cases, the instruction cache and the data cache exist separately, or there may be a multi-level cache.

  Some caches may be shared by a plurality of processors, and all processors and caches can share the same main memory. A particular line can exist simultaneously in the cache hierarchy of memory and multiple processors. However, the cached memory copy must be the same and up-to-date between shared processors. This characteristic is called coherency.

  There may be only one holder “owner” in the line. A cache "holds" a line when the cache is allowed to change the line without issuing further coherency transactions. Any cache coherency protocol needs to obtain an up-to-date copy of the cache line from the owner (if present) and provide a copy of this data to the requester. When updating or acquiring a line, the requester must acquire ownership and all shared copies must be disabled.

To determine where a line owner exists, use either a snoop-based cache coherency protocol or a directory-based cache coherency protocol.
In the snoop-based protocol, the owner (owner) of the data copy of the memory is unknown, and it is necessary to query (snoop) all the caches to determine the position of the latest copy of the requested line. All access requests to the cache line by any device in the system are forwarded to all caches in the system. Eventually, the location where the latest copy of the line exists is identified and a copy is provided to the requester.

  In directory-based protocols, memory is provided to hold information about the state of each line in memory. For example, for each line in memory, the directory may include a bit for each cache hierarchy that indicates whether the cache hierarchy holds a copy of the line and whether the cache hierarchy has ownership. . For each cache line access request, it is necessary to query the directory to determine the owner. Then get the latest copy of the line and serve it to the requester. In general, directory tags and status bits are stored in the main memory, so a request for state information triggers a main memory cycle, and main memory call time occurs.

When a snoop is issued, the completion processing for the request is performed after all responses are received. Therefore, if the number of issued snoops is large, it takes time to process the request. Therefore, a method using a snoop filter is known in order to prevent a snoop broadcast. For example, Patent Document 1 (Japanese Patent Laid-Open No. 10-222423) has a copy tag indicating the cache state of all data existing in the cache memory, and snoops to the cache memory only when the data has the latest value. A snoop filter is disclosed.
In this manner, the number of snoops issued can be reduced by using the snoop filter, and the time required for the processor to access the memory in the multiprocessor system can be reduced.

Japanese Patent Laid-Open No. 10-222423

  Usually, in the snoop filter, the line address and the state information indicating the processor that caches the address are compared, and if it is found that the address is hit and the line is held, the snoop can be limited. . In addition, if there is no line owner even if the address hits, it is possible to prevent the snoop from being issued.

  However, when a request for an address not registered in the entry is received, the snoop is broadcast. Normally, it is difficult to prepare an entry for storing information about the entire memory space in the snoop filter because of physical size and mounting cost. When the size of the memory space that the processor actually accesses exceeds the size of the memory space that can be handled by the snoop filter, the snoop filter is overwritten. This overwriting of the snoop filter entry may cause a snoop filter error and may cause a snoop broadcast.

  Further, in a normal snoop filter, registration and update to an entry are performed due to reception of a request. A snoop is broadcast without being hit at the time of start-up or after initialization without registration information in the entry.

  An object of the present invention is to reduce the number of issued snoops for maintaining cache coherency, to reduce request processing time, and to make a multiprocessor system function efficiently.

The computer system according to the present invention is preferably a computer system in which a plurality of nodes are connected, each node having a main memory, at least one processor having a cache memory, and a node controller for controlling between the nodes. In a computer system having a snoop filter that manages snoop issuance to maintain cache coherence, and a processor at one node can access main memory at another node,
As the snoop filter, a fine-grained snoop filter that manages a predetermined unit address of the cache acquired by accessing the memory by the processor, and state information indicating which processor has a memory data copy at the address;
The memory area is divided into a plurality of memory spaces larger than a predetermined unit size of the cache, and an entry for managing state information indicating that a data copy of the memory space included in each memory space exists in the cache entry of the processor A coarse-grained snoop filter having the entire memory area;
A registration control unit that registers a predetermined unit address of the cache accompanying the access request and the state information in the fine-grained snoop filter and the coarse-grained snoop filter;
A collation unit that collates with the information registered in the fine-grained snoop filter and the coarse-grained snoop filter for the cache address of the data copy accompanying the access request and the status information indicating the processor that caches the address;
The computer system includes a snoop issuance control unit that controls the issuing of snoops to related processors according to the result of collation by the collation unit.

The present invention can also be applied to a global Knoop filter for access requests from remote nodes in a computer system in which a plurality of nodes are connected.
In a preferred example, the predetermined unit of the cache is described as a line of the cache, but it can also be applied to a block or page unit of the cache.
In the case of a cache line, the coarse-grained snoop filter may divide the entire memory space into multiple memory spaces larger than the cache line size, and each of the multiple processors may hold one or more lines in that space. Register status information indicating
The fine-grained snoop filter registers a line address storage unit that stores a cache tag, a status information unit that indicates whether each of a plurality of processors holds a cache line, and a valid bit that indicates that an address is valid.
In addition, in a preferred example, the system includes a reset control unit that substantially invalidates information of entries registered in the coarse-grained snoop filter and the fine-grained snoop filter when the system is started or initialized.

  According to the present invention, using a coarse-grained snoop filter in which all addresses are divided into a plurality of memory spaces and a fine-grained snoop filter, the information held in the memory copy of the accessed address is managed, and the snoop issuance is controlled based on the information. As a result, the number of snoops issued to processors other than the processor holding the memory copy can be reduced. Thereby, the number of transactions in the system can be reduced and the efficiency of the entire system can be increased. Also, by clearing the entry registration of the snoop filter at the time of activation, the number of snoop issues can be reduced from the time of activation.

An embodiment of the present invention will be described below with reference to the drawings.
Reference is made to the computer system shown in FIG.
This computer system constitutes an SMP (shared memory) type system in which four nodes 100a to 100d are respectively connected by a connection line 160 and can access main memories of other nodes. Each node has the same configuration, and includes three processors CPUA 110a, CPUB 110b, and CPUC 110c each having a cache memory 120, a main memory 130, and a node controller 140 having a snoop filter 150. The node controller 140 performs control between the nodes.

  The CPU 110 is connected to the main memory 130 in its own node via connection lines 180a to 180c, and can directly access the memory. When the CPU 110 accesses the main memory 130 in the remote nodes 100b to 100d, it is performed via the node controller 140 from the connection lines 170a to 170c.

FIG. 2 shows the configuration of the snoop filter 150.
The snoop filter 150 has two snoop filters, a coarse grain snoop filter (Coarse grain) 32 and a fine grain snoop filter (Fine grain) 34 therein. The address requested to be accessed is input from the input 30 to the snoop filter 150 and further input to the coarse-grained snoop filter 32 and the fine-grained snoop filter 34 for processing. The results processed by the coarse-grained snoop filter 32 and the fine-grained snoop filter 34 are integrated and the snoop issue destination is output from the output 31.

FIG. 3 shows configurations of a coarse-grained snoop filter and a fine-grained snoop filter, and represents information registered by each filter.
The coarse-grained snoop filter 32a divides the entire memory space into a plurality of memory spaces larger than the cache line size, and a state information unit 33 indicating that the processor may hold one or more lines in the space. Exists.

In the example shown in the figure, all address spaces of all nodes in the system are divided by 512 units, and the status information unit 33 indicates that one bit is provided for each processor. In this embodiment, there are 3 processors in the node, so 3 bits. When it is set to “1”, it indicates that there is a possibility that the processor set in the area has one or more lines.
The fine-grained snoop filter 34a includes a line address storage unit 35 that stores a cache tag, a status information unit 36 that indicates which processor holds the line, and a valid bit 37 that indicates that the address is valid. Consists of. The number of entries depends on the implementation. The line address storage unit 35 prepares for the bit width of the line address. Similarly to the state information unit 33, the state information unit 36 has a bit width corresponding to the number of processors.

FIG. 4 shows a specific control block configuration of the snoop filter.
The coarse grain snoop filter 32 outputs the state information 33 of the area including the address requested from the access request 50. The comparator 51 compares the address of the input access request 50 with the address storage unit 35 of the fine-grained snoop filter 34 line by line, and outputs a hit or miss. The fine-grain snoop filter 34 outputs line status information 36.

  The selector 52 selects whether to output the cache information of the coarse-grained snoop filter 32 or the fine-grained snoop filter 34 based on the hit check result output from the comparator 51. In the case of a hit, the selector 52 selects to output the cache information of the fine-grained snoop filter 34. At this time, the fine-grained snoop filter 34 outputs cache information that matches the address of the access request. On the other hand, in the case of a miss, the selector 52 selects the cache information of the coarse grain snoop filter 32. In this case, the cache information of the area including the address of the access request of the coarse grain snoop filter 32 is output.

The access request 50 is also input to the snoop issue control unit 54 to determine whether snoop issue is necessary. Here, it is determined that snoop issuance is necessary in the case of a READ request, and it is determined that it is unnecessary in the case of a WRITE request. The determination result in the snoop issue control unit 54 is input to the snoop generator 53 to control snoop generation and issue. When it is determined that snoop issuance is necessary, the generated snoop is output from the output 55. If it is judged unnecessary, snoops are not generated or issued.
The response totaling logic 56 totalizes the response of the access request and outputs which processor owns the cache line. The coarse-grained snoop filter 32 updates the owner information of the area including the address of the access request from the result from the response aggregation logic 56.

  The information registration control unit 57 performs control for registering information in the fine-grained snoop filter 34, and configures and registers an entry including an address storage unit 35, a status information unit 36, and a valid bit 37. More specifically, when the access request 50 is input, the address of the access request 50 is registered in the address storage unit 35. The line owner information output from the response counting logic 56 is registered in the status information unit 36 of the information registration control unit 57. In the entry information, the valid bit 37 is set to “1” and added to the empty entry of the snoop filter. If there is no vacancy, the entry is removed after the entry by FIFO or LRU method.

  The reset control unit 58 receives a reset command at startup or initialization, and resets the entries of the coarse-grained snoop filter and the fine-grained snoop filter 34. The coarse-grained snoop filter 32 that has received the reset instruction clears all entry state information. Further, the fine-grained snoop filter 34 that has received the reset instruction resets the valid bits 37 of all entries to “0”.

FIG. 5 shows an example of a set associative method for determining a cache miss hit of the fine-grained snoop filter.
Reference numeral 40 denotes a tag which is an upper bit of the memory address, reference numeral 41 denotes an intermediate index of the memory address excluding the bit of the lowest line size of the memory address, and reference numeral 42 denotes an offset address. The fine-grained snoop filter can adopt a set associative method, a direct map method, or a full associability method.

  When the local processor attempts to cache a copy of the memory belonging to the remote node, it registers with the coarse-grained snoop filter and the fine-grained snoop filter. In the coarse-grained snoop filter 32a of FIG. 3, information is registered by setting the bit corresponding to the processor holding the copy of the line to “1” in the cache status information 33 of the entry corresponding to the address.

  In the fine-grained snoop filter 34a shown in FIG. 3, the entry is searched for registration. If there is no entry registration, an empty entry is searched. If there is an entry, the valid bit 37 is set to “1”. Then, the address portion 35 of the entry corresponding to the corresponding address is registered, and information registration is performed by setting the bit corresponding to the processor holding the copy of the corresponding line in the cache status information to “1”. If there is no empty entry, the valid entry is cleared and registered. If there is an entry registered in the fine-grained snoop filter 34a, the bit corresponding to the requested processor is set to “1”, otherwise it is set to “0”.

For example, in FIG. 1, when the CPU 110c issues a read request to the memory address of “000011000000” of the remote node, as shown in FIG. The bit of the processor C is set and the C bit of the address “000011000000” is set in the fine-grained snoop filter 34b.
At the time of initialization and reset, all the state information 33 of the coarse-grained snoop filter 32a and the entry valid bits of the fine-grained snoop filter 34a are cleared.

  As indicated by the input 30 in FIG. 2, the requested address is input to the memory, and it is determined whether the address requested by the coarse-grained snoop filter 32 is registered in the state information 33 in FIG. At the same time, it is determined whether or not there is registration in the status information 36 and the matching confirmation with the address storage unit 35 of the fine-grain snoop filter 34. Judgment is made from the output results of the coarse-grained snoop filter 32 and the fine-grained snoop filter 34, and the processor that issues the snoop is determined.

  The example of FIG. 6 shows that the CPU 110c may have a cache line in the area from the address “000000000000” to “000100000000” of the coarse-grained snoop filter 32b. From the fine-grained snoop filter 34b, if the "000011000000" line is possessed by the CPU 100c, and the "001110000000" line is possessed by the CPU 110a, the owner (processor) for the requested address is determined.

  When the processor issues a READ request to the main memory of the remote node, the coarse grain snoop filter 32 and the fine grain snoop filter 34 check whether the owner of the line is in the node. When an access request comes, the snoop issue destination is determined from the entry registration information of the coarse-grained snoop filter and the fine-grained snoop filter.

If the requested address is not registered in the status information 33 of the coarse-grained snoop filter 32a, if the status information 33 of the coarse-grained snoop filter 32a corresponding to the requested address is all “0”, It can be determined that the processor does not hold the line. Therefore, in this case, no snoop is issued.
The requested address hits the state information 33 of the coarse-grained snoop filter 32a and is registered in the address storage unit 35 of the fine-grained snoop filter 34a, but there is no processor set in the state information unit 36. In this case, since there is no registration in the status information, it can be determined that there is no holder of the line, so no snoop is issued.

  The case where the snoop is issued is a case where the requested address hits the status information 33 of the coarse-grained snoop filter 32a but does not hit the address storage unit 35 of the fine-grained snoop filter 34a. In this case, the snoop is multicast only to the processors registered in the coarse-grained snoop filter 32a.

  Further, when the requested address is registered in the state information 33 of the coarse-grained snoop filter 32a, hits the address storage unit 35 of the fine-grained snoop filter 34a, and is registered in the state information unit 36. Since the holder information is registered for the line address, a snoop is issued only to the holder of the address line.

FIG. 7 shows an operation example of a memory access request from the local node to the remote node.
The illustrated example shows a case where a read transaction 170c is issued from the node 100a to the memory of the remote node 100b. A memory access access request 160b is issued from the CPU 110c of the node 100a to the node 100b. First, the node controller 150 is accessed. Here, when accessing the memory “000011000000” of the node 100b, the address and status information are registered as in the coarse-grained snoop filter 32c and the fine-grained snoop filter 34c in FIG.

  The example in FIG. 9 shows that both the processors 100a and 100b have copies in the coarse-grained snoop filter 32d, but when the fine-grained snoop filter 34d is hit, anyone other than the processor 100c has the line. It shows no. In this case, the retained information of the coarse-grained snoop filter 32d can be determined to be information related to another cache line in the same memory area managed by the coarse-grained snoop filter, and the snoop is suppressed using the information of the fine-grained snoop filter 34d. can do.

  The example of FIG. 10 shows that the coarse-grained snoop filter 32e is registered in the status information, but the fine-grained snoop filter 34e has no address registration and no owner registration. There is a limit to the number of entries that can be registered in the fine-grained snoop filter 34e, and addresses that have conflicted indexes may be overwritten from entries in the fine-grained snoop filter 34e. In this case, since it indicates that the coarse-grained snoop filter 32e may own the line, the snoop is broadcast to the processors 110a and 110b by 170a and 170b as shown in FIG.

  FIG. 12 shows a case where the accuracy is improved by hitting the fine-grained snoop filter 34f. From the registration status of the fine-grained snoop filter 34f, it can be seen that the CPU 100a owns the line with the address “000011000000”, so the snoop 170a is issued to the CPU 110a as shown in FIG.

  The example of FIG. 14 shows a case where a line is shared by a plurality of CPUs. The state information of the coarse-grained snoop filter 32g and the fine-grained snoop filter 34g is registered, and the fine-grained snoop filter 34g has a line “000011000000” shared by the CPUs 110a and 110b. In this case, a snoop is issued to each of the CPUs 110a and 110b sharing the line.

When a reset command is received at startup or initialization, the entry control information of both snoop filters is reset as shown in FIG. When resetting the coarse-grained snoop filter 32h, it is necessary to reset the fine-grained snoop filter 34h and purge all the cache.
In order to improve the performance of the coarse-grained snoop filter, it is preferable to perform the reset when the processor or partition is reset or when the effect of the coarse-grained snoop filter is reduced. At that time, one line of coarse-grained snoop filter is shared by multiple lines, so it is difficult to reset by hardware. After a cache purge is performed by software, a coarse-grained snoop filter reset command is issued. To reset.

  FIG. 16 shows that a READ transaction has been issued from the remote node 100b to the node 100a. An access request is issued from the node controller 240 to the CPU 110a, and a snoop is issued via the snoop filter 250 having a global property.

  The configuration of this global snoop filter is shown in FIG. The area of the coarse-grained snoop filter 70 having a global property is a plurality of memory spaces obtained by dividing the address of the local main memory, and the owner 71 becomes a node. In the figure, R1, R2, and R3 indicate remode node 1 (100b), remode node 2 (100c), and remode node 3 (100d), respectively, and L indicates a local node.

  Similarly, the holder 73 for the address storage unit 72 of the fine-grained snoop filter 75 having a global property indicates a node. 74 is a valid bit indicating whether or not the line is valid. Similar to the above description, the filter is registered in the coarse-grained snoop filter 70 and the fine-grained snoop filter 75 because a request is issued from a remote processor. When a request from a remote node is received, a node requested in an area including the requested address is registered in the coarse-grained snoop filter 70, and the referenced address and the requested node are registered in the fine-grained snoop filter 75. Record.

  In the example of FIG. 16, if the access request from the node 1 requests the line “000011000000”, it can be seen from the entry information of FIG. 17 that the nodes 2 and 3 are owned. It is registered that the node 1 is owned by the entry in the area from “000000000000” to “000100000000” of the coarse-grained snoop filter 70, and the node “000011000000” is owned by the node 1 of the fine-grained snoop filter 75. sign up. Then, a snoop is issued to the nodes 2 and 3 as shown in FIG.

  In addition, this invention is not limited to an above-described Example, Various modifications can be implemented. For example, in the above embodiment, the snoop issuance control is performed on the assumption that the cache is configured around a memory amount called a line. However, a cache may be configured around a memory amount called a block or page. In this case, the line in the above embodiment is a predetermined memory unit such as a block or a page, and snoop control is performed in this predetermined memory unit. This can be easily understood without any special explanation.

The figure which shows the structure of the computer system in one Example. The figure which shows the structure of the snoop filter which has both the coarse grain snoop filter and fine grain snoop filter in one Example, The figure which shows the structure of the coarse grain snoop filter and fine grain snoop filter in one Example, The concrete control block diagram of the snoop filter in one Example, The figure which shows the operation example in the set associative system in one Example, The figure which shows the operation example of the entry registration of the coarse grain snoop filter and fine grain snoop filter in one Example, The figure which shows the operation example of the memory access request | requirement from the local node in one Example to a remote node, The figure which shows the operation example of the entry registration at the time of the first starting and reset in one Example. The figure which shows the example of an entry when it cannot specify where the applicable line exists in one Example, The figure which shows the example of an entry when the applicable line in one Example does not exist in an entry, The figure which shows the operation example in the case of broadcasting the snoop in one Example. The figure which shows the example of an entry which the processor in a local node possesses the data of the applicable line in one Example. The figure which shows the operation example which issues a snoop only to the owner of a line from the registration information of the fine grain snoop filter in one Example. The figure which shows the example of an entry in case the processor in a local node shares the remote line in one Example. The figure which shows the example of an entry at the time of initialization and reset in one Example. The figure which shows the operation example in the global snoop filter in one Example. The figure which shows the structure of the global snoop filter in one Example.

Explanation of symbols

100a, 100b, 100c, 100d: nodes,
110a, 110b, 110c: processors,
120a, 120b, 120c: cache memory,
130: main memory, 140: node controller, 150: snoop filter,
160: Connection between nodes, 170: Connection line between node controller and processor,
180: connection line between processor and memory,
30: Input of snoop filter,
31: Output of the snoop filter,
32, 32a to 32h: coarse grain snoop filter, 33: state information,
34, 34a to 34h: fine grain snoop filter, 35: address storage unit,
36: Status information, 37: Valid bit, 40: Cache tag, 41: Index, 42: Data field, 50: Access request,
51: Comparator, 52: Selector,
53: Snoop generator 54: Snoop issue control unit,
55: Snoop, 56: Response aggregation logic part,
57: Information registration control unit, 58: Reset control unit,
70: Coarse grain snoop filter with global properties,
71: Status information,
75: A fine-grained snoop filter with global properties,
72: Address storage unit 73: Status information 74: Valid bit

Claims (10)

A computer system in which a plurality of nodes are connected, each node managing a main memory, at least one processor having a cache memory, a node controller for controlling the nodes, and issuing a snoop for maintaining cache coherence In a computer system having a snoop filter that allows a processor of one node to access main memory of another node,
As the snoop filter, a fine-grained snoop filter that manages a predetermined unit address of the cache acquired by accessing the memory by the processor, and state information indicating which processor has a memory data copy at the address;
The memory area is divided into a plurality of memory spaces larger than a predetermined unit size of the cache, and an entry for managing state information indicating that a data copy of the memory space included in each memory space exists in the cache entry of the processor A coarse-grained snoop filter having the entire memory area;
A registration control unit that registers a predetermined unit address of the cache accompanying the access request and the state information in the fine-grained snoop filter and the coarse-grained snoop filter;
A collation unit that collates with the information registered in the fine-grained snoop filter and the coarse-grained snoop filter for the cache address of the data copy accompanying the access request and the status information indicating the processor that caches the address;
And a snoop issuance control unit that controls the issuing of snoops to related processors according to a result of collation by the collation unit. A computer system in which a plurality of nodes are connected, each node managing a main memory, at least one processor having a cache memory, a node controller for controlling the nodes, and issuing a snoop for maintaining cache coherence In a computer system having a snoop filter that allows a processor of one node to access main memory of another node,
As the snoop filter, a fine-grained snoop filter that manages a predetermined unit address of the cache acquired by accessing the memory by the processor of the node and status information indicating which node has a memory data copy of the address; ,
The memory area is divided into a plurality of memory spaces larger than a predetermined unit size of the cache, and an entry for managing state information indicating that a data copy of the memory space included in each memory space exists in the cache entry of the node A coarse-grained snoop filter having the entire memory area;
A control unit that registers a predetermined unit address of the cache accompanying the access request and the state information in the fine-grained snoop filter and the coarse-grained snoop filter,
A collation unit that collates with the information registered in the fine-grained snoop filter and the coarse-grained snoop filter for the cache address of the data copy accompanying the access request and the status information indicating the processor that caches the address;
And a snoop issuance control unit that controls the issuing of snoops to related nodes in accordance with a result of collation by the collation unit. 3. The computer system according to claim 1, wherein the predetermined unit of the cache is a cache line, block, or page unit. 4. The system according to claim 1, further comprising: a reset control unit that substantially invalidates information of the entry registered in the coarse-grained snoop filter and the fine-grained snoop filter when the system is started or initialized. Any computer system. The coarse-grained snoop filter divides the entire memory space into a plurality of memory spaces larger than the cache line size, and status information indicating that each of the plurality of processors may hold one or more lines in the space And register
The fine-grained snoop filter registers a line address storage unit that stores a cache tag, a status information unit that indicates whether each of a plurality of processors holds a cache line, and a valid bit that indicates that the address is valid. The computer system according to claim 1. A selector that outputs cache information of either the coarse-grained snoop filter or the fine-grained snoop filter depending on the result of the hit or miss by the matching unit;
When a hit occurs, the selector causes the fine-grain snoop filter to output cache information that matches the address of the access request,
5. The computer system according to claim 1, wherein when a miss occurs, the selector outputs cache information of an area including an access request address from the coarse-grained snoop filter.   6. The snoop issuance control unit does not issue a snoop when the requested address is not registered in the status information of the coarse-grained snoop filter as a result of the collation by the collation unit. Computer system.   As a result of the collation by the collation unit, the requested address hits the status information of the coarse-grained snoop filter and is registered in the address storage unit of the fine-grain snoop filter, but is set in the status information unit. 6. The computer system according to claim 5, wherein when no processor is used, the snoop issue control unit does not issue a snoop.   As a result of the collation by the collation unit, when the requested address hits the status information of the coarse-grained snoop filter but does not hit the address storage unit of the fine-grain snoop filter, the snoop issue control unit 6. The computer system according to claim 5, wherein a snoop is issued by multicast only to processors registered in the coarse-grained snoop filter.   As a result of the collation by the collation unit, the requested address is registered in the state information of the coarse-grained snoop filter, and hits the address storage unit of the fine-grain snoop filter and registers in the state information unit. 6. The computer system according to claim 5, wherein the snoop issuance control unit issues a snoop only to a processor serving as a holder of the address line.

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