JP2008306296A - Mixer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mixer circuit which has high saturation characteristics by suppressing a decrease in the collector current of a bipolar transistor for signal input even when an input signal is a large signal. <P>SOLUTION: The mixer circuit comprises: a pair of input transistors 4a and 4b inputting differential signals of intermediate or high frequency; signal conversion circuits 5a to 5d which convert the differential signals of intermediate or high frequency input by the input transistor pair into differential signals of high or intermediate frequency using differential signal of local oscillation waves; a transistor 7 connected to emitter terminals of the input transistor pair; a biasing transistor 8 constituting a current mirror with the transistor 7; a power monitor circuit 11 which monitors the output differential signals or input differential signals of the signal conversion circuits as input electric power; and P-type current mirroring circuits 10a and 10b which use the output current of the power monitoring circuit as a reference current, and the output current of the P-type current mirror circuits is the reference current of a biasing bipolar transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a mixer circuit used in a communication satellite, terrestrial microwave communication, mobile communication, and the like.

  In general, in a mixer circuit using NPN bipolar transistors such as BJT and HBT, a constant current bias circuit in which a current flowing through a pair of transistors is constant is used in order to stabilize output amplitude (for example, patents). Reference 1). However, when a constant current bias circuit is used, when a high-power high-frequency signal or intermediate-frequency signal is input, saturation characteristics may deteriorate due to the nonlinear characteristics of the transistor. Therefore, there is a need for a bias circuit that compensates for the saturation characteristics of the transistor at the time of high power input.

JP-A-10-190358

  As described above, the conventional mixer circuit has a problem that the output voltage is not proportional to the input voltage due to the non-linearity of the bipolar transistor when high power is input, and the saturation characteristic is deteriorated.

  The present invention has been made to solve the above-described problems, and suppresses a drop in the collector current of the signal input bipolar transistor pair even when the signal input to the signal input bipolar transistor pair is a large signal. An object of the present invention is to provide a mixer circuit capable of realizing high saturation characteristics.

  The present invention provides an input bipolar transistor pair for inputting an intermediate frequency or high frequency differential signal, and an intermediate frequency or high frequency differential signal input by the input bipolar transistor pair using a local oscillation wave differential signal. A signal conversion circuit for converting a high-frequency or intermediate-frequency differential signal; a bipolar transistor connected to an emitter terminal of the input bipolar transistor pair; a bias bipolar transistor that forms a current mirror with the bipolar transistor; and the signal A power monitoring circuit that monitors the output differential signal or input differential signal of the conversion circuit as input power, and a P-type current mirror circuit that uses the output current of the power monitoring circuit as a reference current. The output current of the current mirror circuit is In mixer circuit, which is a quasi-current.

  In this invention, a bipolar circuit for bias and a current control circuit for compensating the collector current of this transistor are provided, and a mixer circuit having a high saturation characteristic is provided by supplying a current according to the compensation amount of the collector current of the bias bipolar transistor. it can.

Prior to the description of the mixer circuit according to the present invention, the conventional mixer circuit disclosed in Patent Document 1 will be described with reference to FIG. The mixer circuit of FIG. 9 includes high frequency (RF) signal input terminals 158 and 160, local oscillation (LO) signal input terminals 132 and 134, intermediate frequency (IF) signal output terminals 142 and 144, RF signal input bipolar transistor 120, 122, LO signal input bipolar transistors 112, 114, 116, 118, collector bias application resistors 146, 148,
A feedback resistor 152 for expanding an input dynamic range and a bias circuit 156 for supplying a DC bias current to the RF signal input bipolar transistors 120 and 122 are provided.

  The differential signals input from the RF signal input terminals 158 and 160 are input to the RF signal input bipolar transistors 120 and 122. Further, the differential signals input from the LO signal input terminals 132 and 134 are input to the LO signal input bipolar transistors 112, 114, 116 and 118. The IF signal output terminals 142 and 144 output a difference frequency signal between the RF signal and the LO signal. The current bias circuit 156 applies a constant current to the RF signal input bipolar transistors 120 and 122.

When the RF signal input bipolar transistors 120 and 122 are operated with a small signal, the collector current Ic of the transistor is expressed by V _in · I ₀ / (4V _T ). _Here, the _{V in} the base potential of the bipolar transistor RF signal input, _{I 0} is the current of current bias circuit 156, the _{V T} is the thermal voltage of the bipolar transistor RF signal input.

When the RF signal input bipolar transistors 120 and 122 are operated with a large signal, the collector current Ic of the transistor is Ic = I ₀ / [exp (−V _in / V _T ) +1]. That is, the collector current is saturated.

  In the present invention, a bias bipolar transistor and various circuits for controlling the current for compensating the collector current of the transistor are provided, and a current corresponding to the compensation amount of the collector current of the bias bipolar transistor is supplied to provide a high saturation characteristic. Get a mixer circuit.

Embodiment 1 FIG.
1 is a diagram showing a mixer circuit according to a first embodiment of the present invention. The mixer circuit includes IF (intermediate frequency) signal input terminals 1a and 1b, LO (local oscillation) signal input terminals 2a and 2b, RF (high frequency) signal output terminals 3a and 3b, and IF signal input terminals 1a through capacitors 21 and 22. 1b, IF signal input bipolar transistor pair 4a, 4b, LO signal input bipolar transistor 5a, 5b, 5c, 5d (signal conversion circuit), load resistors 6a, 6b, IF signal input bipolar transistor pair 4a , 4b for supplying a DC bias, a bipolar transistor 7 for forming a current mirror with the bipolar transistor 7, a power source 9, and a p-type current mirror circuit for providing a reference current for the bias bipolar transistor. -MOSFETs 10a and 10b, RF signal output terminals 3a and 3b Bipolar transistor 11 (power monitoring circuit) for supplying gate current (reference current) of p-MOSFETs 10a and 10b constituting a P-type current mirror circuit connected to one side 3b via a capacitor 23, and applying a DC bias to the bipolar transistor 11 It consists of a bias application resistor 12. Transistors 4a, 4b, 5a, 5b, 5c, 5d, 7, 8, and 11, and transistors 11a, 11b, 13, 13a, and 13b described later are NPN transistors.

  To describe the circuit configuration, the circuit of FIG. 1 mainly includes an upper circuit including a pair of differential amplifiers and a lower circuit including another differential amplifier. A signal conversion circuit for converting an intermediate frequency (or high frequency) differential signal input by the IF signal input bipolar transistor pair 4a and 4b into a high frequency (or intermediate frequency) differential signal using a differential signal of an LO oscillation wave The transistors 5a and 5b and the transistors 5c and 5d constitute a differential amplifier, respectively.

  The emitter terminals of the transistors 5a and 5b are connected to each other so as to form a common connection point, and the emitter terminals of the transistors 5c and 5d are also connected to each other so as to form a common connection point. These common connection points are connected to the collector terminals of the transistors 4a and 4b in the lower circuit. The base terminals of the transistors 5a and 5d are interconnected and connected to the input terminal 2a, and the base terminals of the transistors 5b and 5c are also interconnected and connected to the input terminal 2b.

  The collector terminals of the transistors 5a and 5c are connected to each other, and the collector terminals of the transistors 5b and 5d are also connected to each other. Either one of the output terminals 3a and 3b and one end of each of the load resistors 6a and 6b, respectively. Either one is connected to each other. The other ends of the load resistors 6a and 6b are connected to each other and connected to a power line 31 to which a power source 9 is connected.

  The emitter terminals of the transistors 4a and 4b are interconnected and connected to the collector terminal of the transistor 7. The base terminals of the transistors 4a and 4b are connected to input terminals 1a and 1b via capacitors 21 and 22, respectively.

  The base terminals of the transistors 7 and 8 constituting the current mirror are connected to each other and further connected to the collector terminal of the transistor 8. The emitter terminals of the transistors 7 and 8 are grounded.

  The gate terminals of the MOSFETs 10a and 10b constituting the current mirror are connected to each other, and further connected to the source terminal of the MOSFET 10b and the collector terminal of the transistor 11. The drain terminals of the MOSFETs 10 a and 10 b are both connected to the power supply line 31. The source terminal of the MOSFET 10 a is connected to the collector terminal of the transistor 8. The source terminal of the MOSFET 10 b is connected to the collector terminal of the transistor 11. The base terminal of the transistor 11 constituting the power monitoring circuit for supplying the reference current of the P-type current mirror circuit is connected to the output terminal 3b via the capacitor 23 and the power supply line 31 via the resistor 12, and the emitter terminal is grounded. Has been.

  Next, the operation will be described. The differential signals input from the IF signal input terminals 1a and 1b are input to the IF signal input bipolar transistor pair 4a and 4b. The differential signals input from the LO signal input terminals 2a and 2b are input to the LO signal input bipolar transistors 5a, 5b, 5c and 5d. From the RF signal output terminals 3a and 3b, a sum of IF signal and LO signal and a difference frequency signal are output.

When the IF signal input bipolar transistor pair 4a, 4b is operating with a small signal, the collector current of the bipolar transistor 11 is I _S · exp (V _BE / V _T ). At this time, if the current feedback rate of the current mirror circuit composed of the p-MOSFETs 10a and 10b and the current mirror circuit composed of the bipolar transistors 7 and 8 is β, the collector current I ₀ of the transistor 7 is β · I _S Expressed as exp (V _BE / V _T ). Where V _BE is the base potential of the transistor 11, _IS is the reverse collector saturation current, and V _T is the thermal voltage. At this time, the collector current of the IF signal input bipolar transistor pair 4a and 4b is expressed by V _in · β · I _S · exp (V _BE / V _T ) / (4V _T ) (V _in is the input terminal) Input voltage).

When the IF signal input bipolar transistor pair 4a, 4b is operating with a large signal, the collector current of the bipolar transistor 11 is I _S · exp {(V _BE + V _out ) / V _T }. Therefore, the collector current I ₀ of the transistor 7 is β · I _S · exp {(V _BE + V _out ) / V _T }. However, _Vout is the voltage amplitude of the RF signal output terminals 3a and 3b. At this time, the collector current of the bipolar transistor pair 4a and 4b for IF signal input is
β · I _S · exp {(V _BE + V _out ) / V _T } / {exp (−Vin / V _T ) +1}. When the input amplitude is increased, exp (−Vin / V _T ) +1 approaches 1, while the output amplitude V _out also saturates, so exp {(V _BE + V _out ) / V _T } also approaches a constant. Therefore, by appropriately setting the current feedback rate β, it is possible to stabilize the collector currents of the IF signal input bipolar transistor pairs 4a and 4b.

  FIG. 2 is a diagram showing the output current dependence of the collector current and gain of the mixer circuit according to the first embodiment of the present invention in comparison with the prior art. (a) is a collector current, (b) is a gain, A is a mixer circuit of the present invention, and B is a conventional mixer circuit. In the conventional circuit, the collector current decreases at the time of high output power, and the gain decreases accordingly. On the other hand, by applying the bias circuit of the present invention, the amount of decrease in collector current at the time of high output power is suppressed, and the amount of decrease in gain is also reduced.

  As described above, in the mixer according to the present invention, it is possible to compensate the collector current and suppress the drop in the base potential even during a large signal operation, so that it is possible to realize a high saturation characteristic.

Embodiment 2. FIG.
FIG. 3 is a diagram showing a mixer circuit according to the second embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. In the mixer circuit of FIG. 3, two bipolar transistors 11a and 11b that provide the gate current of the p-MOSFET 10b are provided as power monitoring circuits, and are connected to both sides of the RF signal output terminals 3a and 3b.

  The base terminals of the bipolar transistors 11a and 11b are connected to the RF signal output terminals 3a and 3b via capacitors 23 and 24, respectively, the collector terminal is connected in common to the gate terminal and the source terminal of the p-MOSFET 10b, and the emitter terminal is grounded. Has been. Even with this configuration, the collector current of the IF signal input bipolar transistor pair 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized.

Embodiment 3 FIG.
4 is a diagram showing a mixer circuit according to a third embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. In the mixer circuit of FIG. 4, the gate current of the p-MOSFET 10b is used as the collector current of the differential amplifier circuit connected to the RF signal output terminals 3a and 3b. That is, the power monitoring circuit is composed of a differential amplifier (circuit).

  The emitter terminals of the bipolar transistors 11a and 11b are connected to each other and grounded, the base terminal is connected to one end of the load resistors 6a and 6b via the capacitors 23 and 24, respectively, and the collector terminals are the RF signal output terminals 3a and 3b and the load. The resistors 12a and 12b are respectively connected to one ends, and the other ends of the load resistors 6a and 6b are interconnected and commonly connected to the gate terminal and the source terminal of the p-MOSFET 10b. Even with this configuration, the collector current of the IF signal input bipolar transistors 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized.

Embodiment 4 FIG.
5 is a diagram showing a mixer circuit according to a fourth embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. In the mixer circuit of FIG. 5, the current of the constant current source 32 is added to the base current of the bias bipolar transistor 8. The constant current source 32 is connected to the collector terminal and the base terminal of the bias bipolar transistor 8. Even with this configuration, the collector current of the IF signal input bipolar transistors 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized. For example, the constant current source may have a configuration in which a high resistance is connected to a voltage source, or may be a band gap circuit.

Embodiment 5. FIG.
FIG. 6 shows a mixer circuit according to the fifth embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. The mixer circuit of FIG. 6 is configured such that the current of the constant current source 32 is subtracted from the base current of the biasing bipolar transistor 8 by using a current mirror circuit constituted by the bipolar transistors 13a and 13b.

  The base terminals of the bipolar transistors 13a and 13b constituting the current mirror circuit are connected to each other and connected to the collector terminal to which the constant current source 32 of the bipolar transistor 13a is connected, and the emitter terminals are grounded. The collector terminal of the bipolar transistor 13b is connected to the collector terminal and base terminal of the biasing bipolar transistor 8 and the source terminal of the p-MOSFET 10a. Even with this configuration, the collector current of the IF signal input bipolar transistors 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized. For example, the constant current source may have a configuration in which a high resistance is connected to a voltage source or a band gap circuit.

Embodiment 6 FIG.
7 is a diagram showing a mixer circuit according to a sixth embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. In the mixer circuit of FIG. 7, the bipolar transistor 11 that supplies the gate current of the p-MOSFET 11b is connected to one side or both sides of the IF signal input terminals 1a and 1b.

  In FIG. 7, the collector terminal of the bipolar transistor 11 is connected to the source terminal and gate terminal of the p-MOSFET 10a, the base terminal is connected to the IF signal input terminal 1a via the capacitor 23, and the emitter terminal is grounded. The circuit comprising the bipolar transistor 11 and the capacitor 23 constituting such a power monitoring circuit may be provided on the IF signal input terminal 1b side, and may be provided on both sides of the IF signal input terminals 1a and 1b. . Even with this configuration, the collector current of the IF signal input bipolar transistors 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized.

Embodiment 7 FIG.
FIG. 8 shows a mixer circuit according to the seventh embodiment of the present invention. The same or corresponding parts as those in the above embodiment are denoted by the same reference numerals, and description thereof is omitted. In the mixer circuit of FIG. 8, the base current compensating bipolar transistor 13 is connected to the base current of the bias bipolar transistor 8.

  The collector terminal of the bipolar transistor 13 is connected to the power supply line 31, the base terminal is connected to the collector terminal and base terminal of the bias bipolar transistor 8 and the source terminal of the p-MOSFET 10 a, and the emitter terminal is the base terminal of the bias bipolar transistor 8. It is connected to the. Even with this configuration, the collector current of the IF signal input bipolar transistors 4a and 4b can be stabilized, and the high saturation characteristic of the mixer circuit can be realized.

  Further, in each of the above-described embodiments, the IF signal is input and the RF signal is output. However, the IF signal input terminal is the RF signal input terminal, the RF signal output terminal is the IF signal output terminal, and the RF signal is output. The circuit can be implemented as a circuit that inputs an IF signal and outputs an IF signal, and the same effect can be obtained.

  Furthermore, each current mirror circuit is not limited to this, and may be constituted by a Wilson mirror circuit or a Wideler mirror circuit.

  Further, a part or all of the bipolar transistor may be replaced with a field effect transistor. For example, the bipolar transistor 7 connected to the emitter terminals of the input bipolar transistor pair 4a and 4b may be replaced with a field effect transistor.

  Furthermore, some or all of the field effect transistors may be replaced with bipolar transistors.

It is the figure which showed the mixer circuit by Embodiment 1 of this invention. It is a figure for demonstrating the characteristic of the mixer circuit by this invention. It is the figure which showed the mixer circuit by Embodiment 2 of this invention. It is the figure which showed the mixer circuit by Embodiment 3 of this invention. It is the figure which showed the mixer circuit by Embodiment 4 of this invention. It is the figure which showed the mixer circuit by Embodiment 5 of this invention. It is the figure which showed the mixer circuit by Embodiment 6 of this invention. It is the figure which showed the mixer circuit by Embodiment 7 of this invention. It is the figure which showed the general structure of the mixer circuit.

Explanation of symbols

  1a, 1b IF signal input terminal, 2a, 2b LO signal input terminal, 3a, 3b RF output terminal, 4a, 4b FI signal input bipolar transistor (pair), 5a to 5d LO signal input bipolar transistor (signal conversion circuit) 6a, 6b Load resistance, 7 bipolar transistor, 8 bias bipolar transistor, 9 power supply, 10a, 10b p-MOSFET (P-type current mirror circuit), 11, 11a, 11b bipolar transistor (power monitor circuit), 12 bias Applied resistance, 12a, 12b Load resistance, 13 Base current compensating bipolar transistor, 13a, 13b Bipolar transistor (current mirror circuit), 21, 22, 23, 24 capacitor, 31 power line, 32 constant current source.

Claims (10)

A pair of input bipolar transistors for inputting an intermediate frequency or high frequency differential signal;
A signal conversion circuit for converting an intermediate frequency or high frequency differential signal input by the input bipolar transistor pair using a local oscillation wave differential signal into a high frequency or intermediate frequency differential signal;
A bipolar transistor connected to the emitter terminal of the input bipolar transistor pair;
A bipolar transistor for bias that constitutes a current mirror with the bipolar transistor;
A power monitoring circuit for monitoring the output differential signal or the input differential signal of the signal conversion circuit as input power;
A P-type current mirror circuit using the output current of the power monitoring circuit as a reference current;
The mixer circuit is characterized in that the output current of the P-type current mirror circuit is a reference current of the bias bipolar transistor.   2. The mixer according to claim 1, wherein the power monitoring circuit for supplying a reference current of the P-type current mirror circuit comprises one bipolar transistor for monitoring one of the output differential signals of the signal conversion circuit as input power. circuit.   2. The power monitoring circuit for supplying a reference current of the P-type current mirror circuit comprises two bipolar transistors that monitor one of the output differential signals of both of the signal conversion circuits as input power. The mixer circuit described.   2. The mixer circuit according to claim 1, wherein the power monitoring circuit for supplying a reference current of the P-type current mirror circuit comprises a differential amplifier circuit using the output differential signal of the signal conversion circuit as input power.   2. The mixer according to claim 1, wherein the power monitoring circuit for supplying a reference current of the P-type current mirror circuit comprises one bipolar transistor that monitors one of the input differential signals of the signal conversion circuit as input power. circuit.   6. The method according to claim 1, further comprising a constant current source, wherein a sum of an output current of the P-type current mirror circuit and an output current of the constant current source is used as a reference current of the bias bipolar transistor. The mixer circuit as described in the paragraph.   6. The method according to claim 1, further comprising a constant current source, wherein a difference between an output current of the P-type current mirror circuit and an output current of the constant current source is used as a reference current of the bias bipolar transistor. The mixer circuit as described in the paragraph.   8. The mixer circuit according to claim 1, further comprising a base current compensating bipolar transistor for the biasing bipolar transistor.   9. The mixer circuit according to claim 1, wherein the bipolar transistor connected to the emitter terminal of the input bipolar transistor pair is replaced with a field effect transistor. 9. The mixer circuit according to claim 1, wherein all bipolar transistors are replaced with field effect transistors.

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