JP2008305982A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new field effect transistor using a semiconductor nanowire, and its manufacturing method. <P>SOLUTION: The field effect transistor includes a gate electrode film 14, the plurality of semiconductor nanowires 11 disposed so as to pass through the gate electrode film 14, a source electrode film 12 formed so as to be in contact with one end of each of the semiconductor nanowires 11 to connect them, and a drain electrode film 13 formed so as to be in contact with the other end of each of the semiconductor nanowires to connect them. The source electrode film 12 and the drain electrode film 13 are composed of a metal. An insulating layer 15 is arranged between the gate electrode film 14 and the semiconductor nanowires 11. The types of the semiconductors at one end and the other end of the semiconductor nanowires 11 are either P type or N type. The type of the semiconductor at the center part held by the one end and the other end is different from the type of the semiconductor at the one end and the other end. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof.

  As the performance and size of electronic devices increase, the elements constituting the electronic circuit are progressing in the direction of size reduction and height reduction. In order to reduce the variation in characteristics due to the miniaturization of the element size, high precision of the element is required.

  On the other hand, as a new electronic device, an electronic device using a member having a diameter smaller than several hundreds of nanometers (hereinafter sometimes referred to as “nano member”) has been studied. Examples of the columnar nano member include carbon nanotubes and semiconductor nano wires.

  A field effect transistor (FET) using semiconductor nanowires has already been disclosed (Non-Patent Document 1). This field effect transistor is realized by forming a source electrode film and a drain electrode film on both end portions of a semiconductor nanowire oriented in a uniaxial direction. In the manufacture of such a field effect transistor using semiconductor nanowires, it is not necessary to form a semiconductor film using a vacuum film forming apparatus, so that many merits including cost reduction can be obtained.

  However, in the above manufacturing method, it is necessary to arrange the semiconductor nanowires in a predetermined direction and a predetermined position. As a method of aligning semiconductor nanowires, a method of applying semiconductor nanowires is disclosed (Patent Document 1). However, with this method, it is difficult to manufacture field effect transistors with good reproducibility.

There has also been proposed a method for manufacturing a field effect transistor using semiconductor nanowires grown on a semiconductor substrate without separating the semiconductor nanowire from the semiconductor substrate (see Patent Document 2). In this method, an interlayer insulating film, a gate electrode, and a source electrode are embedded between semiconductor nanowires standing on a semiconductor substrate by a vacuum deposition method or the like.
US Pat. No. 7,067,867 JP 2004-197612 A D. Wang, et al. "German nanofield field-effect transistors with SiO2 and high-k HfO2 gate dielectric", Appl. Phys. Lett. , Vol. 83, pp. 2432, 2003

  However, in the conventional field effect transistor, a semiconductor substrate exists between the semiconductor nanowire and the drain electrode. For this reason, it is necessary to polish and thin the semiconductor substrate before forming the drain electrode. However, since the semiconductor substrate may be damaged in the process of polishing the semiconductor substrate, the yield may be reduced.

  Under such circumstances, an object of the present invention is to provide a novel field effect transistor using a semiconductor nanowire and a method for manufacturing the same.

  In order to achieve the above object, a field effect transistor of the present invention is in contact with a gate electrode film, a plurality of semiconductor nanowires disposed so as to penetrate the gate electrode film, and one end of each of the plurality of semiconductor nanowires. A source electrode film formed to connect them, and a drain electrode film formed to contact and connect the other ends of the plurality of semiconductor nanowires, and the source electrode film and The drain electrode film is made of metal, an insulating layer is disposed between the gate electrode film and the semiconductor nanowire, and the semiconductor type of the one end and the other end of the semiconductor nanowire is both P-type or N-type The type of the semiconductor in the central part sandwiched between the one end and the other end is the type of the one end and the other end. It made.

  In addition, the method of the present invention for manufacturing a field effect transistor includes the steps of (i) forming a plurality of semiconductor nanowires standing on the substrate such that one end of each is fixed to the substrate; Fixing the semiconductor nanowire with a removable solid so that the other ends of the plurality of semiconductor nanowires are exposed; and (iii) connecting the first electrode film so as to connect the other ends of the plurality of semiconductor nanowires. Forming, (iv) removing the substrate, (v) forming a second electrode film so as to connect the one ends of the plurality of semiconductor nanowires, and (vi) removing the solid (Vii) forming an insulating layer on the surface of each central portion of the plurality of semiconductor nanowires; and (viii) contacting the insulating layer and the first and second electrode films. Do not touch Forming a third electrode film as described above, and the semiconductor type of the one end and the other end of the semiconductor nanowire is either P-type or N-type, and the one end and the other end are The type of the semiconductor at the sandwiched central portion is different from the type of the one end and the other end.

  According to the present invention, a field effect transistor using a semiconductor nanowire can be manufactured with a high yield. In addition, since the field effect transistor of the present invention is a chip type, it can be easily mounted on a circuit board of an electronic device.

  Hereinafter, embodiments of the present invention will be described with examples. The present invention is not limited to the following embodiment. In the following description, specific numerical values and specific materials may be exemplified, but other numerical values and other materials may be applied as long as the effect of the present invention is obtained.

[Field Effect Transistor (FET)]
The FET of the present invention includes a plurality of semiconductor nanowires, a gate electrode film, a source electrode film, a drain electrode film, and an insulating layer (gate insulating layer).

  The plurality of semiconductor nanowires are disposed so as to penetrate the gate electrode film. An insulating layer (gate insulating layer) is disposed between the gate electrode film and the semiconductor nanowire.

  The source electrode film is in contact with one end of each of the plurality of semiconductor nanowires. The source electrode film is formed so as to connect one end thereof. The drain electrode film is in contact with the other ends of the plurality of semiconductor nanowires. The drain electrode film is formed so as to connect the other ends. Both the source electrode film and the drain electrode film are made of metal. The gate electrode film is also made of metal.

  The semiconductor type at one end and the other end of the plurality of semiconductor nanowires is either P-type or N-type. That is, one end and the other end of the semiconductor nanowire are both P-type or both N-type. Further, the semiconductor type at the center between the one end and the other end is different from the semiconductor type at the one end and the other end.

  In the FET of the present invention, an alloy of a semiconductor constituting the semiconductor nanowire and a metal constituting the source electrode film may be formed at the connection portion between the semiconductor nanowire and the source electrode film. Moreover, the alloy of the semiconductor which comprises a semiconductor nanowire, and the metal which comprises a drain electrode film may be formed in the connection part of a semiconductor nanowire and a drain electrode film. By forming an alloy at the connection portion between the semiconductor nanowire and the electrode, the connection resistance between them can be reduced. When the semiconductor nanowire is made of silicon, the alloy is a metal silicide.

  The gate electrode film, the source electrode film, and the drain electrode film are independently made of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), rhodium (Rh), and gold (Au). It may be formed of any selected metal. The material of the gate electrode film, the material of the source electrode film, and the material of the drain electrode film may be the same or different. These electrode films may be films formed by a plating method (preferably an electroless plating method).

  The gate electrode film, the source electrode film, and the drain electrode film are formed substantially parallel to each other. The semiconductor nanowire is oriented in a direction substantially perpendicular to these electrode films.

  The semiconductor nanowire is a needle-like semiconductor. The diameter of the semiconductor nanowire is, for example, in the range of 50 nm to 500 nm, and in the example of 80 nm to 150 nm. The length of the semiconductor nanowire is, for example, in the range of 5 μm to 50 μm, and in one example, in the range of 13 μm to 22 μm.

  The semiconductor nanowire may be made of any of silicon, germanium, and silicon-germanium.

  In the FET of the present invention, the central portion of the semiconductor nanowire may be a type opposite to the semiconductor type at one end and the other end. For example, the center portion may be P-type, and both end portions (one end portion and the other end portion) may be N-type. Further, the central portion may be N-type and both end portions may be P-type.

  In the FET of the present invention, the central portion of the semiconductor nanowire may be an intrinsic semiconductor that does not contain impurities. The semiconductor nanowire in this case has a structure of any of P-type semiconductor / intrinsic semiconductor / P-type semiconductor or N-type semiconductor / intrinsic semiconductor / N-type semiconductor.

  The P-type semiconductor region can be formed by doping with boron (B), aluminum (Al), gallium (Ga), indium (In), or the like. The N-type semiconductor region can be formed by doping phosphorus (P), arsenic (As), antimony (Sb), or the like. The intrinsic semiconductor region can be formed without doping.

[Method of manufacturing FET]
In the following, the method of the present invention for producing an FET will be described. According to this manufacturing method, the FET of the present invention can be manufactured. In addition, since the matter demonstrated about FET of this invention is applicable to the following manufacturing methods, the overlapping description may be abbreviate | omitted. The production method of the present invention includes the following steps (i) to (viii).

  In step (i), a plurality of semiconductor nanowires standing on the first substrate are formed such that one end of each is fixed to the substrate (hereinafter referred to as “first substrate”). Hereinafter, of the end portions of the semiconductor nanowire, the one fixed to the first substrate is referred to as “one end”, and the other is referred to as the “other end”. The plurality of semiconductor nanowires are formed substantially perpendicular to the surface of the first substrate. The conductivity type of one end and the other end of the semiconductor nanowire is either p-type or n-type. Further, the conductivity type of the central portion sandwiched between the one end and the other end is different from the conductivity type of the one end and the other end. An example of a method for forming the semiconductor nanowire will be described later.

  In step (ii), the semiconductor nanowires are fixed with a removable solid (hereinafter sometimes referred to as “solid (A)”) so that the other ends of the plurality of semiconductor nanowires are exposed. In step (ii), the semiconductor nanowire other than the other end is fixed with the solid (A). The solid (A) may be a thermoplastic organic material. For example, the solid (A) may be a paraffin wax organic material, a coal tar organic material, or a thermoplastic resin such as polyethylene.

In step (iii), a first electrode film is formed so as to connect the other ends of the plurality of semiconductor nanowires. For example, the first electrode film may be formed on one surface of the solid (A) surface on which the other end of the semiconductor nanowire protrudes. The first electrode film is a source electrode or a drain electrode. The first electrode film may be formed by a vapor deposition method (vacuum deposition method or sputtering method), but is preferably formed by a plating method (for example, electroless plating).
Heat treatment may be performed after step (iii). By heat treatment, an alloy of the semiconductor constituting the semiconductor nanowire and the metal constituting the first electrode film can be formed at the connection portion between the semiconductor nanowire and the first electrode film.

Moreover, you may perform the process of adhere | attaching a 1st electrode film on a 2nd board | substrate after process (iii). By adhering the first electrode film to the second substrate, subsequent handling becomes easy. The first electrode film and the second substrate may be bonded using an adhesive or may be bonded using an adhesive sheet. Alternatively, the first electrode film may be bonded to the second substrate by forming the second substrate using a curable resin or the like.
In step (iv), the first substrate is removed. There is no limitation on the method for removing the first substrate, and the first substrate may be removed physically or chemically. In the case where the first substrate is made of a material that is softened or melted by heating, the first substrate may be removed by heating.

  In the step (v), a second electrode film is formed so as to connect the one ends of the plurality of semiconductor nanowires. When the first electrode film is a source electrode, the second electrode film is a drain electrode. When the first electrode film is a drain electrode, the second electrode film is a source electrode. The second electrode film may be formed on one surface of the solid (A) surface from which one end of the semiconductor nanowire protrudes.

  In step (vi), the solid (A) is removed. The solid (A) may be removed chemically. Further, when the solid (A) is made of a substance that is softened or melted by heating, the solid (A) may be removed by heating.

  In the step (vii), an insulating layer is formed on the surface of each central portion of the plurality of semiconductor nanowires. The insulating layer can be formed, for example, by oxidizing the surface of the semiconductor nanowire. The insulating layer may be formed in a region other than the central portion. Usually, the insulating layer is formed over the entire surface of the exposed semiconductor nanowire.

  In the step (viii), a third electrode film is formed so as to be in contact with the insulating layer and not in contact with the first and second electrode films. The third electrode film is formed between the first electrode film and the second electrode film. The third electrode film is a gate insulating film. The third electrode film can be formed by a plating method (electroless plating method).

  In the manufacturing method of the present invention, the central part of the semiconductor nanowire may be a semiconductor type opposite to the semiconductor type at one end and the other end. Moreover, the intrinsic | native semiconductor which does not contain an impurity may be sufficient as the center part of semiconductor nanowire.

  In the production method of the present invention, the solid (A) may be a thermoplastic organic material. Examples of the thermoplastic organic material include thermoplastic resins such as paraffin wax, coal tar, and polyethylene.

  The first, second and third electrode films can be made of metal. In the manufacturing method of the present invention, the first, second and third electrode films may be formed by a plating method (for example, an electroless plating method). By forming an electrode film by a plating method, it is possible to form a dense film without voids unlike the case of using a vapor phase film forming method. Therefore, an FET with little variation in characteristics can be formed by using a plating method.

[An example of FET and an example of its manufacturing method]
Below, an example of FET of this invention and an example of the manufacturing method are demonstrated.

  A perspective view of an example of the FET of the present invention is shown in FIG. The FET 10 in FIG. 1 has a size in the x-axis direction of 10 μm, a size in the y-axis direction of 5 μm, and a size in the z-axis direction of 21 μm.

  A cross-sectional view of the FET 10 is shown in FIG. The FET 10 includes a silicon nanowire 11, a source electrode film 12, a drain electrode film 13, a gate electrode film 14, and an insulating layer 15. The insulating layer 15 is formed on the outer peripheral surface of the silicon nanowire 11.

  The source electrode film 12 and the drain electrode film 13 have a size of 10 μm × 5 μm and a thickness of 5 μm. The source electrode film 12 and the drain electrode film 13 are made of nickel. Nickel silicide 16 is formed at the connection between the silicon nanowire 11 and the source electrode film 12 and at the connection between the silicon nanowire 11 and the drain electrode film 13.

  The gate electrode film 14 has a size of 10 μm × 5 μm and a thickness of 6 μm. The gate electrode film 14 is made of nickel.

  The silicon nanowire 11 is profile-doped. The both ends (one end and the other end) of the silicon nanowire 11 are N-type regions 11n, and the central portion other than both ends is a P-type region 11p. The N-type region 11n is doped with phosphorus, and the P-type region 11p is doped with boron. Two ends of the N-type region 11n are buried in the source electrode film 12 and the drain electrode film 13, respectively. The silicon nanowire 11 penetrates the gate electrode film 14. The gate electrode film 14 is disposed so as to surround the P-type region 11p with the insulating layer 15 interposed therebetween.

  A method of forming the silicon nanowire 11 is shown in FIG. First, a silicon wafer 31 having an oxide film formed on the surface is prepared, and catalyst particles 32 made of gold are arranged on the surface on one side (FIG. 3A). The catalyst particles 32 can be formed by aggregating gold colloidal particles by applying a suspension in which gold colloidal particles (average particle size: 80 nm) are dispersed on the silicon wafer 31 and then heating in a vacuum.

Next, the silicon wafer 31 on which the catalyst particles 32 are disposed is disposed in a chamber of a vacuum apparatus. Then, the N-type region 11n of the silicon nanowire 11 (average diameter: 100 nm) is grown by the CVD method using the catalyst particles 32 (FIG. 3B). The N-type region 11n is formed by flowing a source gas over the substrate surface while the silicon wafer 31 is heated to 400 ° C. with an infrared heater. The source gas is a disilane gas to which a slight amount of phosphine (PH ₃ ) gas is added.

Next, the source gas is switched to a disilane gas to which a slight amount of diborane (B ₂ H ₆ ) gas is added, and silicon is crystal-grown by the same CVD method as described above. Thereby, the P-type region 11p of the silicon nanowire 11 is grown (FIG. 3C). At this time, if only pure disilane gas is used as the source gas, a region made of pure silicon of an intrinsic semiconductor not containing impurities grows instead of the P-type region 11p.

Next, the source gas is switched to a disilane gas to which a slight amount of phosphine (PH ₃ ) gas is added, and silicon is crystal-grown by the same CVD method as described above. Thereby, the N-type region 11n of the silicon nanowire 11 is grown (FIG. 3D). In this way, the silicon nanowire 11 constituted by two N-type regions 11n and one P-type region 11p is formed. The silicon nanowire 11 is formed substantially perpendicular to the surface of the silicon wafer 31. The length of the N-type region 11n and the length of the P-type region 11p can be controlled, for example, by changing the crystal growth time.

  Next, a method for forming a field effect transistor using a silicon wafer on which silicon nanowires are erected is described.

  First, a silicon wafer (first substrate) 31 on which silicon nanowires 11 (average length: 18 μm) are formed is formed by the method shown in FIG. 3 (FIG. 4A). Here, the length of each of the two N-type regions 11n is 8 μm, and the length of the P-type region 11p is 2 μm.

  Next, the thermoplastic organic substance that is solid at 70 ° C. or lower is heated to 120 ° C. to form a liquid thermoplastic organic substance 41 a and is placed in the transparent container 42. Then, the silicon wafer 31 shown in FIG. 4A is immersed in it while being held horizontally. At this time, the liquid amount of the thermoplastic organic material 41 is controlled so that the tip portion (about 3 μm) of the silicon nanowire 11 protrudes from the thermoplastic organic material 41a (FIG. 4B).

  Thereafter, the temperature of the thermoplastic organic material 41a is lowered to room temperature to obtain a solidified thermoplastic organic material 41. Next, the thermoplastic organic material 41 is taken out from the transparent container 42. Next, only the surface of the surface of the thermoplastic organic material 41 from which the tip portion of the silicon nanowire 11 protrudes is subjected to electroless plating activation treatment using palladium. Then, the thermoplastic organic material 41 is placed in a nickel electroless plating tank maintained at 60 ° C., and the plating process is performed slowly. In this way, a first electrode film 43 (thickness 5 μm) made of nickel is formed (FIG. 4C).

  In addition, a well-known method is applicable as a method of the activation process of electroless plating. For example, a method of attaching a palladium catalyst by reduction using an aqueous palladium solution or a method of depositing a palladium catalyst by a vacuum process may be used.

  Next, the first electrode film 43 is bonded to the second substrate 45 using the adhesive sheet 44 (FIG. 4D). The second substrate 45 can facilitate the following steps and prevent damage to the silicon nanowires 11 and the like.

  Next, the obtained object is put into the transparent container 46 with the second substrate 45 facing down. Then, the thermoplastic organic material 41 is heated to a liquid thermoplastic organic material 41a and is moved to the second substrate 45 side. As a result, at least all of the surface of the silicon wafer 31 other than the surface on which the silicon nanowires 11 are formed are exposed (FIG. 4E). In this state, the temperature of the thermoplastic organic material 41a is lowered to room temperature to obtain a solidified thermoplastic organic material 41.

  Next, the silicon wafer 31 is removed (FIG. 4F).

  Next, the thermoplastic organic material 41 is heated to obtain a liquid thermoplastic organic material 41a. Then, the liquid surface of the thermoplastic organic material 41a is leveled so that the tip portion (3 μm) of the silicon nanowire 11 protrudes from the liquid surface of the thermoplastic organic material 41a (FIG. 4G). In this state, the temperature of the thermoplastic organic material 41a is lowered to obtain a solidified thermoplastic organic material 41.

  Next, the obtained object is taken out from the transparent container 46. Then, the second electrode film 47 (thickness 5 μm) made of nickel is formed only on the surface of the thermoplastic organic material 41 where the tip portion of the silicon nanowire 11 protrudes (FIG. 4H). The second electrode film 47 can be formed by a method similar to that for the first electrode film 43.

  Next, the thermoplastic organic material 41 is liquefied and removed by heating (FIG. 4 (i)).

  Next, the adhesive sheet 44 and the second substrate 45 are separated from the first electrode film 43. In this way, an object in which both ends of the plurality of silicon nanowires 11 are connected by the first electrode film 43 and the second electrode film 47 is obtained (FIG. 4 (j)).

  Next, the obtained object is heat-treated at 450 ° C. in an argon gas atmosphere containing oxygen gas. By this heat treatment, the nickel plating film (first and second electrode films 43 and 47) is stabilized. Further, an insulating layer (not shown, corresponding to the insulating layer 15 in FIG. 2) is formed on the exposed surface of the silicon nanowire 11 by the heat treatment. Further, nickel silicide (not shown in FIG. 2) having low electrical resistance is formed at the interface between the first electrode film 43 and the silicon nanowire 11 and the interface between the second electrode film 47 and the silicon nanowire 11 by the heat treatment. Corresponding to nickel silicide 16).

  Next, the 1st electrode film 43 is affixed on the 3rd board | substrate 49 using the adhesive sheet 48 (FIG.5 (k)).

  Next, a part of the obtained object is immersed in the thermoplastic organic material 51a liquefied by heating. The thermoplastic organic material 51 a is disposed in the transparent container 50. Then, the surface of the first electrode film 43 on the silicon nanowire 11 side is submerged by 3 μm from the liquid surface of the thermoplastic organic material 51a (FIG. 5L). In this state, the temperature of the thermoplastic organic material 51a is lowered to obtain a solidified thermoplastic organic material 51.

  Next, the obtained object is taken out from the transparent container 50. And the thermoplastic organic substance 52a liquefied by heating is arrange | positioned in the transparent container 50 again. The thermoplastic organic materials 51a and 52a may be the same material as the thermoplastic organic material 41a.

  Next, a part of the object on the third electrode film 47 side is immersed in the thermoplastic organic material 52a. At this time, the surface of the third electrode film 47 on the silicon nanowire 11 side is submerged by 3 μm from the liquid surface of the thermoplastic organic material 52a (FIG. 5 (m)). In this state, the temperature of the thermoplastic organic material 52a is lowered to obtain a solidified thermoplastic organic material 52. In addition, it is preferable to perform the process of FIG.5 (m), cooling the thermoplastic organic substance 51 so that the thermoplastic organic substance 51 solidified may not liquefy.

  Next, the obtained object is taken out from the transparent container 50. In this way, an object is obtained in which the insulating layer present on the surface of the central portion of the silicon nanowire 11 is exposed (FIG. 5 (n)).

  Next, a third electrode film 53 (thickness 6 μm) made of nickel is formed on the exposed insulating layer by an electroless plating method (FIG. 5 (o)). The third electrode film 53 is formed by the same method as the first electrode film 43.

  Next, the thermoplastic organic material 51 and the thermoplastic organic material 52 are removed by heating. Further, the adhesive sheet 48 and the third substrate 49 are removed. Next, the obtained object is heat-treated at 300 ° C. in an argon gas atmosphere. In this way, the object shown in FIG. 5 (p) is obtained. The first, second and third electrodes are formed substantially parallel to each other. Further, the silicon nanowire 11 is oriented substantially perpendicular to the surfaces of the first, second and third electrodes.

  Next, the obtained object is divided into a size of 5 μm in length and 10 μm in width perpendicular to the surface of the electrode film (FIG. 5 (q)). There is no limitation on the division method, and for example, a dicing method or a method combining a lithography method and a dry etching method may be used. In this way, the FET 10 shown in FIG. 1 is obtained.

  Instead of the silicon nanowire 11, a nanowire made of germanium or silicon-germanium may be used. Further, the N-type semiconductor region and the P-type semiconductor region may be formed by an ion implantation method. Further, the N-type semiconductor region may be formed by doping arsenic or antimony instead of phosphorus. The P-type semiconductor region may be formed by doping aluminum, gallium or indium instead of boron. The silicon nanowire 11 may be profile-doped in the order of P type / N type / P type.

  The first, second and third electrode films may be formed of any one of cobalt, platinum, palladium, rhodium, and gold. Electrode films made of these metals can be formed by electroless plating.

  Furthermore, as the thermoplastic organic substances 41, 51 and 52, any of a paraffin wax organic substance, a coal tar organic substance, and a thermoplastic resin such as polyethylene may be used. Depending on the material used, the processing temperature is adjusted.

  Further, the insulating layer formed on the center surface of the silicon nanowire 11 may be formed by a CVD method or the like. For example, a silicon nitride layer may be formed by a CVD method.

  The present invention can be applied to a field effect transistor using a semiconductor nanowire and an electronic apparatus using the same.

It is a perspective view which shows typically an example of FET of this invention. It is sectional drawing of FET shown in FIG. It is process drawing which shows an example of the manufacturing method of semiconductor nanowire. It is process drawing which shows an example of the manufacturing method of FET based on this invention. FIG. 5 is a diagram showing a step that follows the step of FIG. 4.

Explanation of symbols

10 Field Effect Transistor (FET)
11 silicon nanowire 11n n-type region 11p p-type region 12 source electrode film 13 drain electrode film 14 gate electrode film 15 insulating layer 16 nickel silicide 31 silicon wafer 32 catalyst particles 41a, 51a, 52a thermoplastic organic substance (liquid)
41, 51, 52 Thermoplastic organic matter (solid)
43 First electrode film 44, 48 Adhesive sheet 45 Second substrate 47 Second electrode film 49 Third substrate 53 Third electrode film

Claims (9)

A gate electrode film;
A plurality of semiconductor nanowires arranged to penetrate the gate electrode film;
A source electrode film formed to contact and connect one end of each of the plurality of semiconductor nanowires;
A drain electrode film formed to come into contact with and connect to the other end of each of the plurality of semiconductor nanowires,
The source electrode film and the drain electrode film are made of metal,
An insulating layer is disposed between the gate electrode film and the semiconductor nanowire,
The semiconductor type of the one end and the other end of the semiconductor nanowire is either P-type or N-type, and the semiconductor type in the central part sandwiched between the one end and the other end is the one end and the other Field effect transistor different from the end type. In the connection portion between the semiconductor nanowire and the source electrode film, an alloy of the semiconductor constituting the semiconductor nanowire and the metal constituting the source electrode film is formed,
The field effect transistor according to claim 1, wherein an alloy of a semiconductor constituting the semiconductor nanowire and a metal constituting the drain electrode film is formed at a connection portion between the semiconductor nanowire and the drain electrode film.   The field effect transistor according to claim 1, wherein the semiconductor nanowire is made of any one of silicon, germanium, and silicon-germanium.   The field effect transistor according to claim 1, wherein the central portion of the semiconductor nanowire is of a type opposite to the semiconductor type of the one end and the other end.   The field effect transistor according to claim 1, wherein the central portion of the semiconductor nanowire is an intrinsic semiconductor containing no impurities. (I) forming a plurality of semiconductor nanowires standing on the substrate such that one end of each is fixed to the substrate;
(Ii) fixing the semiconductor nanowire with a removable solid so that the other ends of the plurality of semiconductor nanowires are exposed;
(Iii) forming a first electrode film so as to connect the other ends of the plurality of semiconductor nanowires;
(Iv) removing the substrate;
(V) forming a second electrode film so as to connect the one ends of the plurality of semiconductor nanowires;
(Vi) removing the solid;
(Vii) forming an insulating layer on the surface of each central portion of the plurality of semiconductor nanowires;
(Viii) forming a third electrode film in contact with the insulating layer and not in contact with the first and second electrode films,
The semiconductor type of the one end and the other end of the semiconductor nanowire is either P-type or N-type, and the semiconductor type in the central part sandwiched between the one end and the other end is the one end and the other A field effect transistor manufacturing method different from the edge type. In the step (ii), the substrate is fixed with the solid together with a central portion of the plurality of semiconductor nanowires,
The manufacturing method according to claim 6, further comprising a step of removing the solid in contact with the substrate after the step (iii) and before the step (iv).   The manufacturing method according to claim 6, wherein the solid is a thermoplastic organic material.   The manufacturing method according to claim 6, wherein the first, second, and third electrode films are formed by a plating method.

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