JP2008305527A - Nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device from which data is read at high speed with high accuracy. <P>SOLUTION: Capacitors C1, C2 are provided between a sense amplifier SA0, an amplifying unit 55 and the other conductive terminals of transistors QV1, QV2. Also a sense amplifier SA1 is provided with capacitors C1#, C2# between an amplifying unit 55# and the other conductive terminals of transistors QV1#, QVB2# and a transistor 80 is provided between nodes N1a and N1b. Also, a transistor 81 is provided between nodes N2a and N2b. When reading data for a memory cell in an odd row, bit lines /BLj, /BLj+1 are connected to dummy memory cells of low resistance Rmin, high resistance Rmax. Then, when data for a memory cell in an odd row is read, a transistor 81 is made conductive. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device, and more particularly to a circuit configuration of a differential amplifier circuit (sense amplifier) that amplifies data stored in a memory cell.

  In recent years, nonvolatile storage devices capable of storing nonvolatile data have become mainstream. For example, a flash memory that can be highly integrated can be cited.

  Furthermore, as a new generation non-volatile memory device, an MRAM (Magnetic Random Access Memory) device that performs non-volatile data storage using a thin film magnetic material and an OUM (Ovonic that performs data storage using a material called chalcogenide of a thin film) (Unified Memories) devices are attracting particular attention.

  Generally, when data stored in a memory cell used as a memory element of these nonvolatile memory devices is read, a data is read by applying a predetermined voltage and detecting a passing current at that time Is common (Non-patent Document 1 and Patent Documents 1 to 3).

FIG. 13 is a schematic configuration diagram for explaining a data read operation using a conventional sense amplifier.
The operation of the conventional sense amplifier will be described.

  Referring to FIG. 13, the conventional sense amplifier is arranged between power supply voltage Vcc and internal node N1, transistor QP1 whose gate is electrically coupled to internal node N1, power supply voltage Vcc and internal node Transistor QP5 arranged between N2 and having its gate electrically coupled to internal node N2, and amplification unit 50 having internal nodes N1 and N2 as input nodes are included.

  Sense amplifier SA is arranged between node N1 and local I / O line LIO, and its gate is arranged between transistor QV1 receiving reference voltage Vref and node N2 and local I / O line / LIO. The gate includes a transistor QV2 receiving a reference voltage Vref.

Here, the transistors QP1 and QP5 are P-channel MOS transistors.
The local input / output lines LIO, / LIO are set to a predetermined voltage equal to or lower than the reference voltage by the transistors QV1 and QV2 receiving the reference voltage Vref at the gate described above, and a passing current according to the predetermined voltage flows to the nodes N1, N2.

  Transistor QP1 has a gate and a drain electrically coupled, and converts a passing current flowing through node N1 into a voltage signal. Transistor QP5 has a gate and a drain electrically coupled, and converts a passing current flowing through node N2 into a voltage signal.

  Amplifying unit 50 receives the voltage signals converted in transistors QP1 and QP5 as a pair of inputs, amplifies a signal corresponding to the passing current flowing through nodes N1 and N2, and outputs read data SOUT.

  The sense amplifier SA amplifies a voltage difference corresponding to a passing current difference generated in the local input / output lines LIO, / LIO, and further performs an amplification operation by a later-stage amplifier (not shown), so that the storage data of the memory cell is output. Data reading is executed.

Next, the data read operation will be specifically described.
Selected column select line CSLk corresponding to input address ADD for executing the data read operation and word line WL provided corresponding to the selected memory cell are activated ("H" level). . In addition, word line DWL provided corresponding to the dummy memory cell is activated (“H” level).

  In response to activation of selected column selection line CSLk, gate transistors CSGa and CSGb are turned on, and bit lines BLj, / BLj and local input / output lines LIO, / LIO of the selected column are electrically coupled. .

  In response to activation of the word line WL, the access transistor ATR is turned on, and the local input / output line LIO is pulled down to the ground voltage GND via the bit line BLj and the selected memory cell MC.

  In response to activation of word line WLD, local input / output line / LIO is pulled down to ground voltage GND via bit line / BLj and dummy memory cell DMC. Accordingly, a current path is formed between sense amplifier SA and selected memory cell MC and dummy memory cell DMC, and a predetermined sense operation is performed in sense amplifier SA.

  Specifically, the sense amplifier tries to supply the same current to each of the local input / output lines LIO and / LIO. However, an electrical resistance difference exists between the memory cell MC and the dummy memory cell DMC.

  Therefore, according to the resistance value Rcell corresponding to the storage data of the selected memory cell MC and the resistance value Rref of the dummy memory cell DMC, a passing current corresponding to the electrical resistance starts to flow through the local input / output lines LIO and / LIO. A voltage difference corresponding to the passing current difference of the passing currents appears at the nodes N1 and N2. In a state where a sufficient voltage difference appears, an amplification operation is further executed to output read data SOUT.

  Here, the resistance value Rref of the dummy memory cell DMC is an intermediate value between the maximum value Rmax and the minimum value Rmin that can be taken by the resistance value Rcell corresponding to the data stored in the tunnel magnetoresistive element TMR of the selected memory cell MC. Although it is required to be set, it is difficult to set the tunnel magnetoresistive element TMR of the dummy memory cell to an intermediate resistance value.

  FIG. 14 is a schematic diagram illustrating another data read operation using a conventional sense amplifier.

  Referring to FIG. 14, here, sense amplifiers SA # similar to the sense amplifiers SA described in FIG. 13 are provided, and an electrical connection is made between node N1 of sense amplifier SA and node N1 # of sense amplifier SA #. A case is shown in which a switch element QSWa that is electrically coupled and a switch element QSWb that electrically couples the node N2 of the sense amplifier SA and the node N2 # of the sense amplifier SA # are provided.

  On the memory cell side, memory cell MC0e and dummy memory cell DMC0e, memory cell MC0o and dummy memory cell DMC0o connected to bit lines BLj and / BLj, respectively, are shown. Also shown are memory cell MC1e and dummy memory cell DMC1e, memory cell MC1o and dummy memory cell DMC1o connected to bit lines BLj + 1 and / BLj + 1, respectively.

  Here, the tunnel magnetoresistive elements of the dummy memory cells DMC0e and DMC0o are set to the resistance value Rmin, and the tunnel magnetoresistive elements of the dummy memory cells DMC1e and DMC1o are set to the resistance value Rmax.

The operation of the sense amplifier is the same, and the data read operation will be described.
Selected column select line CSLk corresponding to input address ADD for executing the data read operation and word line provided corresponding to the selected memory cell are activated ("H" level). A word line provided corresponding to the dummy memory cell is activated (“H” level). In the case of this configuration, a case where two columns are selected in parallel and data reading is executed will be described. As an example, the data read operation of even-numbered memory cells MC0e and MC1e will be described.

  In this example, a word line WLe is provided corresponding to the even-numbered row of memory cells, and a word line WLo is provided corresponding to the odd-numbered row. Similarly, the word line WLDe is provided corresponding to the even-numbered rows of the dummy memory cells, and the word line WLDo is provided corresponding to the odd-numbered rows.

  In response to activation of selected column selection line CSLk, gate transistors CSGa and CSGb are turned on, and bit lines BLj, / BLj and local input / output lines LIO0, / LIO0 of the selected column are electrically coupled. . In response to the activation of the selected column selection line CSLk, the gate transistors CSGa # and CSGb # are turned on, and the bit lines BLj + 1 and / BLj + 1 and the local input / output lines LIO1 and / LIO1 in the selected column are electrically connected. Combined with

  In response to activation of the word line WLe according to the selection of the memory cells MC0e and MC1e in the even row, the access transistor ATR is turned on, and the local input / output line LIO0 is connected to the ground voltage GND via the bit line BLj and the selected memory cell MC0e. Pulled down to In response to activation of word line WLDo, local input / output line / LIO0 is pulled down to ground voltage GND via bit line / BLj and dummy memory cell DMC0o. Accordingly, a current path is formed between sense amplifier SA and selected memory cell MC0e and dummy memory cell DMC0o.

  Similarly, in response to activation of the word line WLe, the access transistor ATR is turned on, and the local input / output line LIO1 is pulled down to the ground voltage GND through the bit line BLj + 1 and the selected memory cell MC1e. In response to activation of word line WLDo, local input / output line / LIO1 is pulled down to ground voltage GND through bit line / BLj + 1 and dummy memory cell DMC1o. Accordingly, a current path is formed between sense amplifier SA # and selected memory cell MC1e and dummy memory cell DMC1o.

  Control signal RAE (“H” level) is input, and node N2 and node N2 # are electrically coupled via switch element QSWb.

  Here, a dummy memory cell DMC0o having a resistance value Rmin is connected to the node N2, and a dummy memory cell DMC1o having a resistance value Rmax is connected to the node N2 #.

  That is, since the nodes N2 and N2 # are set to substantially the same potential, a current corresponding to the resistance value (Rmax + Rmin) / 2 is supplied. That is, the same reference current Iref as that when the dummy memory cell is set to an intermediate value between the maximum value Rmax and the minimum value Rmin is supplied.

  In this case, ideally, regarding the voltages of the nodes N2 and N2 #, the voltage V1 = V0 is desired, but a voltage difference is generated because of the ON resistance value Ron of the switch element QSWb.

Here, resistance value RL corresponds to the load resistance of transistors QP5 and QP5 #.
In the amplification units 50 and 50 #, the voltage difference according to the on-resistance value Ron of the switch element QSWb described above changes the potential on the reference side of the amplification units 50 and 50 #, so that there is no margin margin and highly accurate data. Reading can be difficult to perform.

  FIG. 15 is a schematic configuration diagram illustrating still another data read operation using a conventional sense amplifier.

  Referring to FIG. 15, here, the sense amplifiers SA and SA # described in FIG. 14 have a configuration in which nodes N1 and N1 # are connected in common without providing switch elements QSWa and QSWb having on-resistance. Has been.

  A so-called switcher 60 is connected between the transistors QV1, QV2 of the sense amplifier SA and the local input / output lines LIO0, / LIO0, and between the transistors QV1 #, QV2 # of the sense amplifier SA # and the local input / output lines LIO1, / LIO1. It is the structure provided in.

  Switcher 60 includes transistors 61-68. Transistors 61-68 are N channel MOS transistors.

  The transistor 61 is a switch element that provides a path between the local input / output line LIO0 and the transistor QV2. Transistor 62 is a switch element that provides a path between transistor QV1 and local input / output line / LIO0. Transistors 61 and 62 receive control signal RAE (“H” level) and are turned on to switch the connection path between transistors QV1 and QV2 and local input / output lines LIO0 and / LIO0.

  The transistor 63 is a switch element that provides a path between the local input / output line LIO0 and the transistor QV1. Transistor 64 is a switch element that provides a path between transistor QV2 and local input / output line / LIO0. Transistors 63 and 64 receive control signal RAO (“H” level) and are turned on to form a connection path between transistors QV1 and QV2 and local input / output lines LIO0 and / LIO0.

  Transistor 65 is a switch element that provides a path between local input / output line LIO1 and transistor QV2 #. Transistor 66 is a switch element that provides a path between transistor QV1 # and local input / output line / LIO1. Transistors 65 and 66 receive control signal RAE (“H” level) and are turned on to switch the connection path between transistors QV1 # and QV2 # and local input / output lines LIO1 and / LIO1.

  Transistor 67 is a switch element that provides a path between local input / output line LIO1 and transistor QV1 #. Transistor 68 is a switch element that provides a path between transistor QV2 # and local input / output line / LIO1. Transistors 67 and 68 receive control signal RAE (“H” level) and are turned on to form a connection path between transistors QV1 # and QV2 # and local input / output lines LIO1 and / LIO1.

  That is, the switcher 60 controls the nodes N1 and N1 # to be always connected to the dummy memory cell DMC according to the input of the control signals RAE and RAO.

In the case of this configuration, since the switch elements QSWa and QSWb are not provided, it is possible to suppress a problem that a voltage difference occurs between the nodes N1 and N1 #. Further, the switcher 60 has a configuration in which one transistor is interposed one by one in any path, so that a resistance difference (or voltage difference) hardly occurs on the local input / output line side.
JP 2004-164766 A JP 2005-366536 A JP 2006-046929 A Takaharu Tsuji, Hiroaki Tanizaki etal, "A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture", 2004 Symposium on VLSI Circuits Digest of Technical Papers, p450-453

  However, in the case of the configuration in which the switcher 60 is provided, as described above, since the transistor is interposed one by one, the applied voltage of the tunnel magnetoresistive element TMR for the on-resistance of the transistor constituting the switcher 60 is reduced. Thus, the data read margin is reduced because the difference in passing current is reduced.

  On the other hand, by adjusting the reference voltage Vref, it is possible to secure a certain amount of source / drain voltages of the transistors QV1, QV1 #, QV2, and QV2 # and raise the applied voltage of the tunnel magnetoresistive element TMR. Therefore, the range of signal amplitudes of the nodes N1, N1 #, N2, and N2 # is narrowed. That is, since the voltage amplitude (voltage signal difference) of the input signals input to the amplification units 50 and 50 # is reduced, the high-speed operation of the amplification units 50 and 50 # is hindered.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory device capable of performing a data reading operation at high speed and high accuracy.

  According to one embodiment of the present invention, each of a plurality of memory cells through which a passing current according to stored data flows during data reading, a first and second data line pair, and a first and second data line First and second differential amplifying units provided corresponding to the pairs, respectively, for executing parallel data reading based on passing currents flowing through the first and second data line pairs during data reading. . At the time of data reading, each of one side of the first and second data line pairs is electrically connected to a first voltage via a selected memory cell selected from the plurality of memory cells. In addition, each of the other side of the first and second data line pairs is electrically coupled to two dummy memory cells used for comparison with the selected memory cell of the plurality of memory cells, respectively. Is done. Each of the first and second differential amplifying units has a gate terminal electrically coupled to a corresponding one of the first and second data line pairs, respectively, and a gate Includes a pair of first transistors connected to a reference voltage. A pair of second transistors each having a gate connected between the other conduction terminal of each of the pair of first transistors and the second voltage and having a gate connected to the other conduction terminal of each of the pair of first transistors. And a pair of capacitors having one electrode connected to the other conduction terminal of each of the pair of first transistors and a second electrode connected to the first and second input nodes. An amplifier circuit that amplifies the potential difference between the first and second input nodes connected to the other electrode of the pair of capacitors is also included. Controls one electrical connection between the first input node and the second input node connected to a capacitor connected to each of the other side of the first and second data line pairs. A connection control unit is further provided. One dummy memory cell of the two dummy memory cells electrically coupled to each of the other side of the first and second data line pairs has a high level indicating one data level of storage data of the memory cell. The resistance state is set, and the other dummy memory cell is set to a low resistance state indicating the other data level of the storage data of the memory cell.

  According to this embodiment, the first differential amplifier section includes a pair of first transistors connected to the amplifier circuit, the first and second input nodes of the amplifier circuit, and the first data line pair. A pair of capacitors is provided between the other conductive terminal of the first and second conductive terminals. The second differential amplifier includes an amplifier circuit, first and second input nodes of the amplifier circuit, and the other conduction terminal of the pair of first transistors connected to the second data line pair, respectively. A pair of capacitors is provided between the two. In addition, a connection control unit that controls any one of the electrical connections between the first input nodes and between the second input nodes is further provided.

  The other side of the first and second data line pairs is connected to two dummy memory cells, one set to a high resistance state and the other to a low resistance state.

  The other side of the data line pair is connected to the dummy memory cell, and one of the first input node and the second input node of the amplifier circuit connected to the other side of the data line pair via the capacitor is Electrically connected.

  Therefore, a passing current corresponding to the high resistance state and a passing current corresponding to the low resistance state flow on the other side of the first and second data line pairs.

  A potential change corresponding to the passing current is transmitted to the input node of the amplifier circuit via the capacitor. One of the input nodes of the amplifier circuit is set to an intermediate potential between the potential change in the high resistance state and the potential change in the low resistance state because the input control nodes are electrically connected by the connection control circuit. Since the potential change in the high resistance state or the potential change in the low resistance state of the selected memory cell, data reading according to the difference in the potential change is executed.

  When the connection control circuit is electrically coupled between the input nodes and set to an intermediate potential, a transient current accompanying the movement of charge flows but no steady current flows, so that the selected memory cell Therefore, a high-speed and highly accurate data reading operation can be performed.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to Embodiment 1 of the present invention.

  As will be apparent from the following description, the application of the present invention is not limited to an MRAM device having an MTJ memory cell, but a memory cell in which a passing current according to the level of written storage data flows. It can apply in common to a non-volatile memory device provided with.

  Referring to FIG. 1, MRAM device 1 includes a control circuit 5 that controls the overall operation of MRAM device 1 in response to a control signal CMD, and a memory array that includes MTJ memory cells MC arranged in a matrix. MA.

  Here, the rows and columns of the plurality of memory cells MC arranged and arranged in a matrix in each memory array MA are also referred to as memory cell rows and memory cell columns, respectively.

  The MRAM device 1 also includes a row decoder 20, a column decoder 25, and an input / output control circuit 30. The row decoder 20 selectively performs row selection in the memory array MA to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 selectively performs column selection of the memory array MA to be accessed based on the column address CA included in the address signal ADD.

  The input / output control circuit 30 controls input / output of data such as input data DIN, output data DOUT, etc., and transmits it to the internal circuit or outputs it to the outside in response to an instruction from the control circuit 5.

  In the following, the binary high voltage state and low voltage state of signals, signal lines, data, etc. are also referred to as “H” level and “L” level, respectively.

Here, the circuit configuration of the memory cell MC will be described.
FIG. 2 is a schematic diagram showing a configuration of an MTJ memory cell MC (hereinafter also simply referred to as a memory cell MC) having a magnetic tunnel junction.

  Referring to FIG. 2, memory cell MC includes a tunnel magnetoresistive element TMR whose electrical resistance changes according to the data level of magnetically written storage data, and access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between bit line BL and ground voltage GND. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR.

  For memory cell MC, there are provided bit line BL and digit line DL for flowing data write currents in different directions at the time of data writing, and word line WL activated at the time of data reading. In data reading, tunnel magnetoresistive element TMR is electrically coupled between ground voltage GND and bit line BL in response to turn-on of access transistor ATR.

Here, the configuration of the MTJ memory cell and the data storage principle will be described.
FIG. 3 is a conceptual diagram for explaining the structure and data storage principle of the MTJ memory cell.

  Referring to FIG. 3, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. And a ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that can be magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB, and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of tunneling magneto-resistance element TMR becomes the minimum value Rmin when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), and the magnetization directions of both are The maximum value Rmax is obtained in the opposite (antiparallel) direction.

  At the time of data writing, word line WL is deactivated and access transistor ATR is turned off. In this state, the data write current for magnetizing free magnetic layer VL flows in the direction corresponding to the level of the write data in each of bit line BL and digit line DL.

  FIG. 4 is a conceptual diagram showing the relationship between the supply of the data write current to the MTJ memory cell and the magnetization direction of the tunnel magnetoresistive element.

  Referring to FIG. 4, the horizontal axis H (EA) represents a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and digit line DL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy axis of the free magnetization layer VL, and the free magnetization layer VL extends in the easy axis direction according to the level of stored data. Along this direction, the magnetization is magnetized in a direction parallel or antiparallel (opposite) to the fixed magnetization layer FL. The MTJ memory cell can store 1-bit data corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As shown by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold necessary to change the magnetization direction along the easy axis can be lowered. it can. As shown in FIG. 4, the operating point at the time of data writing is that the data stored in the MTJ memory cell, that is, the tunnel magnetoresistance when a predetermined data write current is passed through both the digit line DL and the bit line BL. It is designed so that the magnetization direction of element TMR can be rewritten.

At the operating point illustrated in FIG. 4, the data write magnetic field in the easy axis direction is designed so that its strength is H _WR in the MTJ memory cell that is the data write target. That is, the value of the data write current that flows through bit line BL or digit line DL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

  The data reading operation of the present invention described below will be described on the assumption that the resistance value of each memory cell is set to the high resistance value Rmax or the low resistance value Rmin in advance according to the stored data. Each of the dummy memory cells DMC arranged in the memory array MA of FIG. 2 is fixedly set to an electrical resistance value Rmid intermediate between the pre-written high resistance value Rmax and low resistance value Rmin. And

  FIG. 5 is a conceptual diagram of a memory array MA and a peripheral circuit that performs data reading of the memory array MA (hereinafter also referred to as a data reading system circuit).

  Referring to FIG. 5, here, a circuit group for a data read operation provided corresponding to memory array MA included in input / output control circuit 30 is shown.

  The memory array MA includes memory cells MC integrated and arranged in a matrix and a plurality of dummy memory cells DMC provided as a comparison target of the memory cells MC. The memory array MA is provided with a bit line pair BLP corresponding to two adjacent memory cell columns. Bit line pair BLP includes BL provided corresponding to the memory cell column and complementary bit line / BL. A plurality of dummy memory cells DMC are provided one by one so as to share a memory cell column. In FIG. 2, memory cell MC0e and dummy memory cell DMC0e provided corresponding to bit line BLj and memory cell MC0o provided corresponding to bit line / BLj and dummy memory of jth bit line pair BLPj. Cell DMC0o is shown representatively. Of the j + 1th bit line pair BLPj + 1, the memory cell MC1e and the dummy memory cell DMC1e provided corresponding to the bit line BLj + 1, the memory cell MC1o provided corresponding to the bit line / BLj + 1, and the dummy memory cell DMC1o Shown representatively.

  With this configuration, dummy memory cells can be efficiently arranged and the area of the memory array can be reduced.

  A plurality of word lines WL are provided corresponding to the memory cell rows. In this example, word lines WLe and WLo provided corresponding to the even and odd rows of the memory cells MC, respectively, and word lines WLDe provided corresponding to the even and odd rows of the dummy memory cells DMC, respectively. , WLDo. A digit line (not shown) to which a data write current for executing data write to memory cell MC is supplied is provided corresponding to each memory cell row.

  Further, a plurality of column selection lines are provided corresponding to each of the two bit line pairs BLP and to which a column selection instruction from the column decoder 25 is transmitted. In this example, column selection line CSLk (k = j / 2) provided corresponding to bit line pair BLPj, BLPj + 1 is shown as an example.

  Input / output control circuit 30 includes a local input / output line pair LIP0 and a gate circuit IOG for controlling electrical connection between local input / output line pair LIP1 and bit line pair BLPj, BLPj + 1, provided in memory array MA. Local input / output line pair LIP0 has local input / output lines LIO0 and / LIO0. The local input / output line pair LIP1 includes local input / output lines LIO1 and / LIO1.

  Gate circuit IOG includes gate transistors CSGa and CSGb that electrically connect local I / O line pair LIP0 and bit line pair BLPj in response to a column selection instruction from a column decoder.

  Gate circuit IOG includes gate transistors CSGa # and CSGb # that electrically connect local input / output line pair LIP1 and bit line pair BLPj + 1 in response to a column selection instruction from a column decoder.

  Gate transistors CSGa and CSGb electrically connect bit lines BLj and / BLj to local input / output lines LIO0 and / LIO0 in response to activation of column select line CSLk. Gate transistors CSGa # and CSGb # electrically connect bit lines BLj + 1 and / BLj + 1 and local input / output lines LIO1 and / LIO1 in response to activation of column select line CSLk.

  In addition, input / output control circuit 30 further amplifies data stored in the selected memory cell detected by sense amplifier SA and sense amplifier SA that detects read data corresponding to a difference in passing current generated in local input / output lines LIO and / LIO. And a preamplifier PA.

  The input / output control circuit 30 is connected to the global input / output line pair GIOP0, GIOP1 and the global input / output line pair GIOP0, GIOP1 provided in common to each memory array MA, and latch circuit LT0 that latches stored data. , LT1. Input / output control circuit 30 includes an output buffer OBF that outputs read data RDT0 and RDT1 latched by latch circuits LT0 and LT1 to the outside as output data DOUT0 and DOUT1. Global input / output line pair GIOP0 includes global input / output lines GIO0 and / GIO0. Global input / output line pair GIOP1 includes global input / output lines GIO1 and / GIO1.

  Gate circuit IOG further includes an equalize circuit EQ for equalizing bit lines BLj and / BLj and bit lines BLj + 1 and / BLj + 1. The equalize circuit EQ electrically connects the bit lines BLj, / BLj and the bit lines BLj + 1, / BLj + 1 in response to the input of the control signal BLEQ generated by the row decoder 20 and equalizes the ground voltage GND although not shown. And are precharged.

  Similar equalize circuits EQ are provided between local input / output lines LIO0 and / LIO0 and between local input / output lines LIO1 and / LIO1. The equalizer circuit EQ is electrically connected to the local input / output lines LIO0, / LIO0 in response to the input of the control signal BLEQ, further electrically connected to the local input / output lines LIO1, / LIO1, and is not shown. Is electrically coupled to ground voltage GND and precharged.

  Thus, before data reading, in response to the input of control signal BLEQ, local I / O line pair LIP0, LIP1 and bit line pair BLPj, BLPj + 1 are electrically coupled to ground voltage GND and precharged. The operation reliability of the memory cell MC can be ensured without applying a high voltage to the cell MC.

  FIG. 6 is a circuit configuration diagram of sense amplifiers SA0 and SA1 according to the first embodiment of the present invention.

  Referring to FIG. 6, sense amplifiers SA0 and SA1 according to the first embodiment of the present invention include transistors QP1, QP5, QC1 #, and QP5 #. Transistors QP1, QP5, QP1 #, and QP5 # are assumed to be P-channel MOS transistors as an example.

  Since transistors QP1, QP5, QC1 #, and QP5 # are similar to those described above, detailed description thereof will not be repeated.

A precharge circuit 70 is further provided.
The precharge circuit 70 includes transistors 71 to 78. Transistor 71 is provided between precharge voltage Vcc and node N1, and has its gate receiving control signal PC. Transistor 72 is provided between precharge voltage VPC and node N1a, and has its gate receiving control signal PC. Transistor 73 is provided between precharge voltage VPC and node N2a, and has its gate receiving control signal PC. Transistor 74 is provided between precharge voltage Vcc and node N2, and has its gate receiving control signal PC. Transistor 75 is provided between precharge voltage Vcc and node N1 #, and its gate receives control signal PC. Transistor 76 is provided between precharge voltage VPC and node N1b, and has its gate receiving control signal PC. Transistor 77 is provided between precharge voltage VPC and node N2b, and has its gate receiving control signal PC. Transistor 78 is provided between precharge voltage Vcc and node N2 #, and has a gate receiving control signal PC. The precharge voltage VPC is set to a voltage level lower than the precharge voltage Vcc (= power supply voltage Vcc), but can be set to the same voltage level as the precharge voltage Vcc.

  Corresponding to sense amplifier SA0, capacitor C1 is provided between transistor QV1 and node N1a. A capacitor C2 is provided between the transistor QV2 and the node N2a.

  Corresponding to sense amplifier SA1, capacitor C1 # is provided between transistor QV1 # and node N1b. Capacitor C2 # is provided between transistor QV2 # and node N2b.

  Precharge circuit 70 operates in response to the input of control signal PC (“H” level), precharges nodes N1, N2, N1 #, and N2 # with precharge voltage Vcc before the data read operation. N1a, N1b, N2a, and N2b are precharged by the precharge voltage VPC.

  Sense amplifier SA0 is arranged between node N1 and local input / output line LIO0, and its gate receives transistor QV1 receiving reference voltage Vref generated by Vref generation circuit 40, and node I2 and local input / output. Disposed between line / LIO0 and its gate includes transistor QV2 receiving reference voltage Vref.

  Sense amplifier SA1 is arranged between node N1 # and local input / output line LIO1, and has its gate receiving transistor QV1 # receiving a reference voltage Vref generated by Vref generation circuit 40, and node N2 #. Arranged between local input / output line / LIO1 and its gate includes a transistor QV2 # receiving an input of reference voltage Vref.

  With respect to sense amplifier SA0, local input / output lines LIO0 and / LIO0 are maintained at a predetermined voltage equal to or lower than reference voltage Vref by transistors QV1 and QV2 receiving reference voltage Vref at their gates. Memory cell MC and dummy memory in which this predetermined voltage is selected A passing current according to the stored data applied to the cell DMC flows through the local input / output lines LIO0 and / LIO0.

  For sense amplifier SA1, local input / output lines LIO1 and / LIO1 are maintained at a predetermined voltage equal to or lower than reference voltage Vref by transistors QV1 # and QV2 # receiving a reference voltage Vref at their gates, and the memory cell in which this predetermined voltage is selected A passing current according to the stored data applied to the MC and the dummy memory cell DMC flows through the local input / output lines LIO1, / LIO1.

  Transistors QV1 and QV2 receiving reference voltage Vref at their gates constitute a constant voltage circuit that applies a constant voltage to memory cell MC and dummy memory cell DMC.

  Transistors QV1 # and QV2 # that receive reference voltage Vref at their gates constitute a constant voltage circuit that applies a constant voltage to memory cell MC and dummy memory cell DMC.

  In order to set local input / output lines LIO0 and / LIO0 to a predetermined voltage or lower, the gates of transistors QV1 and QV2 can be electrically coupled to nodes N1 and N2 to form a diode connection. Similarly, in order to set local input / output lines LIO1 and / LIO1 to a predetermined voltage or lower, the gates of transistors QV1 # and QV2 # may be electrically coupled to nodes N1 # and N2 # to form a diode connection. Is possible.

  Sense amplifier SA0 includes an amplification unit 55 that amplifies the voltage difference between the input nodes and outputs read data SOUT0 with nodes N1a and N2a as input nodes corresponding to sense amplifier SA0.

  Sense amplifier SA1 includes an amplification unit 55 # that amplifies the voltage difference between the input nodes and outputs read data SOUT1 with nodes N1b and N2b as input nodes corresponding to sense amplifier SA1.

  Further, the transistor 80 that controls electrical connection between the node N1a of the sense amplifier SA0 and the node N1b of the sense amplifier SA1, and the electrical connection between the node N2a of the sense amplifier SA0 and the node N2b of the sense amplifier SA1. A transistor 81 for controlling connection is provided. Transistors 80 and 81 receive control signals RAO and RAE, respectively.

  The row decoder 20 sets the control signal RAO or RAE to the “H” level in accordance with the input address signal ADD. In response, internal node N1a and internal node N1b are electrically coupled. Alternatively, internal node N2a and internal node N2b are electrically coupled. When the selected memory cell row is an even row, the row decoder 20 sets the control signal RAE to the “H” level. When the selected memory cell row is an odd row, control signal RAO is set to “H” level.

  Further, as described in FIG. 5, on the memory cell side, memory cell MC0e and dummy memory cell DMC0e, memory cell MC0o and dummy memory cell DMC0o connected to bit lines BLj and / BLj, respectively, are shown. . Also shown are memory cell MC1e and dummy memory cell DMC1e, memory cell MC1o and dummy memory cell DMC1o connected to bit lines BLj + 1 and / BLj + 1, respectively.

  Here, the tunnel magnetoresistive elements of the dummy memory cells DMC0e and DMC0o are set to the resistance value Rmin, and the tunnel magnetoresistive elements of the dummy memory cells DMC1e and DMC1o are set to the resistance value Rmax.

Next, the configuration of the amplification unit 55 will be described.
FIG. 7 is a diagram for explaining the amplification unit 55.

  Referring to FIG. 7, amplifying unit 55 includes a transistor QP2 which is arranged between a power supply node to which power supply voltage Vcc is supplied and internal node N4 and whose gate is electrically coupled to internal node N1a. . Further, transistor QP3 is arranged between a power supply node to which power supply voltage Vcc is supplied and internal node N7, and has its gate electrically coupled to internal node N2a. Further, transistor QP6 is arranged between a power supply node supplied with power supply voltage Vcc and internal node N6, and has its gate electrically coupled to internal node N2a. Further, transistor QP7 is arranged between a power supply node to which power supply voltage Vcc is supplied and internal node N8, and has its gate electrically coupled to internal node N1a. Transistor QN1 is arranged between internal node N4 and internal node N5, and has its gate electrically coupled to internal node N4. In addition, transistor QN2 is arranged between internal node N7 and internal node N5, and its gate is electrically coupled to internal node N4, and is arranged between internal node N8 and internal node N5. Transistor QN3 electrically coupled to internal node N6 is included. Transistor QN4, which is arranged between internal node N5 and internal node N6 and whose gate is electrically coupled to internal node N6, and voltage supply unit 56 for supplying ground voltage GND to internal node N5, including.

  Voltage supply unit 56 includes a transistor QNS provided between internal node N5 and ground voltage GND, and transistor QNS receives control signal SAE.

  Although not shown in FIG. 6, a voltage supply unit 57 provided between the source side of the transistors QP1 and QP5 and the power supply voltage Vcc is provided here.

  Voltage supply unit 57 includes a transistor QPS provided between power supply voltage Vcc and the source side of transistors QP1 and QP5, and transistor QPS receives control signal / SAE.

  Control signals SAE and / SAE are set to “H” level and “L” level when data is read by row decoder 20. In response to the input of control signals SAE and / SAE, sense amplifier SA0 is activated. Here, the configuration in which the control signals SAE and / SAE are output from the row decoder 20 has been described. However, the configuration is not limited thereto, and for example, the control signal 5 may be output from the control circuit 5.

  Here, transistors QP1 to QP7 and QPS are assumed to be P-channel MOS transistors as an example. Transistors QN1-QN4, QNS, QV1, and QV2 are N-channel MOS transistors as an example. In this example, the transistors QP1 to QP7 have the same transistor size. The transistor sizes of the transistors QN1 to QN4 are assumed to be equal.

  In this example, the description will be made assuming that the transistor sizes are equal. However, it is also possible to adjust the operating current amount by adjusting the transistor size. Specifically, an operating current corresponding to the transistor size ratio is supplied. The same applies to the following.

  The local input / output lines LIO0 and / LIO0 are maintained at a predetermined voltage equal to or lower than the reference voltage by the transistors QV1 and QV2 receiving the reference voltage Vref at the gate described above, and a passing current according to the predetermined voltage flows to the nodes N1 and N2.

  Transistor QP1 has a gate and a drain electrically coupled, and converts a passing current flowing through node N1 into a voltage signal. Transistor QP5 has a gate and a drain electrically coupled, and converts a passing current flowing through node N2 into a voltage signal.

  Here, the capacitor C1 is provided between the node N1 and the node N1a, and the capacitor C2 is provided between the node N2 and the node N2a.

  Therefore, voltage signals generated at nodes N1 and N2 are transmitted to nodes N1a and N2a by capacitive coupling.

  Transistors QP2, QP3, QP6, QP7, QN1, QN2, QN3, and QN4 receive the voltage signals converted in transistors QP1 and QP5 as a pair of inputs, and amplify a signal corresponding to the passing current flowing through nodes N1 and N2. Thus, an amplification unit that outputs to the internal nodes N7 and N8 is configured. The amplification unit includes two differential input amplifier circuits provided corresponding to internal nodes N7 and N8. Specifically, the first differential input amplifier circuit includes transistors QP2, QP3, QN1, and QN2 provided corresponding to internal node N7, and the voltage signal converted in transistors QP1 and QP5 is a pair of input signals. Is equivalent to a source-type ground differential input amplifier circuit which is input to the gates of the transistors QP2 and QP3 and detects and amplifies the difference between them. The second differential input amplifier circuit includes transistors QP7, QP6, QN3, QN4 provided corresponding to internal node N8, and the voltage signal converted in transistors QP1, QP5 is used as a pair of input signals as transistor QP7. , QP6, which corresponds to a common source differential input amplifier circuit that detects and amplifies the difference.

  In the above description, the configuration of the amplification unit 55 of the sense amplifier 0 is described, but the configuration of the amplification unit 55 # of the sense amplifier SA1 is the same.

Next, the circuit configuration of the preamplifier PA will be described.
Here, preamplifiers PA0 and PA1 (hereinafter collectively referred to as preamplifier PA) provided corresponding to sense amplifiers SA0 and SA1, respectively, will be described.

FIG. 8 is a circuit configuration diagram of preamplifier PA according to the first embodiment of the present invention.
Referring to FIG. 8, preamplifier PA according to the first embodiment of the present invention further amplifies read data SOUT, / SOUT from internal nodes N7, N8, and amplifies voltage signals to internal nodes PAO and / PAO. And a voltage adjustment unit SCT for adjusting the voltage levels of global input / output lines GIO and / GIO in response to voltage signals generated at internal nodes PAO and / PAO.

  Amplified signal generation circuit AMP is arranged between node NN0 and power supply voltage Vcc, and supplies a power supply voltage Vcc to node NN0 in response to control signal / PAE from row decoder 20, and node NN0 and node NN0. Transistor TP1 is arranged between NN1 and has its gate electrically coupled to node NN1. Further, transistor TP2 is arranged between node NN0 and internal node / PAO, and its gate is electrically coupled to node NN1, and is arranged between node NN0 and internal node PAO, and its gate is connected to node NN2. Includes a transistor TP3 electrically coupled to node NN0 and node NN2, and a transistor TP4 having a gate electrically coupled to node NN2. Further, transistor TN1 is arranged between node NN1 and ground voltage GND, and its gate is electrically coupled to sense node SN, and is arranged between internal node PAO and ground voltage GND, and its gate is sensed. Transistor TN2 electrically coupled to node SN and transistor TN3 arranged between internal node / PAO and ground voltage GND and having its gate electrically coupled to sense node / SN are included. Transistor TN4 is arranged between node NN2 and ground voltage GND, and has its gate electrically coupled to sense node / SN.

  Here, the transistors TP1 to TP4 and TPS are assumed to be P-channel MOS transistors as an example. As an example, the transistors TN1 to TN4 are N-channel MOS transistors. In this example, the transistors TP1 to TP4 have the same transistor size. The transistor sizes of the transistors TN1 to TN4 are assumed to be equal.

  As an example, when read data SOUT, / SOUT are at “H” level and “L” level, transistor TN2 is turned on and internal node PAO is electrically connected to ground voltage GND and set to “L” level. . On the other hand, with respect to internal node / PAO, the same operating current as transistor TP1 is about to be supplied from transistor TP2, but read data / SOUT is at "L" level, so that almost no current flows from transistor TN3. Therefore, the voltage level of internal node / PAO is set to “H” level.

  Also in the sense amplifier SA, a voltage difference corresponding to the data stored in the selected memory cell is generated, but an operation of further amplifying the voltage difference is executed by the amplification signal generation circuit AMP in order to execute more stable data reading. Is done.

  Voltage adjustment unit SCT is arranged between buffers 26 and 27 that stably output the voltage level generated at internal nodes PAO and / PAO, global input / output line GIO and ground voltage GND, and its gate is a buffer. 26 includes a transistor TN0 receiving an output signal of 26, and a transistor TN5 arranged between global input / output line / GIO and ground voltage GND and having a gate receiving an output signal of buffer 27. Transistors TN0 and TN5 are N-channel MOS transistors as an example.

  Global input / output lines GIO and / GIO are precharged to a predetermined voltage level by a predetermined precharge operation before data reading.

  One of global input / output lines GIO and / GIO is electrically coupled to ground voltage GND in accordance with a voltage signal generated at internal nodes PAO and / PAO. Accordingly, one of the logical levels of global input / output lines GIO, / GIO is set to “H” level and the other is set to “L” level.

  Therefore, global input / output lines GIO, / GIO can be set to fixed power supply voltage Vcc and ground voltage GND logic levels corresponding to the stored data of the memory cells, so that stable data reading is performed. Can do.

  A preamplifier PA0 is provided corresponding to sense amplifier SA0, and preamplifier PA0 is connected to global input / output line pair GIOP0.

  A preamplifier PA1 is provided corresponding to the sense amplifier SA1, and the preamplifier PA1 is connected to the global input / output line pair GIOP1.

Next, the circuit configuration of the latch circuit LT will be described.
Here, latch circuits LT0 and LT1 (hereinafter also collectively referred to as latch circuit LT) provided corresponding to global input / output line pairs GIOP0 and GIOP1, respectively, will be described.

FIG. 9 is a circuit configuration diagram of latch circuit LT according to the first embodiment of the present invention.
Referring to FIG. 9, latch circuit LT includes an equalize unit EQC for equalizing global input / output lines GIO, / GIO, and NAND circuits ND0 and ND1.

  Equalize unit EQC includes transistors 21-23. Transistors 21 and 22 are connected in series between global input / output lines GIO and / GIO, and their gates receive control signal IOEQ from row decoder 20. The connection node of transistors 21 and 22 is electrically coupled to power supply voltage Vcc. Transistor 23 is arranged between global input / output lines GIO and / GIO, and has a gate receiving control signal IOEQ. That is, when control signal IOEQ at “L” level is input before data reading, power supply voltage Vcc (“H” level) is electrically coupled to global input / output lines GIO and / GIO and precharged. Is done. Transistors 21 to 23 are P-channel MOS transistors as an example.

  NAND circuit ND1 receives inputs from global input / output line GIO and output node Nf, and outputs the NAND logical operation result to an input node of ND0. NAND circuit ND0 receives the global input / output line / GIO and the output signal of NAND circuit ND1, and outputs the NAND logical operation result to output node Nf. The latch circuit LT outputs the voltage level generated at the output node Nf to the output buffer OBF as read data RDT.

  For example, output node Nf is assumed to be set at “L” level in the initial state. Here, when global input / output line GIO is set to “L” level after global input / output line pair GIOP is precharged, the voltage level of output node Nf is set to “0” by the logical operation of NAND circuits ND0 and ND1. Latched to “L” level. On the other hand, when global input / output line / GIO is set to “L” level, the voltage level of output node Nf is latched to “H” level by the logical operation. Read data RDT corresponding to the latched voltage signal is output to output buffer OBF. Note that the latch circuit LT and the output buffer OBF shown in this example constitute a data generation circuit that generates output data.

  In this example, read data RDT0 is output to output buffer OBF from latch circuit LT0 provided corresponding to global input / output line pair GIOP0. Read data RDT1 is output to output buffer OBF from latch circuit LT1 provided corresponding to global input / output line pair GIOP1.

  The output buffer OBF receives the read data RDT0 and RDT1, and outputs the output data DOUT0 and DOUT1.

  A data read operation of sense amplifiers SA0 and SA1 according to the first embodiment of the present invention will be described using FIG.

  In the case of this configuration, a case where two columns are selected in parallel and data reading is executed will be described. As an example, the data read operation of even-numbered memory cells MC0e and MC1e will be described.

  When the data read operation is started, the selected column select line CSLk corresponding to the input address ADD for executing the data read operation and the word line WLe provided corresponding to the selected memory cell are activated. (“H” level). In addition, word line WLDo provided corresponding to the dummy memory cell is activated (“H” level). Before executing the data read operation, the control signal PC is set to “H” level, each node is precharged by the precharge voltage Vcc or the precharge voltage VPC, and the control signal PC is set to “L”. The precharge ends as the level is set.

  In response to activation of selected column selection line CSLk, gate transistors CSGa and CSGb are turned on, and bit lines BLj, / BLj and local input / output lines LIO0, / LIO0 of the selected column are electrically coupled. . In response to the activation of the selected column selection line CSLk, the gate transistors CSGa # and CSGb # are turned on, and the bit lines BLj + 1 and / BLj + 1 and the local input / output lines LIO1 and / LIO1 in the selected column are electrically connected. Combined with

  In response to activation of the word line WLe according to the selection of the memory cells MC0e and MC1e in the even row, the access transistor ATR is turned on, and the local input / output line LIO0 is connected to the ground voltage GND via the bit line BLj and the selected memory cell MC0e. Pulled down to In response to activation of word line WLDo, local input / output line / LIO0 is pulled down to ground voltage GND via bit line / BLj and dummy memory cell DMC0o. Accordingly, a current path is formed between sense amplifier SA and selected memory cell MC0e and dummy memory cell DMC0o.

  Similarly, in response to activation of the word line WLe, the access transistor ATR is turned on, and the local input / output line LIO1 is pulled down to the ground voltage GND through the bit line BLj + 1 and the selected memory cell MC1e. In response to activation of word line WLDo, local input / output line / LIO1 is pulled down to ground voltage GND through bit line / BLj + 1 and dummy memory cell DMC1o. Accordingly, a current path is formed between the sense amplifier SA1, the selected memory cell MC1e, and the dummy memory cell DMC1o.

  Control signal RAE (“H” level) is input, and node N 2 a and node N 2 b are electrically coupled through transistor 81. Control signal RAO is set to the “L” level.

  Here, as described above, the capacitor C2 is provided between the node N2a and the node N2, and the node N2 is connected to the dummy memory cell DMC0o having the resistance value Rmin. As described above, capacitor C2 # is provided between node N2b and node N2 #, and node N2 # is connected to dummy memory cell DMC1o having resistance value Rmax.

  Therefore, currents Imax and Imin according to dummy memory cells DMC0o and DMC1o having resistance values Rmin and Rmax flow through nodes N2 and N2 #, respectively.

  The potentials of the nodes N2 and N2 # are lowered from the power supply voltage Vcc by a voltage drop based on the product of the currents Imax and Imin and the load resistances of the transistors QP5 and QP5 #.

  The potential of the node N2a changes from the precharge voltage VPC by the potential change of the node N2 due to capacitive coupling of the capacitor C2. That is, the voltage drop changes based on the product of the current Imax and the load resistance of the transistor QP5.

  On the other hand, the potential of the node N2b changes from the precharge voltage VPC by the potential change of the node N2 # due to capacitive coupling of the capacitor C2 #. That is, the voltage drop changes based on the product of current Imin and the load resistance of transistor QP5 #.

  As described above, since the node N2a and the node N2b are electrically coupled via the transistor 81, the node N2a and the node N2b are set to the same potential due to the movement of charges.

  That is, an intermediate voltage drop corresponding to a voltage drop generated at nodes N2 and N2 # by transistors QP5 and QP5 # due to currents Imax and Imin flowing due to capacitive coupling of capacitors C2 and C2 # to nodes N2a and N2b, respectively. A potential change in minutes will occur.

  In other words, this is equivalent to the case where a dummy memory cell having an intermediate resistance value (Rmax + Rmin) / 2 for supplying the reference current Iref, which is an intermediate current between the currents Imax and Imin, is connected to each of the transistors QP5 and QP5 #.

  Then, the amplification unit 55 uses, as a reference, an intermediate potential due to a potential change corresponding to an intermediate voltage drop generated at each of the nodes N2 and N2 # at the input nodes N2a and N2b.

  The sense amplifier SA0 amplifies the potential difference between the intermediate potential of the node N2a and the potential generated at the node N1a based on the resistance value of the selected memory cell MC0e in the amplification unit 55, and outputs it as read data SOUT0.

  Sense amplifier SA1 amplifies the potential difference between the intermediate potential of node N2b and the potential generated at node N1b based on the resistance value of selected memory cell MC1e in amplification unit 55 #, and outputs the result as read data SOUT1.

  In the above, as an example, the word line WLe corresponding to the even-numbered memory cell row selected as an example is activated, the word line WLDo corresponding to the memory cell row of the dummy memory cell is activated, and the memory cells MC0e and MC1e are activated. Although the case where data reading is executed has been described, the same can be applied to memory cells MC0o and MC1o which are odd-numbered memory cell rows. Specifically, the corresponding word line WLo is activated and the word line WLDe is activated. In the sense amplifiers SA0 and SA1, the control signal RAO is set to the “H” level. Further, the control signal RAE is set to the “L” level. Since subsequent operations are similar, detailed description thereof will not be repeated.

  In the configuration according to the first embodiment of the present invention, a configuration in which transistor 81 for controlling electrical coupling between nodes N2a and N2b is provided is described. The accompanying transient current flows, but no steady current flows, and no potential difference occurs on the reference side.

  As shown in FIG. 10, when a current flows between the node N2a and the node N2b, a current difference that fills the current difference × a voltage difference of on-resistance of the transistor is generated. That is, a reference on the high resistance side and a reference on the low resistance side are generated.

  Therefore, with the configuration according to the first embodiment of the present invention, since no current flows, the amplification unit 55, 55 # does not generate a high resistance side reference and a low resistance side reference, and the signal amplitude range is Data reading can be performed widely and with high accuracy.

  Further, in the configuration according to the first embodiment of the present invention, the switcher 60 as described in FIG. 15 is not provided, and a voltage drop corresponding to the on-resistance of the transistor due to the provision of the switcher 60 does not occur. The signal amplitude ranges of the nodes N1, N1 #, N2, and N2 # are never narrowed. Furthermore, since the potential fluctuations of the nodes N1, N1 #, N2, and N2 # are directly transmitted to the input nodes of the amplification units 50 and 50 # by capacitive coupling, the voltage signal difference is sufficiently secured and high-speed operation is performed. Is also possible.

  In the configuration of FIG. 6 described above, only the configuration of the sense amplifiers SA0 and SA1 provided corresponding to the local input / output line pairs LIOP0 and LIOP1 has been described. However, for example, a plurality of local input / output line pairs are provided. The present invention is also applicable to the case where a sense amplifier SA is provided corresponding to each local input / output line pair.

  Specifically, according to a pair of two adjacent sense amplifiers, the two transistors 80 and 81 described above that electrically couple the nodes of two adjacent sense amplifiers are provided, and the two selected A data read system similar to the above can be realized by selectively turning on the corresponding transistors 80 and 81 according to each sense amplifier group.

  Alternatively, it is possible to realize a data read system similar to the above by dividing each sense amplifier into two groups and providing transistors 80 and 81 for each group.

(Embodiment 2)
FIG. 11 is a circuit configuration diagram of sense amplifiers SA0a and SA1a according to the second embodiment of the present invention.

  Referring to FIG. 11, sense amplifier SA0a according to the second embodiment of the present invention is provided with a pair of capacitors C3 and C4 by removing transistors 80 and 81, and a switch provided corresponding to capacitor C3. Circuits SW1 and SW2 and switch circuits SW3 and SW4 provided corresponding to capacitor C4 are further included. The switch circuits SW1 to SW4 are provided corresponding to the capacitors C3 and C4, and constitute a connection control circuit 90 that controls the connection thereof.

  The sense amplifier SA1a newly includes a pair of capacitors C3 # and C4 #, switch circuits SW5 and S6 provided corresponding to the capacitor C3 #, and a switch circuit SW7 provided corresponding to the capacitor C4 #. , SW8. Switch circuits SW5 to SW8 are provided corresponding to capacitors C3 # and C4 #, and constitute a connection control circuit 91 for controlling the connection.

  Since precharge circuit 70 is similar, detailed description thereof will not be repeated.

  Each switch circuit SW1-SW8 includes a P-channel MOS transistor and an N-channel MOS transistor whose source and drain are connected in parallel in common.

  Regarding sense amplifier SA0a, capacitor C3 has one electrode connected to node N1, and the other electrode connected to node N1a of sense amplifier SA0a or node N1b of sense amplifier SA1a via switch circuits SW1 and SW2. Capacitor C4 has one electrode connected to node N2, and the other electrode connected to node N2a of sense amplifier SA0a or node N2b of sense amplifier SA1a via switch circuits SW3 and SW4.

  Regarding sense amplifier SA1a, capacitor C3 # has one electrode connected to node N1 # and the other electrode connected to node N1a of sense amplifier SA0a or node N1b of sense amplifier SA1a via switch circuits SW5 and SW6. Capacitor C4 # has one electrode connected to node N2 # and the other electrode connected to node N2a of sense amplifier SA0a or node N2b of sense amplifier SA1a via switch circuits SW7 and SW8.

  Switch circuits SW1 and SW2 operate complementarily with each other in response to control signals RAE and RAO. Switch circuits SW3 and SW4 operate complementarily with each other in response to control signals RAE and RAO.

  Similarly, the switch circuits SW5 and SW6 operate complementarily with each other in response to the control signals RAE and RAO. Switch circuits SW7 and SW8 operate complementarily with each other in response to control signals RAE and RAO.

  Specifically, when the selected memory cell row is an even row, the row decoder 20 sets the control signals RAE and RAO to “H” level and “L” level. When the selected memory cell row is an odd row, the row decoder 20 sets the control signals RAE and RAO to “L” level and “H” level.

  When the control signals RAE and RAO are set to “H” level and “L” level, the switch circuits SW2, SW4, SW6 and SW8 are turned on. On the other hand, the switch circuits SW1, SW3, SW5, SW7 are set in a non-conductive state.

  On the other hand, when the control signals RAE and RAO are set to the “L” level and the “H” level, the switch circuits SW1, SW3, SW5, and SW7 are turned on. On the other hand, the switch circuits SW2, SW4, SW6, SW8 are set in a non-conductive state.

  Here, as an example, a data read operation of even-numbered memory cells MC0e and MC1e will be described.

  Data read operation is started in the same manner as described above, and column select line CSLk and word line WLe provided corresponding to the selected memory cell are activated ("H" level). In addition, word line WLDo provided corresponding to the dummy memory cell is activated (“H” level).

  In response to activation of selected column selection line CSLk, gate transistors CSGa and CSGb are turned on, and bit lines BLj, / BLj and local input / output lines LIO0, / LIO0 of the selected column are electrically coupled. . In response to the activation of the selected column selection line CSLk, the gate transistors CSGa # and CSGb # are turned on, and the bit lines BLj + 1 and / BLj + 1 and the local input / output lines LIO1 and / LIO1 in the selected column are electrically connected. Combined with

  In response to the activation of the word line WLe, a current path is formed between the sense amplifier SA0a and the selected memory cell MC0e and the dummy memory cell DMC0o as described above.

  Similarly, in response to activation of the word line WLe, a current path is formed between the sense amplifier SA1a and the selected memory cell MC1e and the dummy memory cell DMC1o.

  Further, the control signals RAE and RAO are set to “H” level and “L” level. Therefore, the switch circuits SW2, SW4, SW6, SW8 are conducted.

  Along with this, the other electrode of the capacitor C3 is connected to the node N1a of the sense amplifier SA0a via the switch circuit SW2. The other electrode of the capacitor C4 is connected to the node N2b of the sense amplifier SA1a through the switch circuit SW4. The other electrode of capacitor C3 # is connected to node N1b of sense amplifier SA1a via switch circuit SW6. The other electrode of capacitor C4 # is connected to node N2a of sense amplifier SA0a through switch circuit SW8.

  Here, the capacitor C2 is provided between the node N2a and the node N2, and a dummy memory cell DMC0o having a resistance value Rmin is connected to the node N2.

  The capacitor C4 is connected between the node N2 and the node N2b when the switch circuit SW4 is turned on.

  Capacitor C2 # is provided between node N2b and node N2 #, and node N2 # is connected to dummy memory cell DMC1o having resistance value Rmax.

  Capacitor C4 # is connected between node N2 # and node N2a when switch circuit SW8 is turned on.

  Then, node N2a of amplification unit 55 is connected to node N2 via capacitor C2, and node N2a is further connected to node N2 # via capacitor C4 #. As described above, node N2 is connected to dummy memory cell DMC0o having resistance value Rmin, and node N2 # is connected to dummy memory cell DMC1o having resistance value Rmax.

  Node N2b of amplification unit 55 # is connected to node N2 # via capacitor C2 #, and node N2b is further connected to node N2 via capacitor C4.

  As described above, node N2 is connected to dummy memory cell DMC0o having resistance value Rmin, and node N2 # is connected to dummy memory cell DMC1o having resistance value Rmax.

  Currents Imax and Imin according to dummy memory cells DMC0o and DMC1o having resistance values Rmin and Rmax flow through nodes N2 and N2 #, respectively.

  The potentials of the nodes N2 and N2 # are lowered from the power supply voltage Vcc by a voltage drop based on the product of the currents Imax and Imin and the load resistances of the transistors QP5 and QP5 #.

Here, the node N2 is connected to the two capacitors C2 and C4.
Therefore, the potential of the node N2a of the amplification unit 55 connected via the capacitor C2 changes from the precharge voltage VPC by 1/2 of the potential change of the node N2 due to the capacitive coupling of the capacitor C2.

  Similarly, the potential at node N2b of amplification unit 55 # connected via capacitor C4 changes by a half of the potential change at node N2 due to capacitive coupling of capacitor C4 from precharge voltage VPC.

  That is, the potentials of the nodes N2a and N2b change by 1/2 of the voltage drop based on the product of the current Imax and the load resistance of the transistor QP5 when the current Imax flows through the node N2.

Node N2 # is connected to two capacitors C2 # and C4 #.
Therefore, the potential of node N2b of amplification unit 55 # connected via capacitor C2 # changes by a half of the potential change of node N2 # due to capacitive coupling of capacitor C2 # from precharge voltage VPC.

  Similarly, the potential of the node N2a of the amplification unit 55 connected via the capacitor C4 # changes by a half of the potential change of the node N2 # due to the capacitive coupling of the capacitor C4 # from the precharge voltage VPC.

  That is, the potentials of nodes N2a and N2b change by ½ of the voltage drop based on the product of current Imin and the load resistance of transistor QP5 # as current Imin flows through node N2 #.

  Therefore, in summary, the potentials of nodes N2a and N2b are voltages based on the product of current Imax and the load resistance of transistor QP5 due to currents Imax and Imin flowing due to capacitive coupling of capacitors C2, C2 #, C4 and C4 #. It changes by the sum of 1/2 of the drop and 1/2 of the voltage drop based on the product of the current Imin and the load resistance of the transistor QP5 #.

  That is, the potential change corresponding to the intermediate voltage drop caused by the transistors QP5 and QP5 # respectively occurs at the nodes N2 and N2 #.

  In other words, as described in the first embodiment, a dummy memory cell having an intermediate resistance value (Rmax + Rmin) / 2 for supplying the reference current Iref, which is an intermediate current between the currents Imax and Imin, to each of the transistors QP5 and QP5 #. Equivalent to connecting.

  Then, the amplification unit 55 uses, as a reference, an intermediate potential due to a potential change corresponding to an intermediate voltage drop generated at each of the nodes N2 and N2 # at the input nodes N2a and N2b.

  The sense amplifier SA0 amplifies the potential difference between the intermediate potential of the node N2a and the potential generated at the node N1a based on the resistance value of the selected memory cell MC0e in the amplification unit 55, and outputs it as read data SOUT0.

  Sense amplifier SA1 amplifies the potential difference between the intermediate potential of node N2b and the potential generated at node N1b based on the resistance value of selected memory cell MC1e in amplification unit 55 #, and outputs the result as read data SOUT1.

  In the above, as an example, the word line WLe corresponding to the even-numbered memory cell row selected as an example is activated, the word line WLDo corresponding to the memory cell row of the dummy memory cell is activated, and the memory cells MC0e and MC1e are activated. Although the case where data reading is executed has been described, the same can be applied to memory cells MC0o and MC1o which are odd-numbered memory cell rows. Specifically, the corresponding word line WLo is activated and the word line WLDe is activated. In the sense amplifiers SA0 and SA1, the control signals RAE and RAO are set to the “L” level and the “H” level.

Therefore, the switch circuits SW1, SW3, SW5, SW7 are conducted.
Accordingly, the other electrode of capacitor C3 is connected to node N1b of sense amplifier SA1a via switch circuit SW1. The other electrode of the capacitor C4 is connected to the node N2a of the sense amplifier SA0a through the switch circuit SW3. The other electrode of capacitor C3 # is connected to node N1a of sense amplifier SA0a through switch circuit SW5. The other electrode of capacitor C4 # is connected to node N2b of sense amplifier SA1a through switch circuit SW7.

  Here, the capacitor C1 is provided between the node N1 and the node N1a, and a dummy memory cell DMC0e having a resistance value Rmin is connected to the node N1.

  The capacitor C3 is connected between the node N1 and the node N1b when the switch circuit SW1 is turned on.

  Capacitor C1 # is provided between node N1 # and node N1b, and dummy memory cell DMC1e having resistance value Rmax is connected to node N1 #.

  Capacitor C3 # is connected between node N1 # and node N1a when switch circuit SW5 is turned on.

  Then, node N1a of amplification unit 55 is connected to node N1 via capacitor C1, and node N1a is further connected to node N1 # via capacitor C3 #. As described above, node N1 is connected to dummy memory cell DMC0e having resistance value Rmin, and node N1 # is connected to dummy memory cell DMC1e having resistance value Rmax.

  Node N1b of amplification unit 55 # is connected to node N1 # via capacitor C1 #, and node N1b is further connected to node N1a via capacitor C3 #.

  As described above, node N1 is connected to dummy memory cell DMC0e having resistance value Rmin, and node N1 # is connected to dummy memory cell DMC1e having resistance value Rmax.

  Currents Imax and Imin according to dummy memory cells DMC0e and DMC1e having resistance values Rmin and Rmax flow through nodes N1 and N1 #, respectively.

  Therefore, as described above, the potentials of the nodes N1a and N1b are set such that the currents Imax and Imin flow due to the capacitive coupling of the capacitors C1, C1 #, C3, and C3 #, and the current Imax and the load resistance of the transistor QP1. Therefore, it changes by the sum of 1/2 of the voltage drop based on the product of ½ and ½ of the voltage drop based on the product of the current Imin and the load resistance of the transistor QP1 #.

  That is, the potential change corresponding to the voltage drop in the middle of the voltage drops generated at the nodes N1 and N1 # is caused by the transistors QP1 and QP1 #.

  In other words, as described in the first embodiment, a dummy memory cell having an intermediate resistance value (Rmax + Rmin) / 2 for supplying the reference current Iref, which is an intermediate current between the currents Imax and Imin, to each of the transistors QP1 and QP1 #. Equivalent to connecting.

  Then, the amplification unit 55 uses the intermediate potential due to the potential change corresponding to the intermediate voltage drop generated at the nodes N1 and N1 # at the input nodes N1a and N1b as a reference.

  The sense amplifier SA0 amplifies the potential difference between the intermediate potential of the node N1a and the potential generated at the node N2a based on the resistance value of the selected memory cell MC0o in the amplification unit 55, and outputs it as read data SOUT0.

  Sense amplifier SA1 amplifies the potential difference between the intermediate potential of node N1b and the potential generated at node N2b based on the resistance value of selected memory cell MC1o in amplification unit 55 #, and outputs the result as read data SOUT1.

Since subsequent operations are similar, detailed description thereof will not be repeated.
In the configuration according to the second embodiment of the present invention, transistors 80 and 81 are deleted as described above, and a pair of capacitors C3 and C4 are newly provided for sense amplifier SA0a and provided corresponding to capacitor C3. The switch circuits SW1 and SW2 and the switch circuits SW3 and SW4 provided corresponding to the capacitor C4 are provided. For sense amplifier SA1a, a pair of capacitors C3 # and C4 # are newly provided and switch circuits SW5 and S6 are provided corresponding to capacitor C3 #, and switch circuit SW7 is provided corresponding to capacitor C4 #. , SW8.

  Then, by controlling the switches SW1 to SW8, a configuration equivalent to the case where a dummy memory cell having an intermediate resistance value (Rmax + Rmin) / 2 for supplying a reference current Iref, which is an intermediate current between the currents Imax and Imin, is connected as described above. Is realized.

  In this respect, the switch circuits SW1 to SW8 are provided. As described in the first embodiment, the transient current accompanying the movement of the charge flows, but the steady current does not flow, and the reference side No potential difference occurs. Therefore, it is possible to execute data reading with a wide signal amplitude range and high accuracy.

  Further, the voltage drop corresponding to the on-resistance of the transistor due to the provision of the switcher 60 does not occur, and the range of the signal amplitude of the nodes N1, N1 #, N2, and N2 # is not narrowed. Furthermore, since the potential fluctuations of the nodes N1, N1 #, N2, and N2 # are directly transmitted to the input nodes of the amplification units 50 and 50 # by capacitive coupling, the voltage signal difference is sufficiently secured and high-speed operation is performed. Is also possible.

  Further, the nodes N1a and N2a of the amplification unit 55 have a configuration in which a switch circuit SW and two capacitors are both connected. In addition, nodes N1b and N2b of amplification unit 55 # are both configured by connecting switch circuit SW and two capacitors.

  Accordingly, since the circuit components connected to the nodes of the amplification units 55 and 55 # are the same, it is possible to suppress the occurrence of an offset voltage caused by the circuit difference between the inputs of the amplification units 55 and 55 #.

  In the configuration of FIG. 11 described above, only the configuration of the sense amplifiers SA0a and SA1a provided corresponding to the local input / output line pairs LIOP0 and LIOP1, respectively, has been described. For example, a plurality of local input / output line pairs are provided. The present invention is also applicable to the case where a sense amplifier SA is provided corresponding to each local input / output line pair.

  For example, although not shown, consider a case where local input / output line pairs LIOP2 and LIOP3 adjacent to local input / output line pair LIOP1 are provided and sense amplifiers SA2a and SA3a corresponding to local input / output line pairs LIOP2 and LIOP3 are provided.

  In this case, the same switching circuit connection relationship as the sense amplifier SA0a and the sense amplifier SA1a is established between the adjacent sense amplifiers SA1a and SA2a or between the sense amplifiers SA2a and SA3a. It is feasible.

  Specifically, according to the same system as the connection relationship of the switches shown in the switch circuits SW3 to SW6 provided between the sense amplifier SA0a and the sense amplifier SA1a, or between the sense amplifier SA1a and the sense amplifier SA2a. This can be realized by providing a switch circuit between the first and second sense amplifiers SA3a.

  Even in this configuration, it is possible to realize the same data reading method as described above according to a pair of two adjacent sense amplifiers.

(Modification of Embodiment 2)
FIG. 12 is a circuit configuration diagram of sense amplifiers SA0b and SA1b according to the modification of the second embodiment of the present invention.

  Referring to FIG. 12, sense amplifier SA0b according to the second embodiment of the present invention further includes a dummy connection control circuit 92 provided corresponding to capacitors C1 and C2 and controlling the connection thereof. Sense amplifier SA1b further includes a dummy connection control circuit 93 that is provided corresponding to capacitors C1 # and C2 # and controls the connection thereof.

  The dummy connection control circuit 92 includes dummy switch circuits DSW1 to DSW4. The dummy connection control circuit 93 includes dummy switch circuits DSW5 to DWS8. Each dummy switch circuit DSW1-DSW8 includes a P-channel MOS transistor and an N-channel MOS transistor whose sources and drains are commonly connected in parallel.

  The gates of the transistors constituting the dummy switch circuits DSW1 to DSW8 are connected to one of the signal lines L1 and L2.

  Regarding sense amplifier SA0b, capacitor C1 has one electrode connected to node N1, and the other electrode connected to precharge voltage VPC or node N1a of sense amplifier SA0b via dummy switch circuits DSW1 and DSW2. Capacitor C2 has one electrode connected to node N2, and the other electrode connected to node N2a of sense amplifier SA0b or precharge voltage VPC via dummy switch circuits DSW3 and DSW4.

  With respect to sense amplifier SA1b, capacitor C1 # has one electrode connected to node N1 # and the other electrode connected to precharge voltage VPC or node N1b of sense amplifier SA1b via dummy switch circuits DSW5 and DSW6. Capacitor C2 # has one electrode connected to node N2 # and the other electrode connected to node N2b of sense amplifier SA1b or precharge voltage VPC via dummy switch circuits DSW7 and DSW8.

  The gates of the N-channel MOS transistors of the dummy switch circuits DSW1, DSW4, DSW5, DSW8 are connected to a signal line L2 connected to the ground voltage GND. Therefore, these transistors are nonconductive.

  The gates of the P channel MOS transistors of the dummy switch circuits DSW2, DSW3, DSW6, DSW7 are connected to a signal line L2 connected to the ground voltage GND. Therefore, these transistors are conductive.

  The gates of the P-channel MOS transistors of the dummy switch circuits DSW1, DSW4, DSW5, DSW8 are connected to the open signal line L1. Therefore, these transistors are nonconductive.

  The gates of the N-channel MOS transistors of the dummy switch circuits DSW2, DSW3, DSW6, DSW7 are connected to the open signal line L1. Therefore, these transistors are nonconductive.

  That is, only the P-channel MOS transistors of the dummy switch circuits DSW2, DSW3, DSW6, DSW7 connected to the signal line L2 are conductive, and the other transistors are nonconductive.

  Therefore, capacitor C1 is connected to node N1a via the P-channel MOS transistor of dummy switch circuit DSW2. Capacitor C2 is connected to node N2a via a P-channel MOS transistor of dummy switch circuit DSW3.

  Capacitor C1 # is connected to node N1b through a P-channel MOS transistor of dummy switch circuit DSW6. Capacitor C2 # is connected to node N2b through a P-channel MOS transistor of dummy switch circuit DSW7.

  This configuration is equivalent to the configuration of sense amplifiers SA0a and SA1a according to the second embodiment described with reference to FIG. Therefore, the operation is the same as in the second embodiment.

  In the configuration according to the second embodiment, the symmetry of the circuit topology can be improved by providing dummy switch circuits DSW1 to DSW8 having the same configuration as the switch circuits SW1 to SW8.

  Both the nodes N1a and N2a of the amplification unit 55 have a configuration in which two switch circuits SW and two capacitors are connected. Also, nodes N1b and N2b of amplification unit 55 # are both configured by connecting two switch circuits SW and two capacitors.

  Accordingly, in the circuit component relationship connected to the nodes of the amplification units 55 and 55 #, the same circuit is connected by the same connection method, and the offset voltage is between the inputs of the amplification units 55 and 55 #. Can be further suppressed.

  The application of the present invention is not limited to an MRAM device having an MTJ memory cell, but is commonly applied to a nonvolatile memory device having a memory cell in which a passing current according to the level of written storage data flows. Can be applied.

  In the above description, the case where the resistance value of the memory cell is set to the high resistance value Rmax or the low resistance value Rmin according to the stored data, that is, the case of the binary value has been described. The same applies to the case of multiple values (three or more values) set in the state.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to a first embodiment of the present invention. 1 is a schematic diagram showing a configuration of an MTJ memory cell MC (hereinafter also simply referred to as a memory cell MC) having a magnetic tunnel junction. It is a conceptual diagram explaining the structure and data storage principle of an MTJ memory cell. It is a conceptual diagram which shows the relationship between supply of the data write current to an MTJ memory cell, and the magnetization direction of a tunnel magnetoresistive element. 1 is a conceptual diagram (hereinafter also referred to as a data reading system circuit) of a memory array MA and a peripheral circuit that performs data reading of the memory array MA. FIG. FIG. 3 is a circuit configuration diagram of sense amplifiers SA0 and SA1 according to the first embodiment of the present invention. It is a figure explaining the amplification unit. FIG. 2 is a circuit configuration diagram of a preamplifier PA according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a latch circuit LT according to the first embodiment of the present invention. A data read operation of sense amplifiers SA0 and SA1 according to the first embodiment of the present invention will be described. FIG. 7 is a circuit configuration diagram of sense amplifiers SA0a and SA1a according to the second embodiment of the present invention. FIG. 11 is a circuit configuration diagram of sense amplifiers SA0b and SA1b according to a modification of the second embodiment of the present invention. It is a schematic block diagram explaining a data read operation using a conventional sense amplifier. It is a schematic block diagram explaining another data read-out operation | movement using the conventional sense amplifier. FIG. 10 is a schematic configuration diagram illustrating still another data read operation using a conventional sense amplifier.

Explanation of symbols

  1 MRAM device, 5 control circuit, 20 row decoder, 25 column decoder, 30 input / output control circuit, 50, 55 # amplification unit, SA0, SA1, SA0a, SA1a, SA0b, SA1b sense amplifier.

Claims (3)

In each of the above, a plurality of memory cells through which a passing current corresponding to stored data flows during data reading;
A first and second data line pair;
The first and second data lines are provided corresponding to the first and second data line pairs, respectively, for executing parallel data reading based on a passing current flowing through the first and second data line pairs during data reading. Two differential amplification units,
At the time of data reading, each of one side of the first and second data line pairs is electrically connected to a first voltage via a selected memory cell selected from the plurality of memory cells. In addition, each of the other side of the first and second data line pairs is electrically coupled to two dummy memory cells used for comparison with the selected memory cell of the plurality of memory cells, respectively. ,
Each of the first and second differential amplification units includes:
A pair of first transistors in which each one conduction terminal is electrically coupled to a corresponding one of the first and second data line pairs, and whose gates are both connected to a reference voltage When,
A pair of second transistors each having a gate connected between the other conduction terminal of each of the pair of first transistors and a second voltage, and having a gate connected to the other conduction terminal of each of the pair of first transistors. A transistor,
A pair of capacitors having one electrode connected to the other conduction terminal of each of the pair of first transistors and the other electrode connected to the first and second input nodes;
An amplifying circuit for amplifying a potential difference between the first and second input nodes connected to the other electrode of the pair of capacitors;
Controls one electrical connection between the first input node and the second input node connected to a capacitor connected to each of the other side of the first and second data line pairs. Further comprising a connection control unit,
One dummy memory cell of two dummy memory cells electrically coupled to each of the other side of the first and second data line pairs indicates one data level of the storage data of the memory cell. A non-volatile memory device, which is set to a high resistance state, and the other dummy memory cell is set to a low resistance state indicating the other data level of data stored in the memory cell. In each of the above, a plurality of memory cells through which a passing current corresponding to stored data flows during data reading;
Parallel data based on passing currents that are provided corresponding to the first and second data line pairs and the first and second data line pairs, respectively, and flow through the first and second data line pairs during data reading. First and second differential amplifying units for performing reading,
At the time of data reading, each of one side of the first and second data line pairs is electrically connected to a first voltage via a selected memory cell selected from the plurality of memory cells. In addition, each of the other side of the first and second data line pairs is electrically coupled to two dummy memory cells used for comparison with the selected memory cell of the plurality of memory cells, respectively. ,
Each of the first and second differential amplification units includes:
A pair of first transistors in which each one conduction terminal is electrically coupled to a corresponding one of the first and second data line pairs, and whose gates are both connected to a reference voltage When,
A pair of second transistors each having a gate connected between the other conduction terminal of each of the pair of first transistors and a second voltage, and having a gate connected to the other conduction terminal of each of the pair of first transistors. A transistor,
A pair of first capacitors having one electrode connected to the other conduction terminal of each of the pair of first transistors and the other electrode connected to the first and second input nodes;
An amplifier circuit for amplifying a potential difference between the first and second input nodes connected to the other electrode of the pair of first capacitors;
A pair of second capacitors connected with one electrode to the other conduction terminal of each of the pair of first transistors;
The first differential amplifier unit controls a connection between the other electrode of the pair of second capacitors and the first and second input nodes of the first and second differential amplifier units. 1 further includes a connection control circuit,
The second differential amplifier section controls a connection between the other electrode of the pair of second capacitors and the first and second input nodes of the first and second differential amplifier sections. Two connection control circuits,
In the first connection control circuit, the first electrode of one of the first and second differential amplifiers and the second input of the other are connected to the other electrode of the pair of second capacitors. The second connection control circuit connects the other electrode of the corresponding pair of second capacitors to the other first input node and the second one of the first and second, respectively. Connect to each input node,
One dummy memory cell of two dummy memory cells electrically coupled to each of the other side of the first and second data line pairs indicates one data level of the storage data of the memory cell. A non-volatile memory device, which is set to a high resistance state, and the other dummy memory cell is set to a low resistance state indicating the other data level of data stored in the memory cell. The first connection control circuit includes:
First and second switch elements for controlling connection between one of the other electrodes of the pair of second capacitors and the first input node of the first and second differential amplifying units;
A third and a fourth switch element for controlling connection between the other electrode of the second capacitor and the second input node of the first and second differential amplifying units;
The second connection control circuit includes:
Fifth and sixth switch elements for controlling connection between one of the other electrodes of the pair of second capacitors and the first input nodes of the first and second differential amplifier units;
Seventh and eighth switch elements for controlling connection between the other electrode of the second capacitor and the second input node of the first and second differential amplifying units;
The first to eighth switch elements include an N-channel MOS transistor and a P-channel MOS transistor whose source and drain are common to each other,
The first differential amplifier includes a first dummy connection control circuit that controls connection between the other electrode of the corresponding pair of first capacitors and the first and second input nodes,
The second differential amplifying unit includes a second dummy connection control circuit that controls connection between the other electrode of the pair of first capacitors and the first and second input nodes,
The first dummy connection control circuit includes:
First and second dummy switch elements that control connection between one of the other electrodes of the corresponding first capacitor and the first input node;
And third and fourth dummy switch elements that control connection between the other electrode of the pair of first capacitors and the second input node,
The second dummy connection control circuit includes:
Fifth and sixth dummy switch elements that control connection between one of the other electrodes of the corresponding first capacitor and the first input node;
And seventh and eighth dummy switch elements for controlling connection between the other electrode of the pair of first capacitors and the second input node,
The said 1st-8th dummy switch element has an N channel MOS transistor and a P channel MOS transistor whose source and drain are mutually common like the said 1st-8th switch element. Non-volatile storage device.

Images