JP2008300979A - Lvds receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize deterioration in signal quality caused by impedance in a transmission path without using an external resistor. <P>SOLUTION: A differential receiver unit 140 is provided, which has two differential input terminals and outputs a logic signal corresponding to an analog differential voltage signal given between the two differential input terminals. A switch unit 150 is provided, which is formed of a transistor between the two differential input terminals and includes a plurality of switches controllable to be on/off from the outside of the LVDS receiver. The two differential input terminals of the differential receiver unit 140 are given with analog differential voltage signals obtained by applying current-voltage conversion to the analog differential current signals by an ON-resistance of each of the switches of the switch unit 150. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an LVDS receiver that receives an analog differential current signal such as LVDS (low voltage differential signal) that realizes high-speed signal transmission between chips, or Sub-LVDS that handles a signal having a smaller signal amplitude than LVDS. is there.

  In the LVDS or Sub-LVDS interface standard, signal transmission between chips is performed with a differential current output. For example, an LVDS receiver for Sub-LVDS receives a high-speed signal (eg, 500 Mbps) as a differential voltage input signal.

  The Sub-LVDS interface standard is described in detail in Non-Patent Document 1 and the like. For example, the Sub-LVDS interface standard specifies a signal amplitude of 150 mV and an output current value of 1.5 mA. The resistance value of the resistor that performs current-voltage conversion on the current output from the transmission block is defined as 100Ω. This resistor is usually an external resistor provided outside the chip in order to suppress variations in resistance value.

  In order to inspect an LVDS transmission system including an LVDS receiver or the like, impedances of a transmission block, an LVDS receiver, and a transmission path are provided on a probe inspection board.

  FIG. 24 is a block diagram illustrating an example of the configuration of the probe inspection board of the LVDS transmission system. As shown in FIG. 24, a transmission block 701, a transmission path 702, a receiver block 704, and an external resistor 705 are provided on the probe inspection board.

  The transmission block 701 (abbreviated as Tx in FIG. 24) outputs a differential current signal via the transmission path 702. The transmission path 702 is a transmission path on the probe inspection board. An impedance 703 in FIG. 24 indicates the impedance of the transmission line, and includes self, mutual inductance, capacitance, and resistance. The receiver block 704 (abbreviated as Rx in FIG. 24) receives the differential signal output from the transmission block 701 via the transmission path 702. The external resistor 705 is a resistor (for example, 100Ω) that performs current-voltage conversion on the output of the transmission block 701.

Since chips using this interface standard transmit and receive high-speed signals, bare chip mounting without using a package has become mainstream.
"Alliance standard for D-PHY", published by MIPI (Mobile Industry Processor Interface), Draft Ver0.79 June 30, 2006

  However, it is physically impossible for the probe inspection board to place an external resistor near the receiver when performing a communication test. For this reason, the impedance of the transmission line on the probe inspection board deteriorates the differential signal quality, making it difficult to perform a communication test at an actual use speed (eg, 500 Mbps).

  For this, it may be possible to create a resistor of about 100Ω with polysilicon (PS) resistance inside the chip of the receiver block, but the variation in resistance value is usually 15% or more. There was a problem in use at the time.

  The present invention has been made paying attention to the above problem, and an object of the present invention is to minimize signal quality degradation due to impedance of a transmission line without using an external resistor in an LVDS receiver.

In order to solve the above problems, one embodiment of the present invention provides:
An LVDS receiver for receiving an analog differential current signal,
A differential receiver having two differential input terminals and outputting a logic signal according to an analog differential voltage signal applied between the two differential input terminals;
A switch unit including a plurality of switches formed by transistors between the two differential input terminals and capable of being turned on / off from the outside of the LVDS receiver;
With
In the differential receiver unit, the analog differential current signal is subjected to current-voltage conversion by ON resistances of the plurality of switches, and is supplied to the two differential input terminals as the analog differential voltage signal. And

  According to the present invention, it is possible to minimize degradation of signal quality due to the impedance of the transmission line without using an external resistor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment, components having the same functions as those described once are given the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
FIG. 1 is a diagram showing a communication test block 100 according to Embodiment 1 of the present invention. The communication test block 100 is realized on a probe inspection board that performs a sub-LVDS communication test. As shown in the figure, the communication test block 100 includes a transmission block 110 (abbreviated as Tx in the figure), a transmission path 120, and an LVDS receiver 130 (abbreviated as Rx in the figure).

  The transmission block 110 outputs an analog differential current signal via the transmission line 120.

  The transmission path 120 is a transmission path on the probe inspection board. The impedance 121 in FIG. 1 indicates the impedance of the transmission line 120, and includes self, mutual inductance, capacitance, and resistance.

  The LVDS receiver 130 receives the analog differential current signal output from the transmission block 110 via the transmission line 120 as an analog differential voltage signal. Specifically, the LVDS receiver 130 includes a differential receiver unit 140 and a switch unit 150.

  The differential receiver section 140 has a + side differential input terminal 141 (DP +) and a − side differential input terminal 142 (DM−), and corresponds to an analog differential voltage signal input from these terminals. Thus, the logic signal (output signal S01) of “H” or “L” is output to the subsequent logic.

  The switch unit 150 includes a plurality of switches that short-circuit the differential input terminals of the differential receiver unit 140. The analog differential voltage signal output from the transmission block 110 is converted into an analog differential voltage signal input to the differential receiver unit 140 using the on-resistances of these switches.

  FIG. 2 is a circuit diagram that embodies the switch unit 150. The switch unit 150 of this example includes a plurality of complementary switches in which a PMOS transistor and an NMOS transistor are combined one by one, and the complementary switches are connected in parallel. The gates of the MOS transistors constituting each switch can be controlled from the outside of the LVDS receiver 130, that is, can be turned on / off.

  FIG. 2 shows three complementary switches composed of PMOS transistors 151 to 153 and NMOS transistors 154 to 156. For example, during testing, several transistors are selected and turned on to form a resistor between the differential input terminals. Note that the number of switches in the switch unit 150 may be determined according to the ON resistance of each switch and the required combined resistance value (the same applies to the following embodiments).

  In the present embodiment, the ratio of the size (W / L ratio) of the PMOS transistor and the NMOS transistor is set to 2 times, 4 times, 8 times, and a power of 2, respectively. Thereby, the resistance value of each switch is weighted, and the ON resistance value with respect to the decimal notation of the control signal given to the gate of each transistor can be a monotonously decreasing function. FIG. 3 is an example of the relationship between the decimal notation of the control signal and the composite value of the parallel resistance. In FIG. 3, the horizontal axis is a numerical value representing a 6-bit [5: 0] control signal in decimal notation, and the vertical axis indicates a combined resistance value of the ON resistance of the switch between the differential input terminals. Also, the three lines in the graph of FIG. 3 indicate the case where the characteristics of the NMOS transistor and the PMOS transistor are both Typ, both Fast-Fast, and both Slow-Slow.

  The resistance value used in Sub-LVDS is about 80-120Ω. For example, if a polysilicon (PS) resistor used in a normal CMOS process is connected in series to the PMOS transistor 151 or the NMOS transistor 154, the size of the NMOS transistor or PMOS transistor becomes too large, so that the differential input terminals are not connected. The received signal deteriorates significantly due to the parasitic capacitance. On the other hand, in this embodiment, only the on-resistance of the transistor is used as the voltage-current conversion resistor, so that the optimum resistance value for the test can be set from the outside even if the process varies. . Therefore, according to the present embodiment, it is possible to minimize the degradation of signal quality due to the impedance of the transmission line without using an external resistor.

  Further, by selecting a switch to be turned on from a plurality of switches, the resistance value by the switch unit 150 can be controlled from the outside of the LVDS receiver. As a result, the amplitude of the analog differential voltage signal input to the differential receiver section can be freely changed, so that the usefulness in the test is high. That is, the defective chip can be easily selected by the above configuration.

  In the example of FIG. 2, both the PMOS transistor and the NMOS transistor are used to suppress the fluctuation of the on-resistance value when the input common voltage fluctuates. However, when the input common voltage is high, As shown in FIG. 4, the switch unit may be formed of only PMOS transistors. On the other hand, when the input common voltage is low, as shown in FIG.

<< Embodiment 2 of the Invention >>
In the second embodiment, an example of a switch unit that can suppress the deterioration of the signal waveform as compared with the first embodiment will be described. FIG. 6 is a diagram illustrating a configuration of the switch unit 150 according to the second embodiment.

  As shown in FIG. 6, in the switch unit 150 of this embodiment, the base of each transistor is connected to the source of each transistor.

  As a result, an increase in Vt (threshold voltage of the MOS transistor) due to the base bias effect can be suppressed. Therefore, the on-resistance of the transistor can be reduced as compared with the switch unit 150 of the first embodiment, and the size of both the PMOS and NMOS transistors can be reduced. As a result, parasitic capacitance between the differential input terminals can be reduced, and signal waveform deterioration can be suppressed as compared with the circuit of the first embodiment.

  In the example of FIG. 6, both PMOS and NMOS transistors are used to suppress fluctuations in the on-resistance value when the input common voltage fluctuates. However, when the input common voltage is high, As shown in FIG. 7, the switch may be formed only by the PMOS transistor. On the other hand, when the input common voltage is low, a switch may be formed only with an NMOS transistor as shown in FIG.

<< Embodiment 3 of the Invention >>
In the third embodiment, an example will be described in which the NMOS and PMOS transistors forming the switch section are formed of low voltage transistors having a withstand voltage of, for example, 1.2 V used for logic. FIG. 9 is a diagram illustrating a configuration of the switch unit 150 according to the third embodiment.

  In FIG. 9, low-voltage PMOS transistors 321 to 323 and low-voltage NMOS transistors 324 to 326 are 1.2V breakdown voltage low-voltage transistors.

  In addition, the clamp circuit 310 is configured to make the voltages of the + side differential input terminal 141 and the − side differential input terminal 142 lower than the withstand voltage of the low voltage transistor constituting the switch unit. 10, FIG. 11, and FIG. 12 are examples of specific circuit diagrams of the clamp circuit 310. FIG. As shown in FIGS. 10, 11, and 12, each clamp circuit has a reference power supply 311. The reference power supply 311 is a power supply that determines a clamp voltage in each clamp circuit.

  For example, the clamp circuit 310 illustrated in FIG. 10 includes a first diode 312 and a second diode 313. With this configuration, the + side differential input terminal 141 and the − side differential input terminal 142 are ( It can be clamped by the voltage of the reference power supply 311 + the forward voltage (Vd) of the diode.

  The clamp circuit 310 illustrated in FIG. 11 includes PMOS transistors 314 to 315. With this configuration, the + side differential input terminal 141 and the − side differential input terminal 142 are set to (voltage of the reference power supply 311 + PMOS). The transistor can be clamped by the gate-source voltage (Vgs) of the transistor.

  Further, the clamp circuit 310 illustrated in FIG. 12 includes comparators 316 to 317 and switches 318 to 319.

  The comparator 316 compares the voltages of the + side differential input terminal 141 and the reference power supply 311. The comparator 317 compares the voltage of the negative differential input terminal 142 and the reference power supply 311.

  The switch 318 is a switch for grounding the + side differential input terminal 141. The switch 318 is turned on when the voltage of the + side differential input terminal 141 is higher than the voltage of the reference power supply 311, and drops the voltage of the + side differential input terminal 141. The switch 319 is a switch for grounding the negative differential input terminal 142. When the voltage of the negative differential input terminal 142 is higher than the voltage of the reference power supply 311, it is turned on to lower the voltage of the negative differential input terminal 142. With the above-described action, the voltages at the + side differential input terminal 141 and the − side differential input terminal 142 can always be kept below the breakdown voltage of the low voltage transistor.

  According to the switch unit 150, when using a low-voltage transistor, the gate length (L) of the transistor can be designed to be about 1/10 as compared with a normal transistor, and the on-resistance is small with a small size transistor. Can be realized. Therefore, in this embodiment, the capacity between the differential input terminals can be reduced by this action, and signal degradation can be suppressed.

  Normally, the driver on the transmission side uses a 3V normal transistor, and the output current is supplied from the 3V power supply of the transmission block. Therefore, as a side effect of this embodiment, it is considered that the voltage at the differential input terminal exceeds the withstand voltage of the low voltage transistor at the time of start-up or the like, causing the breakdown of the low voltage transistor device. However, in this embodiment, since the clamp circuit 310 is inserted, the voltages of the + side differential input terminal 141 and the − side differential input terminal 142 do not exceed the withstand voltage of the low voltage transistor forming the switch. I can do it.

  In the example of FIG. 9, both low-voltage PMOS transistors and low-voltage NMOS transistors are used to suppress fluctuations in the on-resistance value when the input common voltage fluctuates, but the input common voltage is high. In this case, as shown in FIG. 13, the switch unit may be formed by only a low voltage PMOS transistor. On the contrary, when the input common voltage is low, the switch unit may be formed by only the low voltage NMOS transistor as shown in FIG.

<< Embodiment 4 of the Invention >>
In the fourth embodiment, an example in which Vt (threshold voltage of the MOS transistor) of the NMOS and PMOS transistors forming the switch unit is suppressed will be described. FIG. 15 is a diagram illustrating a configuration of the switch unit 150 according to the fourth embodiment.

  As shown in FIG. 15, the switch unit 150 of the present embodiment connects the bases of the NMOS transistor and PMOS transistor forming the switch to the sources of the respective transistors. Thereby, the increase due to the base bias effect of Vt is suppressed.

  As described above, Vt can be kept low in this embodiment, so that the on-resistance of the transistor can be reduced as compared with Embodiment 3 (see FIG. 9). Therefore, the size of both the low voltage PMOS transistor and the low voltage NMOS transistor can be reduced. As a result, parasitic capacitance between the differential input terminals can be reduced, and signal waveform deterioration can be suppressed as compared with the circuit of the third embodiment.

  In the example of FIG. 15, both low-voltage PMOS transistor and low-voltage NMOS transistor are used in order to suppress fluctuations in the on-resistance value when the input common voltage fluctuates. If it is high, the switch may be formed by only a low-voltage PMOS transistor as shown in FIG. On the other hand, when the input common voltage is low, the switch may be formed by only the low voltage NMOS transistor as shown in FIG.

<< Embodiment 5 of the Invention >>
In the fifth embodiment, an example will be described in which device destruction that can occur when the voltage at the differential input terminal exceeds the withstand voltage between the D-S (between the drain and source) of the low-voltage transistor can be described. FIG. 18 is a diagram illustrating a configuration of the switch unit 150 according to the fifth embodiment.

  The switch unit 150 of this embodiment includes low voltage PMOS transistors 321 to 323, low voltage PMOS transistors 511 to 513, low voltage NMOS transistors 324 to 326, and low voltage NMOS transistors 514 to 516. Low voltage PMOS transistor 321 and low voltage PMOS transistor 511, low voltage NMOS transistor 324 and low voltage NMOS transistor 514, low voltage PMOS transistor 322 and low voltage PMOS transistor 512, low voltage NMOS transistor 325 and low voltage NMOS transistor 515,. The low voltage PMOS transistor 323 and the low voltage PMOS transistor 513, and the low voltage NMOS transistor 326 and the low voltage NMOS transistor 516 are connected in series.

  In the present embodiment, the voltage applied between the drain and the source can be reduced to half compared to the example of FIG. Further, the total combined on-resistance value is doubled by the series connection as compared with the example of FIG. 9, but the drain-source capacitance is also halved by the series connection. Therefore, signal degradation is equivalent to the example of FIG.

  As described above, in the switch unit 150 of this embodiment, the low voltage NMOS transistor and the low voltage PMOS transistor forming the switch are connected in series. Therefore, it is possible to prevent device destruction that occurs when the voltage at the differential input terminal exceeds the drain-source breakdown voltage of the low-voltage transistor.

  In the present embodiment, two-stage series connection is shown as an example, but it is obvious that the same effect can be obtained with three or more series connections.

  In the example of FIG. 18, both low-voltage PMOS transistor and low-voltage NMOS transistor are used to suppress fluctuations in on-resistance when the input common voltage fluctuates. If it is high, the switch may be formed by only a low-voltage PMOS transistor as shown in FIG. On the other hand, when the input common voltage is low, the switch may be formed by only the low voltage NMOS transistor as shown in FIG.

Embodiment 6 of the Invention
In the sixth embodiment, an example in which Vt (the threshold voltage of the MOS transistor) of the NMOS and PMOS transistors forming the switch unit is suppressed will be described. FIG. 21 is a diagram illustrating a configuration of the switch unit 150 according to the sixth embodiment.

  As shown in FIG. 21, the switch unit 150 of the present embodiment connects the bases of NMOS transistors and PMOS transistors forming switches to the sources of the respective transistors. Thereby, the increase due to the base bias effect of Vt is suppressed.

  As described above, in this embodiment, Vt can be kept low, so that the on-resistance of the transistor can be reduced as compared with the example of FIG. Therefore, the size of both the low voltage PMOS transistor and the low voltage NMOS transistor can be reduced. As a result, the parasitic capacitance between the differential input terminals can be reduced, and the deterioration of the signal waveform can be suppressed as compared with the circuit of FIG.

  In the example of FIG. 21, both the low-voltage PMOS transistor and the low-voltage NMOS transistor are used in order to suppress the fluctuation of the on-resistance value when the input common voltage fluctuates. If it is high, the switch may be formed by only a low-voltage PMOS transistor as shown in FIG. On the contrary, when the input common voltage is low, the switch may be formed by only the low voltage NMOS transistor as shown in FIG.

  The LVDS receiver according to the present invention has an effect that signal quality deterioration due to the impedance of the transmission path can be minimized without using an external resistor, and realizes high-speed signal transmission between chips. Alternatively, it is useful as an LVDS receiver that receives an analog differential current signal such as a Sub-LVDS that handles a signal having a signal amplitude smaller than that of the LVDS.

1 is a block diagram showing a communication test block 100 according to Embodiment 1. FIG. 3 is a circuit diagram that embodies a switch unit 150. FIG. It is an example of the relationship between the decimal notation of a control signal and the composite value of parallel resistance. In Embodiment 1, it is a structural example of a switch part in case an input common voltage is high. In Embodiment 1, it is an example of a structure of a switch part in case an input common voltage is low. It is a figure which shows the structure of the switch part 150 which concerns on Embodiment 2. FIG. In Embodiment 2, it is a structural example of a switch part in case an input common voltage is high. In Embodiment 2, it is a structural example of a switch part in case an input common voltage is low. It is a figure which shows the structure of the switch part 150 which concerns on Embodiment 3. FIG. 3 is an example of a specific circuit diagram of a clamp circuit 310. FIG. 3 is an example of a specific circuit diagram of a clamp circuit 310. FIG. 3 is an example of a specific circuit diagram of a clamp circuit 310. FIG. In Embodiment 3, it is the structural example of a switch part in case an input common voltage is high. In Embodiment 3, it is a structural example of a switch part in case an input common voltage is low. It is a figure which shows the structure of the switch part 150 which concerns on Embodiment 4. FIG. In Embodiment 4, it is an example of a structure of a switch part in case an input common voltage is high. In Embodiment 4, it is an example of a structure of a switch part in case an input common voltage is low. It is a figure which shows the structure of the switch part 150 which concerns on Embodiment 5. FIG. In Embodiment 5, it is a structural example of a switch part in case an input common voltage is high. In Embodiment 5, it is a structural example of a switch part in case an input common voltage is low. It is a figure which shows the structure of the switch part 150 which concerns on Embodiment 6. FIG. In Embodiment 6, it is an example of a structure of a switch part in case an input common voltage is high. In Embodiment 6, it is a structural example of a switch part in case an input common voltage is low. It is a block diagram which shows an example of a structure of the probe test | inspection board of an LVDS transmission system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Communication test block 110 Transmission block 120 Transmission path 121 Impedance 130 LVDS receiver 140 Differential receiver part 141 + side differential input terminal 142-side differential input terminal 150 Switch part 151-153 PMOS transistor 154-156 NMOS transistor 310 Clamp circuit 311 Reference power supply 312 First diode 313 Second diode 314 to 315 PMOS transistor 316 to 317 Comparator 318 to 319 Switch 321 to 323 Low voltage PMOS transistor 324 to 326 Low voltage NMOS transistor 511 to 513 Low voltage PMOS transistor 514 to 516 Low voltage NMOS transistor S01 Output signal

Claims (10)

An LVDS receiver for receiving an analog differential current signal,
A differential receiver having two differential input terminals and outputting a logic signal according to an analog differential voltage signal applied between the two differential input terminals;
A switch unit including a plurality of switches formed by transistors between the two differential input terminals and capable of being turned on / off from the outside of the LVDS receiver;
With
In the differential receiver unit, the analog differential current signal is subjected to current-voltage conversion by ON resistances of the plurality of switches, and is supplied to the two differential input terminals as the analog differential voltage signal. LVDS receiver. The LVDS receiver of claim 1,
Each switch of the switch unit is any one of a complementary switch of an NMOS transistor and a PMOS transistor, a switch of only an NMOS transistor, and a switch of only a PMOS transistor. The LVDS receiver according to claim 1, wherein a source and a base are connected to each of the transistors constituting each switch of the switch unit. The LVDS receiver of claim 1,
An LVDS receiver, further comprising a clamp circuit for lowering a voltage between the differential input terminals to a withstand voltage of a transistor constituting the switch unit. The LVDS receiver of claim 4, wherein
Each switch of the switch unit is any one of a complementary switch of an NMOS transistor and a PMOS transistor, a switch of only an NMOS transistor, and a switch of only a PMOS transistor. The LVDS receiver of claim 4, wherein
In the LVDS receiver, a transistor and each base of the switch section are connected to a source and a base. The LVDS receiver of claim 4, wherein
The LVDS receiver, wherein the clamp circuit is any one of a combination of a reference power supply and a diode, a combination of a reference power supply and a PMOS transistor, and a combination of a reference power supply, a comparator, and a switch. The LVDS receiver of claim 2, wherein
The LVDS receiver according to claim 1, wherein the transistors constituting each switch of the switch unit are a plurality of low voltage transistors connected in series. The LVDS receiver of claim 8, wherein
In the LVDS receiver, a transistor and each base of the switch section are connected to a source and a base. The LVDS receiver of claim 1,
The LVDS receiver is characterized in that each switch is set so that the ratio of the size of the transistors constituting each switch increases in units of powers of 2 in order from the largest resistance value.

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