JP2008299642A - Pattern drawing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern drawing device, for efficiently drawing a pattern in a small hardware scale. <P>SOLUTION: An SIMD processor 101 performs geometric processing of 3D graphics and edge intersection calculation processing of vector graphics, and outputs processing results thereof to shared SP output buffers 104-107. A pixel shader 112 performs pixel shader processing in the 3D graphic and the vector graphics. A fragment processing part 114 performs fragment processing using a first auxiliary buffer 116 which is used as a depth buffer in the 3D graphics and as a mask buffer in the vector graphics, a second auxiliary buffer 117 used as a stencil buffer in the 3D graphics and as a scissor buffer in the vector graphics, and a shared color buffer 115. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a graphics drawing apparatus that simultaneously realizes vector graphics drawing and 3D graphics drawing in the field of drawing vector graphics defined by mathematical expressions.

  In vector graphics, input data is given by a mathematical expression such as a Bezier curve, and the outline is divided into minute line segments to draw a polygon. Therefore, there is a feature that high-quality graphic drawing can be performed without generating jaggy even if the image is enlarged or reduced like a bitmap image. OpenVG has been used as a programming interface for 2D vector graphics processing. This OpenVG is a graphics API specified by the Khronos Group, which is a standards organization, and is designed to fill paths and strokes defined by curves, matrix conversion processing, clipping and mask processing, and pattern paint processing to paste images Various functions such as anti-aliasing, blending, and dithering are defined. In general, vector graphics are often implemented by dedicated hardware or software in order to perform drawing by converting or dividing a contour curve defined by a mathematical expression into a polygon (see, for example, Patent Document 1).

International Publication No. 03/096275 Pamphlet

  In vector graphics, contour curves defined by mathematical formulas are decomposed into pixels. The decomposed pixels are anti-aliased and then written into the frame buffer based on mask information and the like. On the other hand, in 3D graphics, data defined by polygons is coordinate-transformed and then decomposed into pixels. Pixels are written while performing a forward / backward determination using a depth buffer or the like. As described above, since the processing contents are different between vector graphics and 3D graphics, when hardware is used, the hardware becomes different.

  The hardware scale is generally large when both vector graphics and 3D graphics are implemented by hardware. Therefore, when both vector graphics and 3D graphics are implemented by hardware, the gate scale becomes very large. This is a big problem especially in the field of embedded use, where it is necessary to keep the hardware scale small, and there is a problem that power consumption increases due to an increase in the gate scale.

  The present invention has been made to solve the above-described problems. By sharing the hardware of vector graphics and 3D graphics, it is possible to efficiently execute graphic drawing processing with a small hardware scale. An object is to obtain a graphic drawing apparatus.

  A graphic drawing apparatus according to the present invention includes a processor that performs 3D graphics geometry processing and vector graphics edge intersection calculation processing, and a scan line expansion unit that expands pixels from scan line information that is the result of edge intersection calculation processing A pixel shader that performs pixel shader processing in 3D graphics and vector graphics, a first auxiliary buffer that is used as a depth buffer in 3D graphics, a mask buffer in vector graphics, and a stencil buffer in 3D graphics A second auxiliary buffer used as a scissor buffer in vector graphics, a color buffer commonly used in 3D graphics and vector graphics, and a first auxiliary buffer, Using two auxiliary buffer and color buffer, the data outputted from the pixel shader, in which a fragment processing unit that performs fragmentation process in 3D graphics and vector graphics.

  In the graphic drawing apparatus of the present invention, the processor and its input / output buffer are shared by vector graphics and 3D graphics, and the drawing related buffer is used for different purposes by vector graphics and 3D graphics. The graphic drawing process can be executed efficiently with a small hardware scale.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a figure drawing apparatus according to Embodiment 1 of the present invention.
In the figure, a graphics drawing apparatus includes an SP input buffer 100, a SIMD processor 101, an SP program memory 102, a VG (Vector Graphics) sequence control unit 103, SP output buffers 104 to 107, a VG scan line development unit 108, a 3D setup 109, A 3D rasterizer 110, a texture fetch unit 111, a pixel shader 112, a pixel shader program memory 113, a fragment processing unit 114, a color buffer 115, a first auxiliary buffer 116, and a second auxiliary buffer 117 are provided.

  The SP input buffer 100 is a buffer for holding input data to the SIMD processor 101. The VG contour information 100a is used for processing vector graphics, and the object is used for processing 3D graphics. 3D model data 100b such as model data and light information to be configured is stored in advance. The SIMD processor 101 is a processor that constitutes 4-SIMD, and includes an arithmetic core of PU0, PU1, PU2, and PU3. The SP program memory 102 is a memory for storing a program executed by the SIMD processor 101, such as a program for calculating contour coordinates from VG contour information for vector graphics processing, and a program for performing OpenVG matrix processing. The VG program 102a is stored. The SP program memory 102 stores a 3D program 102b such as a program (equivalent to a vertex shader program) for performing geometric calculation processing and lighting processing for 3D graphics processing. The SIMD processor 101 may be an arithmetic processor such as a vertex shader generally used in 3D graphics.

  The VG sequence control unit 103 is a programmable logic controller for controlling the SIMD processor 101 to perform vector graphics processing. The SP output buffers 104 to 107 are buffers for temporarily storing the results calculated by the respective arithmetic cores in the SIMD processor 101, and VG edge data 104a to 107a and 3D vertex data 104b to 107b for vector graphics, respectively. Is stored. The VG scanline development unit 108 is a functional unit used for vector graphics processing, and is configured to read the edge list of the contour line in the SP output buffers 104 to 107 and develop it from the scanline information to pixels. . The 3D setup 109 is a functional unit that calculates incremental parameters necessary for viewport conversion, clip processing, and rasterization from the 3D vertex data 104b to 107b in the SP output buffers 104 to 107. The 3D rasterizer 110 is a functional unit that calculates pixel values included in a polygon from the incremental parameters output from the 3D setup 109. The texture fetch unit 111 is a functional unit that obtains texel data based on the texture coordinates output from the VG scanline development unit 108 and the 3D rasterizer 110 and outputs the texel data to the pixel shader 112.

  The pixel shader 112 is a 4-SIMD processor for performing pixel calculation processing, and is executed by a program stored in the pixel shader program memory 113. The pixel shader program memory 113 stores different pixel shader programs (a VG program 113a and a 3D program 113b) for vector graphics processing and 3D graphics processing.

  The fragment processing unit 114 has a function of performing pixel blending processing and alpha blending processing as well as scissor clip processing when performing vector graphics processing. Further, when performing the 3D graphics process, the fragment processing unit 114 performs a depth test and a stencil test, and performs a process of writing the pixel value to the color buffer 115. The color buffer 115 is a buffer for storing color information for each pixel. The first auxiliary buffer 116 stores VG mask alpha 116a for vector graphics processing and 3D depth information 116b for 3D graphics processing, and the second auxiliary buffer 117 stores vector graphics processing. The buffer stores VG scissor information 117a and 3D stencil information 117b for 3D graphics processing.

Next, Embodiment 1 by the graphic drawing apparatus of Embodiment 1 will be described.
Prior to the rendering process, it is assumed that the SP input buffer 100 stores VG outline information 100a when processing vector graphics and 3D model data 100b when processing 3D graphics.
The SIMD processor 101 executes the program while reading the program from the SP program memory 102. In the case of vector graphics processing, contour information such as a curve is divided into minute line segments (edges), the coordinates of both ends of the edge are v0 (x0, y0), v1 (x1, y1), and the Y coordinate of the scan line. If y is y, the intersection coordinates xs (y) between the scan line and the edge can be obtained by the following equation. However, intersection coordinates are not calculated when y0 = y1.

In addition, the intersection coordinates with the scan line can be calculated directly from a secondary Bezier curve as follows without decomposing the curve into minute line segments. A Bezier curve is defined in the following parametric format using a parameter t (0 ≦ t ≦ 1).
x (t) = (1-t) ² * x0 + 2 * (1-t) * t * x1 + t ² * x2 (1)
y (t) = (1-t) ² * y0 + 2 * (1-t) * t * y1 + t ² * y2 (2)

ここで、
ａ＝ｙ０−２＊ｙ１＋ｙ２（定数）
ｂ＝２＊（ｙ１−ｙ０） （定数）
ｃ＝ｙ０−ｙ When the equations are solved by arranging (1) and (2) with respect to t,

here,
a = y0-2 * y1 + y2 (constant)
b = 2 * (y1-y0) (constant)
c = y0-y

In this way, if the Y coordinate y of the scan line is uniquely determined, the value of the parameter t is obtained by the equation (3) (when discriminant b ² −4 * a * c ≧ 0), and is expressed by the equation (1). Can be calculated, the intersection point coordinate x between the Bezier curve and the scan line can be calculated. These intersection calculation and other OpenVG matrix processing are usually performed by writing a program, but in order to increase the speed and reduce the program area, the SIMD processor's arithmetic units and registers are directly connected to the VG sequence. By controlling by the control unit 103, the processing may be performed hard-wired without using a program.

  The SIMD processor 101 outputs the calculation result to the SP output buffers 104 to 107 after executing the VG program 102a or the 3D program 102b in the SP program memory 102. In the case of vector graphics processing, a list (four pieces) of intersection coordinates x of contour lines and scan lines is written in parallel. In the case of 3D graphics processing, the following vertex data of a polygon subjected to geometric calculation processing is written. Since each data is composed of four components, each component is written in parallel to the SP output buffers 104-107.

Position (x, y, z, w)
Front Color (r, g, b, a)
Back Color (r, g, b, a)
Fog (-,-,-, f)
Texture (n) (s, t, r, q)

The VG scan line development unit 108 reads the edge list of the contour lines in the SP output buffers 104 to 107 and develops them from the scan line information into pixels. That is, the x and y coordinates of the pixel to be drawn and the coverage information for anti-aliasing are calculated.
The 3D setup 109 calculates incremental parameters necessary for viewport conversion, clip processing, and rasterization from the vertex data in the SP output buffers 104-107. Incremental parameters include edge function parameters required for rasterization and coefficients A, B, and C of plane equations for each attribute.

The 3D rasterizer 110 calculates the pixel value included in the polygon from the incremental parameter output from the 3D setup 109. In general, the x and y coordinates are obtained by using an edge function or the like in order to specify pixels included in a polygon. Next, color and fog values are calculated using the coefficients A, B, and C of the plane equation for each attribute. Division processing is also required to perform perspective collection like texture coordinates.

The texture fetch unit 111 accesses a texture memory (not shown) using the texture coordinates output from the VG scanline development unit 108 and the 3D rasterizer 110 as an address, and reads texel data. The read texel data is output to the pixel shader 112 after being subjected to bilinear, trilinear, or other filtering.
The pixel shader 112 performs pixel calculation processing corresponding to each processing using the VG program 113a or the 3D program 113b in the pixel shader program memory 113, depending on whether the vector graphics processing or the 3D graphics processing is performed. Various arithmetic processes in the pixel shader 112 are performed using pixel information (color, fog, texture coordinates) output from the VG scanline development unit 108 and 3D rasterizer 110 and texel data output from the texture fetch unit 111. Done.

  When performing the vector graphics processing, the fragment processing unit 114 reads the destination color from the color buffer 115 and performs pixel blending processing. Thereafter, the coverage is multiplied by the mask alpha value (VG mask alpha 116a) read from the first auxiliary buffer 116, and alpha blending processing for anti-aliasing is performed. Mask alpha is a function defined in OpenVG. This function can perform an equivalent process by storing the mask alpha value in the texture memory and processing it as a multi-texture. The fragment processing unit 114 also performs scissor clip processing by reading scissor information (VG scissor information 117a) from the second auxiliary buffer 117. In the scissor information, a rectangular area to be drawn with 1-bit data per pixel is set in advance. This scissor clip is also a function defined by OpenVG. If the pixel is to be drawn, the final color value is written into the color buffer 115.

  On the other hand, when the fragment processing unit 114 performs 3D graphics processing, the depth information (3D depth information 116b) is read from the first auxiliary buffer 116 and a depth test is performed, and stencil information (from the second auxiliary buffer 117) The 3D stencil information 117b) is read and a stencil test is performed. If both the tests are passed, the pixel value is written into the color buffer 115 and the depth information and stencil information of the first auxiliary buffer 116 and the second auxiliary buffer 117 are updated at the same time. These functions are functions defined in OpenGL.

  In this way, the SIMD processor and its input / output buffer are shared by vector graphics and 3D graphics, and the drawing-related buffer is used for different purposes in vector graphics and 3D graphics, so that most of the exceptions of the rasterizer are used. It becomes possible to use hardware in common. In addition, the hardware scale can be reduced without installing unnecessary hardware, and the number of computing units that are in an idle state is reduced, so that power consumption can be reduced.

  As described above, according to the graphics drawing apparatus of the first embodiment, a processor that performs 3D graphics geometry processing and vector graphics edge intersection calculation processing, and scan line information that is the result of edge intersection calculation processing are converted into pixels. A scan line developing unit for developing the image, a pixel shader for performing pixel shader processing in 3D graphics and vector graphics, a first auxiliary buffer used as a depth buffer in 3D graphics, and as a mask buffer in vector graphics, A second auxiliary buffer used as a stencil buffer in 3D graphics, a scissor buffer in vector graphics, and a color buffer commonly used in 3D graphics and vector graphics; Since a single auxiliary buffer, a second auxiliary buffer, and a color buffer are used and a fragment processing unit that performs fragment processing in 3D graphics and vector graphics on data output from the pixel shader is provided, less hardware is required. The graphic drawing process can be executed efficiently on a wear scale.

  In addition, according to the graphic drawing apparatus of the first embodiment, either input data for performing geometry processing of 3D graphics input to the processor or input data for performing edge intersection calculation processing of vector graphics is input. An input buffer for holding, and an output buffer for holding output data of a processing result of either 3D graphics or vector graphics output from the processor, and the processor includes vector graphics and 3D graphics to be executed. Since the corresponding program is executed according to the processing, the hardware scale can be further reduced, and the power consumption can be further reduced.

Embodiment 2. FIG.
FIG. 2 is a diagram for specifically explaining the operation of the SIMD processor 101 in FIG. 1 in vector graphics.
In vector graphics, in order to calculate anti-aliasing coverage, one scan line is divided into a plurality of sub-scan lines. In FIG. 2, it is divided into four sub scan lines y0, y1, y2 and y3. Since the SIMD processor 101 has a 4-SIMD configuration, sub-scan lines y0, y1, y2, and y3 are assigned to the arithmetic cores PU0, PU1, PU2, and PU3 to perform processing in parallel. Then, PU 0, PU 1, PU 2, and PU 3 sequentially obtain X coordinate intersections between the sub-scan lines assigned to the PU 0, PU 2, and PU 3 and write them to the SP output buffers 104, 105, 106, and 107. In the example of FIG. 2, PU0 calculates the intersection x00 of edge 0, the intersection x01 of edge 1, the intersection x02 of edge 2, and the intersection x03 of edge 3, and writes it to the SP output buffer 104 together with the UP / DOWN information of each edge. Go. Similarly, PU1, PU2, and PU3 also write each intersection X coordinate and UP / DOWN information to the SP output buffers 105, 106, and 107.

  Next, the VG scan line development unit 108 reads out the information written in the SP output buffers 104, 105, 106, and 107, and covers the pixel coverage (pixel occupancy for performing anti-aliasing processing) in the area surrounded by the outline. Rate) and generate pixels. In order to obtain this coverage, the VG scan line development unit 108 is provided with a mask information generation scan line counter (not shown), which performs processing. The scan line counter is composed of a counter group for one scan line, and counts the number of intersections with edges for each pixel. The counter is a total value incremented / decremented based on the UP / DOWN information of the edge intersecting the scan line. By using this scan line counter, even a complicated figure can be generated at high speed without sorting the X coordinate.

  As described above, the calculation cores of the SIMD processor perform the calculation of the intersection X coordinate of the sub-scan line and the UP / DOWN information in parallel, thereby efficiently generating data necessary for vector graphics pixel generation.

  As described above, according to the graphic drawing apparatus of the second embodiment, vector graphics edge intersection calculation processing is used for antialiasing processing, and the processor calculates edge intersections of a plurality of sub-scan lines in parallel. Therefore, it is possible to efficiently execute data creation necessary for pixel generation in the anti-aliasing process.

Embodiment 3 FIG.
FIG. 3 is a flowchart showing the operation of the SIMD processor in FIG.
The minimum value of the Y coordinate of the object to be drawn (for one pass) is Ymin, and the maximum value of the Y coordinate is Ymax. First, in step ST301, the current scan line Y is set to Ymin, and the values of the sub scan lines y0, y1, y2, and y3 are set (y0 = Y, y1 = Y + 0.25, y2 = Y + 0.5, y3 = Y + 0). .75). Next, in step ST302, contour data (edge) is read from the SP input buffer 100, and in step ST303, the intersection X coordinate of the edge and the sub-scan lines y0, y1, y2, y3 is calculated as PU0, PU1, PU2, PU3. In parallel. In step ST304, the calculated intersection X coordinate is simultaneously written into the SP output buffer 104, PU1 into the SP output buffer 105, PU2 into the SP output buffer 106, and PU3 into the SP output buffer 107 simultaneously.

  Next, in step ST305, it is determined whether all edges (or curves defined by Beziers) divided into line segments from one object have been processed, and if there are still unprocessed edges, Returning to step ST302, the calculation of the intersection X coordinate between the sub-scan lines y0, y1, y2, and y3 and the unprocessed edge is repeated. When the processing of all edges is completed in the determination in step ST305, the VG scan line development unit 108 is activated in step ST306. With this activation, the VG scan line developing unit 108 generates pixels for one scan line. When the pixel generation is completed, the current scan line is advanced by 1 in step ST307, and the sub-pixel scan lines y0, y1, y2, and y3 are also updated. In step ST308, it is compared whether or not the current scan line Y exceeds Ymax. If not, the read pointer of the SP input buffer 100 is reset in step ST310, and the intersection X coordinates of the sub-scan lines y0, y1, y2, and y3 and all edges are calculated in the same manner.

  As described above, in the graphic drawing apparatus according to the third embodiment, the vector graphic is obtained by alternately calculating the intersection X coordinate of the sub-scan line that intersects all edges for each scan line and generating the pixel of the scan line. Can be filled. In order to simplify the description, the calculation of the intersection X coordinate and the pixel generation of the scan line are sequentially performed. However, these two processes can be executed in parallel by pipeline processing. However, in order to perform pipeline processing, the SP output buffer needs to have a double buffer configuration or the like.

Embodiment 4 FIG.
FIG. 4 is a flowchart showing the operation of the SIMD processor in FIG.
The minimum value of the Y coordinate of the object to be drawn (for one pass) is Ymin, and the maximum value of the Y coordinate is Ymax. First, in step ST401, the current scan line Y is set to Ymin, and the values of the sub scan lines y0, y1, y2, and y3 are set (y0 = Y, y1 = Y + 0.25, y2 = Y + 0.5, y3 = Y + 0). .75). Next, in step ST402, contour data (edge) is read from the SP input buffer 100. In step ST403, the intersection X coordinate of the edge and the sub scan lines y0, y1, y2, y3 is calculated as PU0, PU1, PU2, PU3. Use in parallel. In step ST404, the calculated intersection X coordinate is simultaneously written into the SP output buffer 104, PU1 into the SP output buffer 105, PU2 into the SP output buffer 106, and PU3 into the SP output buffer 107 at the same time. At this time, unlike the case of the third embodiment, not only the current scan line but also the intersection X coordinate of the next scan line is sequentially written, so an edge list is created with a pair with the Y coordinate. That is, since the SP output buffer stores the intersection X coordinates of all edges that intersect with one object, a larger area than that in the third embodiment is required.

  Next, in step ST405, it is determined whether all edges (or curves defined by Bezier) divided from one object into line segments have been processed, and if there are still unprocessed edges, Returning to step ST402, the calculation of the intersection X coordinate between the sub-scan lines y0, y1, y2, and y3 and the unprocessed edge is repeated. When all edge processing is completed in the determination in step ST405, the current scan line is advanced by 1 in step ST406, and the sub-pixel scan lines y0, y1, y2, and y3 are updated. In step ST407, it is compared whether or not the current scan line Y exceeds Ymax. If it exceeds, the intersection calculation of all the sub-scan lines intersecting with one object is completed, so in step ST408 the VG scan line is determined. The expansion unit 108 is activated. Unlike the case of the third embodiment, the VG scan line development unit 108 reads out the intersection X coordinates of all the sub scan lines intersecting with one object stored in the SP output buffers 104 to 107 to obtain the pixel Will be generated.

  If the current scan line Y does not exceed Ymax in step ST407, the read pointer of the SP input buffer 100 is reset in step ST410, and the process returns to step ST402 to calculate the intersection X coordinate of the sub scan line and all edges in the same manner. Do it.

  As described above, according to the graphic drawing apparatus of the fourth embodiment, the calculation of the intersection X coordinate of all the sub-scan line edges intersecting with one object and the pixel generation are performed, thereby performing vector graphics filling processing. Can be performed at high speed.

Embodiment 5 FIG.
FIG. 5 is a diagram for more specifically explaining the operation in vector graphics when the SIMD processors 101 in FIG. 1 are in parallel (comprised of the SIMD processor 101a and the SIMD processor 101b).
In vector graphics, processing is performed by dividing one scan line into a plurality of sub-scan lines in order to calculate anti-aliasing coverage. In FIG. 5, the sub-scan lines are divided into eight sub-scan lines y0, y1, y2, y3, y4, y5, y6, and y7.
Since the SIMD processor generally has a 4-SIMD configuration, sub-scan lines y0, y1, y2, and y3 are assigned to the arithmetic cores PU0, PU1, PU2, and PU3 of the SIMD processor 101a to perform processing in parallel. Then, sub scan lines y4, y5, y6, and y7 are allocated to the arithmetic cores PU0, PU1, PU2, and PU3 of the other SIMD processor 101b. Each calculation core sequentially obtains the X coordinate intersections of the sub-scan lines and all contour lines assigned to it, and writes them to the SP output buffers 104 to 107. In the example of FIG. 5, PU0 of the SIMD processor 101a calculates the intersection point x00 of edge 0, the intersection point x01 of edge 1, the intersection point x02 of edge 2, and the intersection point x03 of edge 3, and SP output together with UP / DOWN information of each edge Write to the buffer 104. Similarly, PU1, PU2, PU3, and PU0, PU1, PU2, PU3 of the SIMD processor 101b also write each intersection X coordinate and UP / DOWN information to the SP output buffer.

  Next, the VG scan line development unit 108 generates pixels by obtaining the coverage of the pixels in the region surrounded by the outline based on the information written in the SP output buffers 104 to 107. In order to obtain the coverage, a scan line counter for generating mask information (not shown) is used. The scan line counter is a group of counters for one scan line and counts the number of intersections with edges for each pixel. The counter is a total value incremented / decremented based on the UP / DOWN information of the edge intersecting the scan line. By using this scan line counter, even a complicated figure can be generated at high speed without sorting the X coordinate.

  In this way, by using a plurality of SIMD processors to calculate the intersection X coordinate of the sub-scan line and the UP / DOWN information in parallel, it is possible to efficiently create data necessary for generating the vector graphics pixel.

  In the above-described embodiment, a plurality of SIMD processors are used to allocate a plurality of scan lines. However, by increasing the number of SIMDs in the SIMD processor 101, a plurality of scan lines are simultaneously processed in parallel. May be.

  As described above, according to the graphic drawing apparatus of the fifth embodiment, a plurality of SIMD processors are prepared using SIMD processors as processors, and edge intersection calculation processing of a plurality of sub-scan lines is performed in parallel by the plurality of SIMD processors. As a result, coverage calculation accuracy can be improved and anti-aliasing quality can be improved.

  Further, according to the graphic drawing apparatus of the fifth embodiment, since the processor is an SIMD processor, the number of SIMDs of the SIMD processor is increased to increase the number of sub-scan lines that perform edge intersection calculation processing in parallel. , Improve coverage calculation accuracy and improve anti-aliasing quality.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the figure drawing apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the operation | movement by the vector graphics of the SIMD processor of the figure drawing apparatus by Embodiment 2 of this invention. It is a flowchart which shows the operation | movement by the vector graphics of the figure drawing apparatus by Embodiment 3 of this invention. It is a flowchart which shows the operation | movement by the vector graphics of the figure drawing apparatus by Embodiment 4 of this invention. It is explanatory drawing which shows the operation | movement by the vector graphics of the SIMD processor of the figure drawing apparatus by Embodiment 5 of this invention.

Explanation of symbols

  100 SP input buffer, 100a VG contour information, 100b 3D model data, 101, 101a, 101b SIMD processor, 102 SP program memory, 102a, 113a VG program, 102b, 113b 3D program, 103 VG sequence controller, 104- 107 SP output buffer, 104a to 107a VG edge data, 104b to 107b 3D vertex data, 108 VG scanline development unit, 109 3D setup, 110 3D rasterizer, 111 texture fetch unit, 112 pixel shader, 113 pixel shader program memory, 114 Fragment processing unit, 115 color buffer, 116 first auxiliary buffer, 116a VG mask alpha, 116b 3D data Scan information, 117 a second auxiliary buffer, 117a VG scissor information, 117b 3D stencil information.

Claims (5)

A processor for performing 3D graphics geometry processing and vector graphics edge intersection calculation processing;
A scan line development unit that develops the pixel from the scan line information that is the result of the edge intersection calculation process;
A pixel shader that performs pixel shader processing in 3D graphics and vector graphics;
A first auxiliary buffer used as a depth buffer in 3D graphics and as a mask buffer in vector graphics;
A second auxiliary buffer used as a stencil buffer in 3D graphics and a scissor buffer in vector graphics;
A color buffer commonly used in 3D graphics and vector graphics;
A fragment processing unit that performs fragment processing in 3D graphics and vector graphics on the data output from the pixel shader using the first auxiliary buffer, the second auxiliary buffer, and the color buffer; Figure drawing device. An input buffer for holding either input data for performing geometry processing of 3D graphics input to the processor or input data for performing edge intersection calculation processing of vector graphics, and 3D graphics output from the processor And an output buffer for holding output data of the processing result of either one of the vector graphics and
2. The graphic drawing apparatus according to claim 1, wherein the processor executes a corresponding program in accordance with vector graphics processing and 3D graphics processing to be executed.   3. The graphic drawing apparatus according to claim 1, wherein the edge intersection calculation processing of vector graphics is used for antialiasing processing, and the processor calculates edge intersections of a plurality of sub scan lines in parallel. Prepare multiple SIMD processors as SIMD processors,
4. The graphic drawing apparatus according to claim 3, wherein the plurality of SIMD processors process edge intersection calculation processing for a plurality of sub-scan lines in parallel.   4. The graphic drawing apparatus according to claim 3, wherein the number of sub-scan lines for performing edge intersection calculation processing in parallel is increased by increasing the number of SIMDs of the SIMD processor, using the processor as a SIMD processor.

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