JP2008294127A

JP2008294127A - Semiconductor device and method of manufacturing the same

Info

Publication number: JP2008294127A
Application number: JP2007136541A
Authority: JP
Inventors: Hiroto Uematsu; 浩人植松
Original assignee: NEC Electronics Corp
Current assignee: NEC Electronics Corp
Priority date: 2007-05-23
Filing date: 2007-05-23
Publication date: 2008-12-04

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of measuring electrical characteristics of TEG (Test Element Group) provided to a semiconductor substrate even when the surface of a measuring pad is damaged by etching a UBM (Under Bumping Metal) layer, and also a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device comprises an interlayer insulating film formed on a semiconductor substrate, a dummy electrode 6 formed as an electrode on the interlayer insulating film, a measuring electrode 8 provided as an electrode to measure electrical characteristics of a circuit formed on the semiconductor substrate, and a first wiring line 26 for electrically connecting the dummy electrode 6 and the measuring electrode 8. A first contact 16 is provided under the measuring electrode 8 to pass through the interlayer insulating film, and the first contact 16 is also electrically connected to the measuring electrode 8. The first contact 16 is electrically connected to the semiconductor substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に半導体基板の回路の電気的特性を測定するためのＴＥＧ（ＴｅｓｔＥｌｅｍｅｎｔＧｒｏｕｐ）を有する半導体装置に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a TEG (Test Element Group) for measuring electrical characteristics of a circuit of a semiconductor substrate.

半導体装置において、半導体基板に形成されたトランジスタの電気的特性を測定するためのモニタ用トランジスタが、半導体装置の半導体基板に形成されることがある。このようなモニタ用トランジスタは、ＴＥＧ（ＴｅｓｔＥｌｅｍｅｎｔＧｒｏｕｐ）と呼ばれ、製造した半導体装置が所定の仕様を満たしているか否かを確認するために形成され、半導体装置の良否や性能の評価、半導体装置の製造工程の異常検知に用いられる。 In a semiconductor device, a monitoring transistor for measuring electrical characteristics of a transistor formed over a semiconductor substrate may be formed over the semiconductor substrate of the semiconductor device. Such a monitoring transistor is called a TEG (Test Element Group) and is formed to check whether or not a manufactured semiconductor device satisfies a predetermined specification. Used to detect abnormalities in the manufacturing process of the device.

図１は、従来技術に係る半導体装置の拡散工程後の上面図を示す。拡散工程後とは、パッシベーション膜形成後パッド部を開口した後を意味する。図１に示すように、半導体装置の半導体基板２には、複数の通常パッド４と呼ばれる電極と、半導体基板２の四隅に半導体基板２の回路に接続せずに単独で形成されたダミーパッド６と呼ばれる電極が形成される。また、ＴＥＧの電極となる複数の測定用パッド８が、形成される。この測定用パッド８に、測定用針を当てて、モニタ用トランジスタの電気的特性を測定する。通常パッド４やダミーパッド６、測定用パッド８は、下層がＴｉＮ膜で上層がＴｉの積層膜か、ＴｉＮの単層膜の上にＡｌＣｕ膜を形成したものが用いられる。 FIG. 1 shows a top view after a diffusion process of a semiconductor device according to the prior art. “After the diffusion step” means after the pad film is opened after the passivation film is formed. As shown in FIG. 1, a semiconductor substrate 2 of a semiconductor device has a plurality of electrodes called normal pads 4 and dummy pads 6 formed independently at the four corners of the semiconductor substrate 2 without being connected to the circuit of the semiconductor substrate 2. An electrode called is formed. In addition, a plurality of measurement pads 8 to be TEG electrodes are formed. A measuring needle is applied to the measuring pad 8 to measure the electrical characteristics of the monitoring transistor. The normal pad 4, dummy pad 6, and measurement pad 8 are formed by using a TiN film as the lower layer and a Ti film as the upper layer or an AlCu film formed on a single layer film of TiN.

図３は、図１のＸ部拡大図を示す。また、図４は、図３のＡ−Ａ’断面図を示す。図４に示すように、測定用パッド８の下層には、例えばタングステン等で作られたコンタクト１６が形成される。測定用パッド８は、コンタクト１６から、さらに下層のコンタクトや配線を経由してモニタ用トランジスタと通電可能となっている。 FIG. 3 shows an enlarged view of a portion X in FIG. FIG. 4 is a cross-sectional view taken along the line A-A ′ of FIG. 3. As shown in FIG. 4, a contact 16 made of tungsten or the like is formed under the measurement pad 8. The measurement pad 8 can be energized with the monitor transistor from the contact 16 via a contact and wiring below.

なお、ダミーパッド６及び測定用パッド８の下層には層間絶縁膜１４が形成されている。さらに、ダミーパッド６及び測定用パッド８の周囲には、パッシベーション膜１２が形成されている。パッシベーション膜１２は、ＳｉＯＮ膜や、下層がＳｉＯ_２膜で上層がＳｉＯＮ膜の積層膜である。つまり、図４は、パッシベーション膜１２を形成した後に、ダミーパッド６あるいは測定用パッド８が露出するように開口処理を行った後の状態を示している。 An interlayer insulating film 14 is formed below the dummy pad 6 and the measurement pad 8. Further, a passivation film 12 is formed around the dummy pad 6 and the measurement pad 8. The passivation film 12, the SiON film and the lower layer is a laminated film of the upper layer is SiON film with SiO ₂ film. That is, FIG. 4 shows a state after the opening process is performed so that the dummy pad 6 or the measurement pad 8 is exposed after the passivation film 12 is formed.

特許文献１に、外部との電気信号伝達の為の電極を有するＩＣチップにおいて、バンプ形成用の電極とは別に電気的に導通している電極を有することを特徴とする半導体装置が開示されている（特許文献１参照）。 Patent Document 1 discloses a semiconductor device characterized in that, in an IC chip having an electrode for electric signal transmission with the outside, an electrode that is electrically conductive is provided separately from an electrode for bump formation. (See Patent Document 1).

特開２００１−２８４３８３号公報JP 2001-284383 A

図５は、バンプ電極形成後の断面図を示す。図４に示すような、半導体装置が形成された後、ＵＢＭ（ＵｎｄｅｒＢｕｍｐｉｎｇＭｅｔａｌ）層１８を形成し、ダミーパッド６の上方にバンプ２０を形成する。 FIG. 5 shows a cross-sectional view after the bump electrode is formed. After the semiconductor device as shown in FIG. 4 is formed, a UBM (Under Bumping Metal) layer 18 is formed, and a bump 20 is formed above the dummy pad 6.

ＵＢＭ層１８は、例えば、下層がＴｉ膜で上層がＡｕ層からなる積層膜で、Ｔｉ膜及びＡｕ膜は、各々、スパッタリングによって形成される。そして、全体にフォトレジストをかけて、バンプ２０を形成する部分のフォトレジストを開口して、Ａｕメッキによって、バンプ２０を形成する。その後、不要なＡｕメッキとフォトレジストを除去する。 The UBM layer 18 is, for example, a laminated film in which a lower layer is a Ti film and an upper layer is an Au layer, and each of the Ti film and the Au film is formed by sputtering. Then, a photoresist is applied to the entire surface, a portion of the photoresist where the bump 20 is to be formed is opened, and the bump 20 is formed by Au plating. Thereafter, unnecessary Au plating and photoresist are removed.

そして、バンプ２０の下層のＵＢＭ層１８を除くＵＢＭ層１８を除去するために、ＵＢＭ層エッチングを行う。ＵＢＭ層エッチングの工程は、上層のＡｕ層を王水、またはヨウ素とヨウ化カリウムを含む水溶液によってエッチングし、下層のＴｉ層を過酸化水素とアンモニアと純水の混合液によってエッチングするものである。Ｔｉ層をエッチングする際、測定用パッド８の表面が、エッチングされてしまう。図６は、ＵＢＭ層エッチング後の断面図を示している。その測定用パッド８の表面のエッチング程度が大きく、測定用パッド８の表面が、図６に示すような損傷２２を受けていると、測定用針を測定用パッド８に当てて、モニタ用トランジスタ等の電気的特性を測定することが困難となる。 Then, in order to remove the UBM layer 18 excluding the UBM layer 18 below the bump 20, UBM layer etching is performed. In the UBM layer etching process, the upper Au layer is etched with aqua regia or an aqueous solution containing iodine and potassium iodide, and the lower Ti layer is etched with a mixed solution of hydrogen peroxide, ammonia and pure water. . When the Ti layer is etched, the surface of the measurement pad 8 is etched. FIG. 6 shows a cross-sectional view after etching the UBM layer. When the surface of the measurement pad 8 is etched to a large extent and the surface of the measurement pad 8 is damaged 22 as shown in FIG. 6, the measurement needle is applied to the measurement pad 8 and the monitor transistor It is difficult to measure electrical characteristics such as.

本発明の目的は、測定用パッドの表面がＵＢＭ層エッチングによって損傷を受けても、半導体基板に設けられたＴＥＧの電気的特性の測定が可能な半導体装置及びその半導体装置の製造方法を提供することである。 An object of the present invention is to provide a semiconductor device capable of measuring electrical characteristics of a TEG provided on a semiconductor substrate and a method of manufacturing the semiconductor device even when the surface of the measurement pad is damaged by etching of the UBM layer. That is.

以下に、（発明を実施するための最良の形態）で使用される番号を用いて、課題を解決するための手段を説明する。これらの番号は、（特許請求の範囲）の記載と（発明を実施するための最良の形態）との対応関係を明らかにするために付加されたものである。ただし、それらの番号を、（特許請求の範囲）に記載されている発明の技術的範囲の解釈に用いてはならない。 Hereinafter, means for solving the problem will be described using the numbers used in (Best Mode for Carrying Out the Invention). These numbers are added to clarify the correspondence between the description of (Claims) and (Best Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

本発明による半導体装置は、半導体基板（２）の上に形成される層間絶縁膜（１４）と、層間絶縁膜（１４）の上に形成され、電極であるダミー電極（６）と、層間絶縁膜（１４）の上に形成され、半導体基板（２）に形成された回路の電気的特性を測定するために設けられた電極である測定用電極（８）と、ダミー電極（６）と測定用電極（８）とを電気的に接続する第１配線（２６）と、測定用電極（８）の下であって、層間絶縁膜（１４）を貫通するように設けられ、測定用電極（８）と電気的に接続された第１コンタクト（１６）とを備え、第１コンタクト（１６）は半導体基板（２）と電気的に接続される。 The semiconductor device according to the present invention includes an interlayer insulating film (14) formed on a semiconductor substrate (2), a dummy electrode (6) formed on the interlayer insulating film (14), and an interlayer insulating film. A measurement electrode (8) which is an electrode formed on the film (14) and provided for measuring the electrical characteristics of the circuit formed on the semiconductor substrate (2), a dummy electrode (6), and measurement The first wiring (26) for electrically connecting the electrode for measurement (8) and the measurement electrode (8), provided so as to penetrate the interlayer insulating film (14), 8) and a first contact (16) electrically connected, and the first contact (16) is electrically connected to the semiconductor substrate (2).

本発明による半導体装置は、層間絶縁膜（１４）と、層間絶縁膜（１４）の上に形成され、電極であるダミー電極（６）と、層間絶縁膜（１４）の上に形成され、半導体基板に形成された回路の電気的特性を測定するために設けられた電極である測定用電極（８）と、層間絶縁膜（１４）の下であって半導体基板（２）の上に形成された下側層間絶縁膜（１４‘）と、測定用電極（８）の下であって、層間絶縁膜（１４）を貫通するように設けられ、測定用電極（８）と電気的に接続された第１コンタクト（１６）と、ダミー電極（６）の下であって、層間絶縁膜（１４）を貫通するように設けられ、ダミー電極（６）と電気的に接続された第３コンタクト（３４）と、第１コンタクト（１６）及び第３コンタクト（３４）の下であって、下側層間絶縁膜（１４’）の一部に形成され、第１コンタクト（１６）及び第３コンタクト（３４）と電気的に接続する第３配線（３６）とを具備し、第３配線（３６）は、半導体基板（２）と電気的に接続される。 The semiconductor device according to the present invention is formed on the interlayer insulating film (14) and the interlayer insulating film (14), and is formed on the dummy electrode (6) which is an electrode and the interlayer insulating film (14), and the semiconductor device. A measurement electrode (8) which is an electrode provided for measuring the electrical characteristics of a circuit formed on the substrate, and an interlayer insulating film (14) which is formed on the semiconductor substrate (2). The lower interlayer insulating film (14 ') and the measurement electrode (8) are provided so as to penetrate the interlayer insulating film (14) and are electrically connected to the measurement electrode (8). The first contact (16) and a third contact (under the dummy electrode (6)) that is provided so as to penetrate the interlayer insulating film (14) and electrically connected to the dummy electrode (6) 34), below the first contact (16) and the third contact (34), A third wiring (36) is formed on a part of the interlayer insulating film (14 ′) and includes a first wiring (36) electrically connected to the first contact (16) and the third contact (34). Are electrically connected to the semiconductor substrate (2).

本発明による半導体装置の製造方法は、半導体基板（２）の上に形成される層間絶縁膜（１４）と、層間絶縁膜（１４）の上に形成され、電極であるダミー電極（６）と、層間絶縁膜（１４）の上に形成され、半導体基板（２）に形成された回路の電気的特性を測定するために設けられた電極である測定用電極（８）と、ダミー電極（６）と測定用電極（８）とを電気的に接続する第１配線（２６）とを具備する半導体装置の製造方法であって、層間絶縁膜（１４）を形成するステップと、測定用電極（８）の下に相当する位置において、層間絶縁膜（１４）を貫通するように第１コンタクト（１６）を開け、第１コンタクト（１６）に金属を埋めるステップと、ダミー電極（６）と測定用電極（８）と第１配線（２６）を形成するステップとを備えている。 The method of manufacturing a semiconductor device according to the present invention includes an interlayer insulating film (14) formed on a semiconductor substrate (2), a dummy electrode (6) which is formed on the interlayer insulating film (14), and is an electrode. A measuring electrode (8) which is formed on the interlayer insulating film (14) and is provided for measuring electrical characteristics of a circuit formed on the semiconductor substrate (2), and a dummy electrode (6) ) And the first wiring (26) for electrically connecting the measurement electrode (8), a step of forming an interlayer insulating film (14), a measurement electrode ( 8) Opening the first contact (16) so as to penetrate the interlayer insulating film (14) at a position corresponding to the lower part, filling the first contact (16) with metal, and measuring the dummy electrode (6) Forming an electrode (8) and a first wiring (26) It is equipped with a.

本発明による半導体装置の製造方法は、層間絶縁膜（１４）と、層間絶縁膜（１４）の上に形成され、電極であるダミー電極（６）と、層間絶縁膜（１４）の上に形成され、半導体基板（２）に形成された回路の電気的特性を測定するために設けられた電極である測定用電極（８）と、層間絶縁膜（１４）の下であって半導体基板（２）の上に形成された下側層間絶縁膜（１４’）と、測定用電極（８）の下であって、層間絶縁膜（１４）を貫通するように設けられ、測定用電極（８）と電気的に接続された第１コンタクト（１６）と、ダミー電極（６）の下であって、層間絶縁膜（１４）を貫通するように設けられ、ダミー電極（６）と電気的に接続された第３コンタクト（３４）と、第１コンタクト（１６）及び第３コンタクト（３４）の下であって、下側層間絶縁膜（１４’）の一部に形成され、第１コンタクト（１６）及び第３コンタクト（３４）と電気的に接続する第３配線（３６）とを具備する半導体装置の製造方法であって、下側層間絶縁膜（１４’）を形成するステップと、第３配線（３６）を形成するステップと、測定用電極（８）の下に相当する位置において、層間絶縁膜（１４）を貫通するように第１コンタクト（１６）を開け、第１コンタクト（１６）に金属を埋め、ダミー電極（６）の下に相当する位置において、層間絶縁膜（１４）を貫通するように第３コンタクト（３４）を開け、第３コンタクト（３４）に金属を埋めるステップと、ダミー電極（６）と測定用電極（８）とを形成するステップとを備えている。 The semiconductor device manufacturing method according to the present invention is formed on the interlayer insulating film (14) and the interlayer insulating film (14), and is formed on the dummy electrode (6) as an electrode and the interlayer insulating film (14). The measurement electrode (8), which is an electrode provided for measuring the electrical characteristics of the circuit formed on the semiconductor substrate (2), and the semiconductor substrate (2) under the interlayer insulating film (14) ) Formed on the lower interlayer insulating film (14 ′) and the measurement electrode (8) so as to penetrate the interlayer insulating film (14), and the measurement electrode (8) The first contact (16) that is electrically connected to the electrode and the dummy electrode (6) are provided so as to penetrate the interlayer insulating film (14) and are electrically connected to the dummy electrode (6). Third contact (34), first contact (16) and third contact (34) A third wiring (36) that is formed on a part of the lower interlayer insulating film (14 ') and is electrically connected to the first contact (16) and the third contact (34). In a method for manufacturing a semiconductor device, a step of forming a lower interlayer insulating film (14 ′), a step of forming a third wiring (36), and a position corresponding to under a measurement electrode (8), The first contact (16) is opened so as to penetrate the interlayer insulating film (14), the first contact (16) is filled with metal, and the interlayer insulating film (14) is located at a position below the dummy electrode (6). A step of opening the third contact (34) so as to penetrate the metal, filling the third contact (34) with metal, and forming a dummy electrode (6) and a measurement electrode (8).

本発明によれば、測定用パッドの表面がＵＢＭ層エッチングによって損傷を受けても、半導体基板に設けられたＴＥＧの電気的特性の測定が可能な半導体装置及びその半導体装置の製造方法が提供される。 ADVANTAGE OF THE INVENTION According to this invention, even if the surface of a measuring pad is damaged by UBM layer etching, the semiconductor device which can measure the electrical property of TEG provided in the semiconductor substrate, and the manufacturing method of the semiconductor device are provided. The

添付図面を参照して、本発明による半導体装置を実施するための最良の形態を以下に説明する。 The best mode for carrying out a semiconductor device according to the present invention will be described below with reference to the accompanying drawings.

（第１の実施形態）
図２に、本発明に係る半導体装置の拡散工程後の上面図を示す。拡散工程後とは、パッシベーション膜形成後パッド部を開口した後を意味する。図２に示すように、半導体装置の半導体基板２には、複数の通常パッド４と呼ばれる電極と、半導体基板２の四隅に半導体基板２の回路に接続せずに単独で形成されたダミーパッド６と呼ばれる電極が形成される。また、ＴＥＧの電極となる複数の測定用パッド８が、形成される。このダミーパッド６と測定用パッド８が、配線１０によって接続される。なお、通常パッド４やダミーパッド６、測定用パッド８は、下層がＴｉＮ膜で上層がＴｉの積層膜か、ＴｉＮの単層膜の上にＡｌＣｕ膜を形成したものが用いられる。 (First embodiment)
FIG. 2 shows a top view of the semiconductor device according to the present invention after the diffusion step. “After the diffusion step” means after the pad film is opened after the passivation film is formed. As shown in FIG. 2, the semiconductor substrate 2 of the semiconductor device has a plurality of electrodes called normal pads 4 and dummy pads 6 formed independently at the four corners of the semiconductor substrate 2 without being connected to the circuit of the semiconductor substrate 2. An electrode called is formed. In addition, a plurality of measurement pads 8 to be TEG electrodes are formed. The dummy pad 6 and the measurement pad 8 are connected by a wiring 10. The normal pad 4, dummy pad 6, and measurement pad 8 are formed by using a TiN film as a lower layer and a Ti film as an upper layer or an AlCu film formed on a single layer film of TiN.

図７は、図２のＸ’部拡大図を示す。また、図８は、第１の実施形態に係る半導体装置の図７のＢ−Ｂ’断面図を示す。半導体装置は、半導体基板の上に層間絶縁膜１４を形成し、さらに層間絶縁膜１４を貫通するようにコンタクト１６が設けられている。層間絶縁膜１４及びコンタクト１６の上に、ダミーパッド６及び測定用パッド８を形成し、それらと同一の層に、配線２６を形成している。したがって、ダミーパッド６と測定用パッド８が、配線２６を介して電気的に接続される。なお、配線２６の材質は、ＡｌＣｕである。また、従来の半導体装置と同様に、パッシベーション膜１２が、ダミーパッド６及び測定用パッド８の上に形成され、開口部が設けられる。コンタクト１６は、半導体基板と電気的に接続する。 FIG. 7 shows an enlarged view of a portion X ′ in FIG. FIG. 8 is a cross-sectional view taken along the line B-B ′ of FIG. 7 of the semiconductor device according to the first embodiment. In the semiconductor device, an interlayer insulating film 14 is formed on a semiconductor substrate, and a contact 16 is provided so as to penetrate the interlayer insulating film 14. A dummy pad 6 and a measurement pad 8 are formed on the interlayer insulating film 14 and the contact 16, and a wiring 26 is formed in the same layer as these. Therefore, the dummy pad 6 and the measurement pad 8 are electrically connected via the wiring 26. The material of the wiring 26 is AlCu. Further, like the conventional semiconductor device, the passivation film 12 is formed on the dummy pad 6 and the measurement pad 8, and an opening is provided. The contact 16 is electrically connected to the semiconductor substrate.

図８に示す半導体装置の製造方法を説明する。半導体基板の上に、図示しない層間絶縁膜をＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）によって成膜する。次に、図示しない下層金属層をスパッタリングによって成膜する。そして、再度、層間絶縁膜１４をＣＶＤにより成膜する。ここで、フォトレジスト技術を用い、層間絶縁膜１４にコンタクト１６を開け、コンタクト１６に例えばタングステンを埋め込む。その後、ダミーパッド６及び測定用パッド８と配線２６を同時にスパッタリングにより成膜する。そして、パッシベーション膜１２をＣＶＤにより成膜する。 A method for manufacturing the semiconductor device shown in FIG. 8 will be described. An interlayer insulating film (not shown) is formed on the semiconductor substrate by CVD (Chemical Vapor Deposition). Next, a lower metal layer (not shown) is formed by sputtering. Then, an interlayer insulating film 14 is again formed by CVD. Here, using a photoresist technique, a contact 16 is opened in the interlayer insulating film 14, and tungsten, for example, is buried in the contact 16. Thereafter, the dummy pad 6 and the measurement pad 8 and the wiring 26 are simultaneously formed by sputtering. Then, a passivation film 12 is formed by CVD.

以上のように、配線２６を設けることによって、測定用パッド８の表面が、ＵＢＭ層エッチングの際に損傷を受けても、ダミーパッド６は、配線２６からコンタクト１６を経由し、コンタクト１６の下層に配置されたＴＥＧである図示しないモニタ用トランジスタと導通しているので、ダミーパッド６の上に形成されたバンプ２０に測定針を当てることで電気的特性の測定が可能となる。 As described above, by providing the wiring 26, even if the surface of the measurement pad 8 is damaged during the UBM layer etching, the dummy pad 6 passes through the contact 16 from the wiring 26 to the lower layer of the contact 16. Therefore, the electrical characteristics can be measured by applying a measuring needle to the bump 20 formed on the dummy pad 6.

（第２の実施形態）
図９に、第２の実施形態に係る半導体装置の図７のＢ−Ｂ’断面図を示す。ダミーパッド６と測定用パッド８を電気的に接続する配線２８を有する点は、第１の実施形態と同様である。配線２８の下層に、コンタクト３０が層間絶縁膜１４を貫通して形成され、配線２８とコンタクト３０とが電気的に接続され、さらに下層に下側層間絶縁膜１４’を設け、その下側層間絶縁膜１４’の一部に配線３２を設けている。配線３２が、２つのコンタクト（コンタクト３０及びコンタクト１６）と電気的に接続している点が第１の実施形態と異なる。配線３２は、半導体基板と電気的に接続する。 (Second Embodiment)
FIG. 9 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the line BB ′ of FIG. The point which has the wiring 28 which electrically connects the dummy pad 6 and the measurement pad 8 is the same as that of 1st Embodiment. A contact 30 is formed in the lower layer of the wiring 28 so as to penetrate the interlayer insulating film 14, the wiring 28 and the contact 30 are electrically connected, and a lower interlayer insulating film 14 ′ is provided in the lower layer, and the lower interlayer A wiring 32 is provided in a part of the insulating film 14 ′. The wiring 32 is different from the first embodiment in that the wiring 32 is electrically connected to two contacts (contact 30 and contact 16). The wiring 32 is electrically connected to the semiconductor substrate.

図９に示す半導体装置の製造方法を説明する。半導体基板の上に、下側層間絶縁膜１４’をＣＶＤによって成膜する。次に、フォトリソグラフィー技術を用い、配線３２を形成するための空間を作り、金属層をスパッタリングによって成膜後、研磨処理により配線３２を形成する。その後、層間絶縁膜１４をＣＶＤにより成膜する。ここで、フォトレジスト技術を用い、層間絶縁膜１４にコンタクト１６及びコンタクト３０を開け、スパッタリングによってコンタクト１６及びコンタクト３０に例えばタングステンを埋め込む。その後、ダミーパッド６及び測定用パッド８と配線２６とを同時にスパッタリングにより成膜する。そして、パッシベーション膜１２をＣＶＤにより成膜する。 A method for manufacturing the semiconductor device shown in FIG. 9 will be described. A lower interlayer insulating film 14 ′ is formed on the semiconductor substrate by CVD. Next, a space for forming the wiring 32 is created by using a photolithography technique, a metal layer is formed by sputtering, and then the wiring 32 is formed by polishing treatment. Thereafter, an interlayer insulating film 14 is formed by CVD. Here, using the photoresist technique, the contact 16 and the contact 30 are opened in the interlayer insulating film 14, and tungsten, for example, is buried in the contact 16 and the contact 30 by sputtering. Thereafter, the dummy pad 6 and the measurement pad 8 and the wiring 26 are simultaneously formed by sputtering. Then, a passivation film 12 is formed by CVD.

図１０に、第２の実施形態に係る半導体装置のＵＢＭ層エッチング後の断面図を示す。ＵＢＭ層エッチングの際に、測定用パッド８が損傷２２を受け、配線２８と測定用パッド８の下層に形成されたコンタクト１６との導通が寸断されることが起き得る。つまり、第１の実施形態の場合、測定用パッド８が、ＵＢＭ層エッチングの際に過度に損傷を受けると、配線２６を設けたにも係わらず、バンプ２０から図示しないモニタ用トランジスタへの導通が図れないことが起き得るのである。したがって、第２の実施形態のように、コンタクト３０及び配線３２を追加することで、バンプ２０から図示しないモニタ用トランジスタへの導通が図れることになる。 FIG. 10 shows a cross-sectional view of the semiconductor device according to the second embodiment after etching the UBM layer. When the UBM layer is etched, the measurement pad 8 may be damaged 22, and conduction between the wiring 28 and the contact 16 formed under the measurement pad 8 may be interrupted. That is, in the case of the first embodiment, when the measurement pad 8 is excessively damaged during the UBM layer etching, the conduction from the bump 20 to the monitor transistor (not shown) is provided despite the provision of the wiring 26. It is possible that things cannot be achieved. Accordingly, by adding the contact 30 and the wiring 32 as in the second embodiment, conduction from the bump 20 to the monitoring transistor (not shown) can be achieved.

以上のように、配線２８及び配線３２、コンタクト３０を設けることによって、測定用パッド８が、ＵＢＭ層エッチングの際に損傷を受けても、ダミーパッド６は、配線２８からコンタクト３０を経由し、配線３２をさらに経由し、配線３２は半導体基板に配置された図示しないモニタ用トランジスタと導通しているので、ダミーパッド６の上に形成されたバンプ２０に測定針を当てることで電気的特性の測定が可能となる。 As described above, by providing the wiring 28, the wiring 32, and the contact 30, even if the measurement pad 8 is damaged during the UBM layer etching, the dummy pad 6 passes through the contact 30 from the wiring 28. Further, the wiring 32 is electrically connected to a monitor transistor (not shown) disposed on the semiconductor substrate via the wiring 32. Therefore, by applying a measuring needle to the bump 20 formed on the dummy pad 6, the electrical characteristics are improved. Measurement is possible.

（第３の実施形態）
図１１に、第３の実施形態に係る図７のＢ−Ｂ’断面図を示す。第１の実施形態及び第２の実施形態においては、ダミーパッド６と測定用パッド８とを接続する配線を、ダミーパッド６と測定用パッド８と同一の層に設けた。第３の実施形態においては、ダミーパッド６の下層にコンタクト３４が層間絶縁膜１４を貫通して形成され、２つのコンタクト（コンタクト３４及びコンタクト１６）の下層に下側層間絶縁膜１４’を設けるとともにその一部に配線３６を形成している。配線３６は、それら２つのコンタクト（コンタクト３４及びコンタクト１６）と電気的に接続している。配線３６は、半導体基板と電気的に接続する。 (Third embodiment)
FIG. 11 shows a BB ′ cross-sectional view of FIG. 7 according to the third embodiment. In the first embodiment and the second embodiment, the wiring for connecting the dummy pad 6 and the measurement pad 8 is provided in the same layer as the dummy pad 6 and the measurement pad 8. In the third embodiment, a contact 34 is formed through the interlayer insulating film 14 below the dummy pad 6, and a lower interlayer insulating film 14 ′ is provided below the two contacts (contact 34 and contact 16). In addition, a wiring 36 is formed in a part thereof. The wiring 36 is electrically connected to these two contacts (contact 34 and contact 16). The wiring 36 is electrically connected to the semiconductor substrate.

第３の実施形態の半導体装置の製造方法について説明する。下側層間絶縁膜１４’をＣＶＤによって成膜する。次に、フォトリソグラフィー技術を用い、配線３６を形成するための空間を作り、金属層をスパッタリングによって成膜後、研磨処理により配線３６を形成する。その後、層間絶縁膜１４をＣＶＤにより成膜する。ここで、フォトレジスト技術を用い、層間絶縁膜１４にコンタクト１６及びコンタクト３４を開け、スパッタリングによってコンタクト１６及びコンタクト３４に例えばタングステンを埋め込む。その後、ダミーパッド６及び測定用パッド８とを同時にスパッタリングにより成膜する。そして、パッシベーション膜１２をＣＶＤにより成膜する。 A method for manufacturing the semiconductor device of the third embodiment will be described. A lower interlayer insulating film 14 'is formed by CVD. Next, a space for forming the wiring 36 is created by using a photolithography technique, and after forming a metal layer by sputtering, the wiring 36 is formed by polishing treatment. Thereafter, an interlayer insulating film 14 is formed by CVD. Here, using the photoresist technique, the contact 16 and the contact 34 are opened in the interlayer insulating film 14, and tungsten, for example, is buried in the contact 16 and the contact 34 by sputtering. Thereafter, the dummy pad 6 and the measurement pad 8 are simultaneously formed by sputtering. Then, a passivation film 12 is formed by CVD.

以上のように、コンタクト３４及び配線３６を設けることによって、測定用パッド８がＵＢＭ層エッチングの際に損傷を受けても、ダミーパッド６は、コンタクト３４を経由し、さらにコンタクト３４の下層に形成された配線３６を経由し、コンタクト１６の下層に配置された図示しないモニタ用トランジスタと導通しているので、ダミーパッド６の上に形成されたバンプ２０に測定針を当てることで電気的特性の測定が可能となる。 As described above, by providing the contact 34 and the wiring 36, the dummy pad 6 is formed via the contact 34 and further below the contact 34 even if the measurement pad 8 is damaged during the UBM layer etching. Since it is electrically connected to a monitor transistor (not shown) disposed under the contact 16 via the formed wiring 36, the electrical characteristics of the electrical characteristics can be obtained by applying a measuring needle to the bump 20 formed on the dummy pad 6. Measurement is possible.

図１は、従来技術に係る半導体装置の拡散工程後の上面図を示す。FIG. 1 shows a top view after a diffusion process of a semiconductor device according to the prior art. 図２は、本発明に係る半導体装置の拡散工程後の上面図を示す。FIG. 2 shows a top view of the semiconductor device according to the present invention after the diffusion step. 図３は、図１のＸ部拡大図を示す。FIG. 3 shows an enlarged view of a portion X in FIG. 図４は、図３のＡ−Ａ’断面図を示す。FIG. 4 is a cross-sectional view taken along the line A-A ′ of FIG. 3. 図５は、バンプ電極形成後の断面図を示す。FIG. 5 shows a cross-sectional view after the bump electrode is formed. 図６は、ＵＢＭ層エッチング後の断面図を示す。FIG. 6 shows a cross-sectional view after etching the UBM layer. 図７は、図２のＸ’部拡大図を示す。FIG. 7 shows an enlarged view of a portion X ′ in FIG. 図８は、第１の実施形態に係る半導体装置の図７のＢ−Ｂ’断面図を示す。FIG. 8 is a cross-sectional view of the semiconductor device according to the first embodiment taken along the line B-B ′ of FIG. 7. 図９は、第２の実施形態に係る半導体装置の図７のＢ−Ｂ’断面図を示す。FIG. 9 is a cross-sectional view of the semiconductor device according to the second embodiment, taken along the line B-B ′ of FIG. 7. 図１０は、第２の実施形態に係る半導体装置のＵＢＭ層エッチング後の断面図を示す。FIG. 10 shows a cross-sectional view of the semiconductor device according to the second embodiment after etching the UBM layer. 図１１は、第３の実施形態に係る図７のＢ−Ｂ’断面図を示す。FIG. 11 is a cross-sectional view taken along the line B-B ′ of FIG. 7 according to the third embodiment.

Explanation of symbols

２：半導体基板
４：通常パッド
６：ダミーパッド
８：測定用パッド
１０：配線
１２：パッシベーション膜
１４：層間絶縁膜
１４’：下側層間絶縁膜
１６：コンタクト
１８：ＵＢＭ層
２０：バンプ
２２：損傷
２４：配線
２６：配線
２８：配線
３０：コンタクト
３２：配線
３４：コンタクト
３６：配線 2: Semiconductor substrate 4: Normal pad 6: Dummy pad 8: Measurement pad 10: Wiring 12: Passivation film 14: Interlayer insulation film 14 ′: Lower interlayer insulation film 16: Contact 18: UBM layer 20: Bump 22: Damage 24: Wiring 26: Wiring 28: Wiring 30: Contact 32: Wiring 34: Contact 36: Wiring

Claims

An interlayer insulating film formed on the semiconductor substrate;
A dummy electrode formed on the interlayer insulating film and serving as an electrode;
A measuring electrode which is formed on the interlayer insulating film and is an electrode provided for measuring electrical characteristics of a circuit formed on the semiconductor substrate;
A first wiring that electrically connects the dummy electrode and the measurement electrode;
A first contact provided below the measurement electrode and penetrating through the interlayer insulating film and electrically connected to the measurement electrode;
The first contact is a semiconductor device electrically connected to the semiconductor substrate.

And a lower interlayer insulating film formed on the semiconductor substrate below the interlayer insulating film;
A second contact provided below the first wiring and penetrating the interlayer insulating film and electrically connected to the first wiring;
A second wiring formed under the first contact and the second contact and in a part of the lower interlayer insulating film and electrically connected to the first contact and the second contact; And
The semiconductor device according to claim 1, wherein the second wiring is electrically connected to the semiconductor substrate.

An interlayer insulating film;
A dummy electrode formed on the interlayer insulating film and serving as an electrode;
A measuring electrode which is formed on the interlayer insulating film and is an electrode provided for measuring electrical characteristics of a circuit formed on the semiconductor substrate;
A lower interlayer insulating film formed on the semiconductor substrate under the interlayer insulating film;
A first contact provided under the measurement electrode and penetrating the interlayer insulating film and electrically connected to the measurement electrode;
A third contact provided below the dummy electrode and penetrating the interlayer insulating film and electrically connected to the dummy electrode;
A third wiring formed under the first contact and the third contact and in a part of the lower interlayer insulating film and electrically connected to the first contact and the third contact; ,
The third wiring is a semiconductor device electrically connected to the semiconductor substrate.

An interlayer insulating film formed on the semiconductor substrate;
A dummy electrode formed on the interlayer insulating film and serving as an electrode;
A measuring electrode which is formed on the interlayer insulating film and is an electrode provided for measuring electrical characteristics of a circuit formed on the semiconductor substrate;
A method of manufacturing a semiconductor device comprising a first wiring that electrically connects the dummy electrode and the measurement electrode,
Forming the interlayer insulating film;
Opening a first contact so as to penetrate the interlayer insulating film at a position corresponding to a position below the measurement electrode, and filling the first contact with metal;
A method of manufacturing a semiconductor device, comprising: forming the dummy electrode, the measurement electrode, and the first wiring.

And a lower interlayer insulating film formed on the semiconductor substrate below the interlayer insulating film;
A second contact provided below the first wiring and penetrating the interlayer insulating film and electrically connected to the first wiring;
A second wiring formed under the first contact and the second contact and in a part of the lower interlayer insulating film and electrically connected to the first contact and the second contact; A method for manufacturing a semiconductor device comprising:
Forming the lower interlayer insulating film;
Forming the second wiring;
5. The method of manufacturing a semiconductor device according to claim 4, further comprising: opening a second contact so as to penetrate the interlayer insulating film at a position corresponding to a position below the first wiring, and filling the second contact with a metal. Method.

An interlayer insulating film;
A dummy electrode formed on the interlayer insulating film and serving as an electrode;
A measuring electrode which is formed on the interlayer insulating film and is an electrode provided for measuring electrical characteristics of a circuit formed on the semiconductor substrate;
A lower interlayer insulating film formed on the semiconductor substrate under the interlayer insulating film;
A first contact provided under the measurement electrode and penetrating the interlayer insulating film and electrically connected to the measurement electrode;
A third contact provided below the dummy electrode and penetrating the interlayer insulating film and electrically connected to the dummy electrode;
A third wiring formed under the first contact and the third contact and in a part of the lower interlayer insulating film and electrically connected to the first contact and the third contact; A method for manufacturing a semiconductor device, comprising:
Forming the lower interlayer insulating film;
Forming the third wiring;
A first contact is opened so as to penetrate the interlayer insulating film at a position corresponding to the measurement electrode, the metal is filled in the first contact, and the interlayer insulation is formed at a position corresponding to the dummy electrode. Opening a third contact to penetrate the film and filling the third contact with metal;
A method of manufacturing a semiconductor device, comprising: forming the dummy electrode and the measurement electrode.