JP2008293591A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve further the stability of data holding in a memory cell. <P>SOLUTION: The semiconductor storage device includes: a memory cell array 11 having a plurality of memory cells MC; first and second word lines RWL, WWL arranged in common to the plurality of memory cells MC; a plurality of power source lines VSSR arranged corresponding to the plurality of memory cells; a plurality of couples of first and second bit lines arranged corresponding to the plurality of memory cells MC; a row decoder 12 for successively activating the first word line PWL and second word line WWL at the write-in of data; and a control circuit 14 for setting the power source line VSSR of a selected memory cell to the floating state and setting the power source line VSSR of a non-selected memory cell to a grounding voltage, at the time of write-in of data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a semiconductor memory device including a static memory cell.

  An SRAM is known as a kind of semiconductor memory device. For example, an SRAM cell (6Tr. Type SRAM cell) composed of six MOS (Metal Oxide Semiconductor) transistors is used as a memory cell constituting the SRAM.

  6Tr. The type SRAM cell includes two sets of inverter circuits, and has a structure in which the output terminal of one inverter circuit is connected to the input terminal of the other inverter circuit. Further, two transfer gates are provided for connecting the data storage node of the inverter circuit to the bit line at the time of data reading and data writing.

  As an index indicating the operation margin of the SRAM, there is a static noise margin (SNM). SNM is a superposition of the input / output characteristics of two inverter circuits when a word line is selected and a bit line is precharged to a power supply voltage. The length of one side of a square that can be written between these curves. It corresponds to.

  In recent years, the size of transistors used in memory cells has been reduced in order to improve the degree of integration of semiconductor memory devices. In addition, the threshold voltage of the transistor also decreases as the power supply voltage decreases. As a result, there is a problem that the threshold voltage variation of the transistors constituting the memory cell becomes large. Furthermore, there is a problem that the SNM is lowered due to the influence of the threshold voltage variation of the transistors constituting the memory cell.

  Therefore, in a memory cell having low data retention stability due to the low SNM, when the word line connected to the memory cell is activated in order to read data from the memory cell or write data to the memory cell, the data There is a problem that the storage state of the inverter pair storing the data is inverted and the data is destroyed.

Also, as this type of related technology, an SRAM is disclosed that can improve data retention characteristics by increasing the SNM at the time of data reading (see Non-Patent Document 1).
Leland Chang et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp.128-129

  The present invention provides a semiconductor memory device capable of further improving the stability of data retention in a memory cell.

A semiconductor memory device according to one aspect of the present invention includes a memory cell array having a plurality of memory cells, first and second word lines provided in common to the plurality of memory cells, and the plurality of memory cells. A plurality of power supply lines provided in correspondence with each other, a plurality of pairs of first and second bit lines provided in correspondence with the plurality of memory cells, and the first word line and the first in writing data A row decoder that sequentially activates two word lines; a control circuit that sets a power line of a selected memory cell to a floating state and sets a power line of a non-selected memory cell to a ground voltage when data is written; It comprises. Each of the plurality of memory cells includes first and second inverter circuits, a first storage node connected to an output terminal of the first inverter circuit and an input terminal of the second inverter circuit; A second storage node connected to an input terminal of the first inverter circuit and an output terminal of the second inverter circuit, connected between the first storage node and the first bit line; And a first transfer gate having a gate terminal connected to the first word line, connected between the second storage node and a second bit line, and connected to the first word line. A second transfer gate having a gate terminal configured;
A first driving transistor having a gate terminal connected to the second storage node and a source terminal connected to a power supply line; a drain terminal of the first driving transistor; and a first bit line. A third transfer gate having a gate terminal connected to the second word line, a gate terminal connected to the first storage node, and a source terminal connected to the power supply line And a second drive transistor having a gate terminal connected between the drain terminal of the second drive transistor and the second bit line and connected to the second word line. Transfer gates.

  According to the present invention, it is possible to provide a semiconductor memory device capable of further improving the stability of data retention in a memory cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  FIG. 1 is a block diagram showing a configuration of an SRAM according to an embodiment of the present invention. The SRAM includes a memory cell array 11 in which a plurality of static memory cells MC are arranged in a matrix. In the memory cell array 11, a plurality of write word lines WWL are arranged so as to extend in the row direction, and a plurality of read word lines RWL are arranged so as to extend in the row direction. The memory cell array 11 is provided with a plurality of bit line pairs BL, / BL so as to extend in the column direction. In the memory cell array 11, a plurality of low power supply lines VSSR are arranged so as to extend in the column direction.

  In the present embodiment, four memory cells MC (MC0 to MC3) are shown as an example. FIG. 1 shows one write word line WWL and one read word line RWL provided in common to these four memory cells MC. FIG. 1 also shows four bit line pairs BL0-3, / BL0-3, and four low power supply lines VSSR0-VSSR3, which are provided corresponding to four memory cells MC.

  The write word line WWL and the read word line RWL are connected to the row decoder 12. The row decoder 12 performs a selection operation of the write word line WWL and the read word line RWL based on an address signal supplied from an external circuit.

  The bit line pairs BL0-3, / BL0-3 are connected to the column selection circuit 13. Further, a common bit line pair CBL, / CBL is connected to the column selection circuit. Further, column selection signals SEL0 to SEL3 are supplied to the column selection circuit 13 from a column decoder (not shown). The column selection circuit 13 connects the bit line pair BL, / BL of the column selected by the column selection signals SEL0 to SEL3 and the common bit line pair CBL, / CBL. Column selection is performed by activating (high level) one of the column selection signals SEL0 to SEL3.

  Write data is input to the column selection circuit 13 from an external circuit via the common bit line pair CBL, / CBL. Read data read from the memory cell array 11 is output to an external circuit via the column selection circuit 13 and the common bit line pair CBL, / CBL.

  The low power supply lines VSSR0 to VSSR3 are connected to the voltage control circuit 14. The voltage control circuit 14 receives column selection signals SEL0 to SEL3 from a column decoder (not shown) and a write signal WRT from the control circuit (not shown). The write signal WRT is activated (high level) when data is written. The voltage control circuit 14 controls the voltage of the low power supply lines VSSR0 to VSSR3. That is, the voltage control circuit 14 sets the low power supply lines VSSR of all the columns to the ground voltage VSS when reading data. In addition, the voltage control circuit 14 sets the lower power supply line VSSR of the selected column to the floating state and sets the lower power supply line VSSSR of the non-selected column to the ground voltage VSS when writing data.

  FIG. 2 is a circuit diagram showing a configuration of memory cell MC shown in FIG. The memory cell MC is a 10Tr. Type SRAM cell.

  The memory cell MC includes a data holding unit 15A and reading units 15B and 15C. The data holding unit 15A includes inverter circuits INV1 and INV2. The inverter circuit INV1 includes a load P-channel MOS transistor (PMOS transistor) LD1 and a driving N-channel MOS transistor (NMOS transistor) DV1. The PMOS transistor LD1 and the NMOS transistor DV1 are connected in series between a power supply terminal to which the power supply voltage VDD is supplied and a ground terminal to which the ground voltage VSS is supplied.

  The inverter circuit INV2 is composed of a load PMOS transistor LD2 and a drive NMOS transistor DV2. The PMOS transistor LD2 and NMOS transistor DV2 are connected in series between the power supply terminal and the ground terminal.

  Specifically, the source terminal of the PMOS transistor LD1 is connected to the power supply terminal. The drain terminal of the PMOS transistor LD1 is connected to the drain terminal of the NMOS transistor DV1 via the storage node N1. The gate terminal of the PMOS transistor LD1 is connected to the gate terminal of the NMOS transistor DV1. The source terminal of the NMOS transistor DV1 is grounded.

  The source terminal of the PMOS transistor LD2 is connected to the power supply terminal. The drain terminal of the PMOS transistor LD2 is connected to the drain terminal of the NMOS transistor DV2 via the storage node N2. The gate terminal of the PMOS transistor LD2 is connected to the gate terminal of the NMOS transistor DV2. The source terminal of the NMOS transistor DV2 is grounded.

  The gate terminal of the PMOS transistor LD1 is connected to the storage node N2. The gate terminal of the PMOS transistor LD2 is connected to the storage node N1. In other words, the output terminal of the inverter circuit INV1 is connected to the input terminal of the inverter circuit INV2, and the output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV1.

  The storage node N1 is connected to the bit line / BL via a transfer gate XF1 made of an NMOS transistor. The storage node N2 is connected to the bit line BL via a transfer gate XF2 made of an NMOS transistor. The gate terminals of the transfer gates XF2 and XF2 are connected to the write word line WWL.

  The read unit 15B includes a read drive transistor RD1 made of an NMOS transistor and a read transfer gate RT1 made of an NMOS transistor. The gate terminal of the drive transistor RD1 is connected to the storage node N2. The source terminal of the driving transistor RD1 is connected to the low power supply line VSSR. The drain terminal of the drive transistor RD1 is connected to the bit line / BL via the read transfer gate RT1. The gate terminal of the read transfer gate RT1 is connected to the read word line RWL.

  The read unit 15C includes a read drive transistor RD2 made of an NMOS transistor and a read transfer gate RT2 made of an NMOS transistor. The gate terminal of the drive transistor RD2 is connected to the storage node N1. The source terminal of the driving transistor RD2 is connected to the low power supply line VSSR. The drain terminal of the drive transistor RD2 is connected to the bit line BL via the read transfer gate RT2. The gate terminal of the read transfer gate RT2 is connected to the read word line RWL.

  FIG. 3 is a circuit diagram showing the configuration of the column selection circuit 13 and the voltage control circuit 14 shown in FIG. The column selection circuit 13 includes a number of inverter circuits 20-0 to 20-3, transfer gates 21-0 to 21-3, and transfer gates 22-0 to 22-3 corresponding to the number of columns. In addition, although the structure of the circuit part corresponding to the column 0 among the column selection circuits 13 is demonstrated below, it is the structure similar to the column 0 also about other columns (columns 1-3).

  The transfer gate 21-0 has one end connected to the bit line / BL0 and the other end connected to the common bit line / CBL. A column selection signal SEL0 is input to the first gate terminal of the transfer gate 21-0. The column selection signal SEL0 is input to the second gate terminal of the transfer gate 21-0 via the inverter circuit 20-0. The transfer gate 21-0 becomes conductive when the column selection signal SEL0 is at a high level, and electrically connects the bit line / BL0 and the common bit line / CBL.

  The transfer gate 22-0 has one end connected to the bit line BL0 and the other end connected to the common bit line CBL. A column selection signal SEL0 is input to the first gate terminal of the transfer gate 22-0. A column selection signal SEL0 is input to the second gate terminal of the transfer gate 22-0 via the inverter circuit 20-0. The transfer gate 22-0 becomes conductive when the column selection signal SEL0 is at a high level, and electrically connects the bit line BL0 and the common bit line CBL.

  The voltage control circuit 14 includes NAND circuits 23-0 to 23-3 and NMOS transistors 24-0 to 24-3 corresponding to the number of columns. The configuration of the circuit portion corresponding to column 0 of voltage control circuit 14 will be described below, but the other columns (columns 1 to 3) have the same configuration as column 0.

  The column selection signal SEL0 is input to the first input terminal of the NAND circuit 23-0. The write signal WRT is input to the second input terminal of the NAND circuit 23-0. The output terminal of the NAND circuit 23-0 is connected to the gate terminal of the NMOS transistor 24-0. The drain terminal of the NMOS transistor 24-0 is connected to the low potential power line VSSR0. The source terminal of the NMOS transistor 24-0 is grounded.

  Next, the operation of the SRAM configured as described above will be described. First, the data read operation of the SRAM will be described.

  At the time of data reading, the write signal WRT is deactivated (low level). Accordingly, in all the columns, the output of the NAND circuit 23 becomes a high level, and the NMOS transistor 24 is turned on. As a result, all the lower power supply lines VSSR are set to the ground voltage VSS.

  Subsequently, any one of the column selection signals SEL0 to SEL3 is activated. Then, the column selection circuit 13 electrically connects the arbitrary bit line pair BL, / BL and the common bit line pair CBL, / CBL.

  Subsequently, the row decoder 12 activates the read word line RWL (high level) and deactivates the write word line WWL (low level). As a result, the read transfer gates RT1 and RT2 are turned on, and the potentials of the bit line pair BL and / BL change according to the data of the storage nodes N1 and N2.

  Specifically, when data “1” is stored in the storage node N1 (data “0” in the storage node N2), the drive transistor RD2 is turned on and the bit line BL is set to a low level. Further, the driving transistor RD1 is turned off, and the bit line / BL remains precharged to a high level.

  Similarly, when data “0” is stored in the storage node N1 (data “1” in the storage node N2), the driving transistor RD1 is turned on and the bit line / BL is set to a low level. Further, the driving transistor RD2 is turned off, and the bit line BL remains precharged to a high level. In this way, data held in the memory cell MC can be read.

  At the time of data reading, the write word line WWL connected to the transfer gates XF1 and XF2 is not activated, so that the transfer gates XF1 and XF2 remain off. For this reason, the potentials of storage nodes N1 and N2 are not affected by the activation of the word line. Therefore, the SNM of the memory cell MC is increased, and the stability of data retention can be increased.

  Next, the data write operation of the SRAM will be described. FIG. 4 is a diagram for explaining the flow of data at the time of data writing. FIG. 5 is a timing chart of the SRAM at the time of data writing. As shown in FIG. 4, a case will be described in which the column 1 including the memory cell MC1 is selected and the other columns (columns 0, 2, and 3) are not selected. FIG. 5 shows a timing chart for the selected column (column 1) and the non-selected column (column 0).

  First, the column 1 is selected by setting the column selection signal SEL1 to the high level and the column selection signals SEL0, SEL2, and SEL3 to the low level. Subsequently, the write signal WRT is set to the high level. The row decoder 12 sets the read word line RWL to high level.

  When the write signal WRT becomes high level, the output of the NAND circuit 23-1 of the selected column becomes low level. As a result, the NMOS transistor 24-1 is turned off, and the low power supply line VSSR1 is in a floating state. In the non-selected column, the output of the NAND circuit 23 is at a high level, and the low power supply lines VSSR0, VSSSR2, and VSSR3 are set to the ground voltage VSS.

  In this case, in the non-selected column, data is read out to the bit line pair BL, / BL by the reading units 15B and 15C of the memory cell MC. Specifically, since the read word line RWL is at a high level, the read transfer gates RT1 and RT2 are turned on. Since the source terminals of the drive transistors RD1 and RD2 are set to the ground voltage VSS, one of the bit line pair BL, / BL changes to low level and the other changes to high level according to the state of the storage nodes N1 and N2. It remains precharged.

  On the other hand, in the selected column, since the low-level power supply line VSSR1 is in a floating state, even if the read word line RWL becomes high level, none of the bit line pair BL1, / BL1 changes to low level. Remains precharged.

  When the column selection signal SEL1 becomes high level, the column selection circuit 13 electrically connects the bit line pair BL1, / BL1 and the common bit line pair CBL, / CBL. Therefore, write data is transferred to the bit line pair BL1, / BL1 via the common bit line pair CBL, / CBL. Here, as described above, since the low power supply line VSSR1 is in the floating state, the write data transferred to the bit line pair BL1, / BL1 does not collide with the data held in the memory cell MC1.

  Subsequently, the row decoder 12 sets the write word line WWL to a high level. Then, in the selected column, the write data transferred to the bit line pair BL1, / BL1 is written to the data holding unit 15A of the memory cell MC1.

  On the other hand, in the non-selected column, the retained data has already been read out to the bit line pair BL, / BL, and one of the bit line pair BL, / BL is at the low level. Therefore, even if the write word line WWL is set to the high level, the data holding stability of the memory cells MC0, MC2 and MC3 in the non-selected column is high and the held data is not destroyed.

  As described above in detail, in this embodiment, at the time of data writing, first, the read word line RWL is set to the high level, and the data held in the memory cells MC in the non-selected columns are read to the bit line pair BL, / BL. Subsequently, the write word line WWL is set to the high level so that the write data is written to the memory cell MC of the selected column.

  Here, in the read operation for setting the read word line RWL to the high level, 6Tr. Since the SNM is greatly improved as compared with the type SRAM cell, there is no risk of data destruction. Further, in the subsequent write operation for setting the write word line WWL to the high level, the data held in the memory cell MC of the non-selected column has already been read out to the bit line pair BL, / BL, and one of them becomes the low level. Therefore, write disturb due to activation of the write word line WWL can be prevented. As a result, it is possible to configure an SRAM with high data retention stability without causing a decrease in SNM during data writing.

  In the selected column, even when the read word line RWL is set to the high level, the read units 15B and 15C are inactivated, so that the write data can be normally written into the memory cell MC.

  At the time of data reading, the write word line WWL connected to the gate terminals of the transfer gates XF1 and XF2 is not activated. Thereby, the fall of SNM at the time of data reading can be prevented.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a block diagram showing a configuration of an SRAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory cell MC shown in FIG. 1. FIG. 2 is a circuit diagram showing configurations of a column selection circuit 13 and a voltage control circuit 14 shown in FIG. The figure explaining the flow of data at the time of data writing. The timing chart of SRAM at the time of data writing.

Explanation of symbols

  WWL: Write word line, RWL: Read word line, VSSR: Low power supply line, BL: Bit line, CBL: Common bit line, MC: Memory cell, LD1, LD2: Load PMOS transistor, DV1, DV2 ... Driving NMOS Transistors, N1, N2 ... storage nodes, INV1, INV2 ... inverter circuits, XF1, XF2 ... transfer gates, RD1, RD2 ... read drive transistors, RT1, RT2 ... read transfer gates, SEL ... column select signals, WRT ... write Signal 11, memory cell array, 12 row decoder, 13 column selection circuit, 14 voltage control circuit, 15 A data holding unit, 15 B, 15 C read unit, 20 inverter circuit, 21, 22 transfer gate, 23 ... NAND circuit, 4 ... NMOS transistor.

Claims (5)

A memory cell array having a plurality of memory cells;
First and second word lines provided in common to the plurality of memory cells;
A plurality of power supply lines provided corresponding to the plurality of memory cells;
A plurality of pairs of first and second bit lines provided corresponding to the plurality of memory cells;
A row decoder for sequentially activating the first word line and the second word line when writing data;
A control circuit that sets a power line of a selected memory cell to a floating state and sets a power line of a non-selected memory cell to a ground voltage when writing data;
Each of the plurality of memory cells includes
First and second inverter circuits;
A first storage node connected to an output terminal of the first inverter circuit and an input terminal of the second inverter circuit;
A second storage node connected to an input terminal of the first inverter circuit and an output terminal of the second inverter circuit;
A first transfer gate connected between the first storage node and a first bit line and having a gate terminal connected to the first word line;
A second transfer gate connected between the second storage node and a second bit line and having a gate terminal connected to the first word line;
A first drive transistor having a gate terminal connected to the second storage node and a source terminal connected to a power supply line;
A third transfer gate connected between the drain terminal of the first drive transistor and the first bit line and having a gate terminal connected to the second word line;
A second drive transistor having a gate terminal connected to the first storage node and a source terminal connected to the power line;
And a fourth transfer gate having a gate terminal connected between the drain terminal of the second driving transistor and the second bit line and connected to the second word line. A semiconductor memory device. The control circuit includes:
An N-type transistor provided corresponding to each memory cell and having a drain terminal connected to the power supply line and a grounded source terminal;
A first input terminal provided corresponding to each of the memory cells, to which a column selection signal is input; a second input terminal to which a write signal activated during data writing is input; and the N-type transistor The semiconductor memory device according to claim 1, further comprising: a NAND circuit having an output terminal connected to the gate terminal of the semiconductor memory device.   3. The semiconductor memory device according to claim 1, further comprising: a column selection circuit that selects any one of the plurality of pairs of first and second bit lines based on a column selection signal. .   4. The semiconductor memory device according to claim 3, further comprising first and second common bit lines connected to the column selection circuit and to which write data is transferred.   5. The semiconductor memory device according to claim 1, wherein each of the first and second inverter circuits includes a P-type transistor and an N-type transistor connected in series.

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