JP2008292423A - Semiconductor integrated circuit and operational amplifier and test method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply a sufficient stress voltage to transistors of CMOS analog circuits in a semiconductor integrated circuit in which CMOS digital circuits and the CMOS analog circuits coexist. <P>SOLUTION: In the transistor Q13 in an operational amplifier 11, a gate and a drain are connected through a switch SW 21. The switch SW 21 carries a current between an input and an output by a stress signal STRES_ENHB at "H", and interrupts the current between the input and the output by the stress signal STRES_ENHB at "L". In the interrupting state of the switch SW 21, the gates of the transistors Q13, Q14 are connected to a low potential power supply GND by a N off signal AMPNOFF at a high level from a gate potential controlling circuit 51. Since the gates are maintained at the GND potential, the transistors Q13, Q14 are turned off. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a circuit for stress testing of an analog circuit.

  In recent years, liquid crystal display devices have been increased in size and definition. Accordingly, in a semiconductor integrated circuit constituting a driving data driver that outputs display data (gradation voltage) to a display panel in a liquid crystal display device, the number of signal output terminals is increased or a multi-value voltage output from the terminals is increased. Multi-gradation is being promoted. For example, a semiconductor integrated circuit (data driver IC) for a current mainstream data driver can output a voltage of 256 gradations and has about 500 output terminals, but 1000 or more outputs. Data driver ICs having terminals are being developed. As for the gradation output voltage, a data driver IC capable of outputting 1024 gradations has been developed along with the increase in the number of colors of the liquid crystal panel.

  In addition, the data driver IC having the above-described tendency has a strong demand for miniaturization as in the case of a semiconductor integrated circuit used other than the liquid crystal display device. For this reason, miniaturization of data driver ICs has been promoted, and accordingly, defects due to gate oxide film defects such as gate oxide film breakdown of transistors constituting internal circuits have become prominent.

  Here, a conventional data driver IC will be described.

  For example, the data driver IC (liquid crystal driving semiconductor integrated circuit) described in Patent Document 1 can output m grayscale output voltages from n liquid crystal driving signal output terminals.

  In this data driver IC, when one latch circuit among a plurality of latch circuits is selected by the pointer shift register circuit according to the clock input signal, the gradation output data input from the gradation data input terminal is output. Are stored in the selected latch circuit. The latch circuit selection signal output from the pointer shift register circuit is sequentially selected from the first latch circuit to the nth latch circuit in accordance with the clock input signal input from the clock input terminal. The data stored in each latch circuit becomes digital input data of n DACs corresponding to each data.

  Each DAC circuit includes a LOAD register, n decoder circuits, m gradation voltage wirings, and m transistor switches. Here, since the digital data is input from the gradation data input terminal 3, the number thereof depends on the number of gradations.

  Based on each voltage input from a plurality of reference power supply terminals, m types of gradation voltages are generated by the reference power supply correction circuit. The gradation voltage is amplified by a plurality of gradation voltage operational amplifiers constituting the gradation voltage operational amplifier circuit, and supplied to the DAC constituting the DAC circuit via m gradation voltage wirings. The DAC selects and outputs one of m kinds of gradation voltages according to the digital data output from the latch circuit.

  FIG. 7 is a circuit diagram of a rail-to-rail operational amplifier 101 which is a general output circuit used in a data driver IC. The operational amplifier 101 is used, for example, as each operational amplifier in the DAC described in Patent Document 1.

  Patent Document 2 discloses a configuration of an operational amplifier similar to the operational amplifier 101.

  The operational amplifier 101 includes transistors Q1 to Q18 and phase compensation capacitors C1 and C2. Transistors Q1-Q3, Q7-Q10, Q15, Q17 are PMOS transistors, and transistors Q4-Q6, Q11-Q14, Q16, Q18 are NMOS transistors.

  The sources of the transistors Q2 and Q3 constituting the first differential pair 12 are connected to the high potential power supply VDD via the first current source 13 (transistor Q1). The sources of the transistors Q4 and Q5 constituting the second differential pair 14 are connected to the low potential power supply GND via the second current source 15 (transistor Q6).

  The drains of the transistors Q2 and Q3 are connected to the low potential power supply GND through a pair of transistors Q13 and Q14 constituting the first current mirror circuit 17. The drain of the transistor Q14 is connected to the gate of the transistor Q16 in the output stage.

  The drain of the transistor Q14 is connected to a fourth current source 19 (transistor Q12) and a sixth current source 21 (transistor Q10) that supply a bias current. The drain of the transistor Q13 is connected to a third current source 18 (transistor Q11) and a fifth current source 20 (transistor Q9) that supply a bias current.

  The drains of the transistors Q4 and Q5 are connected to the high potential power supply VDD via a pair of transistors Q7 and Q8 constituting the second current mirror circuit 18. A constant voltage VBP1 supplied from a bias circuit described later is applied to the gates of the transistors Q7 and Q8.

  The drain of the transistor Q8 is connected to the gate of the PMOS transistor Q15 in the output stage, the fourth current source 19 and the sixth current source 21. The source of the transistor Q15 is connected to the high potential power supply VDD, and the drain is connected to the output terminal T3 of the operational amplifier 101. The drain of the transistor Q7 is connected to the third current source 18 and the fifth current source 20.

  In the first current source 13, a constant current flows by the constant voltage VBP1, and in the second current source 15, a constant current flows by the constant voltage VBN1. When the constant voltages TVINP and VINM are the same, the currents I1 and I2 flowing through the differential pair 12 (transistors Q2 and Q3) and the currents I3 and I4 flowing through the differential pair 14 (transistors Q4 and Q5) are the same current.

  The currents I5 and I6 of the circuit formed by the second current mirror circuit 17, the first current mirror circuit 16, the third current source 18, the fourth current source 19, the fifth current source 20, and the sixth current source 21 are also shown. When the constant voltages VINP and VINM are the same, the same current is obtained.

  When the constant voltages VINP and VINM are different, the current amounts of the currents I1 and I2 and the currents I3 and I4 change, the balance of the currents I5 and I6 changes, and the output voltage OUT by the transistors Q15 and Q16 changes. Since the output voltage OUT is fed back to the inverting input terminal T2, the output voltage OUT is adjusted so that the output voltage OUT and the constant voltage VINP are equal. After adjustment of the output voltage OUT, the constant voltages VINP and VINM are equal, and the current amounts of the currents I1 and I2, the current amounts of the currents I3 and I4, and the current amounts of the currents I5 and I6 are equal.

  In FIG. 7, constant voltages VBP1, VBP0, VBN1, and VBN0 are generated by the bias circuit 102 shown in FIG.

  As shown in FIG. 8, in the bias circuit 102, the areas of the diodes D1 and D2 are designed so that the area of the diode D2 is larger (for example, D1: D2 = 1: 10). Becomes larger in the diode D1 (for example, D1: D2 = 10: 1). For this reason, a forward junction voltage difference ΔV is generated. On the other hand, the feedback circuit composed of the transistors Q20 to Q26 is self-biased so that the potentials of the nodes A and B are equal. Therefore, a voltage of ΔV is applied to both ends of the resistor R1 connected to the anode of the diode D2, and a constant current of current Ib (ΔV / R1) is generated.

  Constant voltages VBP1, VBP0, VBN1, and VBN0 are generated from the generated constant current Ib by a constant current inverter circuit including transistors Q27 to Q50.

  By the way, the data driver IC as described above has a problem that the frequency of occurrence of gate oxide film defects increases in proportion to the area of the transistor (gate area) due to fine processing. Further, in the manufacturing process of the semiconductor integrated circuit, an advanced thinning technique is used, and the gate oxide film is formed very thin with a thickness of 30 to 40 nm, and thus often includes defects. Therefore, the importance of the stress test at the time of shipping inspection of the data driver IC is increasing.

  Conventionally, when a transistor has a stuck-at fault due to the presence of a gate oxide film defect in a semiconductor integrated circuit to be measured, it has been possible to screen a defective product by a function test in a shipping inspection process of the semiconductor integrated circuit. Further, in the leak current test using the power supply terminal, it was possible to detect a semiconductor integrated circuit in which the leak current of the power supply terminal increased (see, for example, Patent Document 3).

  However, if a minute gate oxide film defect that does not cause a stuck-at fault in a transistor exists in a semiconductor integrated circuit, in many cases, it cannot be screened by a functional test. The stuck-at fault is a fault in which the logical value of the signal is fixed to a certain value. If such a transistor has a gate oxide film defect that does not cause a stuck-at fault in the semiconductor integrated circuit, it may not malfunction even in the use process by the user. However, since gate oxide film defects often deteriorate over time, they are a major cause of aging defects and defects due to deterioration over time.

  Therefore, it is important to perform a stress test as a screening test to remove defective devices including gate oxide film defects and improve the shipping quality of semiconductor integrated circuits at the shipping inspection stage of semiconductor integrated circuit manufacturers. The nature is increasing.

  Next, an outline of the stress test will be described with reference to an example disclosed in Patent Document 1.

  FIG. 9 is a schematic configuration diagram of an NMOS transistor for explaining the stress test. FIG. 10 is a schematic configuration diagram of a PMOS transistor for explaining the stress test.

  As shown in FIG. 9A, the NMOS transistor 71 having a general configuration includes a gate oxide film 77 between a bulk 76 between a source 74 and a drain 75 provided on a P-type substrate 73 and a gate 72. It is the structure which has. When a ground potential is applied to the gate 72 and the source 74 of the NMOS transistor 71, no channel structure is generated.

  However, as shown in FIG. 9B, in the NMOS transistor 71, when a power supply potential is applied as the potential of the gate 72, a channel 79 is generated in the bulk 76 between the source 74 and the drain 75. The potential of the channel 79 is equal to the potential of the source 74 if the load on the drain 75 side is in a high resistance state. When a ground potential is applied as the potential of the source 74, the potential difference between the gate 72 and the bulk 76 (channel structure portion) is equal to the power supply voltage. Therefore, a stress voltage having a potential difference equivalent to the power supply voltage can be applied to the gate oxide film 77 that is an insulator.

  Further, as shown in FIG. 9C, when a defect exists in the gate oxide film 77 of the NMOS transistor 71, the gate oxide film 77 between the gate 72 and the bulk 76 is destroyed by applying a stress voltage. Therefore, it becomes a short circuit state or a high resistance connection state. It is well known that the NMOS transistor 71 in which the gate oxide film 77 which is an insulating layer is broken and short-circuited often causes a stuck-at failure. Further, when the gate 72 and the bulk 76 are in a high resistance connection state, the leakage current of the power supply terminal increases.

  On the other hand, in the case of the PMOS transistor 81, as shown in FIG. 10, when a ground potential is applied to the gate 82, a channel 89 is generated in the bulk 86 between the source 84 and the drain 85. The potential of the channel 89 is equal to the potential of the source 84 if the load on the drain 85 side is in a high resistance state. When a power supply potential is applied as the potential of the source 84, the potential difference between the gate 82 and the bulk 86 (channel structure portion) becomes equal to the power supply potential. Therefore, a stress voltage having a potential difference equivalent to the power supply voltage can be applied to the gate oxide film 87 which is an insulator. Further, when the gate oxide film 87 is defective, a stuck-at failure occurs like the NMOS transistor 71.

The fine gate oxide film defect of the NMOS transistor that becomes prominent by the stress test can generally be detected and removed by a test that follows the stress test in the shipping test of the semiconductor integrated circuit. That is, as described above, in the function test, a stuck-at fault of a transistor can be detected. In the power terminal leakage current test, a semiconductor integrated circuit in which the power terminal leakage current is increased can be detected.
Japanese Patent Laid-Open No. 2003-130921 (published on May 8, 2003) JP 2001-326547 A (published on November 22, 2001) JP 2006-317398 A (published November 24, 2006)

  Since a CMOS digital circuit handles binary values of a power supply potential signal (“1”) and a substrate potential signal (“0”), in general, the source of a PMOS transistor is given a power supply potential and the source of an NMOS transistor. Is given a substrate potential. Further, since the gate potential is the power supply potential signal (“1”) and the substrate potential signal (“0”), the stress test as described above can be easily performed. In addition, the power supply potential and the substrate potential may not be applied as in the transfer gate, but since the signal level of the source and drain is the power supply potential or the substrate potential, the stress test as described above is performed by controlling the signal. It can be easily implemented.

  However, in a CMOS analog circuit, since a signal to be handled is an analog signal, the potentials of all the sources of the constituent transistors are not necessarily the power supply potential or the substrate potential. In addition, since the gate signal also has an analog value, it may not be set to a power supply potential signal or a substrate potential signal.

  When a stress voltage is applied to the high potential power supply VDD of the analog circuit such as the operational amplifier 101, for example, the gate signal of the first current source 13 is the constant voltage VBP1 generated by the bias circuit 102. For this reason, the gate potential of the transistor Q1 is considerably higher than the GND potential. Therefore, the stress voltage is not sufficient. The same thing occurs in other current sources, differential pairs, and current mirror circuits. Such a problem also occurs in the bias circuit 102 as well. Particularly, in the case of diode connection (configuration in which the drain and gate of the transistor are connected) like the transistor Q29 in the constant current inverter circuit described above, there is no means for applying a voltage difference between the drain and the gate.

  When a CMOS digital circuit and a CMOS analog circuit are mixed like a driver IC for a liquid crystal display device, a transistor to which a stress voltage is not sufficiently applied exists in the analog circuit portion as described above. For this reason, when a stress test is performed on such an integrated circuit, there arises a problem that a portion where sufficient screening is not performed occurs.

  The present invention has been made in view of the above problems, and an object thereof is to apply a sufficient stress voltage to a transistor of a CMOS analog circuit in a semiconductor integrated circuit in which a CMOS digital circuit and a CMOS analog circuit are mixed. There is to do.

  A semiconductor integrated circuit according to the present invention is a test circuit for forcibly fixing a gate signal applied to a MOS transistor to a power supply potential or a substrate potential in order to solve the above problems in a semiconductor integrated circuit constituted by MOS transistors. It is characterized by having.

  In the above configuration, the gate signal applied to the MOS transistor is forcibly fixed to the power supply potential or the substrate potential by the test circuit, so that a desired stress voltage can be applied to the MOS transistor. Thereby, a stress test can be easily performed in a CMOS analog circuit including a MOS transistor.

  In the semiconductor integrated circuit test method described above, a stress test is performed by operating the test circuit and setting the gate of the PMOS transistor to the substrate potential. In this test method, the gate of the NMOS transistor may be set to the substrate potential by operating the test circuit.

  In another test method for the semiconductor integrated circuit, a stress test is performed by operating the test circuit and setting the gate of the NMOS transistor to the power supply potential. In this test method, the test circuit may be operated to further set the gate of the PMOS transistor to the power supply potential.

  Another semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit including a MOS transistor in which a source or drain and a gate are connected. In order to solve the above-mentioned problem, the connection between the source or drain and the gate is selected. And a test circuit for fixing the gate potential to the power supply potential or the substrate potential when the connection between the source or drain and the gate is released by the connection release circuit. It is a feature.

  With the above configuration, when performing a stress test, in a so-called diode-connected MOS transistor in which the source or drain and the gate are connected, the connection between the source or drain and the gate is released by the connection release circuit. Then, since the gate potential is fixed to the power supply potential or the substrate potential by the test circuit, a desired stress voltage can be applied to the diode-connected MOS transistor. Thus, a stress test can be easily performed in a CMOS analog circuit including a diode-connected MOS transistor.

  The semiconductor integrated circuit test method is characterized in that a stress test is performed by operating the test circuit and setting a gate of a PMOS transistor to the substrate potential. In this test method, the gate of the NMOS transistor may be set to the substrate potential by operating the test circuit.

  Another test method for the semiconductor integrated circuit is characterized in that a stress test is performed by operating the test circuit and setting the gate of an NMOS transistor to the power supply potential. In this test method, the test circuit may be operated to further set the gate of the PMOS transistor to the power supply potential.

  In order to solve the above problems, an operational amplifier according to the present invention includes a first test circuit capable of fixing a bias potential to a power supply potential or a substrate potential, and a gate potential of a current mirror circuit. A second test circuit that can be fixed to the power supply potential or the substrate potential and a third test circuit that can fix the non-inverting input terminal to the power supply potential or the substrate potential are provided.

  In the above configuration, the gate potential of the MOS transistor to which the bias potential is applied to the gate is fixed to the power supply potential or the substrate potential by the first test circuit. Further, the gate potential of the transistor in the current mirror circuit is fixed to the power supply potential or the substrate potential by the second test circuit. Further, the third test circuit fixes the gate potential of the transistor whose gate is connected to the non-inverting input terminal to the power supply potential or the substrate potential. By such a gate potential fixing operation of the first to third test circuits, the gate potential of the output buffer is fixed, and the output terminal and the inverting input terminal are fixed to the power supply potential or the substrate potential. Thereby, a stress test can be easily performed in an operational amplifier including a MOS transistor.

  The operational amplifier fixes one terminal of the phase compensation capacitor to the power supply potential or the substrate potential when operating the phase compensation capacitor provided in the output stage and the first to third test circuits. It is preferable to further include a potential fixing circuit.

  When one terminal of the phase compensation capacitor is open, an abnormal voltage may occur. For this reason, when the stress test is performed by operating the first to third test circuits, the potential of the phase compensation capacitor is fixed to the power supply potential or the substrate potential, thereby preventing the occurrence of an abnormal voltage. .

  In the operational amplifier test method described above, the first to third test circuits are operated to set a gate of a PMOS transistor other than the PMOS transistor constituting the output buffer to the substrate potential, thereby performing a stress test.

  In another test method of the operational amplifier, a stress test is performed by operating the first to third test circuits and setting the gates of NMOS transistors other than the NMOS transistors constituting the output buffer to the power supply potential. I do.

  As described above, the semiconductor integrated circuit according to the present invention includes the test circuit for forcibly fixing the gate signal applied to the MOS transistor to the power supply potential or the substrate potential. Therefore, in the CMOS analog circuit including the MOS transistor, A stress test can be easily performed.

  As described above, another semiconductor integrated circuit according to the present invention includes a connection release circuit that selectively releases the connection between the source or drain and the gate, and the connection between the source or drain and the gate is reduced by the connection release circuit. Since it is provided with a test circuit that fixes the gate potential to the power supply potential or the substrate potential when released, a stress test can be easily performed in a CMOS analog circuit including a diode-connected MOS transistor.

  In order to solve the above problems, an operational amplifier according to the present invention includes a first test circuit capable of fixing a bias potential to a power supply potential or a substrate potential, and a gate potential of a current mirror circuit. Since the second test circuit that can be fixed to the power supply potential or the substrate potential and the third test circuit that can fix the non-inverting input terminal to the power supply potential or the substrate potential, a stress test is performed in the operational amplifier including the MOS transistor. It can be easily implemented.

  As a result, even in a semiconductor integrated circuit in which a CMOS digital circuit and a CMOS analog circuit are mixed, a stress test can be performed on almost all transistors. Therefore, it is possible to improve the detection accuracy of a defective device including a gate oxide film defect.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

  FIG. 1 is a circuit diagram showing a configuration of an operational amplifier 11 corresponding to a stress test. FIG. 2 shows a circuit diagram of a bias circuit 31 corresponding to a stress test for generating a bias voltage to be applied to the operational amplifier 11.

  First, the bias circuit 31 will be described.

  As shown in FIG. 2, the bias circuit 31 is a circuit that generates constant voltages (bias voltages) VBP1, VBP0, VBN1, and VBN0.

  Similar to the bias circuit 102 described above, the bias circuit 31 includes transistors Q21 to Q50, diodes D1 and D2, and a resistor R1. The bias circuit 31 further includes switches SW6 to SW20 and gate potential control circuits 51 and 52 that are not included in the bias circuit 102. Transistors Q21, Q22, Q29, Q30, Q33, Q34, Q37, Q38, Q41, Q42, Q45, Q46, Q49, and Q50 are NMOS transistors. Transistors Q23 to Q28, Q31, Q32, Q35, Q36, Q39, Q40, Q43, Q44, Q47, and Q48 are PMOS transistors.

  The gates of the transistors Q21 and Q22 are connected to each other. Transistors Q23, Q24, Q28 gates, transistors Q25-Q27 gates, transistors Q29, Q33, Q37, Q41 gates, transistors Q30, Q34, Q38, Q42 gates, transistors Q39, Q43, Q47 gates, and transistor Q40 , Q44, and Q48 are also connected to each other.

  The gate and drain of the transistor Q21 are connected via a switch SW14. The gates and drains of the transistors Q24, Q26, Q29 to Q32, Q35, Q36, Q39, Q40, Q45, Q46, Q49, Q50 are connected through switches SW7, SW6, SW15, SW16, SW8 to SW20, respectively. ing. The switches SW6 to SW20 will be described in detail later.

  Transistors Q21, Q23, Q25 are connected in series, and transistors Q22, Q24, Q26 are also connected in series. The source of the transistor Q20 is connected to the anode of the diode D1. The source of the transistor Q21 is connected to the anode of the diode D2 via the resistor R1. The sources of the transistors Q25 and Q26 are connected to the high potential power supply VDD.

  The transistors Q27 to Q30 are connected in series between the high potential power supply VDD and the low potential power supply GND. Similarly, the transistors Q31 to Q34, the transistors Q35 to Q38, the transistors Q39 to Q42, the transistors Q43 to Q46, and the transistors Q47 to Q50 are connected in series between the high potential power supply VDD and the low potential power supply GND, respectively. The series circuits formed by transistors Q27 to Q30, transistors Q31 to Q34, transistors Q35 to Q38, transistors Q39 to Q42, transistors Q43 to Q46, and transistors Q47 to Q50 constitute a constant current inverter.

  The diodes D1 and D2 are diodes and are designed so that the area ratio of D1 and D2 is, for example, 1:10. The cathodes of the diodes D1 and D2 are connected to the low potential power supply GND. The areas of the diodes D1 and D2 are designed so that the diode D2 is larger than the diode D2 (for example, 1:10). For this reason, the forward current density of the diode D1 is larger than that of the diode D2 (for example, 10: 1). For this reason, a forward junction voltage difference ΔV is generated. On the other hand, since the feedback circuit composed of the transistors Q21 to Q26 is self-biased so that the potentials of the node A and the node B are equal, a voltage of ΔV is applied to both ends of the resistor R1, and the current Ib (ΔV / R1) A constant current is generated.

  The generated constant current Ib is used to generate constant voltages VBP1, VBP0, VBN1, and VBN0 by a constant current inverter circuit including transistors Q27 to Q50.

  The bias circuit 31 is configured such that switches SW6 to SW20 are provided in a portion where the gate potential cannot be controlled in the bias circuit 102 (see FIG. 10) and can be controlled by a test signal.

  The switches SW6 to SW20 are controlled to be opened and closed by a stress signal STRS_ENHB. The stress signal STRS_ENHB becomes “L” when the stress test is performed, and becomes “H” when the stress test is not performed. The stress signal STRES_ENHB is an inverted signal of the stress signal STRES_ENH, but is referred to as a “stress signal” here for convenience. Therefore, the stress signal STRES_ENH becomes “H” when the stress test is performed, and becomes “L” when the stress test is not performed. These stress signals STRS_ENHB and STRS_ENH are supplied from an external tester (not shown).

  Specifically, the switches SW6 to SW20 are switches for controlling the state between X and Y by the control signal G as shown in FIG. In this switch, as shown in Table 1, when the control signal G signal is “H”, X and Y have the same potential (conduction), and when the control signal G signal is “L”, the switch is in a high impedance state. (Non-conduction). As a result, the switches SW6 to SW20 enter a high impedance state (Z) when the stress signal STRS_ENHB as the control signal G is “L”, and block the input of the original signal to the gate.

  The gates of the transistors Q21 to Q50 are supplied with a VDD potential (potential of the high potential power supply VDD) and a GND potential (potential of the low potential power supply GND) by the gate potential control circuits 51 and 52 separately from the gate signal given originally. Either one is given.

  The gate potential control circuit 51 selects and connects either the high potential power supply VDD or the low potential power supply GND to the gate of the NMOS transistor. Specifically, when the NMOS transistor is turned on, the gate potential control circuit 51 connects the high potential power supply VDD to the gate by the “H” N on signal AMPNON, and the low potential power supply by the “L” N off signal AMPNOFF. Block GND from the gate. Further, when the NMOS transistor is turned off, the gate potential control circuit 51 cuts off the high potential power supply VDD from the gate by the “L” N ON signal AMPPN, and gates the low potential power supply GND by the “H” N OFF signal AMPNOFF. Connect to.

  The gate potential control circuit 52 selects and connects either the high potential power supply VDD or the low potential power supply GND to the gate of the PMOS transistor. Specifically, when turning off the PMOS transistor, the gate potential control circuit 52 connects the high potential power supply VDD to the gate by the “H” P-off signal AMPPPOFF and the low potential power supply by the “L” P-on signal AMPPON. Block GND from the gate. When the PMOS transistor is turned on, the gate potential control circuit 52 shuts off the high potential power supply VDD from the gate by the “L” P-off signal AMPPPOFF and gates the low potential power supply GND by the “H” P-on signal AMPPON. Connect to.

  The N-on signal AMPNON, the N-off signal AMPNOFF, the P-off signal AMPPPOFF, and the P-on signal AMPPON are also supplied from an external tester, like the stress signals STRS_ENHB and STRS_ENH.

  By setting the state of the bias circuit 31 using the stress signal STRS_ENH, the P-off signal AMPPPOFF, the P-on signal AMPPON, the N-off signal AMPPNOFF, and the N-on signal AMPPN, conventionally, a sufficient stress voltage has not been provided. A sufficient stress voltage can be applied to the transistor.

  Here, Table 2 shows the state of the stress signal STRS_ENH, the P-off signal AMPPPOFF, the P-on signal AMPPON, the N-off signal AMPPNOFF, and the N-on signal AMPPON.

  1) is a normal use state, 2) and 3) are stress voltage application states.

  By using the above switch configuration and adding a gate control signal that turns off the transistors Q15 and Q16 of the output stage, which will be described later, of the operational amplifier 11, all the transistors in the state 4) can be set to the off state. Become. This state is a mode in which off-leakage currents of all transistors can be measured, and defects can be found by measuring the leakage currents.

  Here, the operation of the bias circuit 31 when the stress voltage is applied will be described.

  First, from the normal state of 1) in Table 2, the stress signal STRS_ENH, the P-on signal AMPPON, and the N-off signal AMPNOFF are set to “H”, and the PMOS is turned on in 2). Then, since the gates of the PMOS transistors are all in the GND state, the source of the PMOS transistor connected to the gate potential control circuit 52 is given the potential of the high potential power supply VDD, and a stress voltage can be applied to the gate of the PMOS transistor. . At this time, since all the NMOS transistors are turned off, no through current flows between the high potential power supply VDD and the low potential power supply GND.

  Next, the stress signal STRS_ENH is set to “H”, the P-on signal AMPPON is set to “L”, the P-off signal AMPPOFF is set to “H”, the N-on signal AMPPN is set to “H”, and the N-off signal AMPPNOFF is set to “L”. In Table 2, 3) NMOS is turned on. Since the gates of the NMOS transistors are all at the VDD potential (power supply potential), the potential of the constant potential power supply GND (GND potential) that is the substrate potential is applied to the source of the NMOS transistor, and a stress voltage is applied to the gate of the NMOS transistor. it can. At this time, since all the PMOS transistors are turned off, no through current flows between the high potential power supply VDD and the low potential power supply GND.

  Next, the operational amplifier 11 will be described.

  As shown in FIG. 1, the operational amplifier 11 is a rail-to-rail operational amplifier circuit, similar to the operational amplifier 101 described above, and includes transistors Q1 to Q18 and phase compensation capacitance capacitors C1 and C2. . The operational amplifier 11 further includes gate potential control circuits 51 and 52 and switches SW21, SW100, and SW101.

  A constant voltage VINP as a bias voltage is applied to the non-inverting input terminal T1 of the operational amplifier 11, and a constant voltage VINM as a bias voltage is applied to the inverting input terminal T2. The non-inverting input terminal T1 is connected to the gates of the transistors Q2 and Q4, and the inverting input terminal T2 is connected to the gates of the transistors Q3 and Q5. Transistors Q2 and Q3, which are PMOS transistors, constitute a first differential pair 12. Transistors Q4 and Q5, which are NMOS transistors, constitute a second differential pair 14.

  The sources of the transistors Q2 and Q3 are both connected to the high potential power supply VDD via the transistor Q1 (PMOS transistor). The transistor Q1 constitutes a first current source 13 that supplies a bias current to the transistors Q2 and Q3. The sources of the transistors Q4 and Q5 are both connected to the low potential power supply GND through the transistor Q6 (NMOS transistor). The transistor Q6 constitutes a second current source 15 that supplies a bias current to the transistors Q4 and Q5.

  The drains of the transistors Q2 and Q3 are connected to the low potential power supply GND through transistors Q13 and Q14 (NMOS transistors), respectively. The transistors Q13 and Q14 form a pair to form the first current mirror circuit 16, and their gates are connected to each other. The connection point is connected to the drain of the transistor Q13 via the switch SW21.

  The drain of the transistor Q14 is connected to the gate of the transistor Q16 (NMOS transistor) in the output stage. The source of the transistor Q16 is connected to the low potential power supply GND, and the drain of the transistor Q16 is connected to the output terminal T3 of the operational amplifier 11. The output voltage OUT is output from the output terminal T3. The drain of the transistor Q14 is connected to the sources of the transistors Q12 and Q18 (NMOS transistors) and the drain of the transistor Q10 (PMOS transistor). The transistor Q12 constitutes a fourth current source 19 that supplies a bias current, and the transistor Q10 constitutes a sixth current source 21 that supplies a bias current. The drain of the transistor Q18 is connected to the output terminal T3 through the phase compensation capacitor C2, and is connected to the low potential power supply GND through the switch SW101.

  On the other hand, the drain of the transistor Q13 is connected to the source of the transistor Q11 (NMOS transistor) and the drain of the transistor Q9 (PMOS transistor). The transistor Q11 constitutes a third current source 18 that supplies a bias current, and the transistor Q9 constitutes a fifth current source 20 that supplies a bias current.

  The drains of the transistors Q4 and Q5 are connected to the high potential power supply VDD via transistors Q7 and Q8 (PMOS transistors), respectively. Transistors Q7 and Q8 form a pair to form a second current mirror circuit 17, and their gates are connected to each other. A constant voltage VBP1 from the bias circuit 102 is applied to the connection point.

  The drain of the transistor Q8 is connected to the gate of the transistor Q15 (PMOS transistor) in the output stage. The source of the transistor Q15 is connected to the high potential power supply VDD, and the drain of the transistor Q15 is connected to the output terminal T3.

  The drain of the transistor Q8 is connected to the drain of the transistor Q12 and the sources of the transistors Q10 and Q17. The drain of the transistor Q17 (PMOS transistor) is connected to the output terminal T3 via the phase compensation capacitor C1 and to the high potential power supply VDD via the switch SW100. The drain of the transistor Q7 is connected to the drain of the transistor Q11 and the source of the transistor Q9.

  A constant voltage VBP0 is applied to the gates of the transistors Q9, Q10, and Q17, and a constant voltage VBN0 is applied to the gates of the transistors Q11, Q12, and Q18.

  The first bias current source 13 causes a current to flow when a constant voltage VBP1 is applied, and the second bias current source 15 causes a constant current to flow when a constant voltage VBN1 is applied. The currents I1 and I2 flowing through the transistors Q2 and Q3 and the currents I3 and I4 flowing through the transistors Q4 and Q5, respectively, have the same value when the constant voltages VINP and VINM are the same.

  Currents I5 and I6 flowing through a circuit composed of the second current mirror circuit 17, the first current mirror circuit 16, the third current source 18, the fourth current source 19, the fifth current source 20, and the sixth current source 21 are also shown. Further, when the constant voltages VINP and VINM are the same, the same value is obtained.

  When the constant voltages VINP and VINM are different, the current amounts of the currents I1 and I2 and the currents I3 and I4 change, the balance of the currents I5 and I6 changes, and the output voltage OUT by the transistors Q15 and Q16 changes. Since the output voltage OUT is fed back to the inverting input terminal T2, the output voltage OUT is adjusted so that the output voltage OUT, that is, the constant voltage VINM and the constant voltage VINP are equal. After adjustment of the output voltage OUT, the constant voltage VINP and the constant voltage VINM are equal, and the current amounts of the currents I1, I2, I3, I4, and I5, I6 are equalized again.

  The operational amplifier 11 is provided with a switch SW21 in a portion where the gate potential cannot be controlled in the operational amplifier 101 (see FIG. 7). Similarly to the switches SW6 to SW20 described above, the switch SW21 includes the switches shown in FIG.

  Thereby, the gate potential can be controlled by the test signal. Specifically, the first current mirror circuit 16 is provided with the switch SW21 for turning on / off the gate signal as described above. The gate potential control circuit 51 is also connected to the gates of the transistors Q13 and Q14. The above-described gate potential control circuit 52 is connected to the non-inverting input terminal T1.

  An abnormal voltage may occur when one terminal of the phase compensation capacitors C1 and C2 is opened. For this reason, switches SW100 and SW101 that are turned on when the stress signal STRS_ENH becomes “H” when performing a stress test or the like are provided. As a result, the potential of the phase compensation capacitor C1 is fixed to the potential of the high potential power supply VDD, while the potential of the phase compensation capacitor C2 is fixed to the potential of the low potential power supply GND, thereby preventing the occurrence of abnormal voltage. be able to.

  Here, the operation of applying a stress voltage in the operational amplifier 11 will be described.

  First, from the normal state of 1) in Table 2, only the stress signal STRS_ENH, the P-on signal AMPPON, and the N-off signal AMPNOFF are changed to “H”, and 2) in FIG. In this state, since the switch SW21 is cut off by the stress signal STRES_ENB which is “L”, the gates of the transistors Q13 and Q14 are connected to the low potential power supply GND by the N-off signal AMPNOFF which is “H”. . As a result, the transistors Q13 and Q14 are turned off because the gates are fixed at the GND potential.

  In the non-inverting input terminal T1, the gates of the transistors Q2 and Q4 are set to the GND potential by the P-on signal AMPPON which is “H”. Thereby, the transistor Q2 is turned on and the transistor Q4 is turned off. Since the terminals to which the constant voltages VBP1 and VBP0 are applied are set to the GND potential by the bias circuit 31, the transistors Q1, Q7 to Q10, Q17 are turned on. The terminals to which the constant voltages VBN1 and VBN0 are applied are also set at the GND potential by the bias circuit 31, so that the transistors Q6, Q11, Q12, and Q18 are turned off.

  When the transistors Q8 and Q10 are turned on, the gate levels of the transistors Q15 and Q16 as output buffers become the VDD potential, so that the transistor Q15 is turned off and the transistor Q16 is turned on. As a result, the inverting input terminal T2 to which the output voltage OUT is fed back becomes the GND potential, so that the gates of the transistors Q3 and Q5 have the same potential. Therefore, transistor Q3 is turned on and transistor Q5 is turned off.

  When the switches SW100 and SW101 are turned on by the stress signal STRES_ENH that is “H”, the potentials of the phase compensation capacitors C1 and C2 are fixed to the VDD potential and the GND potential, respectively.

  Since one end of the phase compensation capacitor C1 is at the VDD potential while the transistors Q8 and Q17 are on, it is not necessary to fix the potential of the phase compensation capacitor C1 to the VDD potential. However, if the potential of the phase compensation capacitor C1 is not fixed to the VDD potential when the transistors Q8 and Q17 are turned off, the potential increases. In order to avoid this inconvenience, the potential of the phase compensation capacitor C1 may be fixed to the VDD potential when the transistors Q8 and Q17 are turned off. However, here, the VDD potential is always fixed to the potential of the phase compensation capacitor C1 when the stress voltage is applied.

  As described above, the PMOS transistors other than the transistor Q15 (PMOS transistor) of the operational amplifier 11 and the transistor Q16 (NMOS transistor) are turned on. Thereby, a stress voltage can be applied to the PMOS transistor other than the transistor Q15 and the gate of the transistor Q16.

  Next, the stress signal STRS_ENH is set to “H”, the P-on signal AMPPON is set to “L”, the P-off signal AMPPOFF is set to “H”, the N-on signal AMPPN is set to “H”, and the N-off signal AMPNOFF is set to “L”. 3) The NMOS is turned on. In this state, the switch SW21 is cut off by the stress signal STRES_ENB which is “L”, so that the gates of the transistors Q13 and Q14 are connected to the high potential power supply VDD by the N-on signal AMPON which is “H”. . As a result, the transistors Q13 and Q14 are turned on because the gate is fixed at the VDD potential.

  In the non-inverting input terminal T1, the gates of the transistors Q2 and Q4 are set to the VDD potential by the P-off signal AMPPOFF which is “H”. Thereby, the transistor Q2 is turned off and the transistor Q4 is turned on. Further, since the terminals to which the constant voltages VBP1 and VBP0 are applied are set to the VDD potential by the bias circuit 31, the transistors Q1, Q7 to Q10, Q17 are turned off. The terminals to which the constant voltages VBN1 and VBN0 are applied are also set to the VDD potential by the bias circuit 31 as described above, so that the transistors Q6, Q11, Q12, and Q18 are turned on.

  When the transistors Q12 and Q14 are turned on, the gate levels of the transistors Q15 and Q16 as output buffers become the GND potential, so that the transistor Q15 is turned on and the transistor Q16 is turned off. As a result, the inverting input terminal T2 to which the output voltage OUT is fed back becomes the VDD potential, so that the gates of the transistors Q3 and Q5 have the same potential. Therefore, transistor Q3 is turned off and transistor Q5 is turned on.

  When the switches SW100 and SW101 are turned on by the stress signal STRES_ENH that is “H”, the potentials of the phase compensation capacitors C1 and C2 are fixed to the VDD potential and the GND potential, respectively.

  As described above, the NMOS transistors other than the transistor Q16 (NMOS transistor) of the operational amplifier 11 and the transistor Q15 (PMOS transistor) are turned on. Thereby, a stress voltage can be applied to the NMOS transistor other than the transistor Q16 and the gate of the transistor Q15.

  FIG. 4 is a block diagram showing the configuration of the data driver IC 1 to which the operational amplifier 11 and the bias circuit 31 are applied. Next, the data driver IC1 will be described with reference to FIG.

  As shown in FIG. 4, the data driver IC 1 can output m-tone output voltages from n liquid crystal driving signal output terminals.

  The data driver IC 1 includes an external clock input terminal 2, a gradation data input terminal 3 having a plurality of signal input terminals, a LOAD signal input terminal 4, V 0 terminals 5, V 1 terminals 6, V 2 terminals 7, which are reference power supply terminals. V3 terminals 8 and V4 terminals 9 and an operational amplifier power supply control terminal 10 are provided. The data driver IC 1 includes n liquid crystal driving signal output terminals (hereinafter simply referred to as “signal output terminals”) 26-1 to 26 -n. The liquid crystal driving signal output terminals 26-1 to 26-n are collectively referred to as a signal output terminal 26. In addition, the data driver IC 1 includes a reference power correction circuit 21, a gradation voltage operational amplifier circuit 22, a pointer shift register circuit 23, a latch circuit unit 24, a D / A converter (Digital Analog Converter, hereinafter referred to as “DAC”). ) Circuit 25 is provided.

  The gradation voltage operational amplifier circuit 22 includes m gradation voltage operational amplifiers 22-1 to 22-m. The pointer shift register circuit 23 includes n shift registers 23-1 to 23-n. Further, the latch circuit unit 24 is configured by n latch circuits 24-1 to 24-n. In addition, the DAC circuit 25 includes DACs 25-1 to 25-n.

  The pointer shift register circuit 23 selects one of the latch circuits 24-1 to 24-n according to the clock input signal input from the clock input terminal 2. Then, the gradation output data input from the gradation data input terminal 3 is stored in the selected latch circuit 24.

  The latch circuit selection signal output from the pointer shift register circuit 23 is sent from the first latch circuit 24-1 to the n-th latch circuit 24-n by the clock input signal input from the clock input terminal 2. Select sequentially. Therefore, when n clocks are input, data can be stored in all the latch circuits 24-1 to 24-n. The latch circuits 24-1 to 24-n can store different values of data. The data stored in the latch circuits 24-1 to 24-n becomes digital input data of the corresponding n DACs 25-1 to 25-n.

Each of the DAC circuits 25-1 to 25-n includes a LOAD register, n decoder circuits, m gradation voltage wirings, and m transistor switches, as will be described later. Here, since the digital data is input from the gradation data input terminal 3, the number thereof depends on the number of gradations. For example, in a data driver IC capable of outputting a gradation output voltage of 64 gradations, since the number of gradations is 64 = ²⁶ , 6 gradation data input terminals 3 are prepared. Each latch circuit and each LOAD register has the same number of bit configurations as the number of gradation data input terminals.

  The voltage inputted from the V0 terminal 5 to the V4 terminal 9 (reference power supply terminal) is converted into m kinds of gradation voltage values by the reference power supply correction circuit 21 and outputted. The voltage output from the reference power correction circuit 21 is amplified by the gradation voltage operational amplifiers 22-1 to 22-m of the gradation voltage operational amplifier circuit 22, and m gradation voltage wirings 47-1. Are supplied to the DACs 25-1 to 25-n constituting the DAC circuit 25 through .about.47-m. The DACs 25-1 to 25-n select and output one of m kinds of gradation voltage values according to the digital data output from the latch circuits 24-1 to 24-n, respectively.

  The gradation voltage operational amplifier circuit 22 can be set to a high resistance output state in accordance with an input signal from the operational amplifier power supply control terminal 10, and each gradation voltage operational amplifier 22-of the gradation voltage operational amplifier circuit 22. 1 to 22-n can be set to a low power consumption state. In the data driver IC 1, one DAC is connected to one signal output terminal 26.

  FIG. 5 is an example of the gradation voltage value of the data driver IC. As shown in FIG. 5, m grayscale output voltages having m different voltage values are output from the DACs 25-1 to 25-n. The m gradation output voltages Vg1 to Vgm are V0 when the maximum input voltage input from the V0 terminal is V0 and the minimum input voltage input from the V4 terminal is V4 among the voltages input to the V0 terminal 5 to the V4 terminal 9. (V0−V4) is a voltage divided by m.

  Next, the configuration of the DAC circuit included in the data driver IC 1 will be described. FIG. 6 is a configuration diagram of the DAC and peripheral circuits of the data driver IC1. FIG. 6 shows one DAC 25-1 of the DAC circuit and peripheral circuits when the data driver IC1 is m = 64.

  As described above, since the data driver IC 1 can output the gradation output voltage of 64 gradations, the data driver IC 1 includes the six gradation data input terminals 3 as described above. The DAC 25-1a includes a LOAD register circuit 41, a first inverter circuit 42, an AND circuit 43, a second inverter circuit 44, a switch circuit 45, an operational amplifier 46, and 64 gradation voltage wirings 47-1 to 47-64. I have. The LOAD register circuit 41 includes six registers 41-1 to 41-6. The first inverter circuit 42 includes six inverters 42-1 to 42-6. The AND circuit 43 includes 64 6-input AND gates 43-1 to 43-64. The second inverter circuit 44 includes 64 inverters 44-1 to 44-64. The switch circuit 45 includes 64 transistor switches 45-1 to 45-64.

  Each of the transistor switches 45-1 to 45-64 includes one PMOS transistor and one NMOS transistor. The gradation voltage wirings 47-1 to 47-64 are PMOS transistors which are output terminals of the gradation voltage operational amplifiers 22-1 to 22-64 and one terminals of the transistor switches 45-1 to 45-64. And connected to the sources of the NMOS transistors, respectively. Further, the drains of the PMOS transistor and the NMOS transistor, which are the other terminals of the transistor switches 45-1 to 45-64, are connected to one input terminal of the operational amplifier 46.

  The latch circuit selection signal is output from the shift register 23-1, stored in the latch circuit 24-1, and further output to the LOAD register circuit 41. Then, one value of the gradation voltage amplified by the gradation voltage operational amplifier circuit 22 composed of 64 gradation voltage operational amplifiers 22-1 to 22-64 is loaded into the LOAD register circuit 41. Are selected by the transistor switches 45-1 to 45-64. Further, the selected gradation voltage is amplified by the operational amplifier 46, and the gradation voltage is output as a liquid crystal panel driving signal from the signal output terminal 26-1.

  In the data driver IC, the operational amplifier 11 is used as the gradation voltage operational amplifiers 22-1 to 22-m and the operational amplifier 46, and the bias circuit 31 is used to supply a bias voltage.

  In the present embodiment, the data driver IC 1 has been described as an example of an integrated circuit in which the operational amplifier 11 and the bias circuit 31 are incorporated. However, as a matter of course, the integrated circuit may be another IC.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  As described above, in the semiconductor integrated circuit of the present invention, the stress test can be performed on all the transistors, and the detection accuracy of a defective device including a gate oxide film defect is improved. It can be suitably used for testing mixed semiconductor integrated circuits.

It is a circuit diagram which shows the structure of the operational amplifier which shows one Embodiment of this invention. It is a circuit diagram which shows the structure of the bias circuit which produces | generates the bias voltage given to the said operational amplifier. It is a figure which shows the structure of the switch used in the said operational amplifier and the said bias circuit. It is a block diagram which shows the structure of the data driver IC in which the said operational amplifier and the said bias circuit are incorporated. It is a graph which shows the display output voltage value which the said data driver IC outputs. It is a circuit diagram which shows the structure of DAC provided in the said data driver IC. It is a circuit diagram which shows the structure of the conventional operational amplifier. FIG. 8 is a circuit diagram illustrating a configuration of a bias circuit that generates a bias voltage to be applied to the operational amplifier of FIG. 7. (A) It is sectional drawing which shows the normal state of an NMOS transistor, (c) And (b) is sectional drawing which shows the state which performed the conventional stress test in an NMOS transistor. It is sectional drawing which shows the state which performed the conventional stress test in the PMOS transistor.

Explanation of symbols

1 Data driver IC
11 operational amplifier 22-1 to 22-m operational amplifier 31 bias circuit 51, 52 gate potential control circuit (test circuit, first to third test circuit)
Q1 to Q18 Transistors Q15 and Q16 Transistors (output buffer)
Q21 to Q50 Transistors SW6 to SW21 Switch (connection release circuit)
T1 Non-inverting input terminal T2 Inverting input terminal T3 Output terminal

Claims (14)

In a semiconductor integrated circuit composed of MOS transistors,
A semiconductor integrated circuit comprising a test circuit for forcibly fixing a gate signal applied to the MOS transistor to a power supply potential or a substrate potential. In a semiconductor integrated circuit including a MOS transistor in which a source or drain and a gate are connected,
A disconnect circuit that selectively disconnects the source or drain and the gate is provided.
A semiconductor integrated circuit, comprising: a test circuit that fixes a gate potential to a power supply potential or a substrate potential when the connection between the source or drain and the gate is released by the connection release circuit. In an operational amplifier composed of MOS transistors,
A first test circuit capable of fixing a bias potential to a power supply potential or a substrate potential;
A second test circuit capable of fixing the gate potential of the current mirror circuit to a power supply potential or a substrate potential;
An operational amplifier, comprising: a third test circuit capable of fixing a non-inverting input terminal to a power supply potential or a substrate potential. A phase compensation capacitor provided in the output stage;
4. A potential fixing circuit for fixing one terminal of the phase compensation capacitor to the power supply potential or the substrate potential when the first to third test circuits are operated. The operational amplifier described in 1.   2. The semiconductor integrated circuit test method according to claim 1, wherein a stress test is performed by operating the test circuit and setting a gate of a PMOS transistor to the substrate potential.   6. The method for testing a semiconductor integrated circuit according to claim 5, wherein the test circuit is operated to further set the gate of the NMOS transistor to the substrate potential.   2. The method of testing a semiconductor integrated circuit according to claim 1, wherein a stress test is performed by operating the test circuit and setting a gate of an NMOS transistor to the power supply potential.   8. The method of testing a semiconductor integrated circuit according to claim 7, wherein the test circuit is operated to further set the gate of a PMOS transistor at the power supply potential.   3. The semiconductor integrated circuit test method according to claim 2, wherein a stress test is performed by operating the test circuit and setting a gate of a PMOS transistor to the substrate potential.   10. The method for testing a semiconductor integrated circuit according to claim 9, wherein the test circuit is operated to further set the gate of an NMOS transistor at the substrate potential.   3. The semiconductor integrated circuit test method according to claim 2, wherein a stress test is performed by operating the test circuit and setting a gate of an NMOS transistor to the power supply potential.   12. The method of testing a semiconductor integrated circuit according to claim 11, wherein the test circuit is operated to further set the gate of a PMOS transistor at the power supply potential.   4. The operational amplifier according to claim 3, wherein the stress test is performed by operating the first to third test circuits and setting a gate of a PMOS transistor other than the PMOS transistor constituting the output buffer to the substrate potential. Test method of the characteristic operational amplifier.   4. The operational amplifier according to claim 3, wherein a stress test is performed by operating the first to third test circuits and setting a gate of an NMOS transistor other than an NMOS transistor constituting an output buffer to the power supply potential. Test method of operational amplifier characterized by

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