JP2008288888A - Pulse waveform generator and transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a plurality of pulse waveforms corresponding to a plurality of frequency bands with low power consumption. <P>SOLUTION: This pulse waveform generator is provided with a delay circuit 103 in which a plurality of delaying devices that can be adjusted to a prescribed delay time are connected in series by making the oscillation frequency of a VCO in a PLL circuit 102 a prescribed value and which outputs a plurality of delay signals DLn obtained by sequentially delaying digital signals TQ outputted by the respective delaying devices at the prescribed delay time by inverting the digital signals TQ to be inputted to the delaying device on the first stage at timing when a pulse waveform is desired to be generated, a square wave generation circuit 104 for generating a square wave having the width of a prescribed time interval by sequentially combining two delay signals outputted from the delaying device to be a prescribed time interval, and an output voltage selection circuit 105 for selecting output voltage by the square wave, and outputs a plurality of specific waveforms by changing the prescribed delay time in the delaying device and selection contents of the output voltage in the output voltage selection circuit 105. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pulse waveform generator for generating an impulse waveform and an ultra-wide band transmitter using the same.

  Various technologies related to UWB-IR (Ultra Wide Band-Impulse Radio) methods have been proposed (see, for example, Patent Document 1).

In Patent Document 1, by using a delay circuit, a square wave pulse corresponding to the delay time difference of one stage of the delay circuit is generated, and an impulse train having a pulse width of this square wave and a predetermined amplitude is output. A pulse waveform generation circuit for generating a pulse having a predetermined envelope shape is disclosed.
JP 2006-229677 A

  With regard to wireless communication, due to the revision of laws and regulations in each country, a communication band has been released to UWB (Ultra Wide Band) communication that uses a wide band with a low power density, and is attracting attention.

  Several communication methods have been proposed to realize UWB communication. Among them, the impulse UWB method has a simple circuit configuration and low power consumption, so that it can be applied to communication with a small device driven by a battery. It is being considered.

  The impulse UWB system uses a pulse train having a length of several nanoseconds to several tens of nanoseconds for transmission of communication bits. The transmitting device generates pulses modulated by PSK (Phase Shift Keying) modulation, OOK (On Off Keying) modulation, PPM (Pulse Position Modulation) modulation, etc. from a pulse waveform generator at regular intervals, and Data communication by transmitting. The pulse waveform generated by the pulse waveform generator forms a specific waveform so as to be within the definition of the communication band and the maximum radiated power permitted to be radiated into the air according to the laws and regulations of each country.

  The band in which power radiation is permitted in UWB varies slightly from country to country, but is allocated in units of GHz between about 3 GHz and about 10 GHz. UWB power emissions are limited to very low, but when using multiple UWB communications in close proximity, it is preferable to use the same frequency band because the influence of interference between UWBs is small. It is desirable that it can be used in a plurality of frequency bands.

  Many of the pulse waveform generators of the existing impulse UWB system generate a pulse envelope waveform having a desired bandwidth, and multiply by using an oscillator and a multiplier that generate a clock having a center frequency of a band to be used. The pulse is generated by up-converting to the target band, and the correspondence to a plurality of frequency bands is supported by changing the frequency of the clock generated by the oscillator. However, in the configuration using the oscillator and the multiplier having the center frequency in the above-described band, it is necessary to always operate the oscillator and the multiplier, and there is a problem that the power consumption increases. For this reason, the pulse waveform generator disclosed in Patent Document 1 employs a configuration that does not use an oscillator and a multiplier to reduce power consumption for transmission.

  However, the pulse waveform generator disclosed in Patent Document 1 is for a specific frequency band, and the configuration for supporting a plurality of frequency bands is not considered at all. Therefore, it has been desired to realize an impulse UWB pulse waveform generator that has low power consumption and supports a plurality of frequency bands.

  The present invention was devised in view of such circumstances, and an object thereof is to provide a pulse waveform generator capable of generating a plurality of pulse waveforms corresponding to a plurality of frequency bands with low power consumption and a transmitter using the same. There is to do.

  The pulse waveform generator of the present invention is a pulse waveform generator for a transmitter that performs impulse communication, and a plurality of delay devices that can be adjusted to a predetermined delay time are connected in series and input to the first delay device. A delay circuit that outputs a plurality of delay signals obtained by sequentially delaying the digital signals output by the delay devices by the predetermined delay time by inverting the digital signal to be generated at a timing at which pulse waveform generation is to be started, A square wave generating circuit for generating a square wave having a width of the predetermined time interval by sequentially synthesizing two delay signals having a predetermined time interval output from the delay device, and an output voltage by the square wave An output voltage selection circuit to select, by changing a predetermined delay time in the delay device and the output voltage selection content in the output voltage selection circuit, a plurality of It is characterized by outputting a constant waveform.

  FIG. 1 shows a configuration example of a transmitter equipped with this pulse waveform generator.

  That is, this transmitter receives a toggle flip-flop (T-FF) 101 to which a transmission bit string and a bit clock are input, a PLL circuit 102 to which a reference clock is input, and a bias voltage from the PLL circuit 102. The circuit includes a delay circuit 103, a square wave generation circuit 104, an output voltage selection circuit 105, a band pass filter (BPF) 106, and an antenna 107.

  As shown in FIG. 2, the PLL circuit 102 includes a delay circuit 201, two switches 203 and 204, an inverter 205, frequency dividing circuits 206 and 207, a phase comparator 208, and a bias control unit 209. It is configured. The delay circuit 201 is configured by connecting a plurality of delay elements 202 in series. Each delay element 202 can be controlled in delay time by a bias voltage supplied from the bias control unit 209, and when the two switches 203 and 204 are turned on / off, the delay elements 202 are passed through the delay elements 202 of different stages. The signal is output to the inverter 205. A loop including the delay circuit 201, the switch 203 or 204, and the inverter 205 forms a VCO (Voltage Controlled Oscillator), and the transmission frequency is controlled by a bias voltage controlled by the bias control unit 209. Depending on whether the switch 203 is turned on or the switch 204 is turned on, two types of delay amounts per delay element 202 can be created even at the same transmission frequency.

  Further, by changing the frequency of the reference clock of the PLL circuit 102, the oscillation frequency of the VCO in the PLL circuit 102 can be changed to a predetermined value. Furthermore, it is possible to change the oscillation frequency of the VCO to a predetermined value by changing the oscillation frequency of the VCO in the PLL circuit 102 and the frequency division ratio of the reference clock.

  As shown in FIG. 3, the output voltage selection circuit 105 includes a plurality of amplitude controllers 302 to which square waves SQ1 to SQ11 output from the square wave generation circuit 104 and having a predetermined time interval are individually input, A plurality of switches 303 corresponding to the number of amplitude controllers 302, and the outputs of the first adder 304 and the even-numbered amplitude controllers 302 to which the outputs of the odd-numbered amplitude controllers 302 are input to the respective input terminals The second adder 305 is input to each input terminal, and includes one differential amplifier 306. The output of the first adder 304 is connected to the negative input terminal of the differential amplifier 306. The output of the two adder 305 is connected to the plus input terminal of the differential amplifier 306.

  The first adder 304 and the second adder 305 add a square wave having a desired amplitude input to each input terminal through the amplitude limiter 302 and the switch 303, and the differential amplifier 306 includes the first adder 304 and the second adder 305. An output difference between the adder 304 and the second adder 305 is amplified. Thereby, a plurality of pulse waveforms corresponding to a plurality of frequency bands can be generated.

  According to the present invention, it is possible to generate a plurality of pulse waveforms corresponding to a plurality of frequency bands with low power consumption.

  FIG. 1 is a block diagram of a transmitter including a pulse waveform generator according to an embodiment of the present invention.

  As shown in FIG. 1, a reference clock, a bit clock, and a transmission bit string are input to the transmitter. The reference clock is a clock that serves as a reference when determining the frequency of the transmission pulse. The transmission bit string is synchronized with the bit clock. In the figure, the reference clock and the bit clock are described as being different from each other, but the reference clock and the bit clock may be the same.

  Note that FIG. 1 is configured to perform OOK (On Off Keying) modulation. Specifically, OOK modulation is a modulation method in which a pulse waveform is transmitted when the value of the transmission bit string is “1”, and nothing is transmitted when the value of the transmission bit string is “0”.

  The transmitter includes a toggle flip-flop (T-FF) 101 to which a transmission bit string and a bit clock are input, a PLL circuit 102 to which a reference clock is input, and a delay circuit 103 to which a bias voltage from the PLL circuit 102 is input. A square wave generation circuit 104, an output voltage selection circuit 105, a bandpass filter (BPF) 106, and an antenna 107.

  The toggle flip-flop 101 inverts the TQ value (“0” or “0” when the value of the transmission bit string is “1” at the rising edge of the bit clock, as in the relationship between the bit clock, the transmission bit string, and the TQ shown in FIG. “1”). As a result, the value of TQ is inverted when the value of the transmission bit string, which is the timing at which pulse waveform generation is desired to start when performing OOK modulation, is “1”.

  FIG. 2 shows a more detailed circuit configuration of the PLL circuit 102 and the delay circuit 103. The details of the PLL circuit 102 and the delay circuit 103 will be described below with reference to FIG.

  The PLL circuit 102 includes a delay circuit 201, two switches 203 and 204, an inverter 205, frequency dividing circuits 206 and 207, a phase comparator 208, and a bias control unit 209.

  The delay circuit 201 is constituted by a series connection of a plurality (seven in this example) of delay elements 202. Each delay element 202 is composed of an inverter or the like whose delay time can be controlled by a bias voltage supplied from the bias control unit 209, and has the same structure. The switches 203 and 204 are exclusively turned on. When the switch 203 is turned on, the switch 204 is turned off. When the switch 204 is turned on, the switch 203 is turned off, and passes through the delay elements 202 having different stages. Is output to the inverter 205. In this example, a switch 203 is disposed between the output of the fifth-stage delay element 202 and the input of the inverter 205, and the switch 204 is disposed between the output of the final-stage delay element 202 and the input of the inverter 205. Is arranged. The inverter 205 is an inverter that performs logic inversion, and is preferably one that operates as fast as possible.

  A loop including the delay circuit 201, the switch 203 or 204, and the inverter 205 forms a VCO (Voltage Controlled Oscillator), and the transmission frequency is controlled by a bias voltage controlled by the bias control unit 209. Depending on whether the switch 203 is turned on or the switch 204 is turned on, two types of delay amounts per delay element 202 can be created even at the same transmission frequency.

  The frequency dividing circuits 206 and 207 are for determining the frequency ratio between the reference clock and the VCO transmission clock. For example, the frequency of the frequency dividing circuit 206 is 16 times when the reference clock is 100 MHz and the frequency dividing circuit 207 is divided. When the frequency is set to 1 time, the VCO transmission clock after the PLL circuit 102 is locked is 100 MHz × 16/1 = 1600 MHz = 1.6 GHz. Here, when the switch 203 is ON and the switch 204 is OFF, the delay amount per stage of each delay element 202 in the delay circuit 201 is 1/8 .5 corresponding to a clock cycle of 1.6 GHz × 5 = 8.0 GHz. 0 GHz = 125 psec (picosecond). On the other hand, when the switch 203 is OFF and the switch 204 is ON, the delay amount per stage of each delay element 202 in the delay circuit 201 is 1 / 1.12 GHz corresponding to a clock cycle of 1.6 GHz × 7 = 11.2 GHz. ≈89 psec (picosecond).

  Thus, by controlling ON / OFF of the switches 203 and 204 and the frequency dividing ratios of the frequency dividing circuits 206 and 207, the delay amount per stage of the delay element 202 can be controlled.

  In this embodiment, two switches 203 and 204 are used for explanation. However, a delay element that can be selected when the number of switches is three or more and the frequency dividing ratios of the frequency dividing circuits 206 and 207 are the same. 202 may be configured to increase the choice of delay amount per stage. Further, the VCO is configured by using the delay element 202 having a fixed number of stages without the switch, and the delay amount per stage of the delay element 202 is controlled only by the division ratios of the frequency dividing circuits 206 and 207. Also good. Further, the delay amount per delay element 202 may be controlled by changing the oscillation frequency of the VCO by changing the frequency of the reference clock.

  The phase comparator 208 detects a phase difference between the output of the frequency divider circuit 206 and the output of the frequency divider circuit 207, and outputs information corresponding to the phase difference to the bias control unit 209 using a voltage or the like.

  Based on the phase difference information from the phase comparator 208, the bias control unit 209 performs control to increase the bias voltage when the VCO transmission frequency is delayed and to decrease the bias voltage when the VCO transmission frequency is advanced. This makes it possible to match the VCO transmission frequency to a desired value.

  The delay circuit 103 is configured by connecting a plurality of delay elements 202 in series. In the present embodiment, an example in which the delay circuit 103 is configured by 11 delay elements 202 is shown. Since these delay elements 202 have the same structure as the delay elements 202 constituting the delay circuit 201 and also share a bias voltage, one stage of the delay elements 202 in the delay circuit 201 as described above. By controlling the amount of delay per hit, the amount of delay per stage of the delay element 202 in the delay circuit 103 can be similarly controlled.

  From the delay circuit 103, signals DL0 to DL11 delayed for each stage of the delay element 202 are output. DL0 is the input TQ itself to the delay circuit 103. FIG. 4 shows the relationship between the input TQ and some of the delayed signals (DL0 to DL2 and DL10 to DL11). In this embodiment, a signal delayed for each stage of the delay element 202 is output. However, the signal is not limited to each stage, and a signal delayed for each of a plurality of stages such as every second stage or every third stage is output. May be.

  3 is a more detailed circuit configuration diagram of the square wave generation circuit 104 and the output voltage selection circuit 105, FIG. 4 is a timing chart of a bit clock, a transmission bit string, and a TQ, and FIGS. 5 and 6 are square wave generation circuits. 104 shows timing charts of the output voltage selection circuit 104 and the output voltage selection circuit 105, respectively. However, the timing chart of FIG. 5 is a timing chart when the switch 203 constituting the VOC shown in FIG. 2 is turned OFF and the switch 204 is turned ON, and the timing chart shown in FIG. 6 is the same as the VOC shown in FIG. It is a timing chart when the switch 203 is turned on and the switch 204 is turned off.

  The details of the square wave generation circuit 104 and the output voltage selection circuit 105 will be described below with reference to FIGS.

  The square wave generation circuit 104 includes a plurality of (11 XOR (exclusive OR) circuits in this example) corresponding to the number of delay elements 202, and is output from the delay circuit 103. Among the delayed signals, those having adjacent delay times are subjected to XOR operation to generate DL0 and DL1 to SQ1, DL1 and DL2 to SQ2,..., DL10 and DL11 to SQ11 as shown in FIG. FIG. 5A shows SQ1 to SQ11 generated based on the rise or fall of TQ in FIG. As shown in FIG. 5A, SQ1 to SQ11 have the same width, and are square waves that are delayed in time by the width.

  As can be seen from FIG. 5A, when the delay amount per stage of the delay element 202 is increased, the width of each square wave output from the square wave generating circuit 104 is also increased in the same manner.

  The output voltage selection circuit 105 includes a plurality (18 in this example) of amplitude controllers 302, a plurality of (in this example, 18 corresponding to the number of amplitude controllers 302) switches 303, and a first addition. And a second adder 305 and one differential amplifier 306. In the following description, when it is necessary to distinguish between the amplitude controller 302 and the switch 303, a continuous number with a hyphen is attached to the side of each symbol.

  That is, the first adder 304 includes odd-numbered stages of XOR circuits 301-1, 301-3, 301-5, 301-7, 301-9, among 11 XOR circuits 301 of the square wave generation circuit 104. Signals SQ1, SQ3, SQ5, SQ7, SQ9, and SQ11 output from 301-11 are input via the amplitude limiter 302 and the switch 303 provided in correspondence with each other, and the second adder 305 receives Among the 11 XOR circuits 301 of the square wave generating circuit 104, the signals SQ2, SQ4, SQ6 output from the even-numbered stages of the XOR circuits 301-2, 301-4, 301-6, 301-8, 301-10. SQ8 and SQ10 are input via an amplitude limiter 302 and a switch 303 provided in correspondence with each other.

  More specifically, the signal SQ1 output from the first-stage XOR circuit 301-1 is supplied to the first input terminal (1) of the first adder 304 via the amplitude limiter 302-1 and the switch 303-1. ) And the second input terminal (2) of the first adder 304 via the amplitude limiter 302-2 and the switch 303-2. The signal SQ3 output from the third-stage XOR circuit 301-3 is input to the third input terminal (3) of the first adder 304 via the amplitude limiter 302-3 and the switch 303-3. At the same time, the signal is input to the fourth input terminal (4) of the first adder 304 via the amplitude limiter 302-4 and the switch 303-4. The signal SQ5 output from the fifth-stage XOR circuit 301-5 is input to the fifth input terminal (5) of the first adder 304 via the amplitude limiter 302-5 and the switch 303-5. At the same time, it is input to the sixth input terminal (6) of the first adder 304 via the amplitude limiter 302-6 and the switch 303-6. The signal SQ7 output from the seventh-stage XOR circuit 301-7 is input to the seventh input terminal (7) of the first adder 304 via the amplitude limiter 302-7 and the switch 303-7. At the same time, the signal is input to the eighth input terminal (8) of the first adder 304 via the amplitude limiter 302-8 and the switch 303-8. The signal SQ9 output from the ninth stage XOR circuit 301-9 is input to the ninth input terminal (9) of the first adder 304 via the amplitude limiter 302-9 and the switch 303-9. Yes. The signal SQ11 output from the eleventh stage XOR circuit 301-11 is input to the tenth input terminal (10) of the first adder 304 via the amplitude limiter 302-10 and the switch 303-10. Yes.

  On the other hand, the signal SQ2 output from the second-stage XOR circuit 301-2 is input to the first input terminal (1) of the second adder 305 via the amplitude limiter 302-11 and the switch 303-11. At the same time, the signal is input to the second input terminal (2) of the second adder 305 via the amplitude limiter 302-12 and the switch 303-12. The signal SQ4 output from the fourth-stage XOR circuit 301-4 is input to the third input terminal (3) of the second adder 305 via the amplitude limiter 302-13 and the switch 303-13. At the same time, it is inputted to the fourth input terminal (4) of the second adder 305 through the amplitude limiter 302-14 and the switch 303-14. The signal SQ6 output from the sixth-stage XOR circuit 301-6 is input to the fifth input terminal (5) of the second adder 305 via the amplitude limiter 302-15 and the switch 303-15. At the same time, it is input to the sixth input terminal (6) of the second adder 305 via the amplitude limiter 302-16 and the switch 303-16. The signal SQ8 output from the XOR circuit 301-8 at the eighth stage is input to the seventh input terminal (7) of the second adder 305 via the amplitude limiter 302-17 and the switch 303-17. Yes. The signal SQ10 output from the 10th stage XOR circuit 301-10 is input to the eighth input terminal (8) of the second adder 305 via the amplitude limiter 302-18 and the switch 303-18. Yes.

  The output of the first adder 304 is connected to the negative input terminal of the differential amplifier 306, and the output of the second adder 305 is connected to the positive input terminal of the differential amplifier 306. Yes.

  In the above configuration, the case where the pulse waveform shown in FIG. 5D is generated will be described.

  As described above, the square waves SQ1 to SQ11 that are the outputs of the square wave generating circuit 104 are as shown in FIG. SQ1 to SQ11 are input to the individual amplitude controllers 302 in the output voltage selection circuit 105 as shown in FIG.

  The amplitude controller 302 outputs a square wave having a desired amplitude during a period in which the square waves SQ1 to SQ11 are input. In FIG. 3, a to j written in the amplitude controller 302 indicate the ratio of the amplitudes of the square waves to be output, and the same alphabets indicate the same amplitude.

  As described above, the switches 303-1 to 303-10 are switches for switching whether or not to transmit the outputs of the corresponding individual amplitude controllers 302-1 to 302-10 to the first adder 304. Similarly, the switches 303-11 to 303-18 are switches for switching whether or not to transmit the outputs of the corresponding individual amplitude controllers 302-11 to 302-18 to the second adder 305. In FIG. 3, the subscript “1” or “2” is attached to each switch. The switches 303 with the same suffix indicate that ON / OFF control is performed at the same time.

  When the pulse waveform shown in FIG. 5D is generated, eleven switches 303-1, 303-3, 303-5, 303-7, 303-9, and 303-10 with the subscript “1” are attached. , 303-11, 303-13, 303-15, 303-17, and 303-18 are all turned on, and the remaining seven switches 303-2, 303-4, and 303-6 with the subscript “2” are attached. , 303-8, 303-12, 303-14 and 303-16 are all turned OFF.

  The first adder 304 and the second adder 305 are square waves having desired amplitudes input to the input terminals (1) to (10) and (1) to (8) through the amplitude limiter 302 and the switch 303. Are added together. Since the square waves having the desired amplitude output from each amplitude controller 302 are all output at different timings, the addition can be realized with a simple configuration such as a wired OR circuit. The addition result by the first adder 304 is shown in FIG. 5B, and the addition result by the second adder 305 is shown in FIG. 5C.

  The differential amplifier 306 is a differential amplifier that amplifies the output difference between the first adder 304 and the second adder 305. The differential amplification results in a waveform shown in FIG. Α is the amplification factor of this differential amplifier.

  On the other hand, the waveform shown in FIG. 6A shows the waveforms of SQ1 to SQ7 when the delay amount per stage of each delay element 202 of the delay circuit 103 shown in FIG. 2 is increased. That is, the pulse width of the waveform shown in FIG. 6A is wider than the waveform shown in FIG. Although SQ8 to SQ11 are output from the square wave generation circuit 104, they are omitted from illustration because they are not used thereafter.

  When the pulse waveform shown in FIG. 6D is generated, the subscript “1” is generated in a state where the square waves SQ1 to SQ7 shown in FIG. All the switches 303 with “” are turned off, and all the switches 303 with the subscript “2” are turned on. The addition result by the first adder 304 at this time is shown in FIG. 6B, and the addition result by the second adder 305 is shown in FIG. Accordingly, the result of differential amplification by the differential amplifier 306 has the waveform shown in FIG.

  The band-pass filter (BPF) 106 is a filter for band-limiting the pulse waveform output from the square wave generation circuit 104 so as to be within the radiation mask permitted by the UWB, and the output waveform conforms to the radiation mask. Will be. An example of an output waveform when the waveform shown in FIG. 7A is input to the band pass filter 106 is shown in FIG.

  In this embodiment, in order to simplify the explanation, two types of pulse waveforms of FIG. 5D and FIG. 6D can be generated, but the delay amount options per delay element 202 are selected. More types of pulse waveforms can be generated by increasing the number of amplitude controllers 302 and the types of switches 303 (subscripts).

It is a block block diagram of the transmitter which comprised the pulse waveform generator which concerns on one Embodiment of this invention. It is a more detailed circuit configuration diagram of a PLL circuit and a delay circuit according to the present embodiment. It is a more detailed circuit configuration diagram of a square wave generation circuit and an output voltage selection circuit according to the present embodiment. 4 is a timing chart of a toggle flip-flop, a delay circuit, and a square wave generation circuit according to the present embodiment. 4 is a timing chart of a square wave generation circuit and an output voltage selection circuit according to the present embodiment. 4 is a timing chart of a square wave generation circuit and an output voltage selection circuit according to the present embodiment. It is operation | movement explanatory drawing of the band pass filter which concerns on this embodiment.

Explanation of symbols

101 Toggle flip-flop 102 PLL circuit 103 Delay circuit 104 Square wave generation circuit 105 Output voltage selection circuit 106 Band pass filter (BPF)
Reference Signs List 107 antenna 201 delay circuit 202 delay element 203, 204 switch 205 inverter 206, 207 frequency divider 208 phase comparator 209 bias controller 301 XOR circuit 302 amplitude controller 303 switch 304 first adder 305 second adder 306 differential amplifier

Claims (7)

A pulse waveform generator for a transmitter that performs impulse communication,
A plurality of delay devices that can be adjusted to a predetermined delay time are connected in series, and a digital signal input to the first-stage delay device is inverted at a timing at which pulse waveform generation is to be started, whereby each of the delay devices outputs the signal. A delay circuit that outputs a plurality of delay signals obtained by sequentially delaying a digital signal by the predetermined delay time;
A square wave generating circuit for generating a square wave having a width of the predetermined time interval by sequentially combining two delay signals output from the delay device and having a predetermined time interval;
An output voltage selection circuit for selecting an output voltage by the square wave,
A pulse waveform generator that outputs a plurality of specific waveforms by changing a predetermined delay time in the delay unit and a selection content of an output voltage in the output voltage selection circuit.   A PLL circuit including a VCO configured by a plurality of delay units having the same configuration as the delay unit, and commonly controlling a bias voltage between the delay unit in the PLL circuit and the delay unit in the delay circuit; 2. The pulse waveform generator according to claim 1, wherein the delay time in each delay unit is controlled to a predetermined value by setting the oscillation frequency of the VCO in the PLL circuit to a predetermined value.   3. The pulse waveform generator according to claim 2, wherein the oscillation frequency of the VCO is changed to a predetermined value by changing the number of delay devices constituting the VCO.   4. The pulse waveform generator according to claim 3, wherein the number of the delay devices is changed by switch switching control.   The pulse waveform generator according to claim 2, wherein the oscillation frequency of the VCO is changed to a predetermined value by changing an oscillation frequency of the VCO and a frequency division ratio of the reference clock in the PLL circuit. .   3. The pulse waveform generator according to claim 2, wherein the oscillation frequency of the VCO in the PLL circuit is changed to a predetermined value by changing the frequency of the reference clock of the PLL circuit.   A transmitter capable of transmitting impulse waveforms for a plurality of frequency bands by mounting the pulse waveform generator according to any one of claims 1 to 6.

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