JP2008287768A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leak current without increasing read access time. <P>SOLUTION: A semiconductor storage device 10 includes: a plurality of word lines WL; a memory cell array 11 including a plurality of static memory cells MC connected to the plurality of word lines WL, respectively, and comprising a plurality of transistors; a plurality of low-potential power supply lines 14 connected to the plurality of memory cells MC, respectively; and a power supply circuit 23 connected to the plurality of low-potential power supply lines 14, setting the low-potential power supply line 14 at a ground voltage for the memory cell MC at a read access destination, and setting the low-potential power supply line 14 at a voltage higher than the ground voltage for the memory cell MC at a write access destination and for the memory cell MC without access. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a semiconductor memory device including a static memory cell.

  An SRAM (Static Random Access Memory) is known as a kind of semiconductor memory device. For example, an SRAM cell (6Tr. Type SRAM cell) composed of six MOS (Metal Oxide Semiconductor) transistors is used as a memory cell constituting the SRAM.

  The SRAM cell is connected to a high level power line and a low level power line for supplying a voltage to the SRAM cell. In the conventional SRAM, the voltage of the low power supply line is always set to the ground voltage VSS for all lines of the memory cell array regardless of read access, write access, and no access.

  Therefore, in the conventional SRAM, a leakage current corresponding to the ground voltage VSS is always generated for all lines regardless of read access, write access, or no access. The current consumption is the sum of the switching current and the leakage current. Since the leakage current is always equal to the ground voltage VSS as the voltage of the lower power supply line in all the lines of the memory cell array, the power consumption of the SRAM is large. turn into.

In addition, as a related technique of this type, a technique for reducing the power consumption of the SRAM is disclosed (see Patent Document 1).
JP-A-9-147564

  The present invention provides a semiconductor memory device capable of reducing leakage current without increasing read access time.

  A semiconductor memory device according to a first aspect of the present invention includes a plurality of word lines, a memory cell array having a plurality of static memory cells each connected to the plurality of word lines and configured by a plurality of transistors. A plurality of low-level power supply lines connected to the plurality of memory cells, and a low-level power supply line connected to the low-level power supply line and set to a ground voltage with respect to a memory cell to be read access destination, and a write access destination And a power supply circuit that sets a lower power supply line to a voltage higher than the ground voltage for a memory cell that is not accessed.

  A semiconductor memory device according to a second aspect of the present invention includes: a plurality of word lines; a memory cell array having a plurality of static memory cells each connected to the plurality of word lines and configured by a plurality of transistors; A plurality of low-level power supply lines connected to the plurality of memory cells, and a low-level power supply line connected to the low-level power supply line and set to the ground voltage for the read access destination and the write access destination memory cell. And a power supply circuit for setting the lower power supply line to a voltage higher than the ground voltage for a memory cell that is not accessed.

  According to the present invention, it is possible to provide a semiconductor memory device capable of reducing leakage current without increasing the read access time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the SRAM 10 according to the first embodiment of the present invention. The SRAM 10 includes a memory cell array 11 composed of a plurality of memory cell columns 12. Each memory cell column 12 is composed of a plurality of static memory cells MC. In the memory cell array 11, a plurality of word lines WL corresponding to the plurality of memory cell columns 12 are arranged so as to extend in the row direction. The memory cell array 11 is provided with a plurality of bit line pairs BL, / BL so as to extend in the column direction. Selection of a row of the memory cell array 11 is performed by the word line WL. The column of the memory cell array 11 is selected by the bit line pair BL, / BL.

  FIG. 2 is a circuit diagram showing a configuration of memory cell MC shown in FIG. The memory cell MC is a 6Tr. Type SRAM cell.

  The memory cell MC includes a first inverter circuit INV1 and a second inverter circuit INV2. The first inverter circuit INV1 includes a load P-channel MOS (Metal Oxide Semiconductor) transistor (PMOS transistor) LD1 and a driving N-channel MOS transistor (NMOS transistor) DV1. The PMOS transistor LD1 and the NMOS transistor DV1 are connected in series between a high power supply line 13 to which a high power supply voltage is supplied and a low power supply line 14 to which a low power supply voltage is supplied.

  The second inverter circuit INV2 includes a load PMOS transistor LD2 and a driving NMOS transistor DV2. The PMOS transistor LD2 and the NMOS transistor DV2 are connected in series between the high level power supply line 13 and the low level power supply line.

  Specifically, the source terminal of the PMOS transistor LD1 is connected to the high-level power line 13. The drain terminal of the PMOS transistor LD1 is connected to the drain terminal of the NMOS transistor DV1 via the storage node N1. The source terminal of the NMOS transistor DV1 is connected to the low potential power line 14. The gate terminal of the PMOS transistor LD1 is connected to the gate terminal of the NMOS transistor DV1.

  The source terminal of the PMOS transistor LD2 is connected to the high level power supply line 13. The drain terminal of the PMOS transistor LD2 is connected to the drain terminal of the NMOS transistor DV2 via the storage node N2. The source terminal of the NMOS transistor DV2 is connected to the low power supply line. The gate terminal of the PMOS transistor LD2 is connected to the gate terminal of the NMOS transistor DV2.

  The gate terminal of the PMOS transistor LD1 is connected to the storage node N2. The gate terminal of the PMOS transistor LD2 is connected to the storage node N1. In other words, the output terminal of the first inverter circuit INV1 is connected to the input terminal of the second inverter circuit INV2, and the output terminal of the second inverter circuit INV2 is connected to the input terminal of the first inverter circuit INV1. .

  The storage node N1 is connected to the bit line BL via a transfer gate XF1 made of an NMOS transistor. Storage node N2 is connected to bit line / BL via transfer gate XF2 made of an NMOS transistor. The gate terminals of the transfer gates XF1 and XF2 are connected to the word line WL. In this way, the memory cell MC is configured.

  An address signal ADD is input to the row decoder 15. The row decoder 15 decodes the address signal ADD and generates a row access signal RAS for selecting one of the plurality of word lines WL. This row access signal RAS is sent to the word line driver 16. A plurality of word lines WL are connected to the word line driver 16. The word line driver 16 drives the word line WL selected by the row access signal RAS.

  An address signal ADD is input to the column decoder 17. The column decoder 17 decodes the address signal ADD and generates a column access signal CAS for selecting one pair of a plurality of bit line pairs BL, / BL. This column access signal CAS is sent to an input / output (I / O) circuit 18.

  Input data DI is input to the I / O circuit 18. The I / O circuit 18 manages the input data DI and the output data DO based on the column access signal CAS. The input data DI input to the I / O circuit 18 is sent to the sense amplifier circuit 19 as write data WD. The sense amplifier circuit 19 amplifies the write data WD and sends it to the memory cell array 11 (specifically, the bit line pair BL, / BL).

  Read data RD read from the memory cell array 11 via the bit line pair BL, / BL is sent to the sense amplifier circuit 19. The sense amplifier circuit 19 amplifies the read data RD and sends it to the I / O circuit 18. Read data RD input to the I / O circuit 18 is output to an external circuit as output data DO.

  The control circuit 20 controls each circuit in the SRAM 10. The control circuit 20 receives a command CMD from an external circuit. The control circuit 20 controls a data write operation, a read operation, and the like based on the command CMD.

  Incidentally, the SRAM 10 includes an access determination circuit 21, a high power supply circuit 22, and a low power supply circuit 23. The high power supply circuit 22 is connected to the high power supply line 13. The high power supply line 13 is provided in common for a plurality of memory cell columns. The high power supply circuit 22 supplies the power supply voltage VDD to the high power supply line 13.

  The access determination circuit 21 receives a command CMD and an address ADD. The access determination circuit 21 determines the access state (write, read, no access) of each memory cell column 12 based on the command CMD and the address ADD. Then, the access determination circuit 21 sends a selection signal SS for selecting one of the two types of low power supply voltages to the low power supply circuit 23 based on the determination result.

  The low power supply circuit 23 includes a plurality of low power supply circuits 24 corresponding to the plurality of memory cell columns 12. A plurality of low power supply lines 14 are connected to the plurality of low power supply circuits 24, respectively. Each low power supply line 14 is connected to a corresponding memory cell column. The low power supply circuit 24 supplies one of two types of low power supply voltages to the low power supply line 14 based on the selection signal SS sent from the access determination circuit 21.

  FIG. 3 is a diagram for explaining the voltage supply operation of the low-level power supply circuit 23. The low power supply circuit 23 sets the voltage of the low power supply line 14 according to the access state of the memory cell column 12. That is, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column. Further, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the voltage VSSH higher than the ground voltage VSS for the memory cell column that is the write access destination. Further, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the voltage VSSH higher than the ground voltage VSS for the memory cell column that is not accessed.

  The voltage VSSH is higher than the ground voltage VSS and lower than the threshold voltage of the inverter circuit INV1 (or INV2), and is set to a voltage at which the memory cell MC can hold data. As the voltage VSSH becomes higher than the ground voltage VSS, the leakage current of the memory cell MC is reduced. However, if the voltage VSSH is too high, the state of the transistors constituting the memory cell MC changes and the data held in the memory cell MC is destroyed. Therefore, “the voltage VSSH at which the memory cell MC can hold data” is a voltage obtained by subtracting a margin for noise from the threshold voltage of the inverter circuit constituting the memory cell MC.

  FIG. 4 is a circuit diagram showing an example of the low-level power supply circuit 24. FIG. 4 shows an extracted low power supply circuit 24 corresponding to one memory cell column. For the other memory cell columns, the same circuit as that of FIG. 4 is connected.

  The low power supply circuit 24 includes an NMOS transistor 24A and a PMOS transistor 24B. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The source of the NMOS transistor 24A is grounded. The drain of the PMOS transistor 24B is grounded. The source of the PMOS transistor 24B is connected to the low potential power line 14. The selection signal SS is input from the access determination circuit 21 to the gates of the NMOS transistor 24A and the PMOS transistor 24B.

  FIG. 5 is a diagram for explaining the operation of the NMOS transistor 24A and the PMOS transistor 24B according to the access state of the memory cell column 12. In FIG. The low power supply circuit 24 shown in FIGS. 4 and 5 is a configuration example in which the threshold voltage of the PMOS transistor 24B is used as the voltage VSSH.

  FIG. 6 is a circuit diagram showing another example of the low-level power supply circuit 24. The low power supply circuit 24 includes an NMOS transistor 24A and an NMOS transistor 24C. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The source of the NMOS transistor 24A is grounded. The drain of the NMOS transistor 24C is connected to the low power supply line. The source of the NMOS transistor 24C is connected to a power supply terminal to which the voltage VSSH is supplied. The selection signal SS is input from the access determination circuit 21 to the gates of the NMOS transistors 24A and 24C.

  FIG. 7 is a diagram for explaining the operation of the NMOS transistors 24A and 24C according to the access state of the memory cell column 12. In FIG. The low power supply circuit 24 shown in FIGS. 6 and 7 is a configuration example in which a voltage supplied from an external circuit is used as the voltage VSSH.

  Hereinafter, the operation of the SRAM 10 will be described by dividing it into a memory cell column that is a read access destination, a memory cell column that is a write access destination, and a memory cell column that is not accessed. In the following description of the operation, the case where the low power supply circuit 24 shown in FIG. 4 is used will be described as an example.

<Read-access destination memory cell column>
The access determination circuit 21 determines a read access destination memory cell column and generates a selection signal SS for the low-level power supply circuit 24 with the low-level power supply line 14 as the ground voltage VSS. By this selection signal SS, the NMOS transistor 24A is turned on and the PMOS transistor 24B is turned off. As a result, the ground voltage VSS is applied to the lower power supply line 14 that is the read access destination.

  In the memory cell column that is the read access destination, the low power supply line 14 is set to the ground voltage VSS, so that the same leakage current as that in the normal read operation is generated from the memory cell MC. Here, since the low-level power supply line 14 is at the ground voltage VSS, the time required for the read access from the memory cell MC can be kept the same as the normal read operation. That is, the read access time is the same as the conventional one and does not increase.

<Write access destination memory cell column>
The access determination circuit 21 determines a memory cell column to be accessed for writing, and generates a selection signal SS for setting the low-level power supply line 14 to a voltage VSSH higher than the ground voltage VSS for the low-level power supply circuit 24. By this selection signal SS, the NMOS transistor 24A is turned off and the PMOS transistor 24B is turned on. As a result, a voltage higher than the ground voltage VSS (a threshold voltage of the PMOS transistor 24B) is applied to the lower power supply line 14 that is the write access destination.

  As a result, in the memory cell column that is the write access destination, the leakage current is reduced by the amount that the voltage of the low-level power supply line 14 has increased from the ground voltage VSS. In addition, by making the voltage of the lower power supply line 14 higher than the ground voltage VSS, it becomes easier to write data to the memory cell MC than when the low power supply line 14 is at the ground voltage VSS, and the write time is shortened. be able to.

<Memory cell row without access>
The access determination circuit 21 determines a memory cell column without access, and generates a selection signal SS for setting the low-level power supply line 14 to a voltage VSSH higher than the ground voltage VSS for the low-level power supply circuit 24. By this selection signal SS, the NMOS transistor 24A is turned off and the PMOS transistor 24B is turned on. As a result, a voltage higher than the ground voltage VSS (the threshold voltage of the PMOS transistor 24B) is applied to the low-level power supply line 14 without access.

  As a result, in the non-accessed memory cell column, the leakage current is reduced by the amount by which the voltage of the lower power supply line 14 is increased from the ground voltage VSS.

  As described above in detail, in this embodiment, the voltage of the low-level power supply line 14 is set to the ground voltage VSS only for the memory cell column to be read access destination, while the memory cell column to which no access is made and the write access destination For the memory cell column, the voltage of the lower power supply line 14 is set to a voltage VSSH higher than the ground voltage VSS. Thereby, it is possible to reduce the leakage current between the memory cell column without access and the memory cell column as the write access destination without increasing the read access time.

  Further, by making the voltage of the lower power supply line 14 higher than the ground voltage VSS with respect to the memory cell column to be accessed for writing, the data of the memory cell MC is transferred more than when the lower power supply line 14 is at the ground voltage VSS. Writing becomes easy and writing time can be shortened.

  Further, the threshold voltage of the PMOS transistor 24B is used as means for generating the voltage VSSH higher than the ground voltage VSS. Therefore, the leakage current of the memory cell MC can be reduced only by a small increase in circuit area.

(Second Embodiment)
In the second embodiment, the voltage of the low-level power supply line 14 is set to the ground voltage VSS for the read access destination memory cell column and the write access destination memory cell column, while the non-accessed memory cell column In contrast, the voltage of the lower power supply line 14 is set to a voltage VSSH higher than the ground voltage VSS.

  FIG. 8 is a block diagram showing a configuration of the SRAM 10 according to the second exemplary embodiment of the present invention. The SRAM 10 includes a low power supply circuit 23 that supplies a voltage to the low power supply line 14. The low power supply circuit 23 includes a plurality of low power supply circuits 24 corresponding to the plurality of memory cell columns 12. A plurality of low power supply lines 14 are connected to the plurality of low power supply circuits 24, respectively. Each low power supply line 14 is connected to a corresponding memory cell column. The low power supply circuit 24 supplies one of two types of low power supply voltages to the low power supply line 14 based on the row access signal RAS sent from the row decoder 15.

  FIG. 9 is a diagram for explaining the voltage supply operation of the low-level power supply circuit 23. The low power supply circuit 23 sets the voltage of the low power supply line 14 according to the access state of the memory cell column 12. That is, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column. Further, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the memory cell column to be accessed for writing. Further, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the voltage VSSH higher than the ground voltage VSS for the memory cell column that is not accessed.

  FIG. 10 is a circuit diagram showing an example of the low-level power supply circuit 24. FIG. 10 shows an extracted low power supply circuit 24 corresponding to one memory cell column. The same circuit as that of FIG. 10 is also connected to the other memory cell columns.

  The low power supply circuit 24 includes an NMOS transistor 24A and a PMOS transistor 24B. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The source of the NMOS transistor 24A is grounded. The drain of the PMOS transistor 24B is grounded. The source of the PMOS transistor 24B is connected to the low potential power line 14. A row access signal RAS is input from the row decoder 15 to the gates of the NMOS transistor 24A and the PMOS transistor 24B.

  FIG. 11 is a diagram for explaining the operation of the NMOS transistor 24A and the PMOS transistor 24B according to the access state of the memory cell column 12. The low power supply circuit 24 is configured to supply the threshold voltage of the PMOS transistor 24B to the low power supply line 14 as the voltage VSSH.

  Hereinafter, the operation of the SRAM 10 will be described by dividing it into a memory cell column that is a read access destination, a memory cell column that is a write access destination, and a memory cell column that is not accessed.

<Read-access destination memory cell column>
The row decoder 15 activates a row access signal RAS corresponding to a read access destination memory cell column. This row access signal RAS is sent to the low power supply circuit 24, the NMOS transistor 24A is turned on, and the PMOS transistor 24B is turned off. As a result, the ground voltage VSS is applied to the lower power supply line 14 that is the read access destination.

  In the memory cell column that is the read access destination, the low power supply line 14 is set to the ground voltage VSS, so that the same leakage current as that in the normal read operation is generated from the memory cell MC. Here, since the low-level power supply line 14 is at the ground voltage VSS, the time required for the read access from the memory cell MC can be kept the same as the normal read operation. That is, the read access time is the same as the conventional one and does not increase.

<Write access destination memory cell column>
The row decoder 15 activates a row access signal RAS corresponding to a write access destination memory cell column. This row access signal RAS is sent to the low power supply circuit 24, the NMOS transistor 24A is turned on, and the PMOS transistor 24B is turned off. As a result, the ground voltage VSS is applied to the lower power supply line 14 of the write access destination.

  In the memory cell column to be accessed for writing, since the low power supply line 14 is set to the ground voltage VSS, the same leakage current as that in the normal writing operation is generated from the memory cell MC. Here, since the low-level power supply line 14 is at the ground voltage VSS, the time required for the write access from the memory cell MC can be kept the same as the normal write operation. That is, the write access time is the same as the conventional one and does not increase.

<Memory cell row without access>
The row decoder 15 deactivates the row access signal RAS corresponding to the memory cell column without access. The row access signal RAS is sent to the low power supply circuit 24, the NMOS transistor 24A is turned off, and the PMOS transistor 24B is turned on. As a result, a voltage higher than the ground voltage VSS (the threshold voltage of the PMOS transistor 24B) is applied to the low-level power supply line 14 without access.

  As a result, in the non-accessed memory cell column, the leakage current is reduced by the amount by which the voltage of the lower power supply line 14 is increased from the ground voltage VSS.

  As described above in detail, in the present embodiment, the voltage of the low-level power supply line 14 is set to the ground voltage VSS only for the memory cell column that is the read access destination and the memory cell column that is the write access destination, while there is no access. For these memory cell columns, the voltage of the lower power supply line 14 is set to a voltage VSSH higher than the ground voltage VSS. As a result, the leakage current of the memory cell column without access can be reduced without increasing the read access time and the write access time.

  Further, a row access signal RAS for selecting the word line WL is used as a signal for controlling the low power supply circuit 23. As a result, the circuit configuration can be simplified as compared with the first embodiment, and an increase in the circuit area of the SRAM can be suppressed.

(Third embodiment)
The third embodiment is based on the configuration of the first embodiment, and further allows the low-level power supply line 14 to be selected from three or more types of voltages, so that the types and conditions of use of the equipment in which the SRAM 10 is used. The amount of leakage current reduction and the level of noise resistance can be selected according to the above.

  FIG. 12 is a block diagram showing a configuration of the SRAM 10 according to the third exemplary embodiment of the present invention. The SRAM 10 includes an access determination circuit 21, a mode selection circuit 25, and a low power supply circuit 23.

  A command CMD and an address ADD are input to the access determination circuit 21. The access determination circuit 21 determines the access state (write, read, no access) of each memory cell column 12 based on the command CMD. Then, the access determination circuit 21 sends to the mode selection circuit 25 a selection signal SS1 for selecting one of the ground voltage VSS and a voltage higher than the ground voltage VSS based on the determination result.

  The mode selection circuit 25 includes a plurality of mode selection circuits 26 corresponding to the plurality of memory cell columns 12. In addition to the selection signal SS1 from the access determination circuit 21, a mode selection signal MS is input to the mode selection circuit 26 from an external circuit. Based on the selection signal SS1 and the mode selection signal MS, the mode selection circuit 26 selects the selection signal SS2 for selecting any one of a plurality of types (three types in this embodiment) of the low-level power supply voltage. Send to circuit 23.

  The low power supply circuit 23 includes a plurality of low power supply circuits 24 connected to a plurality of mode selection circuits 26, respectively. A plurality of low power supply lines 14 are connected to the plurality of low power supply circuits 24, respectively. Each low power supply line 14 is connected to a corresponding memory cell column. The low power supply circuit 24 supplies any one of the three types of low power supply voltages to the low power supply line 14 based on the selection signal SS2 sent from the mode selection circuit 26.

  FIG. 13 is a diagram for explaining the voltage supply operation of the low-level power supply circuit 23. The low-level power supply circuit 23 has three modes (modes 1 to 3). These three modes (modes 1 to 3) are selected by a mode selection signal MS from an external circuit.

  In mode 1, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column, and for the write access destination memory cell column and the non-accessed memory cell column. Thus, the voltage of the lower power supply line 14 is set to the voltage VSSH1.

  In mode 2, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column, and for the write access destination memory cell column and the non-accessed memory cell column. Thus, the voltage of the lower power supply line 14 is set to the voltage VSSH2. In mode 3, the low power supply circuit 23 sets the voltage of the low power supply line 14 to the ground voltage VSS for all the memory cell columns.

  The voltages VSSH1 and VSSH2 are set to voltages that are higher than the ground voltage VSS and lower than the threshold voltage of the inverter circuit INV1 (or INV2), and that the memory cell MC can hold data. Further, the voltage VSSH1 is set higher than VSSH2.

  FIG. 14 is a circuit diagram illustrating an example of the low-level power supply circuit 24. FIG. 14 shows an extracted low power supply circuit 24 corresponding to one memory cell column. For the other memory cell columns, the same circuit as that in FIG. 14 is connected.

  The low power supply circuit 24 includes an NMOS transistor 24A, a PMOS transistor 24B, and a PMOS transistor 24D. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The source of the NMOS transistor 24A is grounded. The drains of the PMOS transistors 24B and 24D are grounded. The sources of the PMOS transistors 24B and 24D are connected to the low power supply line. The selection signal SS2 is input from the mode selection circuit 26 to the gates of the NMOS transistor 24A and the PMOS transistors 24B and 24D.

  FIG. 15 is a diagram for explaining the operation of the NMOS transistor 24A and the PMOS transistors 24B and 24D according to the access state of the memory cell column 12. The threshold voltage of the PMOS transistor 24B is set larger than that of the PMOS transistor 24D. The threshold voltage of the PMOS transistor 24B corresponds to the voltage VSSH1, and the threshold voltage of the PMOS transistor 24D corresponds to the voltage VSSH2.

  In the SRAM 10 configured as described above, in the mode 1 and the mode 2, the low-level power supply line 14 is set to the ground voltage VSS for the memory cell column to be read access. Therefore, the read access time is the same as the conventional one and does not increase.

  In mode 1, the low-level power supply line 14 is set to the voltage VSSH1 for the memory cell column that is the write access destination and the memory cell column that is not accessed. In mode 2, the low-level power supply line 14 is set to the voltage VSSH2 (<VSSH1) for the memory cell column that is the write access destination and the memory cell column that is not accessed. Therefore, the mode 1 can reduce the leakage current compared to the mode 2. Also, mode 2 can increase noise tolerance compared to mode 1.

  That is, mode 1 may be selected when the noise tolerance may be small and it is desired to increase the leakage current reduction amount. Mode 2 may be selected when the leakage current reduction amount may be small and noise tolerance is to be increased. Mode 3 is selected when it is not necessary to reduce the leakage current, or when it is necessary to have the same noise tolerance. As described above, according to the present embodiment, it is possible to select the leakage current reduction amount and the noise resistance level according to the type of equipment in which the SRAM 10 is used and the use conditions. Other effects are the same as those of the first embodiment.

  Note that the voltages VSSH1 and VSSH2 may be supplied from an external circuit. FIG. 16 is a circuit diagram showing another example of the low-level power supply circuit 24. The low-level power supply circuit 24 includes NMOS transistors 24A, 24C, and 24E. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The drains of the NMOS transistors 24A, 24C, and 24E are connected to the low power supply line 14. The source of the NMOS transistor 24A is grounded. The source of the NMOS transistor 24C is connected to a power supply terminal to which the voltage VSSH1 is supplied. The source of the NMOS transistor 24E is connected to a power supply terminal to which the voltage VSSH2 is supplied. The selection signal SS2 is input from the mode selection circuit 26 to the gates of the NMOS transistors 24A, 24C, and 24E.

  FIG. 17 is a diagram for explaining the operation of the NMOS transistor 24A and the PMOS transistors 24B and 24D according to the access state of the memory cell column 12. As shown in FIGS. 16 and 17, even when the voltages VSSH1 and VSSH2 are supplied from an external circuit, the same operation as the circuit of FIG. 14 is possible.

(Fourth embodiment)
The fourth embodiment is based on the configuration of the second embodiment, and further enables the low-level power supply line 14 to be selected from three or more types of voltages, so that the types and conditions of use of the equipment in which the SRAM 10 is used. The amount of leakage current reduction and the level of noise resistance can be selected according to the above.

  FIG. 18 is a block diagram showing a configuration of the SRAM 10 according to the fourth exemplary embodiment of the present invention. The SRAM 10 includes a mode selection circuit 25 and a low power supply circuit 23.

  The mode selection circuit 25 includes a plurality of mode selection circuits 26 corresponding to the plurality of memory cell columns 12. The mode selection circuit 26 receives a row access signal RAS from the row decoder 15 and a mode selection signal MS from an external circuit. Based on the row access signal RAS and the mode selection signal MS, the mode selection circuit 26 selects a selection signal SS for selecting one of a plurality of types (three types in this embodiment) of the low-level power supply voltage. This is sent to the power supply circuit 23.

  The low power supply circuit 23 includes a plurality of low power supply circuits 24 connected to a plurality of mode selection circuits 26, respectively. A plurality of low power supply lines 14 are connected to the plurality of low power supply circuits 24, respectively. Each low power supply line 14 is connected to a corresponding memory cell column. The low-level power supply circuit 24 supplies any one of three types of low-level power supply voltages to the low-level power supply line 14 based on the selection signal SS sent from the mode selection circuit 26.

  FIG. 19 is a diagram for explaining the voltage supply operation of the low-level power supply circuit 23. The low-level power supply circuit 23 has three modes (modes 1 to 3). These three modes (modes 1 to 3) are selected by a mode selection signal MS from an external circuit.

  In mode 1, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column and the write access destination memory cell column, and the non-accessed memory cell column Thus, the voltage of the lower power supply line 14 is set to the voltage VSSH1.

  In mode 2, the low-level power supply circuit 23 sets the voltage of the low-level power supply line 14 to the ground voltage VSS for the read access destination memory cell column and the write access destination memory cell column, and the non-accessed memory cell column Thus, the voltage of the lower power supply line 14 is set to the voltage VSSH2. In mode 3, the low power supply circuit 23 sets the voltage of the low power supply line 14 to the ground voltage VSS for all the memory cell columns.

  FIG. 20 is a circuit diagram illustrating an example of the low-level power supply circuit 24. FIG. 20 shows an extracted low power supply circuit 24 corresponding to one memory cell column. The same circuit as that of FIG. 20 is also connected to the other memory cell columns.

  The low power supply circuit 24 includes an NMOS transistor 24A, a PMOS transistor 24B, and a PMOS transistor 24D. The drain of the NMOS transistor 24A is connected to the low potential power line 14. The source of the NMOS transistor 24A is grounded. The drains of the PMOS transistors 24B and 24D are grounded. The sources of the PMOS transistors 24B and 24D are connected to the low power supply line. A selection signal SS is input from the mode selection circuit 25 to the gates of the NMOS transistor 24A and the PMOS transistors 24B and 24D.

  FIG. 21 is a diagram for explaining the operation of the NMOS transistor 24A and the PMOS transistors 24B and 24D according to the access state of the memory cell column 12. The threshold voltage of the PMOS transistor 24B is set larger than that of the PMOS transistor 24D. The threshold voltage of the PMOS transistor 24B corresponds to the voltage VSSH1, and the threshold voltage of the PMOS transistor 24D corresponds to the voltage VSSH2.

  In the SRAM 10 configured as described above, in the mode 1 and the mode 2, the low power supply line 14 is set to the ground voltage VSS for the read access destination memory cell column and the write access destination memory cell column. Therefore, the read access time and the write access time are the same as the conventional one and do not increase.

  In mode 1, the low power supply line 14 is set to the voltage VSSH1 for the memory cell column without access. In mode 2, the low-level power supply line 14 is set to the voltage VSSH2 (<VSSH1) for the memory cell column without access. Therefore, the mode 1 can reduce the leakage current compared to the mode 2. Also, mode 2 can increase noise tolerance compared to mode 1.

  That is, mode 1 may be selected when the noise tolerance may be small and it is desired to increase the leakage current reduction amount. Mode 2 may be selected when the leakage current reduction amount may be small and noise tolerance is to be increased. Mode 3 is selected when it is not necessary to reduce the leakage current, or when it is necessary to have the same noise tolerance. As described above, according to the present embodiment, it is possible to select the leakage current reduction amount and the noise resistance level according to the type of equipment in which the SRAM 10 is used and the use conditions. Other effects are the same as those of the second embodiment.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a block diagram showing a configuration of an SRAM 10 according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory cell MC shown in FIG. 1. The figure explaining the voltage supply operation | movement of the low power supply circuit 23 which concerns on 1st Embodiment. FIG. 3 is a circuit diagram showing an example of a low-level power supply circuit 24 according to the first embodiment. FIG. 5 is a diagram for explaining an operation according to an access state of a memory cell column 12 in the low-level power supply circuit 24 shown in FIG. FIG. 5 is a circuit diagram showing another example of the low-level power supply circuit 24 according to the first embodiment. FIG. 7 is a diagram for explaining an operation according to the access state of the memory cell column 12 in the low power supply circuit 24 shown in FIG. The block diagram which shows the structure of SRAM10 which concerns on the 2nd Embodiment of this invention. The figure explaining the voltage supply operation | movement of the low power supply circuit 23 which concerns on 2nd Embodiment. The circuit diagram which shows an example of the low power supply circuit 24 which concerns on 2nd Embodiment. FIG. 11 is a diagram illustrating an operation according to an access state of the memory cell column 12 in the low-level power supply circuit 24 illustrated in FIG. 10. The block diagram which shows the structure of SRAM10 which concerns on the 3rd Embodiment of this invention. The figure explaining the voltage supply operation | movement of the low power supply circuit 23 which concerns on 3rd Embodiment. The circuit diagram which shows an example of the low level power supply circuit 24 which concerns on 3rd Embodiment. FIG. 15 is a diagram illustrating an operation according to an access state of the memory cell column 12 in the low-level power supply circuit 24 illustrated in FIG. 14. FIG. 10 is a circuit diagram showing another example of the low-level power supply circuit 24 according to the third embodiment. FIG. 17 is a diagram illustrating an operation according to an access state of the memory cell column 12 in the low-level power supply circuit 24 illustrated in FIG. 16. The block diagram which shows the structure of SRAM10 which concerns on the 4th Embodiment of this invention. The figure explaining the voltage supply operation | movement of the low power supply circuit 23 which concerns on 4th Embodiment. The circuit diagram which shows an example of the low-order power supply circuit 24 which concerns on 4th Embodiment. FIG. 21 is a diagram illustrating an operation according to an access state of the memory cell column 12 in the low-level power supply circuit 24 illustrated in FIG. 20.

Explanation of symbols

  MC ... memory cell, LD1, LD2 ... load PMOS transistor, DV1, DV2 ... drive NMOS transistor, N1, N2 ... storage node, INV1, INV2 ... inverter circuit, XF1, XF2 ... transfer gate, WL ... word line, BL , / BL... Bit line, 10... SRAM, 11... Memory cell array, 12... Memory cell column, 13... High power line, 14. DESCRIPTION OF SYMBOLS 18 ... Input / output (I / O) circuit, 19 ... Sense amplifier circuit, 20 ... Control circuit, 21 ... Access judgment circuit, 22 ... High power circuit, 23 ... Low power circuit, 24 ... Low power circuit, 24A, 24C, 24E ... NMOS transistor, 24B, 24D ... PMOS transistor, 25 ... mode selection circuit, 2 ... mode selection circuit.

Claims (5)

Multiple word lines,
A memory cell array having a plurality of static memory cells each connected to the plurality of word lines and composed of a plurality of transistors;
A plurality of low power lines connected to the plurality of memory cells,
A voltage that is connected to the lower power supply line and is set to the ground voltage for the memory cell that is the read access destination, and a voltage that is higher than the ground voltage for the memory cell that is not the write access destination and the access. A semiconductor memory device comprising: a power supply circuit set to: A determination circuit for determining an access state of the memory cell;
The semiconductor memory device according to claim 1, wherein the power supply circuit sets a voltage of the low-order power supply line based on a determination result by the determination circuit. Multiple word lines,
A memory cell array having a plurality of static memory cells each connected to the plurality of word lines and composed of a plurality of transistors;
A plurality of low power lines connected to the plurality of memory cells,
A voltage connected to the low power supply line and set to the ground voltage for the read access destination and the write access destination memory cell, and a voltage higher than the ground voltage for the memory cell without access to the low power supply line A semiconductor memory device comprising: a power supply circuit set to: A row decoder for selecting any one of the plurality of word lines;
4. The semiconductor memory device according to claim 3, wherein the power supply circuit sets a voltage of the low-order power supply line based on a selection result by the row decoder.   5. The semiconductor memory device according to claim 1, wherein the voltage is set to a voltage that does not destroy data held in the memory cell.

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