JP2008287194A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having a panel wiring structure capable of protecting a pixel circuit against electrostatic stress applied from the outside. <P>SOLUTION: A scanner arranged in the peripheral part of a panel has a shift register for successively generating an input signal by corresponding to a scanning line DS, and a buffer 5B for outputting a control signal to each scanning line DS in response to the input signal input from a power source wiring VddDS. The panel has a first power source terminal for connecting the power source wiring Vdd of the side of a pixel array part to an outside power source, a second power source terminal for connecting the power source wiring VddDS of the scanner of the side of a drive part to the outside power source, and protection resistors R2, R1 for connecting each power source terminal to grounding wiring GND. The power source wiring Vdd and the power source wiring VddDS are mutually connected with common wiring BL on the panel to be at the same potential. The characteristic variation of a switching transistor Tr4 in the pixel circuit 2 from the electrostatic stress applied on the first power source terminal or the second power source terminal is prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device that performs display by driving a light emitting element arranged for each pixel. More specifically, the present invention relates to a so-called active matrix type image display device that controls an amount of current supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel circuit. More specifically, the present invention relates to a wiring structure for protecting an insulated gate field effect transistor formed in each pixel circuit from external electrostatic stress.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional image display device basically includes a flat panel in which a pixel array unit and a driving unit for driving the pixel array unit are formed on a single substrate. The pixel array unit includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at the intersections thereof. Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, and a light emitting element. The sampling transistor is turned on in response to a control signal supplied from the scanning line and samples the video signal from the signal line. The drive transistor supplies a drive current to the light emitting element in accordance with the sampled video signal. The switching transistor controls the operation of the pixel according to another control signal supplied from another scanning line.

  A panel in which pixel circuits having such a configuration are integrated and formed in a matrix (matrix) is connected to an external power source or a signal source via an external connection terminal. Here, when external stress is applied to the terminal of the panel in the state where the external power supply is turned off, the switching transistor formed in the pixel circuit may cause a characteristic variation. When the characteristics of the switching transistor fluctuate due to electrostatic stress, there is a problem that the pixel circuit does not operate normally.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device having a panel wiring structure capable of protecting a pixel circuit against externally applied electrostatic stress. In order to achieve this purpose, the following measures were taken. That is, the display device according to the present invention includes a panel in which a pixel array section, a driving section for driving the pixel array section, and a ground wiring are formed. The pixel array section includes row-shaped first scanning lines and second scanning lines, column-shaped signal lines, matrix-shaped pixels arranged at portions where the first scanning lines and the signal lines intersect, And a first power supply wiring for supplying a potential necessary for the operation of each pixel. Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, and a light emitting element. The sampling transistor has a control end connected to the first scanning line, and a pair of current ends connected between the signal line and the control end of the drive transistor. The drive transistor has a current terminal connected to the light emitting element. The switching transistor has a control end connected to the second scanning line, one of a pair of current ends connected to the first power supply line, and the other connected to the control end or current end of the drive transistor, The sampling transistor is turned on according to the control signal supplied from the first scanning line and samples a video signal from the signal line, and the drive transistor emits a drive current according to the sampled video signal. The switching transistor controls the operation of the pixel in accordance with another control signal supplied from the second scanning line. The driving unit includes a first scanner that supplies a control signal to each first scanning line, a second scanner that supplies another control signal to each second scanning line, and a signal selector that supplies a video signal to each signal line. And a second power supply wiring for supplying power to the drive unit. The second scanner supplies a shift register that sequentially generates an input signal corresponding to each second scanning line, and outputs a control signal to each second scanning line in response to the power supplied from the second power supply wiring. And a buffer. The panel includes a first power supply terminal for connecting the first power supply wiring on the pixel array unit side to an external power supply, a second power supply terminal for connecting the second power supply wiring on the drive unit side to an external power supply, A protective resistor for connecting each power supply terminal to the ground wiring, and the first power supply wiring and the second power supply wiring are connected to each other on the panel so as to have the same potential and applied to the first power supply terminal or the second power supply terminal. It is characterized by preventing fluctuations in characteristics of the switching transistor from electrostatic stress.

  In one aspect, the switching transistor is disposed between the first power supply wiring and the current terminal of the drive transistor, and switches the light emitting element between lighting and extinguishing according to the control signal. In another aspect, the switching transistor is disposed between the first power supply wiring and the current end or control end of the drive transistor, and the potential of the current end or control end of the drive transistor is set according to the control signal. Reset operation is performed.

  The display device according to the present invention has a flat structure in which a pixel array unit and a drive unit are integrally formed on a single panel. The pixel array unit constitutes a screen, and peripheral driving units drive the pixel array unit. The first power supply wiring for supplying power to the pixel array portion is connected to a current terminal on the source side of the switching transistor included in each pixel. On the other hand, the second power supply line for supplying power to the drive unit is connected to the control terminal serving as the gate of the switching transistor via the output buffer and the scanning line of the scanner. Schematically, the circuit configuration is such that the first power supply wiring is connected to the source of the switching transistor and the second power supply wiring is connected to the gate. Here, the first power supply wiring and the second power supply wiring are configured to be connected to a power supply outside the panel through corresponding connection terminals. A protective resistor is connected to each terminal, and electrostatic stress applied from the outside flows to the ground wiring through the protective resistor.

  When electrostatic stress (surge voltage) is applied to one of the pair of connection terminals corresponding to the first power supply wiring and the second power supply wiring, the surge voltage is also applied to the other terminal via the protective resistor. As a result, the voltages of the first power supply wiring and the second power supply wiring change abruptly. However, since the resistance value of the protective resistor is high, a relative delay occurs in the voltage transition time between both power supply wirings. This delay causes an instantaneous but very large potential difference between the gate and source of the switching transistor. An excessive potential difference applied between the gate and source of the switching transistor may cause a characteristic variation of the switching transistor, which may hinder normal operation of the pixel.

  Therefore, according to the present invention, the first power supply wiring on the pixel array unit side and the second power supply wiring on the drive unit side are connected to each other on the panel to have the same potential. As a result, even if a surge voltage is applied to one of the pair of connection terminals corresponding to the first power supply wiring and the second power supply wiring, a potential difference is not generated between the other terminal. Therefore, even if electrostatic stress is applied to the connection terminal of the panel, an excessive potential difference does not occur between the gate and the source of the switching transistor, so that fluctuations in the characteristics can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a display device according to the present invention. As shown in the figure, this display device basically includes a pixel array section 1 and a drive section. The pixel array unit 1 and the peripheral driving unit are formed on one panel. The pixel array unit 1 includes first and second scanning lines WS and AZ1, AZ2, and DS arranged in rows, signal lines SL arranged in columns, and the scanning lines WS, AZ1, AZ2, and DS. In addition, the pixel circuits 2 are arranged in a row connected to the signal lines SL, and a plurality of power supply lines for supplying reference potentials Vini1, Vini2, and Vdd necessary for the operation of each pixel circuit 2. On the other hand, the drive unit has a horizontal selector (signal selector) 3 and supplies a video signal to the signal line SL. Further, the drive unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72, and sequentially supplies control signals to the corresponding scanning lines WS, DS, AZ1, and AZ2, respectively. The pixel circuit 2 is scanned for each row. Although not shown, power supply wiring and ground wiring for supplying power to the scanners 4, 5, 71, 72 are also formed on the panel. In addition, in order to supply a predetermined power supply voltage from the outside to the power supply wiring on the pixel array unit 1 side and the power supply wiring on the drive unit side, connection terminals are formed in the peripheral portion of the panel. Each pixel 2 is assigned with three primary colors RGB, and is displayed in color. However, the present invention is not limited to this, and can be applied to a single color display.

  FIG. 2 is a circuit diagram illustrating a configuration example of a pixel incorporated in the image display device illustrated in FIG. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a storage capacitor Cs, and a light emitting element EL. Including. The sampling transistor Tr1 conducts according to a control signal supplied from the first scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the holding capacitor Cs. The storage capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 is turned on according to the control signal supplied from the scanning line AZ1 prior to the sampling period, and sets the source S of the drive transistor Trd to the reference potential Vini2. The second switching transistor Tr3 is turned on in accordance with a control signal supplied from the scanning line AZ2 prior to the sampling period, and sets the gate G of the drive transistor Trd to another reference potential Vini1. The third switching transistor Tr4 is turned on in response to a control signal supplied from the scanning line DS prior to the sampling period to connect the drive transistor Trd to the power supply potential Vdd, and thus a voltage corresponding to the threshold voltage Vth of the drive transistor Trd. Is held in the holding capacitor Cs to correct the influence of the threshold voltage Vth. Further, the switching transistor Tr4 is turned on again in response to the control signal supplied from the scanning line DS during the light emission period, connects the drive transistor Trd to the power supply potential Vdd, and flows the output current Ids to the light emitting element EL.

  As is apparent from the above description, the pixel circuit 2 includes five transistors Tr1 to Tr4 and Trd, one holding capacitor Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N-channel double gate polysilicon TFTs. Only the transistor Tr4 is a P-channel double-gate polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. This timing chart represents the waveform of a control signal applied to each scanning line WS, AZ2, AZ1, DS. In this specification, the control signal applied to the corresponding scanning line is represented by the same reference numeral as the corresponding scanning line. For example, the control signal supplied to the scanning line WS is represented by the control signal WS. This timing chart also shows temporal transitions of the potentials of the gate G and the source S of the drive transistor Trd. Since the sampling transistor Tr1 and the switching transistors Tr2 and Tr3 are N-channel transistors, they are turned on when the control signals WS, AZ1 and AZ2 are at a high level and turned off when they are at a low level. On the other hand, since the switching transistor Tr4 is a P-channel type, it is opposite to the N-channel type and is turned off when the control signal DS is at a high level and turned on when it is at a low level.

  In the timing chart of FIG. 3, timings T1 to T8 are one field. In the state before the timing T1 when the field starts, the control signals WS, AZ1, AZ2, and DS are all at the low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vdd via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vdd, so that the light emission is stopped and a non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, the control signal AZ1 becomes high level, and the switching transistor Tr2 is turned on. As a result, the source potential of the drive transistor Trd becomes a predetermined power supply potential (reference potential) Vini2.

  At the next timing T3, the control signal AZ2 is switched to the high level, and the switching transistor Tr3 is turned on. As a result, the gate potential of the drive transistor Trd becomes a predetermined power supply potential (reference potential) Vini1. Here, Vini1−Vini2> Vth is satisfied, and Vni1−Vini2 = Vgs> Vth is satisfied, thereby completing the preparation operation for Vth correction performed after timing T4.

  At timing T4, the control signal AZ1 returns to the low level, the switching transistor Tr2 is turned off, the control signal DS is switched to the low level, and the switching transistor Tr4 is turned on. As a result, a current flows through the drive transistor Trd in accordance with the potential difference between the gate G and the source S of the drive transistor Trd. At this time, the cathode potential Vcat of the light emitting element EL is higher than the source potential of the drive transistor Trd, and the light emitting element EL is in a reverse bias state. Therefore, the current flowing from the drive transistor Trd does not flow to the light emitting element EL side, but flows into the storage capacitor Cs connected between the gate G and the source S of the drive transistor Trd, and charges are charged. As a result, the source potential rises. When the potential difference Vgs between the gate G and the source S becomes equal to Vth of the drive transistor Trd, the drive transistor Trd is cut off and no current flows. At this time, Vgs is just Vth, and this Vth is held in the holding capacitor Cs connected between the gate G and the source S of the drive transistor Trd. In this way, the Vth correction operation of the drive transistor Trd is completed.

  At timing T5, the control signal DS is returned to the high level, and the control signal AZ2 is returned to the low level. As a result, the switching transistors Tr4 and Tr3 are turned off. The gate G of the drive transistor Trd is disconnected from the reference potential Vini1.

  Thereafter, the process proceeds to timing T6 and enters a signal writing period. At timing T6, the control signal WS is switched to the high level, and the sampling transistor Tr1 is turned on. As a result, the signal potential Vsig of the video signal is written to the gate G of the drive transistor Trd. Therefore, the potential difference Vgs between the gate G and the source S of the drive transistor Trd is Vsig + Vth. That is, in this signal writing period, the signal potential Vsig of the video signal is sampled and written to the gate G of the drive transistor Trd. At this time, since Vth is subtracted from Vsig, variation in the threshold voltage Vth of the drive transistor Trd can be canceled.

  Thereafter, at timing T7, the control signal DS becomes low level again, and the switching transistor Tr4 is turned on while the sampling transistor Tr1 is turned on. As a result, current flows from the power supply potential Vdd to the drive transistor Trd, and the storage capacitor Cs connected between the gate G and the source S of the drive transistor Trd is charged, so that the source potential of the drive transistor Trd increases. To do. The increase (Vsig−Va) of the source potential negatively fed back to the holding capacitor Cs has an effect of correcting the variation in mobility μ of the drive transistor Trd. That is, the mobility correction of the drive transistor Trd of each pixel is performed in the overlap period in which both the sampling transistor Tr1 and the switching transistor Tr4 are on. The overlap period in which both the sampling transistor Tr1 and the switching transistor Tr4 are on is represented by a mobility correction period t. When considering a drive transistor having a high mobility μ and a drive transistor having a low mobility μ, the drive transistor Trd having a high mobility μ in the mobility correction period t has a source potential larger than that of a drive transistor Trd having a low mobility μ. To rise. When the source potential rises greatly, the potential difference Vgs between the gate G and the source S becomes small and the output current hardly flows. In other words, the output current is negatively fed back to the holding capacitor Cs during the mobility correction period t, thereby correcting the variation in mobility μ of the drive transistor Trd of each pixel. As a result, the drive transistor of any pixel has the mobility μ. Regardless of the difference, if the video signal is at the same level, the same output current can be supplied to the light emitting element.

  Subsequently, at timing T8, the control signal WS becomes low level, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. When the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be raised and rises together with the source potential (S). Accordingly, the reverse bias state of the light emitting element EL is canceled, and the light emitting element EL emits light according to the drive current Ids.

  FIG. 4 is a schematic circuit diagram illustrating a connection relationship between the pixel circuit 2 included in the pixel array unit and the scanner included in the peripheral driving unit. This circuit diagram focuses on the switching transistor Tr4. The gate of the switching transistor Tr4 is connected to the output buffer 5B of the drive scanner via the scanning line DS. The switching transistor Tr4 performs duty control for switching between the light emission period and the non-light emission period of the pixel 2 in accordance with the control signal DS supplied from the scanning line DS. That is, the switching transistor Tr4 is arranged between the first power supply wiring Vdd on the pixel array side and the current end on the drain side of the drive transistor Trd, and the light emitting element EL is turned on and off according to the control signal DS. Switching operation is in progress.

  On the other hand, the drive scanner basically includes a shift register and an output buffer 5B. A shift register (not shown) sequentially generates an input signal corresponding to each scanning line DS. The output buffer 5B is supplied with power from the second power supply wiring VddDS on the drive unit side, and outputs a control signal DS to each scanning line DS in accordance with an input signal supplied from each stage of the shift register. In the illustrated example, the output buffer 5B is configured by an inverter in which a pair of P-channel transistors and N-channel transistors are connected in series, and the output buffer 5B is connected in series between the second power supply line VddDS on the positive side and the power supply line VssDS on the negative side. Has been.

  The panel in which the pixel circuit 2 and the peripheral drive scanner described above are integrated and integrated includes a first power supply terminal for connecting the first power supply wiring Vdd on the pixel array side to an external power supply, and a second on the drive unit side. The power supply wiring VddDS has a second power supply terminal that connects to an external power supply, and protective resistors R1 and R2 that connect each power supply terminal and the ground wiring GND.

  With continued reference to FIG. 4, the problem of electrostatic stress will be described. When the power of the normal display device (display) is turned off, all the power supply wirings are basically connected to the ground wiring GND via protective resistors R1 and R2 of about 1.5 MΩ as shown in FIG. Becomes 0V. Consider a case where a surge voltage such as static electricity is applied to a terminal (connection pad) on the VddDS side. When the surge voltage is applied to the terminal on the VddDS side, the level is normally higher than Vth of the P-channel transistor of the output buffer 5B, so the surge voltage is output from the output buffer 5B to the scanning line DS side, and the drive Applied to the gate of the transistor Tr4.

  At this time, as described above, since the power supply wiring VddDS is connected to the ground wiring GND via the protective resistance R1, the surge voltage applied to the terminal on the VddDS side is protected by the protective resistance R1, ground wiring GND and The voltage is transmitted to the first power supply wiring Vdd on the pixel array side through the protective resistor R2, and finally applied to the source terminal of the switching transistor Tr4. At this time, the surge voltage applied to the source of the switching transistor Trd is greater than the surge voltage applied from the output buffer 5B to the scanning line DS due to the wiring resistance, the capacitance between the wirings, and the CR time constant of the protective resistors R1 and R2. The pulse is delayed in time.

  FIG. 5 shows a surge voltage waveform applied to the gate and source of the switching transistor Tr4. When electrostatic stress is applied to the terminal on the VddDS side, the gate G of the drive transistor Tr4 rising quickly rises to the surge voltage immediately.

  On the other hand, since the surge voltage applied to the source of the drive transistor Tr4 is affected by the wiring resistance, the capacitance between the wirings, and the protective resistance as described above, it gradually increases in a delayed waveform.

  As a result, the potential difference Vgs between the gate and the source of the switching transistor Tr4 rises to a level substantially corresponding to the surge voltage, although instantaneously, resulting in a characteristic variation of the switching transistor Tr4. If the Vth of the switching transistor Tr4 is shifted to the depletion side, the source potential rapidly rises at the time of signal writing. Therefore, the gate-source voltage Vgs of the drive transistor Trd immediately reaches the Vth of the drive transistor Trd, and current flows. As a result, no light is emitted. Conversely, when the Vth of the switching transistor Tr4 is shifted to the enhancement side, the speed of the change in the source potential of the drive transistor Trd during the Vth cancellation period or the mobility correction period t changes.

  FIG. 6 is a schematic circuit diagram showing the first embodiment of the display device according to the present invention. For easy understanding, portions corresponding to those of the display device shown in FIG. 4 are denoted by corresponding reference numerals. The present embodiment proposes a wiring system in which the switching transistor Tr4 is not destroyed even when a surge voltage is applied to the terminal on the VddDS side from the outside. The breakdown or deterioration of the switching transistor Tr4 due to the surge voltage is applied to the source of the switching transistor Tr4 via the surge voltage pulse applied from the buffer 5B on the scanner side to the gate G of the switching transistor Tr4 and the protective resistors R1 and R2. It has been described with reference to FIGS. 4 and 5 that the phase difference from the delayed surge voltage pulse is the cause. Therefore, in the present embodiment, as shown in the drawing, the second power supply on the buffer 5B side connected to the power supply wiring Vdd connected to the source end of the switching transistor Tr4 and the gate of the switching transistor Tr4 via the scanning line DS. The wiring VddDS is connected to each other by the common wiring BL. As a result, even if a surge voltage is applied to the terminal, the potential of the gate and source of the switching transistor Tr4 changes almost simultaneously, so that destruction or deterioration does not occur. As described above, according to the present invention, the first power supply wiring Vdd on the pixel array side and the second power supply wiring VddDS on the peripheral drive unit side are connected to each other on the panel so as to have the same potential, and are connected to the first power supply terminal or the second power supply terminal. The characteristic variation of the switching transistor Tr4 is prevented from the applied electrostatic stress.

  FIG. 7 is a circuit diagram showing a second embodiment of the display device according to the present invention. Basically, it is similar to the first embodiment shown in FIG. 6, and corresponding reference numerals are assigned to corresponding parts for easy understanding. The difference from the first embodiment shown in FIG. 6 is that the second embodiment prevents another switching transistor Tr3 from electrostatic breakdown. As shown in the drawing, the output buffer 72B of the second correction scanner 72 (not shown) is connected to the gate of the switching transistor Tr3 via the scanning line AZ2. A power supply wiring Vss is connected to the output buffer 72B, and a power supply voltage Vss is supplied from the outside through connection terminals (pads) arranged on the panel. Further, as described above, the predetermined power supply potential (reference potential) Vini1 is supplied to the source of the switching transistor Tr3. This power supply potential Vini1 is supplied from an external power supply via a corresponding connection terminal.

  The first power supply wiring Vini1 on the pixel array side is connected to the ground wiring GND via the protective resistor R3. Further, the power supply wiring Vss on the peripheral drive unit side is also connected to the ground wiring GND via the protective resistor R4. Here, the common wiring BL, which is a characteristic element of the present invention, is formed between the pair of connection terminals (Vss, Vini1). With such a configuration, the first power supply wiring Vini1 and the second power supply wiring Vss are connected to each other on the panel so as to have the same potential, thereby preventing the characteristic fluctuation of the switching transistor Tr3 from electrostatic stress applied to the first power supply terminal or the second power supply terminal. Yes.

  As described above, in the second embodiment, the switching transistor Tr3 is arranged between the first power supply line Vini1 and the control terminal (gate G) of the drive transistor Trd, and the potential of the gate G of the drive transistor Trd according to the control signal AZ2. The reset is operating. However, the present invention is not limited to this, and can be applied to other switching transistors Tr2. In this case, the switching transistor Tr2 is arranged between the first power supply line Vini2 and the current end (source S) of the drive transistor Trd, and resets the potential of the source S of the drive transistor Trd in accordance with the control signal AZ1.

  FIG. 8 is a waveform diagram for explaining the operation of the second embodiment shown in FIG. However, the state when Vss and Vini1 are not connected by the common wiring BL is shown. Here, when a negative surge voltage is applied to the terminal on the Vss side, the gate of the switching transistor Tr3 instantaneously drops to the surge voltage level via the buffer 72B. On the other hand, a surge voltage delayed in time is applied to the source S of the switching transistor Tr3. The reason is that a delay occurs while the surge voltage applied from the outside to the terminal on the Vss side reaches the source S of the switching transistor Tr3 through the protective resistors R3 and R4 and the wiring resistance. Since a relative phase difference occurs in the surge voltage applied to the gate and source of the switching transistor Tr3, the Vgs of the switching transistor Tr3 changes instantaneously to the surge voltage level, resulting in characteristic fluctuations. In the embodiment shown in FIG. 7, a common wiring BL is provided between the wiring on the Vss side and the wiring on the Vini1 side in order to prevent the characteristic fluctuation due to the electrostatic stress, and both have the same potential.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all fields which display the image signal produced | generated in the inside as an image or an image | video. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 11 shows a television to which the present invention is applied, which includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 12 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 13 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters and the like, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 14 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 15 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

1 is a block diagram showing an overall configuration of an image display device according to the present invention. It is a circuit diagram which shows the pixel formed in the image display apparatus shown in FIG. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a circuit diagram which shows the reference example of an image display apparatus. FIG. 5 is a waveform diagram for explaining the operation of the reference example shown in FIG. 4. 1 is a circuit diagram showing a first embodiment of an image display apparatus according to the present invention. It is a circuit diagram which shows 2nd Embodiment of the image display apparatus concerning this invention. It is a wave form diagram with which it uses for operation | movement description of 2nd Embodiment. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel circuit, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 71 ... First correction scanner, 72 ... Second correction scanner, Tr1... Sampling transistor, Tr2... First switching transistor, Tr3... Second switching transistor, Tr4... Third switching transistor, Trd. -Retention capacitance, EL ... Light emitting element, WS ... Scanning line, AZ1 ... Scanning line, AZ2 ... Scanning line, DS ... Scanning line, BL ... Common wiring

Claims (4)

It consists of a panel in which a pixel array part, a drive part that drives this, and a ground wiring are formed,
The pixel array section includes row-shaped first scanning lines and second scanning lines, column-shaped signal lines, matrix-shaped pixels arranged at portions where the first scanning lines and the signal lines intersect, A first power supply wiring for supplying a potential necessary for the operation of each pixel,
Each pixel includes at least a sampling transistor, a drive transistor, a switching transistor, and a light emitting element,
The sampling transistor has a control end connected to the first scanning line, a pair of current ends connected between the signal line and the control end of the drive transistor,
The drive transistor has a current terminal connected to the light emitting element,
The switching transistor has a control end connected to the second scanning line, one of a pair of current ends connected to the first power supply line, and the other connected to the control end or current end of the drive transistor,
The sampling transistor is turned on according to the control signal supplied from the first scanning line and samples a video signal from the signal line,
The drive transistor supplies a drive current to the light emitting element according to the sampled video signal,
The switching transistor controls the operation of the pixel according to another control signal supplied from the second scanning line,
The driving unit includes a first scanner that supplies a control signal to each first scanning line, a second scanner that supplies another control signal to each second scanning line, and a signal selector that supplies a video signal to each signal line. And a second power supply wiring for supplying power to the drive unit,
The second scanner supplies a shift register that sequentially generates an input signal corresponding to each second scanning line, and outputs a control signal to each second scanning line in response to the power supplied from the second power supply wiring. A buffer,
The panel includes a first power supply terminal for connecting the first power supply wiring on the pixel array unit side to an external power supply, a second power supply terminal for connecting the second power supply wiring on the drive unit side to an external power supply, A protective resistor for connecting each power supply terminal to the ground wiring,
The first power supply wiring and the second power supply wiring are connected to each other on the panel so as to have the same potential, and characteristic fluctuations of the switching transistor are prevented from electrostatic stress applied to the first power supply terminal or the second power supply terminal. Display device.   The switching transistor is disposed between the first power supply wiring and a current terminal of the drive transistor, and switches the light emitting element between lighting and extinguishing according to the control signal. The display device according to 1.   The switching transistor is arranged between the first power supply wiring and the current end or control end of the drive transistor, and resets the potential of the current end or control end of the drive transistor according to the control signal. The display device according to claim 1, characterized in that:   An electronic device comprising the display device according to claim 1.

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