JP2008283039A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which wiring between cells is easily possible over different power supply regions without affecting any timing characteristic, wireability and element area. <P>SOLUTION: The semiconductor device includes: a cell 101 that is provided in a power supply region A to which a power supply voltage VDD-A is supplied and is operated by a supply of the power supply voltage VDD-A and outputs a signal; relay cells 111 to 113 that are provided in a power supply region D to which a power supply voltage VDD-D is supplied and are operated by the supply of the power supply voltage VDD-A to receive and output a signal outputted from the cell 101; and a cell 102 that is provided in the power supply region A and is operated by the supply of the power supply voltage VDD-A and receives a signal outputted from the relay cell 113. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  In the semiconductor device, as the miniaturization progresses, the subthreshold leakage current and the gate leakage current increase, and the ratio of the power consumed by these currents to the whole increases.

  In a semiconductor device for portable equipment, low power consumption is required because of its use. However, on the other hand, very high performance is also required in order to cope with high functionality. Therefore, the conflicting requirements of low power consumption and high performance must be satisfied at the same time.

  At present, in order to achieve high performance and low power consumption, various ideas have been made such as supplying different power supply voltages for each functional block. Further, the leakage current is reduced by lowering the power supply voltage when the function block capability is not required to the maximum, or by cutting off the power supply when the function block capability is not required at all.

  For example, four power supply regions A, B, C, and D are provided. A power supply voltage of 1.2 V is always supplied to the power supply region A, and a power supply voltage of 1.0 V is always supplied to the power supply region B. It shall be. The power supply region C is supplied with any one of 1.2V / 1.0V / 0V depending on the operation mode, and the power supply region D is supplied with any of 1.2V / 0V depending on the operation mode. It is assumed that the power supply voltage is supplied and the power supply is cut off when no operation is required.

  In such an apparatus, when the cell X and the cell Y arranged in the power supply region A are wired, the distance between the two is long and a relay cell may be required on the way. However, when a different power supply region D exists between the cell X and the cell Y, a relay cell cannot be arranged in the power supply region D.

  This is because when the power supply region D is when the power supply is shut off, the relay cell does not operate and the level of the signal received by the cell Y becomes indefinite. Therefore, the relay cell must be arranged over a long distance so as to bypass the power supply region D, but there may be a case where the signal timing constraint cannot be satisfied.

  In order to avoid the detour so as to satisfy the timing constraint, the power supply region D existing between the cell X and the cell Y is divided into two, and a route for connecting the two at a short distance is secured, or the transmission side The driving ability of the cell X is increased to eliminate the necessity of the relay cell.

  However, dividing the power supply region D significantly affects the cell timing characteristics and the wiring characteristics in the power supply region D. Even when the cell X on the transmission side is a cell having a high driving capability, the relay cell may not be completely required depending on the arrangement and length of the signal path.

  Furthermore, when a relay cell passes through the power supply area D, it is necessary to consider so that crosstalk does not occur, and measures such as setting a wiring prohibited area on both sides of the wiring path of the relay cell are necessary. . As a result, the area of the element has been increased.

The following is a list of document names disclosing techniques related to a standard cell using a plurality of conventional power supplies.
Japanese Patent Laid-Open No. 2004-22877

  An object of the present invention is to provide a semiconductor device in which wiring between cells is possible without affecting timing characteristics, wiring properties, and element area.

  A semiconductor device according to one embodiment of the present invention is provided in a first power supply region to which a first power supply voltage is supplied, operates by being supplied with the first power supply voltage, and outputs a signal. Provided in a second power supply region to which a second power supply voltage is supplied, operates by being supplied with the first power supply voltage, and is provided with the signal output from the first cell. And at least one relay cell, and a second cell that is provided in the first power supply region, operates by being supplied with the first power supply voltage, and receives the signal output from the relay cell; It is characterized by providing.

  According to the semiconductor device of the present invention, it is possible to easily perform wiring between cells without affecting timing characteristics, wiring performance, and element area.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

(1) Embodiment 1
The semiconductor device according to the first embodiment of the present invention has the configuration shown in FIG.

  Four power supply regions A, B, C, and D are provided, and the power supply region A is constantly supplied with a power supply voltage VDD-A of 1.2 V without being shut off. The power supply region B is always supplied with a power supply voltage VDD-B of 1.0V. The power supply region C is supplied with any one of the power supply voltages VDD-C of 1.2V / 1.0V / 0V depending on the operation mode. It is assumed that any power supply voltage VDD-D of 1.2 V / 0 V is supplied to the power supply region D according to the operation mode, and when the operation is unnecessary, the power supply is shut off. Further, it is assumed that the ground voltage VSS is the same in all the regions A to D.

  Standard cells 101 and 102 are arranged in the power supply region A, and a signal is output from the standard cell 101 to the standard cell 102. A power supply region D in which the power is shut off is disposed between the two.

  In the signal path from the standard cell 101 to the standard cell 102, three relay cells, specifically, buffers 111, 112, and 113 are arranged and connected in series by a signal line 121. The buffers 111, 112, and 113 are supplied with the power supply voltage VDD-A from the power supply voltage terminal 131 to which the power supply voltage VDD-A in the power supply region A is applied via the power supply line 132.

  As a result, the path from the standard cell 101 to 102 can be connected at the shortest distance without detouring the power source region D where the power is shut off, so that the timing characteristics and wiring properties are not affected. Further, since it is not necessary to divide the power supply region D, the wiring property and the element area in the power supply region D are not affected.

  FIG. 2 shows a layout of elements included in the buffers 111, 112, and 113 in the semiconductor device according to the first embodiment.

  A power supply line VDD-D1 to which a power supply voltage VDD-D is applied in a power supply region D and a ground line VSS1 to which a ground voltage VSS is applied are arranged in a horizontal direction in the figure, and a vertical direction is provided in the region between them. Is formed with an inverter IN1 composed of one P-channel MOSFET P1 and an N-channel MOSFET N1, and similarly, an inverter IN2 composed of one P-channel MOSFET P2 and an N-channel MOSFET N2 is formed on the side. Yes.

  The source regions PS1 and PS2 of the P-channel MOSFETs P1 and P2 of the two-stage inverters IN1 and IN2, respectively, are connected to the power supply line VDD-A1 to which the power supply voltage VDD-A in the power supply region A is supplied. The drain regions PD1 and PD2 are connected to the drain regions ND1 and ND2 of the corresponding N-channel MOSFETs N1 and N2. The source regions NS1 and NS2 of the N-channel MOSFETs N1 and N2 are connected to the ground line VSS1.

  The drain region PD1 of the P-channel MOSFET P1 and the drain region ND1 of the N-channel MOSFET N1 in the previous stage inverter IN1 arranged on the left side in the drawing are connected to the input terminal A. The drain region PD2 of the P-channel MOSFET P2 and the drain region ND2 of the N-channel MOSFET ND2 in the subsequent inverter IN2 arranged on the right side are connected to the output terminal Z.

  As described above, in the semiconductor device according to the first embodiment, when the standard cells 101 and 102 in the power supply region A are connected, the power supply line VDD-D1 in the power supply region D is present in the power supply region D existing in the middle path. Buffers 101 to 103 composed of two-stage inverters IN1 and IN2 connected to the power supply line VDD-A1 to which the power supply voltage VDD-A of the power supply area A is applied are arranged in the region between the ground line VSS1 and the ground line VSS1. ing.

  The power supply line VDD-A1 connected to the inverters IN1 and IN2 is connected to the power supply region D in the middle when a signal is output from the standard cells 101 to 102 arranged in the power supply region A as shown in FIG. In order to pass through the inside, a signal line 121 is provided as a power line 132. As a result, according to the first embodiment, the buffers 101 to 103 can be arranged at arbitrary positions in the power supply region D without adversely affecting the arrangement and wiring property and timing of the power supply region D.

  FIG. 3 shows the arrangement of power supply lines and ground lines between the two standard cells in the first embodiment and the buffer connecting them. In the figure, the standard cell 101 is arranged in the power supply area A1 arranged in the upper part, the standard cell 102 is arranged in the power supply area A2 arranged in the lower part, and the two-stage buffer 111 as a relay cell in the power supply area D between them. , 112 are arranged.

  The output terminal Z of the standard cell 101 and the input terminal A of the buffer 111 are connected by a signal line 121a, the output terminal Z of the buffer 111 and the input terminal A of the buffer 112 are connected by a signal line 121b, The output terminal Z of the buffer 112 and the input terminal A of the standard cell 102 are connected by a signal line 121c.

  Further, the respective power supply voltage VDD-A terminals in the buffers 111 and 112 are connected to the power supply line VDD-A in one power supply area A1 so as to cut through the power supply area D, and the power supply line in the other power supply area A2 is further connected. Connected to VDD-A.

  Here, the arrangement of the signal lines and the power supply lines is not necessarily linear as shown in FIG. As shown in FIG. 4, signal lines 121d, 121e, and 121f having portions bent in an L shape in the middle may be used. Further, the power supply line VDD-A in the power supply area A1 and the power supply line VDD-A in the power supply area A2 are connected by a linear power supply line 132, and the power supply line 132a branched to the buffers 111 and 112 provided in the middle. You may connect using 132b.

  Alternatively, as shown in FIG. 5, linear or L-shaped signal lines 121g, 121h, and 121j are used, and further, linear or L-shaped power lines 132c, 132d, and 132e are used in the power supply region A1. The power supply line VDD-A, the power supply terminals VDD-A of the buffers 111 and 112, and the power supply line VDD-A in the power supply area A2 may be connected.

  Further, as shown in FIG. 6, the signal line 121 k that connects the output terminal Z of the standard cell 101 and the input terminal of the buffer 111, and the signal line that connects the output terminal of the buffer 111 and the input terminal of the buffer 112. 121 m, fixed potential power supply lines 132 a and 132 a 2, 132 b 1 and 132 b 2, respectively, so that the signal line 121 n connecting the output terminal of the buffer 112 and the input terminal A of the standard cell 102 is parallel to each other with a predetermined interval. 132c1 and 132c2 may be arranged. Thereby, the phenomenon in which the change in the level of the signal lines 121k, 121m, and 121n affects the surroundings can be suppressed, and the influence that the signal lines 121k, 121m, and 121n are affected by the level change in the surrounding wirings can be suppressed. It is possible to easily take measures against crosstalk.

(2) Embodiment 2
A semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.

  As described in the first embodiment, the power supply voltage VDD-A in the power supply region A different from the power supply voltage VDD-D in the power supply region D is supplied to the buffers 111 to 113 arranged in the power supply region D. The For this reason, when a power supply voltage is applied to the substrate, the substrate potential of the N well to which the power supply voltage VDD-A is supplied is maintained in the buffers 111 to 113 when the power supply is cut off in the power supply region D. It is necessary to do so.

  In the second embodiment, buffers 111 to 113 arranged in the power supply region D and operating with the power supply voltage VDD-A of the power supply region A are formed as shown in FIG.

  One inverter IN11 having an N-channel type MOSFET N11 and a P-channel type MOSFET P11 and an inverter IN12 having an N-channel type MOSFET N12 and a P-channel type MOSFET P12 border the power supply line VDD-D1 to which the power supply voltage VDD-D is applied. As shown, the back-to-back (Double Height) structure, that is, two stages are arranged in the vertical direction in the figure.

  Further, in the power supply region D, a power supply voltage VDD-A different from the power supply voltage VDD-D of the power supply region D is supplied, and an N well in which P-channel MOSFETs P11 and P12 are formed and an adjacent power supply (not shown) Isolation regions 201 to 204 are provided between the N well to which cells in region D are formed and to which power supply voltage VDD-D is applied.

  As a result, even when the power supply is cut off in the power supply region D, the power supply voltage VDD-A is applied to the n-well region in which the P-channel MOSFETs P11 and P12 included in the buffer arranged in this region are formed. Is continuously supplied to maintain the substrate potential. For this reason, since not only the power supply voltage but also the substrate potential can be separated between the buffers 111 to 113 and the surrounding cells in the power supply region D, the buffers 111 to 113 can operate without trouble.

(3) Embodiment 3
A semiconductor device according to the third embodiment of the present invention will be described with reference to FIG.

  In the first embodiment, only the power supply voltage is different between the power supply region A and the power supply region D, and the ground voltage is the same. On the other hand, in the third embodiment, not only the power supply voltage but also the ground voltage is different.

  Four power supply areas A, B, C, and D are provided. The power supply area A is always supplied with the power supply voltage VDD-A of 1.2 V without being shut off, and supplied with the ground voltage VSS-A. Is done. The power supply region B is always supplied with a power supply voltage VDD-B of 1.0 V and supplied with a ground voltage VSS-B. The power supply region C is supplied with one of the power supply voltages VDD-C of 1.2V / 1.0V / 0V according to the operation mode and the ground voltage VSS-C. Depending on the operation mode, any one of the power supply voltages VDD-D of 1.2V / 0V is supplied to the power supply region D, and a ground voltage VSS-D different from the voltage VSS-A is supplied. It is assumed that the power is cut off. Here, the ground voltages VSS-B and VSS-C may be the same as the other ground voltages VSS-A and VSS-D, respectively.

  It is assumed that standard cells 101 and 102 are arranged in the power supply region A, and a signal is output from the standard cell 101 to the standard cell 102. A power supply region D in which the power is shut off is disposed between the two.

  Three buffers 111, 112, and 113 are arranged on the signal path from the standard cell 101 to the standard cell 102, and are connected in series by a signal line 121. The buffers 111, 112, and 113 are supplied with the power supply voltage VDD-A through the power supply line 132 from the voltage terminal 131 to which the power supply voltage VDD-A in the power supply region A is applied. Further, in the buffers 111 to 113, the ground voltage VSS-A is supplied via the ground line 142 from the ground terminal 141 to which the ground voltage VSS-A in the power supply region A is applied.

  As a result, even when the power supply region D having different power supply voltage and ground voltage is disposed between the two standard cells 101 and 102, the path from the standard cell 101 to the power supply 102 is interrupted. Since the connection can be made at the shortest distance without detouring the power supply region D, the timing characteristics and wiring properties are not affected. Further, since it is not necessary to divide the power supply region D, it is possible to avoid a situation that affects the wiring property and the element area in the power supply region D.

  The above-described embodiments are merely examples and do not limit the present invention, and various modifications can be made within the technical scope of the present invention. For example, in the above embodiment, buffers as relay cells are provided in two to three stages in series.

1 is a layout diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a layout diagram illustrating a configuration of a buffer in the semiconductor device. FIG. 3 is a layout diagram showing an example of the arrangement of power supply lines and ground lines in the semiconductor device. FIG. 6 is a layout diagram illustrating another example regarding the arrangement of power supply lines and ground lines in the semiconductor device. FIG. 6 is a layout diagram illustrating another example regarding the arrangement of power supply lines and ground lines in the semiconductor device. FIG. 6 is a layout diagram illustrating another example regarding the arrangement of power supply lines and ground lines in the semiconductor device. The layout figure which showed the structure of the buffer in the semiconductor device by Embodiment 2 of this invention. FIG. 6 is a layout diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention.

Explanation of symbols

11 Power supply area A
14 Power supply area D
101-102 Standard cells 111-113 Buffer 121 Signal line 132 Power supply line

Claims (5)

A first cell that is provided in a first power supply region to which a first power supply voltage is supplied, operates by being supplied with the first power supply voltage, and outputs a signal;
Provided in a second power supply region to which a second power supply voltage is supplied, operates by being supplied with the first power supply voltage, and receives and outputs the signal output from the first cell. A one-stage relay cell;
A second cell provided in the first power supply region, operated by being supplied with the first power supply voltage, and receiving the signal output from the relay cell;
A semiconductor device comprising: The relay cell is arranged in a cell region between the second power supply line to which the second power supply voltage is applied and the ground line to which the ground voltage is applied in the second power supply region. ,
2. The semiconductor device according to claim 1, further comprising a first power supply line to which the first power supply voltage is applied in the cell region. A first signal line for transferring the signal from the first cell to the relay cell is sandwiched on both sides at a predetermined interval by a pair of third power supply lines to which the first power supply voltage is applied. Are arranged in parallel,
A second signal line for transferring the signal from the relay cell to the second cell is sandwiched on both sides at a predetermined interval by a pair of fourth power lines to which the first power voltage is applied. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged in parallel. The relay cell has an element formed in a well to which the first power supply voltage is applied in the second power supply region,
4. The semiconductor according to claim 1, wherein the well has an electrically isolated region between a region to which a voltage different from the first power supply voltage is applied. 5. apparatus.   The first power supply voltage is supplied to the first power supply region, and there is a period in which the second power supply voltage is not supplied to the second power supply region. 5. The semiconductor device according to any one of 4.

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