JP2008283014A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which can manufacture the semiconductor device including a fine and highly precise pattern with high production efficiency. <P>SOLUTION: Using an exposure apparatus A, a mask A which is transferable within a predetermined accuracy is prepared (s1), a plurality of critical pattern portions, which should be transferred within the predetermined accuracy, is selected in a transfer pattern in the mask A, and the numerical aperture about the proximity region of the each critical pattern portion is calculated respectively (s2). Among the plurality of critical pattern portions, a critical pattern portion α in which the numerical aperture becomes maximum and a critical pattern portion β in which the numerical aperture becomes minimum are identified (s3, s4). When the mask A has been transferred using an exposure apparatus B, whether each dimension of the critical pattern portion α, β is settled in the predetermined tolerance is evaluated (s5). In this case, when each dimension is settled in the predetermined tolerance, exposure is carried out by the combination of the exposure apparatus B and the mask A (s6). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device suitable for, for example, EUV (Extreme Ultra Violet) lithography and the like, and performing exposure using an exposure apparatus and a mask.

  Conventionally, optical lithography such as i-line lithography with a wavelength of 365 nm, KrF lithography with a wavelength of 248 nm, and ArF lithography with a wavelength of 193 nm has been used as a lithography technique used in the manufacturing process of a semiconductor device. Recently, immersion lithography that meets the requirement of higher resolution than ArF lithography has been actively researched. However, even in this immersion lithography, the resolution of 45 nm at the half pitch is the limit. Therefore, EUV lithography having a shorter wavelength of 13.5 nm has been actively studied, and this EUV lithography can achieve a resolution of a half pitch of 32 nm.

  One of the challenges of EUV lithography is the problem of lens flare. Since the exposure wavelength in EUV lithography is as extremely short as 13.5 nm, projection exposure is performed using a reflective optical system instead of a refractive lens system because of the relationship between light absorption and refractive index. In a reflective optical system composed of multilayer mirrors, exposure light is scattered under the influence of extremely fine surface roughness, and flare that is stray light is generated. Due to this flare, exposure fogging occurs according to the aperture ratio around the pattern, and the pattern dimension changes. This is a problem of lens flare, and a dimensional change of 0.7 nm occurs every time the aperture ratio increases by 1%.

  Since the target dimension of EUV lithography is at the level of 32 nm, this lens is used in the manufacture of LSIs in which various patterns coexist with various densities, especially in the manufacture of logic LSIs such as SoC (System on a Chip) with many types of patterns. Flare becomes a big problem.

  In order to solve this lens flare problem, a flare correction technique that adjusts the width of the pattern on the mask according to the aperture ratio of the peripheral pattern and obtains a pattern with a desired dimensional accuracy is disclosed in, for example, Patent Document 1 below. It is proposed in 2nd.

US Pat. No. 6,815,129 JP 2004-62096 A

  The flare of EUV lithography changes according to the surface roughness state of the multilayer mirror, the spatial frequency distribution of the roughness, or the intensity of the roughness according to optical analysis. Not only the amount of flare but also the width of the peripheral area that affects the pattern dimension varies depending on the surface roughness. Therefore, the mask dimension correction amount of the flare correction technique described above needs to be changed according to the surface roughness state of the multilayer mirror.

  Therefore, when the state of the optical system changes due to a change in the exposure apparatus to be used, or when the state of the optical system changes due to a change in the generation (for example, resolution) of the exposure apparatus, the pattern dimensions on the mask must also be changed. Redesign of the mask is necessary. For this reason, fixing the combination of the exposure apparatus and the mask or redesigning a dedicated mask for each exposure apparatus causes a reduction in facility utilization efficiency and an increase in manufacturing cost.

  An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device including a fine and highly accurate pattern with high production efficiency.

  According to an embodiment of the present invention, a mask having a transfer pattern that requires a high resolution is exposed using a dedicated exposure apparatus, whereas a mask having a transfer pattern that does not require a high resolution so much. Provides a method of manufacturing a semiconductor device that can be exposed using another exposure apparatus.

  Regarding the resolution determination method, in the transfer pattern on the mask, a plurality of critical pattern portions to be transferred within a predetermined dimensional accuracy are selected, and the first critical pattern portion having the maximum aperture ratio and the aperture ratio is minimized. Each second critical pattern portion is specified. Then, when the mask is transferred using another exposure apparatus, it is evaluated whether each dimension of the first critical pattern portion and the second critical pattern portion falls within a predetermined allowable range.

  When each dimension falls within a predetermined allowable range, exposure is performed using another exposure apparatus. On the other hand, when each dimension does not fall within a predetermined allowable range, exposure is performed with a combination of the exposure apparatus and the mask fixed.

  When determining the aperture ratio of the critical pattern portion, a plurality of determination values may be employed instead of the maximum value or the minimum value of the aperture ratio.

  As such a critical pattern portion, it is preferable to select a gate pattern portion provided on the active layer of the FET, a wiring pattern portion in contact with the connection hole, or a wiring pattern portion adjacent to the connection hole.

  Further, the present invention is preferably applied to an EUV exposure apparatus and EUV mask used for EUV lithography.

According to this embodiment, when a high resolution is required at the time of exposure, the combination of the exposure apparatus and the mask is fixed, but when the high resolution is not so required, without limiting the combination of the exposure apparatus and the mask, Another exposure apparatus can be used. Therefore, the utilization efficiency of equipment such as an exposure apparatus and a mask can be increased, and the manufacturing cost can be reduced.

Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a flowchart showing a first embodiment of the present invention. In the present embodiment, three EUV exposure apparatuses A to C are prepared as exposure apparatuses.

  FIG. 2 is a graph showing PSD (Power Spectrum Density) characteristics of the projection optical systems A to C mounted on the exposure apparatuses A to C. The vertical axis represents power intensity (logarithmic display), and the horizontal axis represents spatial frequency (logarithmic display).

  The exposure apparatus A and the exposure apparatus B are exposure apparatuses of the same generation and have the same resolution, but the shape of the PSD curve is caused by polishing of the reflecting mirror constituting the projection optical system and slight manufacturing variations of the multilayer coating. Is different. However, the MSFR (Mid Spatial Frequency Roughness) value defined by the roughness intensity in the spatial frequency range of 1 / mm to 1 / μm is the same.

  The projection optical system C of the exposure apparatus C has a higher resolution advanced by one generation than the exposure apparatuses A and B, and generally has a low roughness. Therefore, the value of MSFR is also smaller than that of the projection optical systems A and B. It has become.

  FIG. 3 is a graph showing the transfer characteristics of the projection optical system A. The vertical axis represents the dimensional change (nm), and the vertical axis represents the aperture ratio (%). As described above, the transfer characteristic of the projection optical system is greatly affected by flare due to the extremely fine surface roughness of the multilayer mirror, and exposure fogging occurs depending on the aperture ratio around the pattern, and the pattern dimension changes. . As the aperture ratio around the pattern (the ratio at which the multilayer film is exposed) increases, the dimensional change amount increases monotonously. For example, when the aperture ratio increases by 1%, the dimensional change amount increases by 0.7 nm.

  Referring to FIG. 1, when lithography is first performed using exposure apparatus A in step s1, mask A that can be transferred within a predetermined dimensional accuracy is prepared. Next, in step s2, a plurality of critical pattern portions to be transferred within a predetermined dimensional accuracy are extracted from the layout pattern on the mask A. In EUV exposure, the pattern dimension is generally critical, that is, the part where the dimensional accuracy is demanded.

  As a method for extracting the critical pattern portion, for example, there are the following methods 1 to 4.

  [Method 1] As the critical pattern portion, a gate pattern portion provided on the active layer (diffusion layer) of the FET is selected. For example, in the case of a pattern layout in which the gate wiring 10 is provided on the active layer (diffusion layer) 11 as shown in FIG. 4, this gate wiring is used as shown in FIG. Ten patterns are extracted and set as the critical pattern portion 21.

  [Method 2] As a critical pattern portion, a portion where an interval between adjacent patterns is narrower than a predetermined interval is extracted. For example, as shown in FIG. 6, when attention is paid to the wiring pattern 31, the portion that is close to the adjacent pattern is a pattern portion 32. When the interval between the pattern portion 32 and the adjacent pattern is smaller than a predetermined determination value, it is extracted as a critical pattern portion.

  The pattern interval to be determined can be defined according to various pattern shapes. For example, as shown in FIG. 7A, when two patterns run in parallel, the distance L1 between pattern edges. Can be defined as Further, as shown in FIG. 7B, when the end of another pattern is approaching from a side with respect to a certain pattern, the pattern interval can be defined as a distance L2 between the pattern edge and the end edge. . Further, as shown in FIG. 7C, when the end portions of the patterns are facing each other and approaching each other, the pattern interval can be defined as a distance L3 between the end portion edges. Further, as shown in FIG. 7D, when the end portions of the patterns are approaching obliquely, the pattern interval can be defined as a distance L4 between the end corners. Further, as shown in FIG. 7E, when the rectangular pattern is approaching and approaching the L-shaped pattern, the pattern interval can be defined as two distances L5 and L6 between the pattern edges.

Such a critical pattern portion can be extracted by using a technique such as pattern calculation. An example is shown in FIG. First, as shown in FIG. 8A, when two patterns 50 are arranged in parallel with a distance L, as shown in FIG. The virtual pattern 51 is created by increasing the thickness by L _1/2 (broadening). At this time, part belonging to the pattern interval distance L ₁ or less will be coalesced. Next, as shown in FIG. 8C, the virtual pattern 52 is created by thinning (lessening) L _1/2 over the entire circumference of the virtual pattern 51. Next, as shown in FIG. 8D, the difference pattern 53 is created by subtracting the original patterns 50 from the virtual pattern 52. Finally, a portion of each pattern 50 that contacts the difference pattern 53 is a critical pattern portion.

  [Method 3] As a critical pattern portion, a wiring pattern portion in contact with the connection hole is extracted. For example, as shown in FIG. 9, in the wiring pattern 31, a portion in contact with the connection hole pattern 33 and its vicinity are extracted as a critical pattern portion 34. As an example of pattern calculation, the connection hole pattern 33 is broadened by a predetermined amount to create a thick virtual pattern, and a portion where the virtual pattern and the wiring pattern 31 overlap is defined as a critical pattern portion 34. However, if the thick virtual pattern is completely included in the wiring pattern 31 and there is a margin, the critical pattern portion is not used.

  [Method 4] As a critical pattern portion, a wiring pattern portion adjacent to the connection hole is extracted. For example, as shown in FIG. 10, a wiring portion close to each other is defined as a critical pattern portion 42 so that the connection hole 41 for connecting to another layer and the wiring layer 10 do not contact each other. As an example of pattern calculation, the connection hole 41 is broadened by a predetermined amount to create a thick virtual pattern, and a contact portion or an overlap portion between the virtual pattern and the wiring layer 10 is defined as a critical pattern portion. Note that when the wiring layer 10 has a gate pattern, contact with the connection hole (contact layer) on the isolation layer (diffusion layer) is avoided by the design rule and the gate pattern accuracy management according to the method 1. It can also be excluded from the target.

  After extracting a plurality of critical pattern parts in this way, the aperture ratio relating to the vicinity area of each critical pattern part is calculated, and the critical pattern part α having the maximum aperture ratio is extracted in step s3 of FIG. The size of this neighborhood region is determined in advance. There are two methods for obtaining the aperture ratio: a method for calculating a simple aperture ratio and a method for calculating a weighted aperture ratio with a weight that becomes heavier as the distance increases and becomes lighter as the distance increases. . The former has the advantage that the calculation is light and the time can be shortened, and the latter has the advantage that management with high dimensional accuracy can be performed.

  Next, in step s4, the critical pattern portion β with the smallest aperture ratio is extracted in the same manner as described above.

  Next, in step s5, when the mask A is transferred using the exposure apparatus B separate from the exposure apparatus A, it is evaluated whether or not the dimensions of the critical pattern portions α and β are within a predetermined allowable range. The evaluation method at this time may be a simulation or an actual exposure experiment.

  When it is determined that each dimension of each critical pattern portion α, β falls within a predetermined allowable range, the process proceeds to step s6, and the mask A has a predetermined dimension regardless of whether the exposure apparatus A or the exposure apparatus B is used. Transfer is possible within accuracy. Therefore, even if the exposure apparatus A cannot be used, exposure can be performed by the combination of the exposure apparatus B and the mask A.

  On the other hand, if it is determined in step s5 that the dimensions of the critical pattern portions α and β are not within the predetermined allowable range, the process proceeds to step s7, where the mask A is predetermined when the exposure apparatus B is used. It is impossible to transfer within the dimensional accuracy. Therefore, when exposure is performed using the mask A, the exposure apparatus A and the mask A are limited to combinations. If the exposure apparatus A cannot be used, a mask B that can be transferred within a predetermined dimensional accuracy is prepared using the exposure apparatus B, and then exposure is performed by a combination of the exposure apparatus B and the mask B.

  In this way, depending on the degree of resolution required for the exposure process of the semiconductor device, the equipment utilization efficiency can be increased by fixing the combination of the exposure apparatus and the mask, or by diverting another exposure apparatus. Reduction.

  Here, an example of extracting the critical pattern portion α having the maximum aperture ratio and the critical pattern portion β having the minimum aperture ratio has been described. However, the aperture ratio is in the range from the maximum to a predetermined first determination value. The critical pattern portion α and the critical pattern portion β in the range from the minimum aperture value to a predetermined second determination value may be extracted. That is, by evaluating the aperture ratio of the critical pattern portion using two determination values (first determination value> second determination value), the target is expanded to evaluate whether the critical pattern portion group falls within the allowable range. A method for limiting the combination of the mask and the exposure apparatus is also effective. By such a method, the probability of occurrence of transfer failure is further reduced, and the yield of the semiconductor device is improved.

  In the above description, an example in which a critical pattern portion that requires high dimensional accuracy in the layout pattern on the mask A is extracted by using a method such as pattern calculation has been described. A predetermined method can also be employed. For example, as an alternative to step s2 in FIG. 1, as shown in step s2a in FIG. 11, in the layout pattern on mask A, a plurality of critical pattern portions to be transferred within predetermined dimensional accuracy are defined in advance. In the pattern layout stage, it is easy to define a critical pattern portion by separating a portion that requires high dimensional accuracy and a portion that does not require so much dimensional accuracy into different layers. The other steps s1, s3 to s7 are the same as in FIG. In this way, the trouble of extracting the critical pattern portion can be saved, so that TAT (turn around time) is improved.

  In the above description, an example of selectively using the same generation exposure apparatus A and exposure apparatus B is shown. However, the present invention is not limited to this, and the PSD characteristics of the optical system shown in FIG. The same technique can be used for selectively using the exposure apparatus A and the exposure apparatus C which are significantly different from each other, or for properly using the exposure apparatus B and the exposure apparatus C.

  According to this embodiment, the combination of the mask and the EUV exposure apparatus can be diversified without causing a transfer failure, and the operation efficiency of the semiconductor device manufacturing line is improved. Both the EUV exposure apparatus and the EUV mask are expensive, and it takes a lot of time to manufacture the mask. Therefore, compared with the conventional method in which a dedicated mask is prepared for each exposure apparatus, both TAT and manufacturing cost are greatly improved. . In particular, a great effect can be obtained when shifting from product development or small-scale production using a single exposure apparatus to mass production using a plurality of exposure apparatuses, or when replacing with a new exposure apparatus. For example, when replacing with a new type of exposure apparatus, it was necessary to redesign all the masks in the past.However, according to the present invention, it is necessary to redesign some of the masks, resulting in long-term manufacturing costs. It can be greatly reduced.

Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a flowchart showing an example of the semiconductor wafer process. First, in order to create isolation (separation between active regions), a film forming process (s201), an isolation layer lithography process (s202), an etching process (s203), and an insulating film embedding process (s204). Then, a lithography process (s205), an etching process (s206), and a CMP process (s207) for manufacturing a CMP (chemical mechanical polishing) dummy pattern for flattening the wafer surface are performed to form isolation.

  Subsequently, a lithography process (s208) and an implantation process (s209) for implantation (ion implantation) separation are performed to form a well layer, followed by a gate deposition process (s210) and a lithography process (s211). , Etching step (s212), lithography step for implant implantation (s213), implantation step (s214), film formation step for LDD (Lightly-Doped-Drain) (s215), LDD processing step (s216), implantation step ( s217) to form a gate.

  Subsequently, a conductive film is formed (s221) after performing an insulating film formation step (s218), a contact layer lithography step (s219), and an etching step (s220) to form a conductive hole, and then a lithography step. (S222) An etching step (s223) is performed to form a wiring layer.

  Subsequently, after forming the interlayer insulating film (s224), openings are formed by the lithography process (s225, s227) and the etching process (s226, s228), the conductive film deposition process (s229), and the CMP process ( In step S230, an interlayer wiring is formed. By repeating these interlayer wiring forming steps (s224 to s230) as necessary (s231 to s237), a multilayer wiring can be formed.

  In these processes, EUV lithography is used for the isolation, gate, contact, first via, second via, and wiring layers, which are critical layers with strict dimensional accuracy.

  An example of a circuit that can be manufactured using these steps is shown in FIG. 13 shows a 2-input NAND gate circuit ND. FIG. 13A is a symbol diagram, FIG. 13B is a circuit diagram, and FIG. 13C is a plan view showing a layout on a wafer.

  In FIG. 13 (c), a part surrounded by an alternate long and short dash line is a unit cell 110, two nMOS portions Qn formed on the n-type semiconductor region 111n on the surface of the p-type well region PW, and an n-type well. This is composed of two pMOS portions Qp formed on the p-type semiconductor region 111p on the surface of the region NW.

  In order to produce this structure, pattern transfer is repeatedly performed using masks M1 to M6 as shown in FIG. Among these, the masks M1, M4 to M6 are required to be fine and have high dimensional accuracy, and therefore EUV lithography is adopted. In FIG. 15, reference numerals 101a, 101d, 101e, and 101f are EUV light reflecting parts using a multilayer film, and reference numerals 102a, 102d, 102e, and 102f are EUV light shielding parts.

  On the other hand, the masks M2 and M3 have a relatively large size pattern, and dimensional accuracy is relaxed. Therefore, photolithography is employed. In FIG. 15, reference numerals 101b and 101c are light transmission portions, and reference numerals 102b and 102c are light shielding portions made of a chromium film or halftone portions made of a MoSi film.

  Next, a process of forming the nMOS portion Qn and the pMOS portion Qp will be described using a cross-sectional view taken along the broken line in FIG. 14 showing the same layout as FIG.

  Referring to FIG. 16, after an insulating film 115 made of, for example, a silicon oxide film is formed on a wafer S (W) made of P-type silicon crystal by an oxidation method, for example, a silicon nitride film 116 is made thereon. Are deposited by a CVD (Chemical Vapor Deposition) method, and a resist film 117 is further formed thereon (FIG. 16A).

  Next, an exposure development process is performed using the mask M1 to form a resist pattern 117a (FIG. 16B). In addition, the code | symbol 1a in the figure shows a multilayer film. Thereafter, using the resist pattern 117a as an etching mask, the insulating film 115 and the silicon nitride film 116 exposed from the resist pattern 117a are sequentially removed, the resist film 117 is further removed, and a groove 118 is formed on the surface of the wafer S (W) (FIG. 16 (c)).

  Next, for example, after an insulating film 119 made of silicon oxide is deposited by a CVD method or the like (FIG. 16D), a planarization process is performed by, for example, CMP, so that the element isolation structure SG is finally formed. It forms (FIG.16 (e)).

  In this embodiment, an example in which a trench type isolation structure is provided as an element isolation structure has been described. However, the present invention is not limited to this, and for example, a field insulating film formed by a LOCOS (Local Oxidation of Silicon) method is used. Also good.

  Subsequently, referring to FIG. 17, exposure development is performed using mask M2 to form a resist pattern 117b. At this time, since the region where the n-type well region is to be formed is exposed, phosphorus or arsenic is ion-implanted to form the n-type well region NW (FIG. 17A).

  Similarly, for the p-type well region PW, a resist pattern 117c is formed using the mask M3, and then, for example, boron is ion-implanted to form the p-type well region PW (FIG. 17B).

  Next, a gate insulating film 120 made of a silicon oxide film is formed to a thickness of 2 nm, and a layer 112 made of polycrystalline silicon and tungsten is further deposited thereon by a CVD method or the like (FIG. 17C).

  Subsequently, after applying a resist, exposure and development are performed using a mask M4 to form a resist pattern 117d, and then the gate insulating film 120 and the gate electrode 112A are formed by etching and removing the layer 112 made of polycrystalline silicon and tungsten. It forms (FIG.17 (d)). In addition, the code | symbol 2a in the figure shows a multilayer film.

  Subsequently, an n-type semiconductor region 111n having a high impurity concentration for n-channel MOS and a p-type semiconductor region 111p having a high impurity concentration for p-channel MOS, which also function as a source region, a drain region, and a wiring layer, are ionized. The gate electrode 112A is formed in a self-aligned manner by implantation or diffusion (FIG. 17E).

  In the subsequent steps, a 2-input NAND gate group is manufactured by appropriately selecting a wiring pattern. It goes without saying that other circuits such as a NOR gate circuit can be formed by changing the shape of the wiring pattern. Hereinafter, an example of manufacturing a two-person NAND gate using the masks M5 and M6 shown in FIGS. 15E and 15D will be described.

  FIG. 18 is a cross-sectional view taken along the broken line shown in FIG. 14 and shows a wiring formation process. First, an interlayer insulating film 121a is deposited on the two n-channel MOS portions Qn and the two p-channel MOS portions Qp by the CVD method (FIG. 18A).

  Subsequently, a resist is applied, exposure development processing is performed using the mask M5 to form a resist pattern 117e, and then contact holes CNT are formed by etching processing (FIG. 18B). In addition, the code | symbol 3a in the figure shows a multilayer film.

  After removing the resist, a metal such as tungsten, a tungsten alloy, or copper is embedded, and CMP is performed to form a metal layer 113 (FIG. 18C).

  Subsequently, after depositing an interlayer insulating film, a resist is applied, and exposure development processing is performed using the mask M6 to form a resist pattern 117f (FIG. 18D). Then, interlayer film etching, resist removal, Wirings 113A to 113C are formed by depositing a conductive film and performing a CMP process (FIG. 18E).

  Thereafter, an interlayer insulating film 121b is formed, and further, a through hole VIA and an upper layer wiring 114A are formed using another mask (not shown) (FIG. 18E).

  Regarding the connection of parts, a semiconductor integrated circuit can be manufactured by repeating the same wiring formation process as many times as necessary to form a pattern.

  FIG. 19 and FIG. 20 are flowcharts showing an example of selectively using the EUV mask and the EUV exposure apparatus used when manufacturing this semiconductor device. FIG. 19A shows a case in which an EUV exposure apparatus No. 1 (using the projection optical system A in FIG. 2) and a mask adapted to the characteristics of the EUV exposure apparatus No. 1 for each layer are used. The case where it fixes to the combination of a machine and the mask 1 is shown. In this case, when a semiconductor integrated circuit was actually manufactured, a semiconductor device could be manufactured with a high yield.

  FIG. 19B shows a case where production is further performed by additionally introducing the EUV exposure apparatus No. 2 (using the projection optical system B in FIG. 2) in order to increase the production amount of the semiconductor device. The case where not only the combination of the mask 1 but the combination of No. 2 machine and the mask 1 is used together is shown. In the first and second EUV exposure apparatuses, as shown in FIG. 2, the MSFR values of the projection optical system are almost the same, but the PSD characteristics are different. For this reason, when only the mask 1 matched to the characteristics for the first machine was used and the first and second machines were used together to actually manufacture the semiconductor integrated circuit, the yield was sometimes lowered.

  As a result of investigating the cause, as shown in FIG. 19B, in the EUV lithography for the isolation layer, the gate layer, the wiring layer 1, and the wiring layer 2, it is necessary to create a dedicated mask 2 that matches the characteristics of the second machine. On the other hand, in the EUV lithography for the contact layer and via layer 1, it has been found that a sufficient yield can be obtained even if the mask 1 for the first machine is used for the second machine.

  In addition, as a result of the same examination in the subsequent multilayer wiring layer, the mask for the first unit can be used as the mask for the connection hole, but the yield for the wiring mask is sufficient unless a mask dedicated to the second unit is manufactured. It turned out that it was not obtained.

  When the EUV exposure apparatus No. 2 is additionally introduced as described above, for example, if a mask that does not require a high resolution, such as a mask for connection holes, the mask for No. 1 machine can be used. This eliminates the need to re-create and is advantageous in terms of manufacturing cost and TAT.

  Further, when the exposure is performed using the EUV exposure apparatus No. 3 (using the projection optical system C in FIG. 2), which is an advanced generation, instead of the EUV exposure apparatus No. 2, the same result as described above is obtained. It was.

  FIG. 20A shows a case where the first and second EUV exposure apparatuses are mixed in order to improve the operation efficiency of the production line. Also in this case, various combinations of exposure apparatuses and masks were examined. As a result, as shown in FIG. 20A, in EUV lithography for the isolation layer, gate layer, wiring layer 1, and wiring layer 2, a semiconductor device must be used unless a dedicated mask adapted to the characteristics of each exposure apparatus is used. However, in EUV lithography for the contact layer and via layer 1, it has been found that a sufficient yield can be obtained even if a mask adapted to the characteristics of another exposure apparatus is used.

  In FIG. 20 (a), the EUV lithography for the via 1 shows an example using the combination of the first machine and the mask 1 for the first machine, but the combination of the second machine and the mask 1 for the first machine, or the first machine. No significant difference was found in the yield of the semiconductor device even with the combination of No. 2 and the mask 2 for Unit 2.

  FIG. 20B shows a case where the EUV exposure apparatus No. 3 of advanced generation is introduced in addition to the first and second EUV exposure apparatuses. Unit 3 uses the projection optical system C of FIG. 2 and can achieve a resolution much higher than that of Units 1 and 2. For this reason, the No. 3 machine was applied to a gate layer forming process and a contact layer forming process that require particularly high dimensional accuracy.

  In the gate layer forming process, a sufficient yield can be obtained by combining the mask 3 for the No. 3 and No. 3 units. However, in the combination of the mask 1 for the No. 3 and No. 1 units, or the combination of the No. 3 and No. 2 mask 2 units. The yield of semiconductor devices decreased.

  On the other hand, in the contact layer forming step, no significant difference was found in the yield of the semiconductor device even with the combination of the No. 3 and No. 1 masks 1.

  Furthermore, as a result of examining a combination of masks having different aperture ratios with various types of exposure apparatuses, if the aperture ratio exceeds 10%, the yield of semiconductor devices may be reduced unless a dedicated mask is used for the exposure apparatus. understood.

  Thus, according to the object of EUV lithography, the yield of semiconductor devices can be determined by distinguishing between the case where a dedicated mask is used for each exposure apparatus and the case where a mask adapted to the characteristics of other exposure apparatuses is used. It is possible to reduce the number of masks to be created and to increase the operational efficiency of the line while ensuring sufficient.

  The present invention is extremely useful industrially in that a semiconductor device including a fine and highly accurate pattern can be manufactured with high production efficiency.

It is a flowchart which shows 1st Embodiment of this invention. It is a graph which shows the PSD characteristic of the projection optical system mounted in the exposure apparatus. 6 is a graph showing transfer characteristics of the projection optical system A. It is a top view which shows an example of the layout of the pattern of a semiconductor device. It is a top view which shows an example of the layout of the pattern of a semiconductor device. It is a top view which shows an example of the layout of the pattern of a semiconductor device. It is explanatory drawing which shows the definition of the pattern space | interval at the time of extracting a critical pattern part. It is explanatory drawing which shows the figure calculation method for extracting a critical pattern part. It is a top view which shows an example of the layout of the pattern of a semiconductor device. It is a top view which shows an example of the layout of the pattern of a semiconductor device. It is a flowchart in the case of defining a critical pattern part beforehand. It is a flowchart which shows an example of a semiconductor wafer process process. FIG. 13 (a) is a symbol diagram, FIG. 13 (b) is a circuit diagram, and FIG. 13 (c) is a plan view showing a layout on a wafer. It is a top view which shows the cross-sectional line in the unit logic cell of a NAND gate circuit. It is a top view which shows the various masks used when forming a unit cell. It is sectional drawing which shows an element isolation process. It is sectional drawing which shows a gate formation process. It is sectional drawing which shows a wiring formation process. FIG. 19A is a flowchart showing a wiring forming process, and FIG. 19A shows a case where the combination of the exposure apparatus No. 1 and the mask 1 is fixed, and FIG. 19B is a combination of the exposure apparatus No. 2 and the mask 1 Shows the case. FIG. 20A shows a case where the first and second exposure apparatuses are used together, and FIG. 20B shows a case where an exposure apparatus No. 3 is additionally introduced.

Explanation of symbols

10 gate wiring, 11 active layer (diffusion layer),
21 critical pattern part, 31 wiring pattern, 32 pattern part,
33 connection hole pattern, 34 critical pattern part, 41 connection hole,
42 critical pattern part, 50 patterns, 51,52 virtual patterns,
53 differential patterns, 110 unit cells, 111n n-type semiconductor regions,
111p p-type semiconductor region, 112 polycrystalline silicon layer, 112A gate electrode,
113 metal layer, 113A to 113C, 114A wiring, 115 insulating film,
116 silicon nitride film, 117 resist film,
117a to 117f resist pattern, 119 insulating film,
120 gate insulating film, 121a interlayer insulating film,
M1-M6 mask, SG element isolation structure,
Qn nMOS part, Qp pMOS part, NW n-type well region,
PW p-type well region, VIA through hole.

Claims (11)

Providing a first mask transferable within a predetermined dimensional accuracy using a first exposure apparatus;
Selecting a plurality of critical pattern portions to be transferred within a predetermined dimensional accuracy in the transfer pattern of the first mask;
A step of calculating an aperture ratio relating to a neighboring region of each critical pattern part,
Of the plurality of critical pattern portions, a step of specifying a first critical pattern portion having a maximum aperture ratio and a second critical pattern portion having a minimum aperture ratio,
A step of evaluating whether each dimension of the first critical pattern portion and the second critical pattern portion falls within a predetermined allowable range when the first mask is transferred using the second exposure apparatus;
And a step of performing exposure using a combination of a second exposure apparatus and a first mask when each of the dimensions falls within a predetermined allowable range. Providing a first mask transferable within a predetermined dimensional accuracy using a first exposure apparatus;
Selecting a plurality of critical pattern portions to be transferred within a predetermined dimensional accuracy in the transfer pattern of the first mask;
A step of calculating an aperture ratio relating to a neighboring region of each critical pattern part,
Among the plurality of critical pattern portions, a first critical pattern portion whose aperture ratio is equal to or higher than a predetermined first determination value and a second critical pattern portion whose aperture ratio is equal to or lower than a predetermined second determination value are specified. Steps,
A step of evaluating whether each dimension of the first critical pattern portion and the second critical pattern portion falls within a predetermined allowable range when the first mask is transferred using the second exposure apparatus;
And a step of performing exposure using a combination of a second exposure apparatus and a first mask when each of the dimensions falls within a predetermined allowable range. When each of the dimensions does not fall within a predetermined tolerance, further preparing a second mask that can be transferred within a predetermined dimensional accuracy using a second exposure apparatus;
Performing exposure with a combination of a first exposure apparatus and a first mask;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing exposure using a combination of a second exposure apparatus and a second mask.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a gate pattern portion provided on an active layer of the FET is selected as the critical pattern portion.   The method of manufacturing a semiconductor device according to claim 1, wherein a wiring pattern portion that contacts the connection hole is selected as the critical pattern portion.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a wiring pattern portion adjacent to the connection hole is selected as the critical pattern portion. A method of manufacturing a semiconductor device for performing exposure using a plurality of exposure apparatuses,
The mask having the first transfer pattern is exposed using an unspecified exposure apparatus,
A method of manufacturing a semiconductor device, wherein a mask having a second transfer pattern is exposed using a specific exposure apparatus.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first transfer pattern is a connection hole pattern, and the second transfer pattern is a wiring pattern. The first semiconductor device is exposed using the first exposure apparatus, and then the second semiconductor device, which is the same product type as the first semiconductor device, is exposed using the second exposure apparatus. A method of manufacturing a semiconductor device for performing
When exposing the first transfer pattern, the same mask is used in the first exposure apparatus and the second exposure apparatus,
A method of manufacturing a semiconductor device, wherein when the second transfer pattern is exposed, different masks are used for the first exposure apparatus and the second exposure apparatus.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the first transfer pattern is a connection hole pattern, and the second transfer pattern is a wiring pattern. The exposure apparatus is an EUV exposure apparatus,
The method of manufacturing a semiconductor device according to claim 1, wherein the mask is an EUV mask.

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